1 /***************************************************************************
2 * Copyright (C) 2013 Synapse Product Development *
3 * Andrey Smirnov <andrew.smironv@gmail.com> *
4 * Angus Gratton <gus@projectgus.com> *
5 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
21 ***************************************************************************/
28 #include <target/algorithm.h>
29 #include <target/armv7m.h>
30 #include <helper/types.h>
33 NRF51_FLASH_BASE
= 0x00000000,
36 enum nrf51_ficr_registers
{
37 NRF51_FICR_BASE
= 0x10000000, /* Factory Information Configuration Registers */
39 #define NRF51_FICR_REG(offset) (NRF51_FICR_BASE + offset)
41 NRF51_FICR_CODEPAGESIZE
= NRF51_FICR_REG(0x010),
42 NRF51_FICR_CODESIZE
= NRF51_FICR_REG(0x014),
43 NRF51_FICR_CLENR0
= NRF51_FICR_REG(0x028),
44 NRF51_FICR_PPFC
= NRF51_FICR_REG(0x02C),
45 NRF51_FICR_NUMRAMBLOCK
= NRF51_FICR_REG(0x034),
46 NRF51_FICR_SIZERAMBLOCK0
= NRF51_FICR_REG(0x038),
47 NRF51_FICR_SIZERAMBLOCK1
= NRF51_FICR_REG(0x03C),
48 NRF51_FICR_SIZERAMBLOCK2
= NRF51_FICR_REG(0x040),
49 NRF51_FICR_SIZERAMBLOCK3
= NRF51_FICR_REG(0x044),
50 NRF51_FICR_CONFIGID
= NRF51_FICR_REG(0x05C),
51 NRF51_FICR_DEVICEID0
= NRF51_FICR_REG(0x060),
52 NRF51_FICR_DEVICEID1
= NRF51_FICR_REG(0x064),
53 NRF51_FICR_ER0
= NRF51_FICR_REG(0x080),
54 NRF51_FICR_ER1
= NRF51_FICR_REG(0x084),
55 NRF51_FICR_ER2
= NRF51_FICR_REG(0x088),
56 NRF51_FICR_ER3
= NRF51_FICR_REG(0x08C),
57 NRF51_FICR_IR0
= NRF51_FICR_REG(0x090),
58 NRF51_FICR_IR1
= NRF51_FICR_REG(0x094),
59 NRF51_FICR_IR2
= NRF51_FICR_REG(0x098),
60 NRF51_FICR_IR3
= NRF51_FICR_REG(0x09C),
61 NRF51_FICR_DEVICEADDRTYPE
= NRF51_FICR_REG(0x0A0),
62 NRF51_FICR_DEVICEADDR0
= NRF51_FICR_REG(0x0A4),
63 NRF51_FICR_DEVICEADDR1
= NRF51_FICR_REG(0x0A8),
64 NRF51_FICR_OVERRIDEN
= NRF51_FICR_REG(0x0AC),
65 NRF51_FICR_NRF_1MBIT0
= NRF51_FICR_REG(0x0B0),
66 NRF51_FICR_NRF_1MBIT1
= NRF51_FICR_REG(0x0B4),
67 NRF51_FICR_NRF_1MBIT2
= NRF51_FICR_REG(0x0B8),
68 NRF51_FICR_NRF_1MBIT3
= NRF51_FICR_REG(0x0BC),
69 NRF51_FICR_NRF_1MBIT4
= NRF51_FICR_REG(0x0C0),
70 NRF51_FICR_BLE_1MBIT0
= NRF51_FICR_REG(0x0EC),
71 NRF51_FICR_BLE_1MBIT1
= NRF51_FICR_REG(0x0F0),
72 NRF51_FICR_BLE_1MBIT2
= NRF51_FICR_REG(0x0F4),
73 NRF51_FICR_BLE_1MBIT3
= NRF51_FICR_REG(0x0F8),
74 NRF51_FICR_BLE_1MBIT4
= NRF51_FICR_REG(0x0FC),
77 enum nrf51_uicr_registers
{
78 NRF51_UICR_BASE
= 0x10001000, /* User Information
79 * Configuration Regsters */
81 NRF51_UICR_SIZE
= 0x100,
83 #define NRF51_UICR_REG(offset) (NRF51_UICR_BASE + offset)
85 NRF51_UICR_CLENR0
= NRF51_UICR_REG(0x000),
86 NRF51_UICR_RBPCONF
= NRF51_UICR_REG(0x004),
87 NRF51_UICR_XTALFREQ
= NRF51_UICR_REG(0x008),
88 NRF51_UICR_FWID
= NRF51_UICR_REG(0x010),
91 enum nrf51_nvmc_registers
{
92 NRF51_NVMC_BASE
= 0x4001E000, /* Non-Volatile Memory
93 * Controller Regsters */
95 #define NRF51_NVMC_REG(offset) (NRF51_NVMC_BASE + offset)
97 NRF51_NVMC_READY
= NRF51_NVMC_REG(0x400),
98 NRF51_NVMC_CONFIG
= NRF51_NVMC_REG(0x504),
99 NRF51_NVMC_ERASEPAGE
= NRF51_NVMC_REG(0x508),
100 NRF51_NVMC_ERASEALL
= NRF51_NVMC_REG(0x50C),
101 NRF51_NVMC_ERASEUICR
= NRF51_NVMC_REG(0x514),
104 enum nrf51_nvmc_config_bits
{
105 NRF51_NVMC_CONFIG_REN
= 0x00,
106 NRF51_NVMC_CONFIG_WEN
= 0x01,
107 NRF51_NVMC_CONFIG_EEN
= 0x02,
112 uint32_t code_page_size
;
113 uint32_t code_memory_size
;
117 int (*write
) (struct flash_bank
*bank
,
118 struct nrf51_info
*chip
,
119 const uint8_t *buffer
, uint32_t offset
, uint32_t count
);
121 struct target
*target
;
124 struct nrf51_device_spec
{
127 const char *build_code
;
128 unsigned int flash_size_kb
;
131 /* The known devices table below is derived from the "nRF51 Series
132 * Compatibility Matrix" document, which can be found by searching for
133 * ATTN-51 on the Nordic Semi website:
135 * http://www.nordicsemi.com/eng/content/search?SearchText=ATTN-51
137 * Up to date with Matrix v2.0, plus some additional HWIDs.
139 * The additional HWIDs apply where the build code in the matrix is
140 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
141 * for x==0, x!=0 means different (unspecified) HWIDs.
143 static const struct nrf51_device_spec nrf51_known_devices_table
[] = {
144 /* nRF51822 Devices (IC rev 1). */
148 .build_code
= "CA/C0",
149 .flash_size_kb
= 256,
155 .flash_size_kb
= 128,
161 .flash_size_kb
= 128,
167 .flash_size_kb
= 256,
173 .flash_size_kb
= 256,
176 /* nRF51822 Devices (IC rev 2). */
181 .flash_size_kb
= 256,
187 .flash_size_kb
= 256,
193 .flash_size_kb
= 256,
199 .flash_size_kb
= 128,
205 .flash_size_kb
= 256,
211 .flash_size_kb
= 256,
217 .flash_size_kb
= 256,
220 /* nRF51822 Devices (IC rev 3). */
225 .flash_size_kb
= 256,
231 .flash_size_kb
= 128,
237 .flash_size_kb
= 256,
243 .flash_size_kb
= 128,
249 .flash_size_kb
= 256,
255 .flash_size_kb
= 256,
258 /* nRF51422 Devices (IC rev 1). */
263 .flash_size_kb
= 256,
269 .flash_size_kb
= 256,
275 .flash_size_kb
= 256,
278 /* nRF51422 Devices (IC rev 2). */
283 .flash_size_kb
= 256,
289 .flash_size_kb
= 256,
295 .flash_size_kb
= 128,
301 .flash_size_kb
= 256,
304 /* nRF51422 Devices (IC rev 3). */
309 .flash_size_kb
= 256,
315 .flash_size_kb
= 128,
321 .flash_size_kb
= 256,
327 .flash_size_kb
= 256,
333 .flash_size_kb
= 256,
339 .flash_size_kb
= 128,
345 .flash_size_kb
= 256,
351 .flash_size_kb
= 256,
355 no idea if variant and build code are correct */
360 .flash_size_kb
= 256,
363 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
364 with built-in jlink seem to use engineering samples not listed
365 in the nRF51 Series Compatibility Matrix V1.0. */
370 .flash_size_kb
= 256,
374 static int nrf51_bank_is_probed(struct flash_bank
*bank
)
376 struct nrf51_info
*chip
= bank
->driver_priv
;
378 assert(chip
!= NULL
);
380 return chip
->bank
[bank
->bank_number
].probed
;
382 static int nrf51_probe(struct flash_bank
*bank
);
384 static int nrf51_get_probed_chip_if_halted(struct flash_bank
*bank
, struct nrf51_info
**chip
)
386 if (bank
->target
->state
!= TARGET_HALTED
) {
387 LOG_ERROR("Target not halted");
388 return ERROR_TARGET_NOT_HALTED
;
391 *chip
= bank
->driver_priv
;
393 int probed
= nrf51_bank_is_probed(bank
);
397 return nrf51_probe(bank
);
402 static int nrf51_wait_for_nvmc(struct nrf51_info
*chip
)
409 res
= target_read_u32(chip
->target
, NRF51_NVMC_READY
, &ready
);
410 if (res
!= ERROR_OK
) {
411 LOG_ERROR("Couldn't read NVMC_READY register");
415 if (ready
== 0x00000001)
421 LOG_DEBUG("Timed out waiting for NVMC_READY");
422 return ERROR_FLASH_BUSY
;
425 static int nrf51_nvmc_erase_enable(struct nrf51_info
*chip
)
428 res
= target_write_u32(chip
->target
,
430 NRF51_NVMC_CONFIG_EEN
);
432 if (res
!= ERROR_OK
) {
433 LOG_ERROR("Failed to enable erase operation");
438 According to NVMC examples in Nordic SDK busy status must be
439 checked after writing to NVMC_CONFIG
441 res
= nrf51_wait_for_nvmc(chip
);
443 LOG_ERROR("Erase enable did not complete");
448 static int nrf51_nvmc_write_enable(struct nrf51_info
*chip
)
451 res
= target_write_u32(chip
->target
,
453 NRF51_NVMC_CONFIG_WEN
);
455 if (res
!= ERROR_OK
) {
456 LOG_ERROR("Failed to enable write operation");
461 According to NVMC examples in Nordic SDK busy status must be
462 checked after writing to NVMC_CONFIG
464 res
= nrf51_wait_for_nvmc(chip
);
466 LOG_ERROR("Write enable did not complete");
471 static int nrf51_nvmc_read_only(struct nrf51_info
*chip
)
474 res
= target_write_u32(chip
->target
,
476 NRF51_NVMC_CONFIG_REN
);
478 if (res
!= ERROR_OK
) {
479 LOG_ERROR("Failed to enable read-only operation");
483 According to NVMC examples in Nordic SDK busy status must be
484 checked after writing to NVMC_CONFIG
486 res
= nrf51_wait_for_nvmc(chip
);
488 LOG_ERROR("Read only enable did not complete");
493 static int nrf51_nvmc_generic_erase(struct nrf51_info
*chip
,
494 uint32_t erase_register
, uint32_t erase_value
)
498 res
= nrf51_nvmc_erase_enable(chip
);
502 res
= target_write_u32(chip
->target
,
508 res
= nrf51_wait_for_nvmc(chip
);
512 return nrf51_nvmc_read_only(chip
);
515 nrf51_nvmc_read_only(chip
);
517 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32
" val: 0x%08"PRIx32
,
518 erase_register
, erase_value
);
522 static int nrf51_protect_check(struct flash_bank
*bank
)
527 /* UICR cannot be write protected so just return early */
528 if (bank
->base
== NRF51_UICR_BASE
)
531 struct nrf51_info
*chip
= bank
->driver_priv
;
533 assert(chip
!= NULL
);
535 res
= target_read_u32(chip
->target
, NRF51_FICR_CLENR0
,
537 if (res
!= ERROR_OK
) {
538 LOG_ERROR("Couldn't read code region 0 size[FICR]");
542 if (clenr0
== 0xFFFFFFFF) {
543 res
= target_read_u32(chip
->target
, NRF51_UICR_CLENR0
,
545 if (res
!= ERROR_OK
) {
546 LOG_ERROR("Couldn't read code region 0 size[UICR]");
551 for (int i
= 0; i
< bank
->num_sectors
; i
++)
552 bank
->sectors
[i
].is_protected
=
553 clenr0
!= 0xFFFFFFFF && bank
->sectors
[i
].offset
< clenr0
;
558 static int nrf51_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
561 uint32_t clenr0
, ppfc
;
562 struct nrf51_info
*chip
;
564 /* UICR cannot be write protected so just bail out early */
565 if (bank
->base
== NRF51_UICR_BASE
)
568 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
573 LOG_ERROR("Code region 0 must start at the begining of the bank");
577 res
= target_read_u32(chip
->target
, NRF51_FICR_PPFC
,
579 if (res
!= ERROR_OK
) {
580 LOG_ERROR("Couldn't read PPFC register");
584 if ((ppfc
& 0xFF) == 0x00) {
585 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
589 res
= target_read_u32(chip
->target
, NRF51_UICR_CLENR0
,
591 if (res
!= ERROR_OK
) {
592 LOG_ERROR("Couldn't read code region 0 size[UICR]");
596 if (clenr0
== 0xFFFFFFFF) {
597 res
= target_write_u32(chip
->target
, NRF51_UICR_CLENR0
,
599 if (res
!= ERROR_OK
) {
600 LOG_ERROR("Couldn't write code region 0 size[UICR]");
605 LOG_ERROR("You need to perform chip erase before changing the protection settings");
608 nrf51_protect_check(bank
);
613 static int nrf51_probe(struct flash_bank
*bank
)
617 struct nrf51_info
*chip
= bank
->driver_priv
;
619 res
= target_read_u32(chip
->target
, NRF51_FICR_CONFIGID
, &hwid
);
620 if (res
!= ERROR_OK
) {
621 LOG_ERROR("Couldn't read CONFIGID register");
625 hwid
&= 0xFFFF; /* HWID is stored in the lower two
626 * bytes of the CONFIGID register */
628 const struct nrf51_device_spec
*spec
= NULL
;
629 for (size_t i
= 0; i
< ARRAY_SIZE(nrf51_known_devices_table
); i
++)
630 if (hwid
== nrf51_known_devices_table
[i
].hwid
) {
631 spec
= &nrf51_known_devices_table
[i
];
635 if (!chip
->bank
[0].probed
&& !chip
->bank
[1].probed
) {
637 LOG_INFO("nRF51822-%s(build code: %s) %ukB Flash",
638 spec
->variant
, spec
->build_code
, spec
->flash_size_kb
);
640 LOG_WARNING("Unknown device (HWID 0x%08" PRIx32
")", hwid
);
644 if (bank
->base
== NRF51_FLASH_BASE
) {
645 res
= target_read_u32(chip
->target
, NRF51_FICR_CODEPAGESIZE
,
646 &chip
->code_page_size
);
647 if (res
!= ERROR_OK
) {
648 LOG_ERROR("Couldn't read code page size");
652 res
= target_read_u32(chip
->target
, NRF51_FICR_CODESIZE
,
653 &chip
->code_memory_size
);
654 if (res
!= ERROR_OK
) {
655 LOG_ERROR("Couldn't read code memory size");
659 if (spec
&& chip
->code_memory_size
!= spec
->flash_size_kb
) {
660 LOG_ERROR("Chip's reported Flash capacity does not match expected one");
664 bank
->size
= chip
->code_memory_size
* 1024;
665 bank
->num_sectors
= bank
->size
/ chip
->code_page_size
;
666 bank
->sectors
= calloc(bank
->num_sectors
,
667 sizeof((bank
->sectors
)[0]));
669 return ERROR_FLASH_BANK_NOT_PROBED
;
671 /* Fill out the sector information: all NRF51 sectors are the same size and
672 * there is always a fixed number of them. */
673 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
674 bank
->sectors
[i
].size
= chip
->code_page_size
;
675 bank
->sectors
[i
].offset
= i
* chip
->code_page_size
;
677 /* mark as unknown */
678 bank
->sectors
[i
].is_erased
= -1;
679 bank
->sectors
[i
].is_protected
= -1;
682 nrf51_protect_check(bank
);
684 chip
->bank
[0].probed
= true;
686 bank
->size
= NRF51_UICR_SIZE
;
687 bank
->num_sectors
= 1;
688 bank
->sectors
= calloc(bank
->num_sectors
,
689 sizeof((bank
->sectors
)[0]));
691 return ERROR_FLASH_BANK_NOT_PROBED
;
693 bank
->sectors
[0].size
= bank
->size
;
694 bank
->sectors
[0].offset
= 0;
696 /* mark as unknown */
697 bank
->sectors
[0].is_erased
= 0;
698 bank
->sectors
[0].is_protected
= 0;
700 chip
->bank
[1].probed
= true;
706 static int nrf51_auto_probe(struct flash_bank
*bank
)
708 int probed
= nrf51_bank_is_probed(bank
);
715 return nrf51_probe(bank
);
718 static struct flash_sector
*nrf51_find_sector_by_address(struct flash_bank
*bank
, uint32_t address
)
720 struct nrf51_info
*chip
= bank
->driver_priv
;
722 for (int i
= 0; i
< bank
->num_sectors
; i
++)
723 if (bank
->sectors
[i
].offset
<= address
&&
724 address
< (bank
->sectors
[i
].offset
+ chip
->code_page_size
))
725 return &bank
->sectors
[i
];
729 static int nrf51_erase_all(struct nrf51_info
*chip
)
731 LOG_DEBUG("Erasing all non-volatile memory");
732 return nrf51_nvmc_generic_erase(chip
,
737 static int nrf51_erase_page(struct flash_bank
*bank
,
738 struct nrf51_info
*chip
,
739 struct flash_sector
*sector
)
743 LOG_DEBUG("Erasing page at 0x%"PRIx32
, sector
->offset
);
744 if (sector
->is_protected
) {
745 LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32
, sector
->offset
);
749 if (bank
->base
== NRF51_UICR_BASE
) {
751 res
= target_read_u32(chip
->target
, NRF51_FICR_PPFC
,
753 if (res
!= ERROR_OK
) {
754 LOG_ERROR("Couldn't read PPFC register");
758 if ((ppfc
& 0xFF) == 0xFF) {
759 /* We can't erase the UICR. Double-check to
760 see if it's already erased before complaining. */
761 default_flash_blank_check(bank
);
762 if (sector
->is_erased
== 1)
765 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
769 res
= nrf51_nvmc_generic_erase(chip
,
770 NRF51_NVMC_ERASEUICR
,
775 res
= nrf51_nvmc_generic_erase(chip
,
776 NRF51_NVMC_ERASEPAGE
,
781 sector
->is_erased
= 1;
786 static const uint8_t nrf51_flash_write_code
[] = {
787 /* See contrib/loaders/flash/cortex-m0.S */
789 0x0d, 0x68, /* ldr r5, [r1, #0] */
790 0x00, 0x2d, /* cmp r5, #0 */
791 0x0b, 0xd0, /* beq.n 1e <exit> */
792 0x4c, 0x68, /* ldr r4, [r1, #4] */
793 0xac, 0x42, /* cmp r4, r5 */
794 0xf9, 0xd0, /* beq.n 0 <wait_fifo> */
795 0x20, 0xcc, /* ldmia r4!, {r5} */
796 0x20, 0xc3, /* stmia r3!, {r5} */
797 0x94, 0x42, /* cmp r4, r2 */
798 0x01, 0xd3, /* bcc.n 18 <no_wrap> */
799 0x0c, 0x46, /* mov r4, r1 */
800 0x08, 0x34, /* adds r4, #8 */
802 0x4c, 0x60, /* str r4, [r1, #4] */
803 0x04, 0x38, /* subs r0, #4 */
804 0xf0, 0xd1, /* bne.n 0 <wait_fifo> */
806 0x00, 0xbe /* bkpt 0x0000 */
810 /* Start a low level flash write for the specified region */
811 static int nrf51_ll_flash_write(struct nrf51_info
*chip
, uint32_t offset
, const uint8_t *buffer
, uint32_t bytes
)
813 struct target
*target
= chip
->target
;
814 uint32_t buffer_size
= 8192;
815 struct working_area
*write_algorithm
;
816 struct working_area
*source
;
817 uint32_t address
= NRF51_FLASH_BASE
+ offset
;
818 struct reg_param reg_params
[4];
819 struct armv7m_algorithm armv7m_info
;
820 int retval
= ERROR_OK
;
823 LOG_DEBUG("Writing buffer to flash offset=0x%"PRIx32
" bytes=0x%"PRIx32
, offset
, bytes
);
824 assert(bytes
% 4 == 0);
826 /* allocate working area with flash programming code */
827 if (target_alloc_working_area(target
, sizeof(nrf51_flash_write_code
),
828 &write_algorithm
) != ERROR_OK
) {
829 LOG_WARNING("no working area available, falling back to slow memory writes");
831 for (; bytes
> 0; bytes
-= 4) {
832 retval
= target_write_memory(chip
->target
, offset
, 4, 1, buffer
);
833 if (retval
!= ERROR_OK
)
836 retval
= nrf51_wait_for_nvmc(chip
);
837 if (retval
!= ERROR_OK
)
847 LOG_WARNING("using fast async flash loader. This is currently supported");
848 LOG_WARNING("only with ST-Link and CMSIS-DAP. If you have issues, add");
849 LOG_WARNING("\"set WORKAREASIZE 0\" before sourcing nrf51.cfg to disable it");
851 retval
= target_write_buffer(target
, write_algorithm
->address
,
852 sizeof(nrf51_flash_write_code
),
853 nrf51_flash_write_code
);
854 if (retval
!= ERROR_OK
)
858 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
) {
860 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
861 if (buffer_size
<= 256) {
862 /* free working area, write algorithm already allocated */
863 target_free_working_area(target
, write_algorithm
);
865 LOG_WARNING("No large enough working area available, can't do block memory writes");
866 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
870 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
871 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
873 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* byte count */
874 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer start */
875 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer end */
876 init_reg_param(®_params
[3], "r3", 32, PARAM_IN_OUT
); /* target address */
878 buf_set_u32(reg_params
[0].value
, 0, 32, bytes
);
879 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
880 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
+ source
->size
);
881 buf_set_u32(reg_params
[3].value
, 0, 32, address
);
883 retval
= target_run_flash_async_algorithm(target
, buffer
, bytes
/4, 4,
886 source
->address
, source
->size
,
887 write_algorithm
->address
, 0,
890 target_free_working_area(target
, source
);
891 target_free_working_area(target
, write_algorithm
);
893 destroy_reg_param(®_params
[0]);
894 destroy_reg_param(®_params
[1]);
895 destroy_reg_param(®_params
[2]);
896 destroy_reg_param(®_params
[3]);
901 /* Check and erase flash sectors in specified range then start a low level page write.
902 start/end must be sector aligned.
904 static int nrf51_write_pages(struct flash_bank
*bank
, uint32_t start
, uint32_t end
, const uint8_t *buffer
)
906 int res
= ERROR_FAIL
;
907 struct nrf51_info
*chip
= bank
->driver_priv
;
908 struct flash_sector
*sector
;
911 assert(start
% chip
->code_page_size
== 0);
912 assert(end
% chip
->code_page_size
== 0);
914 /* Erase all sectors */
915 for (offset
= start
; offset
< end
; offset
+= chip
->code_page_size
) {
916 sector
= nrf51_find_sector_by_address(bank
, offset
);
918 LOG_ERROR("Invalid sector @ 0x%08"PRIx32
, offset
);
919 return ERROR_FLASH_SECTOR_INVALID
;
922 if (sector
->is_protected
) {
923 LOG_ERROR("Can't erase protected sector @ 0x%08"PRIx32
, offset
);
927 if (sector
->is_erased
!= 1) { /* 1 = erased, 0= not erased, -1 = unknown */
928 res
= nrf51_erase_page(bank
, chip
, sector
);
929 if (res
!= ERROR_OK
) {
930 LOG_ERROR("Failed to erase sector @ 0x%08"PRIx32
, sector
->offset
);
934 sector
->is_erased
= 0;
937 res
= nrf51_nvmc_write_enable(chip
);
941 res
= nrf51_ll_flash_write(chip
, start
, buffer
, (end
- start
));
945 return nrf51_nvmc_read_only(chip
);
948 nrf51_nvmc_read_only(chip
);
950 LOG_ERROR("Failed to write to nrf51 flash");
954 static int nrf51_erase(struct flash_bank
*bank
, int first
, int last
)
957 struct nrf51_info
*chip
;
959 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
963 /* For each sector to be erased */
964 for (int s
= first
; s
<= last
&& res
== ERROR_OK
; s
++)
965 res
= nrf51_erase_page(bank
, chip
, &bank
->sectors
[s
]);
970 static int nrf51_code_flash_write(struct flash_bank
*bank
,
971 struct nrf51_info
*chip
,
972 const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
976 /* Need to perform reads to fill any gaps we need to preserve in the first page,
977 before the start of buffer, or in the last page, after the end of buffer */
978 uint32_t first_page
= offset
/chip
->code_page_size
;
979 uint32_t last_page
= DIV_ROUND_UP(offset
+count
, chip
->code_page_size
);
981 uint32_t first_page_offset
= first_page
* chip
->code_page_size
;
982 uint32_t last_page_offset
= last_page
* chip
->code_page_size
;
984 LOG_DEBUG("Padding write from 0x%08"PRIx32
"-0x%08"PRIx32
" as 0x%08"PRIx32
"-0x%08"PRIx32
,
985 offset
, offset
+count
, first_page_offset
, last_page_offset
);
987 uint32_t page_cnt
= last_page
- first_page
;
988 uint8_t buffer_to_flash
[page_cnt
*chip
->code_page_size
];
990 /* Fill in any space between start of first page and start of buffer */
991 uint32_t pre
= offset
- first_page_offset
;
993 res
= target_read_memory(bank
->target
,
1002 /* Fill in main contents of buffer */
1003 memcpy(buffer_to_flash
+pre
, buffer
, count
);
1005 /* Fill in any space between end of buffer and end of last page */
1006 uint32_t post
= last_page_offset
- (offset
+count
);
1008 /* Retrieve the full row contents from Flash */
1009 res
= target_read_memory(bank
->target
,
1013 buffer_to_flash
+pre
+count
);
1014 if (res
!= ERROR_OK
)
1018 return nrf51_write_pages(bank
, first_page_offset
, last_page_offset
, buffer_to_flash
);
1021 static int nrf51_uicr_flash_write(struct flash_bank
*bank
,
1022 struct nrf51_info
*chip
,
1023 const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
1026 uint8_t uicr
[NRF51_UICR_SIZE
];
1027 struct flash_sector
*sector
= &bank
->sectors
[0];
1029 if ((offset
+ count
) > NRF51_UICR_SIZE
)
1032 res
= target_read_memory(bank
->target
,
1038 if (res
!= ERROR_OK
)
1041 if (sector
->is_erased
!= 1) {
1042 res
= nrf51_erase_page(bank
, chip
, sector
);
1043 if (res
!= ERROR_OK
)
1047 res
= nrf51_nvmc_write_enable(chip
);
1048 if (res
!= ERROR_OK
)
1051 memcpy(&uicr
[offset
], buffer
, count
);
1053 res
= nrf51_ll_flash_write(chip
, NRF51_UICR_BASE
, uicr
, NRF51_UICR_SIZE
);
1054 if (res
!= ERROR_OK
) {
1055 nrf51_nvmc_read_only(chip
);
1059 return nrf51_nvmc_read_only(chip
);
1063 static int nrf51_write(struct flash_bank
*bank
, const uint8_t *buffer
,
1064 uint32_t offset
, uint32_t count
)
1067 struct nrf51_info
*chip
;
1069 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
1070 if (res
!= ERROR_OK
)
1073 return chip
->bank
[bank
->bank_number
].write(bank
, chip
, buffer
, offset
, count
);
1077 FLASH_BANK_COMMAND_HANDLER(nrf51_flash_bank_command
)
1079 static struct nrf51_info
*chip
;
1081 switch (bank
->base
) {
1082 case NRF51_FLASH_BASE
:
1083 bank
->bank_number
= 0;
1085 case NRF51_UICR_BASE
:
1086 bank
->bank_number
= 1;
1089 LOG_ERROR("Invalid bank address 0x%08" PRIx32
, bank
->base
);
1094 /* Create a new chip */
1095 chip
= calloc(1, sizeof(*chip
));
1099 chip
->target
= bank
->target
;
1102 switch (bank
->base
) {
1103 case NRF51_FLASH_BASE
:
1104 chip
->bank
[bank
->bank_number
].write
= nrf51_code_flash_write
;
1106 case NRF51_UICR_BASE
:
1107 chip
->bank
[bank
->bank_number
].write
= nrf51_uicr_flash_write
;
1111 chip
->bank
[bank
->bank_number
].probed
= false;
1112 bank
->driver_priv
= chip
;
1117 COMMAND_HANDLER(nrf51_handle_mass_erase_command
)
1120 struct flash_bank
*bank
= NULL
;
1121 struct target
*target
= get_current_target(CMD_CTX
);
1123 res
= get_flash_bank_by_addr(target
, NRF51_FLASH_BASE
, true, &bank
);
1124 if (res
!= ERROR_OK
)
1127 assert(bank
!= NULL
);
1129 struct nrf51_info
*chip
;
1131 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
1132 if (res
!= ERROR_OK
)
1137 res
= target_read_u32(target
, NRF51_FICR_PPFC
,
1139 if (res
!= ERROR_OK
) {
1140 LOG_ERROR("Couldn't read PPFC register");
1144 if ((ppfc
& 0xFF) == 0x00) {
1145 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1146 "mass erase command won't work.");
1150 res
= nrf51_erase_all(chip
);
1151 if (res
!= ERROR_OK
) {
1152 LOG_ERROR("Failed to erase the chip");
1153 nrf51_protect_check(bank
);
1157 for (int i
= 0; i
< bank
->num_sectors
; i
++)
1158 bank
->sectors
[i
].is_erased
= 1;
1160 res
= nrf51_protect_check(bank
);
1161 if (res
!= ERROR_OK
) {
1162 LOG_ERROR("Failed to check chip's write protection");
1166 res
= get_flash_bank_by_addr(target
, NRF51_UICR_BASE
, true, &bank
);
1167 if (res
!= ERROR_OK
)
1170 bank
->sectors
[0].is_erased
= 1;
1175 static int nrf51_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1179 struct nrf51_info
*chip
;
1181 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
1182 if (res
!= ERROR_OK
)
1186 const uint32_t address
;
1189 { .address
= NRF51_FICR_CODEPAGESIZE
},
1190 { .address
= NRF51_FICR_CODESIZE
},
1191 { .address
= NRF51_FICR_CLENR0
},
1192 { .address
= NRF51_FICR_PPFC
},
1193 { .address
= NRF51_FICR_NUMRAMBLOCK
},
1194 { .address
= NRF51_FICR_SIZERAMBLOCK0
},
1195 { .address
= NRF51_FICR_SIZERAMBLOCK1
},
1196 { .address
= NRF51_FICR_SIZERAMBLOCK2
},
1197 { .address
= NRF51_FICR_SIZERAMBLOCK3
},
1198 { .address
= NRF51_FICR_CONFIGID
},
1199 { .address
= NRF51_FICR_DEVICEID0
},
1200 { .address
= NRF51_FICR_DEVICEID1
},
1201 { .address
= NRF51_FICR_ER0
},
1202 { .address
= NRF51_FICR_ER1
},
1203 { .address
= NRF51_FICR_ER2
},
1204 { .address
= NRF51_FICR_ER3
},
1205 { .address
= NRF51_FICR_IR0
},
1206 { .address
= NRF51_FICR_IR1
},
1207 { .address
= NRF51_FICR_IR2
},
1208 { .address
= NRF51_FICR_IR3
},
1209 { .address
= NRF51_FICR_DEVICEADDRTYPE
},
1210 { .address
= NRF51_FICR_DEVICEADDR0
},
1211 { .address
= NRF51_FICR_DEVICEADDR1
},
1212 { .address
= NRF51_FICR_OVERRIDEN
},
1213 { .address
= NRF51_FICR_NRF_1MBIT0
},
1214 { .address
= NRF51_FICR_NRF_1MBIT1
},
1215 { .address
= NRF51_FICR_NRF_1MBIT2
},
1216 { .address
= NRF51_FICR_NRF_1MBIT3
},
1217 { .address
= NRF51_FICR_NRF_1MBIT4
},
1218 { .address
= NRF51_FICR_BLE_1MBIT0
},
1219 { .address
= NRF51_FICR_BLE_1MBIT1
},
1220 { .address
= NRF51_FICR_BLE_1MBIT2
},
1221 { .address
= NRF51_FICR_BLE_1MBIT3
},
1222 { .address
= NRF51_FICR_BLE_1MBIT4
},
1224 { .address
= NRF51_UICR_CLENR0
, },
1225 { .address
= NRF51_UICR_RBPCONF
},
1226 { .address
= NRF51_UICR_XTALFREQ
},
1227 { .address
= NRF51_UICR_FWID
},
1230 for (size_t i
= 0; i
< ARRAY_SIZE(ficr
); i
++) {
1231 res
= target_read_u32(chip
->target
, ficr
[i
].address
,
1233 if (res
!= ERROR_OK
) {
1234 LOG_ERROR("Couldn't read %" PRIx32
, ficr
[i
].address
);
1239 for (size_t i
= 0; i
< ARRAY_SIZE(uicr
); i
++) {
1240 res
= target_read_u32(chip
->target
, uicr
[i
].address
,
1242 if (res
!= ERROR_OK
) {
1243 LOG_ERROR("Couldn't read %" PRIx32
, uicr
[i
].address
);
1248 snprintf(buf
, buf_size
,
1249 "\n[factory information control block]\n\n"
1250 "code page size: %"PRIu32
"B\n"
1251 "code memory size: %"PRIu32
"kB\n"
1252 "code region 0 size: %"PRIu32
"kB\n"
1253 "pre-programmed code: %s\n"
1254 "number of ram blocks: %"PRIu32
"\n"
1255 "ram block 0 size: %"PRIu32
"B\n"
1256 "ram block 1 size: %"PRIu32
"B\n"
1257 "ram block 2 size: %"PRIu32
"B\n"
1258 "ram block 3 size: %"PRIu32
"B\n"
1259 "config id: %" PRIx32
"\n"
1260 "device id: 0x%"PRIx32
"%08"PRIx32
"\n"
1261 "encryption root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1262 "identity root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1263 "device address type: 0x%"PRIx32
"\n"
1264 "device address: 0x%"PRIx32
"%08"PRIx32
"\n"
1265 "override enable: %"PRIx32
"\n"
1266 "NRF_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1267 "BLE_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1268 "\n[user information control block]\n\n"
1269 "code region 0 size: %"PRIu32
"kB\n"
1270 "read back protection configuration: %"PRIx32
"\n"
1271 "reset value for XTALFREQ: %"PRIx32
"\n"
1272 "firmware id: 0x%04"PRIx32
,
1275 (ficr
[2].value
== 0xFFFFFFFF) ? 0 : ficr
[2].value
/ 1024,
1276 ((ficr
[3].value
& 0xFF) == 0x00) ? "present" : "not present",
1279 (ficr
[6].value
== 0xFFFFFFFF) ? 0 : ficr
[6].value
,
1280 (ficr
[7].value
== 0xFFFFFFFF) ? 0 : ficr
[7].value
,
1281 (ficr
[8].value
== 0xFFFFFFFF) ? 0 : ficr
[8].value
,
1283 ficr
[10].value
, ficr
[11].value
,
1284 ficr
[12].value
, ficr
[13].value
, ficr
[14].value
, ficr
[15].value
,
1285 ficr
[16].value
, ficr
[17].value
, ficr
[18].value
, ficr
[19].value
,
1287 ficr
[21].value
, ficr
[22].value
,
1289 ficr
[24].value
, ficr
[25].value
, ficr
[26].value
, ficr
[27].value
, ficr
[28].value
,
1290 ficr
[29].value
, ficr
[30].value
, ficr
[31].value
, ficr
[32].value
, ficr
[33].value
,
1291 (uicr
[0].value
== 0xFFFFFFFF) ? 0 : uicr
[0].value
/ 1024,
1292 uicr
[1].value
& 0xFFFF,
1293 uicr
[2].value
& 0xFF,
1294 uicr
[3].value
& 0xFFFF);
1299 static const struct command_registration nrf51_exec_command_handlers
[] = {
1301 .name
= "mass_erase",
1302 .handler
= nrf51_handle_mass_erase_command
,
1303 .mode
= COMMAND_EXEC
,
1304 .help
= "Erase all flash contents of the chip.",
1306 COMMAND_REGISTRATION_DONE
1309 static const struct command_registration nrf51_command_handlers
[] = {
1312 .mode
= COMMAND_ANY
,
1313 .help
= "nrf51 flash command group",
1315 .chain
= nrf51_exec_command_handlers
,
1317 COMMAND_REGISTRATION_DONE
1320 struct flash_driver nrf51_flash
= {
1322 .commands
= nrf51_command_handlers
,
1323 .flash_bank_command
= nrf51_flash_bank_command
,
1325 .erase
= nrf51_erase
,
1326 .protect
= nrf51_protect
,
1327 .write
= nrf51_write
,
1328 .read
= default_flash_read
,
1329 .probe
= nrf51_probe
,
1330 .auto_probe
= nrf51_auto_probe
,
1331 .erase_check
= default_flash_blank_check
,
1332 .protect_check
= nrf51_protect_check
,
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