Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
flash/nor: Use proper data types in driver API
[openocd.git] / src / flash / nor / nrf5.c
1 /***************************************************************************
2 * Copyright (C) 2013 Synapse Product Development *
3 * Andrey Smirnov <andrew.smironv@gmail.com> *
4 * Angus Gratton <gus@projectgus.com> *
5 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
19 ***************************************************************************/
20
21 #ifdef HAVE_CONFIG_H
22 #include "config.h"
23 #endif
24
25 #include "imp.h"
26 #include <target/algorithm.h>
27 #include <target/armv7m.h>
28 #include <helper/types.h>
29 #include <helper/time_support.h>
30
31 /* Both those values are constant across the current spectrum ofr nRF5 devices */
32 #define WATCHDOG_REFRESH_REGISTER 0x40010600
33 #define WATCHDOG_REFRESH_VALUE 0x6e524635
34
35 enum {
36 NRF5_FLASH_BASE = 0x00000000,
37 };
38
39 enum nrf5_ficr_registers {
40 NRF5_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
41
42 #define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
43
44 NRF5_FICR_CODEPAGESIZE = NRF5_FICR_REG(0x010),
45 NRF5_FICR_CODESIZE = NRF5_FICR_REG(0x014),
46
47 NRF51_FICR_CLENR0 = NRF5_FICR_REG(0x028),
48 NRF51_FICR_PPFC = NRF5_FICR_REG(0x02C),
49 NRF51_FICR_NUMRAMBLOCK = NRF5_FICR_REG(0x034),
50 NRF51_FICR_SIZERAMBLOCK0 = NRF5_FICR_REG(0x038),
51 NRF51_FICR_SIZERAMBLOCK1 = NRF5_FICR_REG(0x03C),
52 NRF51_FICR_SIZERAMBLOCK2 = NRF5_FICR_REG(0x040),
53 NRF51_FICR_SIZERAMBLOCK3 = NRF5_FICR_REG(0x044),
54
55 NRF5_FICR_CONFIGID = NRF5_FICR_REG(0x05C),
56 NRF5_FICR_DEVICEID0 = NRF5_FICR_REG(0x060),
57 NRF5_FICR_DEVICEID1 = NRF5_FICR_REG(0x064),
58 NRF5_FICR_ER0 = NRF5_FICR_REG(0x080),
59 NRF5_FICR_ER1 = NRF5_FICR_REG(0x084),
60 NRF5_FICR_ER2 = NRF5_FICR_REG(0x088),
61 NRF5_FICR_ER3 = NRF5_FICR_REG(0x08C),
62 NRF5_FICR_IR0 = NRF5_FICR_REG(0x090),
63 NRF5_FICR_IR1 = NRF5_FICR_REG(0x094),
64 NRF5_FICR_IR2 = NRF5_FICR_REG(0x098),
65 NRF5_FICR_IR3 = NRF5_FICR_REG(0x09C),
66 NRF5_FICR_DEVICEADDRTYPE = NRF5_FICR_REG(0x0A0),
67 NRF5_FICR_DEVICEADDR0 = NRF5_FICR_REG(0x0A4),
68 NRF5_FICR_DEVICEADDR1 = NRF5_FICR_REG(0x0A8),
69
70 NRF51_FICR_OVERRIDEN = NRF5_FICR_REG(0x0AC),
71 NRF51_FICR_NRF_1MBIT0 = NRF5_FICR_REG(0x0B0),
72 NRF51_FICR_NRF_1MBIT1 = NRF5_FICR_REG(0x0B4),
73 NRF51_FICR_NRF_1MBIT2 = NRF5_FICR_REG(0x0B8),
74 NRF51_FICR_NRF_1MBIT3 = NRF5_FICR_REG(0x0BC),
75 NRF51_FICR_NRF_1MBIT4 = NRF5_FICR_REG(0x0C0),
76 NRF51_FICR_BLE_1MBIT0 = NRF5_FICR_REG(0x0EC),
77 NRF51_FICR_BLE_1MBIT1 = NRF5_FICR_REG(0x0F0),
78 NRF51_FICR_BLE_1MBIT2 = NRF5_FICR_REG(0x0F4),
79 NRF51_FICR_BLE_1MBIT3 = NRF5_FICR_REG(0x0F8),
80 NRF51_FICR_BLE_1MBIT4 = NRF5_FICR_REG(0x0FC),
81
82 /* Following registers are available on nRF52 and on nRF51 since rev 3 */
83 NRF5_FICR_INFO_PART = NRF5_FICR_REG(0x100),
84 NRF5_FICR_INFO_VARIANT = NRF5_FICR_REG(0x104),
85 NRF5_FICR_INFO_PACKAGE = NRF5_FICR_REG(0x108),
86 NRF5_FICR_INFO_RAM = NRF5_FICR_REG(0x10C),
87 NRF5_FICR_INFO_FLASH = NRF5_FICR_REG(0x110),
88 };
89
90 enum nrf5_uicr_registers {
91 NRF5_UICR_BASE = 0x10001000, /* User Information
92 * Configuration Regsters */
93
94 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
95
96 NRF51_UICR_CLENR0 = NRF5_UICR_REG(0x000),
97 NRF51_UICR_RBPCONF = NRF5_UICR_REG(0x004),
98 NRF51_UICR_XTALFREQ = NRF5_UICR_REG(0x008),
99 NRF51_UICR_FWID = NRF5_UICR_REG(0x010),
100 };
101
102 enum nrf5_nvmc_registers {
103 NRF5_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
104 * Controller Registers */
105
106 #define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
107
108 NRF5_NVMC_READY = NRF5_NVMC_REG(0x400),
109 NRF5_NVMC_CONFIG = NRF5_NVMC_REG(0x504),
110 NRF5_NVMC_ERASEPAGE = NRF5_NVMC_REG(0x508),
111 NRF5_NVMC_ERASEALL = NRF5_NVMC_REG(0x50C),
112 NRF5_NVMC_ERASEUICR = NRF5_NVMC_REG(0x514),
113
114 NRF5_BPROT_BASE = 0x40000000,
115 };
116
117 enum nrf5_nvmc_config_bits {
118 NRF5_NVMC_CONFIG_REN = 0x00,
119 NRF5_NVMC_CONFIG_WEN = 0x01,
120 NRF5_NVMC_CONFIG_EEN = 0x02,
121
122 };
123
124 struct nrf52_ficr_info {
125 uint32_t part;
126 uint32_t variant;
127 uint32_t package;
128 uint32_t ram;
129 uint32_t flash;
130 };
131
132 enum nrf5_features {
133 NRF5_FEATURE_SERIES_51 = 1 << 0,
134 NRF5_FEATURE_SERIES_52 = 1 << 1,
135 NRF5_FEATURE_BPROT = 1 << 2,
136 NRF5_FEATURE_ACL_PROT = 1 << 3,
137 };
138
139 struct nrf5_device_spec {
140 uint16_t hwid;
141 const char *part;
142 const char *variant;
143 const char *build_code;
144 unsigned int flash_size_kb;
145 enum nrf5_features features;
146 };
147
148 struct nrf5_info {
149 uint32_t refcount;
150
151 struct nrf5_bank {
152 struct nrf5_info *chip;
153 bool probed;
154 } bank[2];
155 struct target *target;
156
157 /* chip identification stored in nrf5_probe() for use in nrf5_info() */
158 bool ficr_info_valid;
159 struct nrf52_ficr_info ficr_info;
160 const struct nrf5_device_spec *spec;
161 uint32_t hwid;
162 enum nrf5_features features;
163 unsigned int flash_size_kb;
164 unsigned int ram_size_kb;
165 };
166
167 #define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize) \
168 { \
169 .hwid = (id), \
170 .part = pt, \
171 .variant = var, \
172 .build_code = bcode, \
173 .flash_size_kb = (fsize), \
174 .features = NRF5_FEATURE_SERIES_51, \
175 }
176
177 #define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize, features) \
178 { \
179 .hwid = (id), \
180 .part = pt, \
181 .variant = var, \
182 .build_code = bcode, \
183 .flash_size_kb = (fsize), \
184 .features = features, \
185 }
186
187 /* The known devices table below is derived from the "nRF5x series
188 * compatibility matrix" documents, which can be found in the "DocLib" of
189 * nordic:
190 *
191 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51422_ic_revision_overview
192 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51822_ic_revision_overview
193 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51824_ic_revision_overview
194 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52810/latest/COMP/nrf52810/nRF52810_ic_revision_overview
195 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52832/latest/COMP/nrf52832/ic_revision_overview
196 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52840/latest/COMP/nrf52840/nRF52840_ic_revision_overview
197 *
198 * Up to date with Matrix v2.0, plus some additional HWIDs.
199 *
200 * The additional HWIDs apply where the build code in the matrix is
201 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
202 * for x==0, x!=0 means different (unspecified) HWIDs.
203 */
204 static const struct nrf5_device_spec nrf5_known_devices_table[] = {
205 /* nRF51822 Devices (IC rev 1). */
206 NRF51_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
207 NRF51_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
208 NRF51_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
209 NRF51_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
210 NRF51_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
211
212 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
213 with built-in jlink seem to use engineering samples not listed
214 in the nRF51 Series Compatibility Matrix V1.0. */
215 NRF51_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
216
217 /* nRF51822 Devices (IC rev 2). */
218 NRF51_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
219 NRF51_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
220 NRF51_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
221 NRF51_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
222 NRF51_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
223 NRF51_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
224 NRF51_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
225 NRF51_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
226 NRF51_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
227
228 /* nRF51822 Devices (IC rev 3). */
229 NRF51_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
230 NRF51_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
231 NRF51_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
232 NRF51_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
233 NRF51_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
234 NRF51_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
235 NRF51_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
236 NRF51_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
237 NRF51_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
238
239 /* nRF51422 Devices (IC rev 1). */
240 NRF51_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
241 NRF51_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
242 NRF51_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
243
244 /* nRF51422 Devices (IC rev 2). */
245 NRF51_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
246 NRF51_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
247 NRF51_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
248 NRF51_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
249
250 /* nRF51422 Devices (IC rev 3). */
251 NRF51_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
252 NRF51_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
253 NRF51_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
254 NRF51_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
255 NRF51_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
256 NRF51_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
257 NRF51_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
258
259 /* The driver fully autodects nRF52 series devices by FICR INFO,
260 * no need for nRF52xxx HWIDs in this table */
261 #if 0
262 /* nRF52810 Devices */
263 NRF5_DEVICE_DEF(0x0142, "52810", "QFAA", "B0", 192, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
264 NRF5_DEVICE_DEF(0x0143, "52810", "QCAA", "C0", 192, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
265
266 /* nRF52832 Devices */
267 NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
268 NRF5_DEVICE_DEF(0x0139, "52832", "QFAA", "E0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
269 NRF5_DEVICE_DEF(0x00E3, "52832", "CIAA", "B0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
270
271 /* nRF52840 Devices */
272 NRF5_DEVICE_DEF(0x0150, "52840", "QIAA", "C0", 1024, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_ACL_PROT),
273 #endif
274 };
275
276 struct nrf5_device_package {
277 uint32_t package;
278 const char *code;
279 };
280
281 /* Newer devices have FICR INFO.PACKAGE.
282 * This table converts its value to two character code */
283 static const struct nrf5_device_package nrf5_packages_table[] = {
284 { 0x2000, "QF" },
285 { 0x2001, "CH" },
286 { 0x2002, "CI" },
287 { 0x2005, "CK" },
288 };
289
290 const struct flash_driver nrf5_flash, nrf51_flash;
291
292 static int nrf5_bank_is_probed(struct flash_bank *bank)
293 {
294 struct nrf5_bank *nbank = bank->driver_priv;
295
296 assert(nbank != NULL);
297
298 return nbank->probed;
299 }
300 static int nrf5_probe(struct flash_bank *bank);
301
302 static int nrf5_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf5_info **chip)
303 {
304 if (bank->target->state != TARGET_HALTED) {
305 LOG_ERROR("Target not halted");
306 return ERROR_TARGET_NOT_HALTED;
307 }
308
309 struct nrf5_bank *nbank = bank->driver_priv;
310 *chip = nbank->chip;
311
312 int probed = nrf5_bank_is_probed(bank);
313 if (probed < 0)
314 return probed;
315 else if (!probed)
316 return nrf5_probe(bank);
317 else
318 return ERROR_OK;
319 }
320
321 static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
322 {
323 uint32_t ready;
324 int res;
325 int timeout_ms = 340;
326 int64_t ts_start = timeval_ms();
327
328 do {
329 res = target_read_u32(chip->target, NRF5_NVMC_READY, &ready);
330 if (res != ERROR_OK) {
331 LOG_ERROR("Couldn't read NVMC_READY register");
332 return res;
333 }
334
335 if (ready == 0x00000001)
336 return ERROR_OK;
337
338 keep_alive();
339
340 } while ((timeval_ms()-ts_start) < timeout_ms);
341
342 LOG_DEBUG("Timed out waiting for NVMC_READY");
343 return ERROR_FLASH_BUSY;
344 }
345
346 static int nrf5_nvmc_erase_enable(struct nrf5_info *chip)
347 {
348 int res;
349 res = target_write_u32(chip->target,
350 NRF5_NVMC_CONFIG,
351 NRF5_NVMC_CONFIG_EEN);
352
353 if (res != ERROR_OK) {
354 LOG_ERROR("Failed to enable erase operation");
355 return res;
356 }
357
358 /*
359 According to NVMC examples in Nordic SDK busy status must be
360 checked after writing to NVMC_CONFIG
361 */
362 res = nrf5_wait_for_nvmc(chip);
363 if (res != ERROR_OK)
364 LOG_ERROR("Erase enable did not complete");
365
366 return res;
367 }
368
369 static int nrf5_nvmc_write_enable(struct nrf5_info *chip)
370 {
371 int res;
372 res = target_write_u32(chip->target,
373 NRF5_NVMC_CONFIG,
374 NRF5_NVMC_CONFIG_WEN);
375
376 if (res != ERROR_OK) {
377 LOG_ERROR("Failed to enable write operation");
378 return res;
379 }
380
381 /*
382 According to NVMC examples in Nordic SDK busy status must be
383 checked after writing to NVMC_CONFIG
384 */
385 res = nrf5_wait_for_nvmc(chip);
386 if (res != ERROR_OK)
387 LOG_ERROR("Write enable did not complete");
388
389 return res;
390 }
391
392 static int nrf5_nvmc_read_only(struct nrf5_info *chip)
393 {
394 int res;
395 res = target_write_u32(chip->target,
396 NRF5_NVMC_CONFIG,
397 NRF5_NVMC_CONFIG_REN);
398
399 if (res != ERROR_OK) {
400 LOG_ERROR("Failed to enable read-only operation");
401 return res;
402 }
403 /*
404 According to NVMC examples in Nordic SDK busy status must be
405 checked after writing to NVMC_CONFIG
406 */
407 res = nrf5_wait_for_nvmc(chip);
408 if (res != ERROR_OK)
409 LOG_ERROR("Read only enable did not complete");
410
411 return res;
412 }
413
414 static int nrf5_nvmc_generic_erase(struct nrf5_info *chip,
415 uint32_t erase_register, uint32_t erase_value)
416 {
417 int res;
418
419 res = nrf5_nvmc_erase_enable(chip);
420 if (res != ERROR_OK)
421 goto error;
422
423 res = target_write_u32(chip->target,
424 erase_register,
425 erase_value);
426 if (res != ERROR_OK)
427 goto set_read_only;
428
429 res = nrf5_wait_for_nvmc(chip);
430 if (res != ERROR_OK)
431 goto set_read_only;
432
433 return nrf5_nvmc_read_only(chip);
434
435 set_read_only:
436 nrf5_nvmc_read_only(chip);
437 error:
438 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
439 erase_register, erase_value);
440 return ERROR_FAIL;
441 }
442
443 static int nrf5_protect_check_bprot(struct flash_bank *bank)
444 {
445 struct nrf5_bank *nbank = bank->driver_priv;
446 struct nrf5_info *chip = nbank->chip;
447
448 assert(chip != NULL);
449
450 static uint32_t nrf5_bprot_offsets[4] = { 0x600, 0x604, 0x610, 0x614 };
451 uint32_t bprot_reg = 0;
452 int res;
453
454 for (unsigned int i = 0; i < bank->num_sectors; i++) {
455 unsigned int bit = i % 32;
456 if (bit == 0) {
457 unsigned int n_reg = i / 32;
458 if (n_reg >= ARRAY_SIZE(nrf5_bprot_offsets))
459 break;
460
461 res = target_read_u32(chip->target, NRF5_BPROT_BASE + nrf5_bprot_offsets[n_reg], &bprot_reg);
462 if (res != ERROR_OK)
463 return res;
464 }
465 bank->sectors[i].is_protected = (bprot_reg & (1 << bit)) ? 1 : 0;
466 }
467 return ERROR_OK;
468 }
469
470 static int nrf5_protect_check(struct flash_bank *bank)
471 {
472 int res;
473 uint32_t clenr0;
474
475 /* UICR cannot be write protected so just return early */
476 if (bank->base == NRF5_UICR_BASE)
477 return ERROR_OK;
478
479 struct nrf5_bank *nbank = bank->driver_priv;
480 struct nrf5_info *chip = nbank->chip;
481
482 assert(chip != NULL);
483
484 if (chip->features & NRF5_FEATURE_BPROT)
485 return nrf5_protect_check_bprot(bank);
486
487 if (!(chip->features & NRF5_FEATURE_SERIES_51)) {
488 LOG_WARNING("Flash protection of this nRF device is not supported");
489 return ERROR_FLASH_OPER_UNSUPPORTED;
490 }
491
492 res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
493 &clenr0);
494 if (res != ERROR_OK) {
495 LOG_ERROR("Couldn't read code region 0 size[FICR]");
496 return res;
497 }
498
499 if (clenr0 == 0xFFFFFFFF) {
500 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
501 &clenr0);
502 if (res != ERROR_OK) {
503 LOG_ERROR("Couldn't read code region 0 size[UICR]");
504 return res;
505 }
506 }
507
508 for (unsigned int i = 0; i < bank->num_sectors; i++)
509 bank->sectors[i].is_protected =
510 clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
511
512 return ERROR_OK;
513 }
514
515 static int nrf5_protect(struct flash_bank *bank, int set, unsigned int first,
516 unsigned int last)
517 {
518 int res;
519 uint32_t clenr0, ppfc;
520 struct nrf5_info *chip;
521
522 /* UICR cannot be write protected so just bail out early */
523 if (bank->base == NRF5_UICR_BASE)
524 return ERROR_FAIL;
525
526 res = nrf5_get_probed_chip_if_halted(bank, &chip);
527 if (res != ERROR_OK)
528 return res;
529
530 if (!(chip->features & NRF5_FEATURE_SERIES_51)) {
531 LOG_ERROR("Flash protection setting of this nRF device is not supported");
532 return ERROR_FLASH_OPER_UNSUPPORTED;
533 }
534
535 if (first != 0) {
536 LOG_ERROR("Code region 0 must start at the begining of the bank");
537 return ERROR_FAIL;
538 }
539
540 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
541 &ppfc);
542 if (res != ERROR_OK) {
543 LOG_ERROR("Couldn't read PPFC register");
544 return res;
545 }
546
547 if ((ppfc & 0xFF) == 0x00) {
548 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
549 return ERROR_FAIL;
550 }
551
552 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
553 &clenr0);
554 if (res != ERROR_OK) {
555 LOG_ERROR("Couldn't read code region 0 size[UICR]");
556 return res;
557 }
558
559 if (clenr0 == 0xFFFFFFFF) {
560 res = target_write_u32(chip->target, NRF51_UICR_CLENR0,
561 clenr0);
562 if (res != ERROR_OK) {
563 LOG_ERROR("Couldn't write code region 0 size[UICR]");
564 return res;
565 }
566
567 } else {
568 LOG_ERROR("You need to perform chip erase before changing the protection settings");
569 }
570
571 nrf5_protect_check(bank);
572
573 return ERROR_OK;
574 }
575
576 static bool nrf5_info_variant_to_str(uint32_t variant, char *bf)
577 {
578 uint8_t b[4];
579
580 h_u32_to_be(b, variant);
581 if (isalnum(b[0]) && isalnum(b[1]) && isalnum(b[2]) && isalnum(b[3])) {
582 memcpy(bf, b, 4);
583 bf[4] = 0;
584 return true;
585 }
586
587 strcpy(bf, "xxxx");
588 return false;
589 }
590
591 static const char *nrf5_decode_info_package(uint32_t package)
592 {
593 for (size_t i = 0; i < ARRAY_SIZE(nrf5_packages_table); i++) {
594 if (nrf5_packages_table[i].package == package)
595 return nrf5_packages_table[i].code;
596 }
597 return "xx";
598 }
599
600 static int nrf5_info(struct flash_bank *bank, char *buf, int buf_size)
601 {
602 struct nrf5_bank *nbank = bank->driver_priv;
603 struct nrf5_info *chip = nbank->chip;
604 int res;
605
606 if (chip->spec) {
607 res = snprintf(buf, buf_size,
608 "nRF%s-%s(build code: %s)",
609 chip->spec->part, chip->spec->variant, chip->spec->build_code);
610
611 } else if (chip->ficr_info_valid) {
612 char variant[5];
613 nrf5_info_variant_to_str(chip->ficr_info.variant, variant);
614 res = snprintf(buf, buf_size,
615 "nRF%" PRIx32 "-%s%.2s(build code: %s)",
616 chip->ficr_info.part,
617 nrf5_decode_info_package(chip->ficr_info.package),
618 variant, &variant[2]);
619
620 } else {
621 res = snprintf(buf, buf_size, "nRF51xxx (HWID 0x%08" PRIx32 ")",
622 chip->hwid);
623 }
624 if (res <= 0)
625 return ERROR_FAIL;
626
627 snprintf(buf + res, buf_size - res, " %ukB Flash, %ukB RAM",
628 chip->flash_size_kb, chip->ram_size_kb);
629 return ERROR_OK;
630 }
631
632 static int nrf5_read_ficr_info(struct nrf5_info *chip)
633 {
634 int res;
635 struct target *target = chip->target;
636
637 chip->ficr_info_valid = false;
638
639 res = target_read_u32(target, NRF5_FICR_INFO_PART, &chip->ficr_info.part);
640 if (res != ERROR_OK) {
641 LOG_DEBUG("Couldn't read FICR INFO.PART register");
642 return res;
643 }
644
645 uint32_t series = chip->ficr_info.part & 0xfffff000;
646 switch (series) {
647 case 0x51000:
648 chip->features = NRF5_FEATURE_SERIES_51;
649 break;
650
651 case 0x52000:
652 chip->features = NRF5_FEATURE_SERIES_52;
653
654 switch (chip->ficr_info.part) {
655 case 0x52810:
656 case 0x52832:
657 chip->features |= NRF5_FEATURE_BPROT;
658 break;
659
660 case 0x52840:
661 chip->features |= NRF5_FEATURE_ACL_PROT;
662 break;
663 }
664 break;
665
666 default:
667 LOG_DEBUG("FICR INFO likely not implemented. Invalid PART value 0x%08"
668 PRIx32, chip->ficr_info.part);
669 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
670 }
671
672 /* Now we know the device has FICR INFO filled by something relevant:
673 * Although it is not documented, the tested nRF51 rev 3 devices
674 * have FICR INFO.PART, RAM and FLASH of the same format as nRF52.
675 * VARIANT and PACKAGE coding is unknown for a nRF51 device.
676 * nRF52 devices have FICR INFO documented and always filled. */
677
678 res = target_read_u32(target, NRF5_FICR_INFO_VARIANT, &chip->ficr_info.variant);
679 if (res != ERROR_OK)
680 return res;
681
682 res = target_read_u32(target, NRF5_FICR_INFO_PACKAGE, &chip->ficr_info.package);
683 if (res != ERROR_OK)
684 return res;
685
686 res = target_read_u32(target, NRF5_FICR_INFO_RAM, &chip->ficr_info.ram);
687 if (res != ERROR_OK)
688 return res;
689
690 res = target_read_u32(target, NRF5_FICR_INFO_FLASH, &chip->ficr_info.flash);
691 if (res != ERROR_OK)
692 return res;
693
694 chip->ficr_info_valid = true;
695 return ERROR_OK;
696 }
697
698 static int nrf5_get_ram_size(struct target *target, uint32_t *ram_size)
699 {
700 int res;
701
702 *ram_size = 0;
703
704 uint32_t numramblock;
705 res = target_read_u32(target, NRF51_FICR_NUMRAMBLOCK, &numramblock);
706 if (res != ERROR_OK) {
707 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
708 return res;
709 }
710
711 if (numramblock < 1 || numramblock > 4) {
712 LOG_DEBUG("FICR NUMRAMBLOCK strange value %" PRIx32, numramblock);
713 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
714 }
715
716 for (unsigned int i = 0; i < numramblock; i++) {
717 uint32_t sizeramblock;
718 res = target_read_u32(target, NRF51_FICR_SIZERAMBLOCK0 + sizeof(uint32_t)*i, &sizeramblock);
719 if (res != ERROR_OK) {
720 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
721 return res;
722 }
723 if (sizeramblock < 1024 || sizeramblock > 65536)
724 LOG_DEBUG("FICR SIZERAMBLOCK strange value %" PRIx32, sizeramblock);
725 else
726 *ram_size += sizeramblock;
727 }
728 return res;
729 }
730
731 static int nrf5_probe(struct flash_bank *bank)
732 {
733 int res;
734 struct nrf5_bank *nbank = bank->driver_priv;
735 struct nrf5_info *chip = nbank->chip;
736 struct target *target = chip->target;
737
738 res = target_read_u32(target, NRF5_FICR_CONFIGID, &chip->hwid);
739 if (res != ERROR_OK) {
740 LOG_ERROR("Couldn't read CONFIGID register");
741 return res;
742 }
743
744 chip->hwid &= 0xFFFF; /* HWID is stored in the lower two
745 * bytes of the CONFIGID register */
746
747 /* guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
748 chip->features = NRF5_FEATURE_SERIES_51;
749
750 /* Don't bail out on error for the case that some old engineering
751 * sample has FICR INFO registers unreadable. We can proceed anyway. */
752 (void)nrf5_read_ficr_info(chip);
753
754 chip->spec = NULL;
755 for (size_t i = 0; i < ARRAY_SIZE(nrf5_known_devices_table); i++) {
756 if (chip->hwid == nrf5_known_devices_table[i].hwid) {
757 chip->spec = &nrf5_known_devices_table[i];
758 chip->features = chip->spec->features;
759 break;
760 }
761 }
762
763 if (chip->spec && chip->ficr_info_valid) {
764 /* check if HWID table gives the same part as FICR INFO */
765 if (chip->ficr_info.part != strtoul(chip->spec->part, NULL, 16))
766 LOG_WARNING("HWID 0x%04" PRIx32 " mismatch: FICR INFO.PART %"
767 PRIx32, chip->hwid, chip->ficr_info.part);
768 }
769
770 if (chip->ficr_info_valid) {
771 chip->ram_size_kb = chip->ficr_info.ram;
772 } else {
773 uint32_t ram_size;
774 nrf5_get_ram_size(target, &ram_size);
775 chip->ram_size_kb = ram_size / 1024;
776 }
777
778 /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
779 uint32_t flash_page_size;
780 res = target_read_u32(chip->target, NRF5_FICR_CODEPAGESIZE,
781 &flash_page_size);
782 if (res != ERROR_OK) {
783 LOG_ERROR("Couldn't read code page size");
784 return res;
785 }
786
787 /* Note the register name is misleading,
788 * NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
789 uint32_t num_sectors;
790 res = target_read_u32(chip->target, NRF5_FICR_CODESIZE, &num_sectors);
791 if (res != ERROR_OK) {
792 LOG_ERROR("Couldn't read code memory size");
793 return res;
794 }
795
796 chip->flash_size_kb = num_sectors * flash_page_size / 1024;
797
798 if (!chip->bank[0].probed && !chip->bank[1].probed) {
799 char buf[80];
800 nrf5_info(bank, buf, sizeof(buf));
801 if (!chip->spec && !chip->ficr_info_valid) {
802 LOG_INFO("Unknown device: %s", buf);
803 } else {
804 LOG_INFO("%s", buf);
805 }
806 }
807
808 free(bank->sectors);
809
810 if (bank->base == NRF5_FLASH_BASE) {
811 /* Sanity check */
812 if (chip->spec && chip->flash_size_kb != chip->spec->flash_size_kb)
813 LOG_WARNING("Chip's reported Flash capacity does not match expected one");
814 if (chip->ficr_info_valid && chip->flash_size_kb != chip->ficr_info.flash)
815 LOG_WARNING("Chip's reported Flash capacity does not match FICR INFO.FLASH");
816
817 bank->num_sectors = num_sectors;
818 bank->size = num_sectors * flash_page_size;
819
820 bank->sectors = alloc_block_array(0, flash_page_size, num_sectors);
821 if (!bank->sectors)
822 return ERROR_FAIL;
823
824 nrf5_protect_check(bank);
825
826 chip->bank[0].probed = true;
827
828 } else {
829 bank->num_sectors = 1;
830 bank->size = flash_page_size;
831
832 bank->sectors = alloc_block_array(0, flash_page_size, num_sectors);
833 if (!bank->sectors)
834 return ERROR_FAIL;
835
836 bank->sectors[0].is_protected = 0;
837
838 chip->bank[1].probed = true;
839 }
840
841 return ERROR_OK;
842 }
843
844 static int nrf5_auto_probe(struct flash_bank *bank)
845 {
846 int probed = nrf5_bank_is_probed(bank);
847
848 if (probed < 0)
849 return probed;
850 else if (probed)
851 return ERROR_OK;
852 else
853 return nrf5_probe(bank);
854 }
855
856 static int nrf5_erase_all(struct nrf5_info *chip)
857 {
858 LOG_DEBUG("Erasing all non-volatile memory");
859 return nrf5_nvmc_generic_erase(chip,
860 NRF5_NVMC_ERASEALL,
861 0x00000001);
862 }
863
864 static int nrf5_erase_page(struct flash_bank *bank,
865 struct nrf5_info *chip,
866 struct flash_sector *sector)
867 {
868 int res;
869
870 LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
871
872 if (bank->base == NRF5_UICR_BASE) {
873 if (chip->features & NRF5_FEATURE_SERIES_51) {
874 uint32_t ppfc;
875 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
876 &ppfc);
877 if (res != ERROR_OK) {
878 LOG_ERROR("Couldn't read PPFC register");
879 return res;
880 }
881
882 if ((ppfc & 0xFF) == 0xFF) {
883 /* We can't erase the UICR. Double-check to
884 see if it's already erased before complaining. */
885 default_flash_blank_check(bank);
886 if (sector->is_erased == 1)
887 return ERROR_OK;
888
889 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
890 return ERROR_FAIL;
891 }
892 }
893
894 res = nrf5_nvmc_generic_erase(chip,
895 NRF5_NVMC_ERASEUICR,
896 0x00000001);
897
898
899 } else {
900 res = nrf5_nvmc_generic_erase(chip,
901 NRF5_NVMC_ERASEPAGE,
902 sector->offset);
903 }
904
905 return res;
906 }
907
908 /* Start a low level flash write for the specified region */
909 static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const uint8_t *buffer, uint32_t bytes)
910 {
911 struct target *target = chip->target;
912 uint32_t buffer_size = 8192;
913 struct working_area *write_algorithm;
914 struct working_area *source;
915 struct reg_param reg_params[6];
916 struct armv7m_algorithm armv7m_info;
917 int retval = ERROR_OK;
918
919 static const uint8_t nrf5_flash_write_code[] = {
920 #include "../../../contrib/loaders/flash/nrf5/nrf5.inc"
921 };
922
923 LOG_DEBUG("Writing buffer to flash address=0x%"PRIx32" bytes=0x%"PRIx32, address, bytes);
924 assert(bytes % 4 == 0);
925
926 /* allocate working area with flash programming code */
927 if (target_alloc_working_area(target, sizeof(nrf5_flash_write_code),
928 &write_algorithm) != ERROR_OK) {
929 LOG_WARNING("no working area available, falling back to slow memory writes");
930
931 for (; bytes > 0; bytes -= 4) {
932 retval = target_write_memory(target, address, 4, 1, buffer);
933 if (retval != ERROR_OK)
934 return retval;
935
936 retval = nrf5_wait_for_nvmc(chip);
937 if (retval != ERROR_OK)
938 return retval;
939
940 address += 4;
941 buffer += 4;
942 }
943
944 return ERROR_OK;
945 }
946
947 retval = target_write_buffer(target, write_algorithm->address,
948 sizeof(nrf5_flash_write_code),
949 nrf5_flash_write_code);
950 if (retval != ERROR_OK)
951 return retval;
952
953 /* memory buffer */
954 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
955 buffer_size /= 2;
956 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
957 if (buffer_size <= 256) {
958 /* free working area, write algorithm already allocated */
959 target_free_working_area(target, write_algorithm);
960
961 LOG_WARNING("No large enough working area available, can't do block memory writes");
962 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
963 }
964 }
965
966 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
967 armv7m_info.core_mode = ARM_MODE_THREAD;
968
969 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* byte count */
970 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer start */
971 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer end */
972 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT); /* target address */
973 init_reg_param(&reg_params[4], "r6", 32, PARAM_OUT); /* watchdog refresh value */
974 init_reg_param(&reg_params[5], "r7", 32, PARAM_OUT); /* watchdog refresh register address */
975
976 buf_set_u32(reg_params[0].value, 0, 32, bytes);
977 buf_set_u32(reg_params[1].value, 0, 32, source->address);
978 buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
979 buf_set_u32(reg_params[3].value, 0, 32, address);
980 buf_set_u32(reg_params[4].value, 0, 32, WATCHDOG_REFRESH_VALUE);
981 buf_set_u32(reg_params[5].value, 0, 32, WATCHDOG_REFRESH_REGISTER);
982
983 retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
984 0, NULL,
985 ARRAY_SIZE(reg_params), reg_params,
986 source->address, source->size,
987 write_algorithm->address, 0,
988 &armv7m_info);
989
990 target_free_working_area(target, source);
991 target_free_working_area(target, write_algorithm);
992
993 destroy_reg_param(&reg_params[0]);
994 destroy_reg_param(&reg_params[1]);
995 destroy_reg_param(&reg_params[2]);
996 destroy_reg_param(&reg_params[3]);
997 destroy_reg_param(&reg_params[4]);
998 destroy_reg_param(&reg_params[5]);
999
1000 return retval;
1001 }
1002
1003 static int nrf5_write(struct flash_bank *bank, const uint8_t *buffer,
1004 uint32_t offset, uint32_t count)
1005 {
1006 struct nrf5_info *chip;
1007
1008 int res = nrf5_get_probed_chip_if_halted(bank, &chip);
1009 if (res != ERROR_OK)
1010 return res;
1011
1012 assert(offset % 4 == 0);
1013 assert(count % 4 == 0);
1014
1015 res = nrf5_nvmc_write_enable(chip);
1016 if (res != ERROR_OK)
1017 goto error;
1018
1019 res = nrf5_ll_flash_write(chip, bank->base + offset, buffer, count);
1020 if (res != ERROR_OK)
1021 goto error;
1022
1023 return nrf5_nvmc_read_only(chip);
1024
1025 error:
1026 nrf5_nvmc_read_only(chip);
1027 LOG_ERROR("Failed to write to nrf5 flash");
1028 return res;
1029 }
1030
1031 static int nrf5_erase(struct flash_bank *bank, unsigned int first,
1032 unsigned int last)
1033 {
1034 int res;
1035 struct nrf5_info *chip;
1036
1037 res = nrf5_get_probed_chip_if_halted(bank, &chip);
1038 if (res != ERROR_OK)
1039 return res;
1040
1041 /* For each sector to be erased */
1042 for (unsigned int s = first; s <= last && res == ERROR_OK; s++)
1043 res = nrf5_erase_page(bank, chip, &bank->sectors[s]);
1044
1045 return res;
1046 }
1047
1048 static void nrf5_free_driver_priv(struct flash_bank *bank)
1049 {
1050 struct nrf5_bank *nbank = bank->driver_priv;
1051 struct nrf5_info *chip = nbank->chip;
1052 if (chip == NULL)
1053 return;
1054
1055 chip->refcount--;
1056 if (chip->refcount == 0) {
1057 free(chip);
1058 bank->driver_priv = NULL;
1059 }
1060 }
1061
1062 static struct nrf5_info *nrf5_get_chip(struct target *target)
1063 {
1064 struct flash_bank *bank_iter;
1065
1066 /* iterate over nrf5 banks of same target */
1067 for (bank_iter = flash_bank_list(); bank_iter; bank_iter = bank_iter->next) {
1068 if (bank_iter->driver != &nrf5_flash && bank_iter->driver != &nrf51_flash)
1069 continue;
1070
1071 if (bank_iter->target != target)
1072 continue;
1073
1074 struct nrf5_bank *nbank = bank_iter->driver_priv;
1075 if (!nbank)
1076 continue;
1077
1078 if (nbank->chip)
1079 return nbank->chip;
1080 }
1081 return NULL;
1082 }
1083
1084 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
1085 {
1086 struct nrf5_info *chip;
1087 struct nrf5_bank *nbank = NULL;
1088
1089 switch (bank->base) {
1090 case NRF5_FLASH_BASE:
1091 case NRF5_UICR_BASE:
1092 break;
1093 default:
1094 LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base);
1095 return ERROR_FAIL;
1096 }
1097
1098 chip = nrf5_get_chip(bank->target);
1099 if (!chip) {
1100 /* Create a new chip */
1101 chip = calloc(1, sizeof(*chip));
1102 if (!chip)
1103 return ERROR_FAIL;
1104
1105 chip->target = bank->target;
1106 }
1107
1108 switch (bank->base) {
1109 case NRF5_FLASH_BASE:
1110 nbank = &chip->bank[0];
1111 break;
1112 case NRF5_UICR_BASE:
1113 nbank = &chip->bank[1];
1114 break;
1115 }
1116 assert(nbank != NULL);
1117
1118 chip->refcount++;
1119 nbank->chip = chip;
1120 nbank->probed = false;
1121 bank->driver_priv = nbank;
1122 bank->write_start_alignment = bank->write_end_alignment = 4;
1123
1124 return ERROR_OK;
1125 }
1126
1127 COMMAND_HANDLER(nrf5_handle_mass_erase_command)
1128 {
1129 int res;
1130 struct flash_bank *bank = NULL;
1131 struct target *target = get_current_target(CMD_CTX);
1132
1133 res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank);
1134 if (res != ERROR_OK)
1135 return res;
1136
1137 assert(bank != NULL);
1138
1139 struct nrf5_info *chip;
1140
1141 res = nrf5_get_probed_chip_if_halted(bank, &chip);
1142 if (res != ERROR_OK)
1143 return res;
1144
1145 if (chip->features & NRF5_FEATURE_SERIES_51) {
1146 uint32_t ppfc;
1147 res = target_read_u32(target, NRF51_FICR_PPFC,
1148 &ppfc);
1149 if (res != ERROR_OK) {
1150 LOG_ERROR("Couldn't read PPFC register");
1151 return res;
1152 }
1153
1154 if ((ppfc & 0xFF) == 0x00) {
1155 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1156 "mass erase command won't work.");
1157 return ERROR_FAIL;
1158 }
1159 }
1160
1161 res = nrf5_erase_all(chip);
1162 if (res != ERROR_OK) {
1163 LOG_ERROR("Failed to erase the chip");
1164 nrf5_protect_check(bank);
1165 return res;
1166 }
1167
1168 res = nrf5_protect_check(bank);
1169 if (res != ERROR_OK) {
1170 LOG_ERROR("Failed to check chip's write protection");
1171 return res;
1172 }
1173
1174 res = get_flash_bank_by_addr(target, NRF5_UICR_BASE, true, &bank);
1175 if (res != ERROR_OK)
1176 return res;
1177
1178 return ERROR_OK;
1179 }
1180
1181 COMMAND_HANDLER(nrf5_handle_info_command)
1182 {
1183 int res;
1184 struct flash_bank *bank = NULL;
1185 struct target *target = get_current_target(CMD_CTX);
1186
1187 res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank);
1188 if (res != ERROR_OK)
1189 return res;
1190
1191 assert(bank != NULL);
1192
1193 struct nrf5_info *chip;
1194
1195 res = nrf5_get_probed_chip_if_halted(bank, &chip);
1196 if (res != ERROR_OK)
1197 return res;
1198
1199 static struct {
1200 const uint32_t address;
1201 uint32_t value;
1202 } ficr[] = {
1203 { .address = NRF5_FICR_CODEPAGESIZE },
1204 { .address = NRF5_FICR_CODESIZE },
1205 { .address = NRF51_FICR_CLENR0 },
1206 { .address = NRF51_FICR_PPFC },
1207 { .address = NRF51_FICR_NUMRAMBLOCK },
1208 { .address = NRF51_FICR_SIZERAMBLOCK0 },
1209 { .address = NRF51_FICR_SIZERAMBLOCK1 },
1210 { .address = NRF51_FICR_SIZERAMBLOCK2 },
1211 { .address = NRF51_FICR_SIZERAMBLOCK3 },
1212 { .address = NRF5_FICR_CONFIGID },
1213 { .address = NRF5_FICR_DEVICEID0 },
1214 { .address = NRF5_FICR_DEVICEID1 },
1215 { .address = NRF5_FICR_ER0 },
1216 { .address = NRF5_FICR_ER1 },
1217 { .address = NRF5_FICR_ER2 },
1218 { .address = NRF5_FICR_ER3 },
1219 { .address = NRF5_FICR_IR0 },
1220 { .address = NRF5_FICR_IR1 },
1221 { .address = NRF5_FICR_IR2 },
1222 { .address = NRF5_FICR_IR3 },
1223 { .address = NRF5_FICR_DEVICEADDRTYPE },
1224 { .address = NRF5_FICR_DEVICEADDR0 },
1225 { .address = NRF5_FICR_DEVICEADDR1 },
1226 { .address = NRF51_FICR_OVERRIDEN },
1227 { .address = NRF51_FICR_NRF_1MBIT0 },
1228 { .address = NRF51_FICR_NRF_1MBIT1 },
1229 { .address = NRF51_FICR_NRF_1MBIT2 },
1230 { .address = NRF51_FICR_NRF_1MBIT3 },
1231 { .address = NRF51_FICR_NRF_1MBIT4 },
1232 { .address = NRF51_FICR_BLE_1MBIT0 },
1233 { .address = NRF51_FICR_BLE_1MBIT1 },
1234 { .address = NRF51_FICR_BLE_1MBIT2 },
1235 { .address = NRF51_FICR_BLE_1MBIT3 },
1236 { .address = NRF51_FICR_BLE_1MBIT4 },
1237 }, uicr[] = {
1238 { .address = NRF51_UICR_CLENR0, },
1239 { .address = NRF51_UICR_RBPCONF },
1240 { .address = NRF51_UICR_XTALFREQ },
1241 { .address = NRF51_UICR_FWID },
1242 };
1243
1244 for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
1245 res = target_read_u32(chip->target, ficr[i].address,
1246 &ficr[i].value);
1247 if (res != ERROR_OK) {
1248 LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address);
1249 return res;
1250 }
1251 }
1252
1253 for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) {
1254 res = target_read_u32(chip->target, uicr[i].address,
1255 &uicr[i].value);
1256 if (res != ERROR_OK) {
1257 LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address);
1258 return res;
1259 }
1260 }
1261
1262 command_print(CMD,
1263 "\n[factory information control block]\n\n"
1264 "code page size: %"PRIu32"B\n"
1265 "code memory size: %"PRIu32"kB\n"
1266 "code region 0 size: %"PRIu32"kB\n"
1267 "pre-programmed code: %s\n"
1268 "number of ram blocks: %"PRIu32"\n"
1269 "ram block 0 size: %"PRIu32"B\n"
1270 "ram block 1 size: %"PRIu32"B\n"
1271 "ram block 2 size: %"PRIu32"B\n"
1272 "ram block 3 size: %"PRIu32 "B\n"
1273 "config id: %" PRIx32 "\n"
1274 "device id: 0x%"PRIx32"%08"PRIx32"\n"
1275 "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1276 "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1277 "device address type: 0x%"PRIx32"\n"
1278 "device address: 0x%"PRIx32"%08"PRIx32"\n"
1279 "override enable: %"PRIx32"\n"
1280 "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1281 "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1282 "\n[user information control block]\n\n"
1283 "code region 0 size: %"PRIu32"kB\n"
1284 "read back protection configuration: %"PRIx32"\n"
1285 "reset value for XTALFREQ: %"PRIx32"\n"
1286 "firmware id: 0x%04"PRIx32,
1287 ficr[0].value,
1288 (ficr[1].value * ficr[0].value) / 1024,
1289 (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
1290 ((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
1291 ficr[4].value,
1292 ficr[5].value,
1293 (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
1294 (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
1295 (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
1296 ficr[9].value,
1297 ficr[10].value, ficr[11].value,
1298 ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
1299 ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
1300 ficr[20].value,
1301 ficr[21].value, ficr[22].value,
1302 ficr[23].value,
1303 ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
1304 ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
1305 (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
1306 uicr[1].value & 0xFFFF,
1307 uicr[2].value & 0xFF,
1308 uicr[3].value & 0xFFFF);
1309
1310 return ERROR_OK;
1311 }
1312
1313 static const struct command_registration nrf5_exec_command_handlers[] = {
1314 {
1315 .name = "mass_erase",
1316 .handler = nrf5_handle_mass_erase_command,
1317 .mode = COMMAND_EXEC,
1318 .help = "Erase all flash contents of the chip.",
1319 .usage = "",
1320 },
1321 {
1322 .name = "info",
1323 .handler = nrf5_handle_info_command,
1324 .mode = COMMAND_EXEC,
1325 .help = "Show FICR and UICR info.",
1326 .usage = "",
1327 },
1328 COMMAND_REGISTRATION_DONE
1329 };
1330
1331 static const struct command_registration nrf5_command_handlers[] = {
1332 {
1333 .name = "nrf5",
1334 .mode = COMMAND_ANY,
1335 .help = "nrf5 flash command group",
1336 .usage = "",
1337 .chain = nrf5_exec_command_handlers,
1338 },
1339 {
1340 .name = "nrf51",
1341 .mode = COMMAND_ANY,
1342 .help = "nrf51 flash command group",
1343 .usage = "",
1344 .chain = nrf5_exec_command_handlers,
1345 },
1346 COMMAND_REGISTRATION_DONE
1347 };
1348
1349 const struct flash_driver nrf5_flash = {
1350 .name = "nrf5",
1351 .commands = nrf5_command_handlers,
1352 .flash_bank_command = nrf5_flash_bank_command,
1353 .info = nrf5_info,
1354 .erase = nrf5_erase,
1355 .protect = nrf5_protect,
1356 .write = nrf5_write,
1357 .read = default_flash_read,
1358 .probe = nrf5_probe,
1359 .auto_probe = nrf5_auto_probe,
1360 .erase_check = default_flash_blank_check,
1361 .protect_check = nrf5_protect_check,
1362 .free_driver_priv = nrf5_free_driver_priv,
1363 };
1364
1365 /* We need to retain the flash-driver name as well as the commands
1366 * for backwards compatability */
1367 const struct flash_driver nrf51_flash = {
1368 .name = "nrf51",
1369 .commands = nrf5_command_handlers,
1370 .flash_bank_command = nrf5_flash_bank_command,
1371 .info = nrf5_info,
1372 .erase = nrf5_erase,
1373 .protect = nrf5_protect,
1374 .write = nrf5_write,
1375 .read = default_flash_read,
1376 .probe = nrf5_probe,
1377 .auto_probe = nrf5_auto_probe,
1378 .erase_check = default_flash_blank_check,
1379 .protect_check = nrf5_protect_check,
1380 .free_driver_priv = nrf5_free_driver_priv,
1381 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)