1 /***************************************************************************
2 * Copyright (C) 2013 Synapse Product Development *
3 * Andrey Smirnov <andrew.smironv@gmail.com> *
4 * Angus Gratton <gus@projectgus.com> *
5 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
19 ***************************************************************************/
26 #include <target/algorithm.h>
27 #include <target/armv7m.h>
28 #include <helper/types.h>
29 #include <helper/time_support.h>
32 NRF5_FLASH_BASE
= 0x00000000,
35 enum nrf5_ficr_registers
{
36 NRF5_FICR_BASE
= 0x10000000, /* Factory Information Configuration Registers */
38 #define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
40 NRF5_FICR_CODEPAGESIZE
= NRF5_FICR_REG(0x010),
41 NRF5_FICR_CODESIZE
= NRF5_FICR_REG(0x014),
42 NRF5_FICR_CLENR0
= NRF5_FICR_REG(0x028),
43 NRF5_FICR_PPFC
= NRF5_FICR_REG(0x02C),
44 NRF5_FICR_NUMRAMBLOCK
= NRF5_FICR_REG(0x034),
45 NRF5_FICR_SIZERAMBLOCK0
= NRF5_FICR_REG(0x038),
46 NRF5_FICR_SIZERAMBLOCK1
= NRF5_FICR_REG(0x03C),
47 NRF5_FICR_SIZERAMBLOCK2
= NRF5_FICR_REG(0x040),
48 NRF5_FICR_SIZERAMBLOCK3
= NRF5_FICR_REG(0x044),
49 NRF5_FICR_CONFIGID
= NRF5_FICR_REG(0x05C),
50 NRF5_FICR_DEVICEID0
= NRF5_FICR_REG(0x060),
51 NRF5_FICR_DEVICEID1
= NRF5_FICR_REG(0x064),
52 NRF5_FICR_ER0
= NRF5_FICR_REG(0x080),
53 NRF5_FICR_ER1
= NRF5_FICR_REG(0x084),
54 NRF5_FICR_ER2
= NRF5_FICR_REG(0x088),
55 NRF5_FICR_ER3
= NRF5_FICR_REG(0x08C),
56 NRF5_FICR_IR0
= NRF5_FICR_REG(0x090),
57 NRF5_FICR_IR1
= NRF5_FICR_REG(0x094),
58 NRF5_FICR_IR2
= NRF5_FICR_REG(0x098),
59 NRF5_FICR_IR3
= NRF5_FICR_REG(0x09C),
60 NRF5_FICR_DEVICEADDRTYPE
= NRF5_FICR_REG(0x0A0),
61 NRF5_FICR_DEVICEADDR0
= NRF5_FICR_REG(0x0A4),
62 NRF5_FICR_DEVICEADDR1
= NRF5_FICR_REG(0x0A8),
63 NRF5_FICR_OVERRIDEN
= NRF5_FICR_REG(0x0AC),
64 NRF5_FICR_NRF_1MBIT0
= NRF5_FICR_REG(0x0B0),
65 NRF5_FICR_NRF_1MBIT1
= NRF5_FICR_REG(0x0B4),
66 NRF5_FICR_NRF_1MBIT2
= NRF5_FICR_REG(0x0B8),
67 NRF5_FICR_NRF_1MBIT3
= NRF5_FICR_REG(0x0BC),
68 NRF5_FICR_NRF_1MBIT4
= NRF5_FICR_REG(0x0C0),
69 NRF5_FICR_BLE_1MBIT0
= NRF5_FICR_REG(0x0EC),
70 NRF5_FICR_BLE_1MBIT1
= NRF5_FICR_REG(0x0F0),
71 NRF5_FICR_BLE_1MBIT2
= NRF5_FICR_REG(0x0F4),
72 NRF5_FICR_BLE_1MBIT3
= NRF5_FICR_REG(0x0F8),
73 NRF5_FICR_BLE_1MBIT4
= NRF5_FICR_REG(0x0FC),
76 enum nrf5_uicr_registers
{
77 NRF5_UICR_BASE
= 0x10001000, /* User Information
78 * Configuration Regsters */
80 NRF5_UICR_SIZE
= 0x100,
82 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
84 NRF5_UICR_CLENR0
= NRF5_UICR_REG(0x000),
85 NRF5_UICR_RBPCONF
= NRF5_UICR_REG(0x004),
86 NRF5_UICR_XTALFREQ
= NRF5_UICR_REG(0x008),
87 NRF5_UICR_FWID
= NRF5_UICR_REG(0x010),
90 enum nrf5_nvmc_registers
{
91 NRF5_NVMC_BASE
= 0x4001E000, /* Non-Volatile Memory
92 * Controller Regsters */
94 #define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
96 NRF5_NVMC_READY
= NRF5_NVMC_REG(0x400),
97 NRF5_NVMC_CONFIG
= NRF5_NVMC_REG(0x504),
98 NRF5_NVMC_ERASEPAGE
= NRF5_NVMC_REG(0x508),
99 NRF5_NVMC_ERASEALL
= NRF5_NVMC_REG(0x50C),
100 NRF5_NVMC_ERASEUICR
= NRF5_NVMC_REG(0x514),
103 enum nrf5_nvmc_config_bits
{
104 NRF5_NVMC_CONFIG_REN
= 0x00,
105 NRF5_NVMC_CONFIG_WEN
= 0x01,
106 NRF5_NVMC_CONFIG_EEN
= 0x02,
111 uint32_t code_page_size
;
115 struct nrf5_info
*chip
;
117 int (*write
) (struct flash_bank
*bank
,
118 struct nrf5_info
*chip
,
119 const uint8_t *buffer
, uint32_t offset
, uint32_t count
);
121 struct target
*target
;
124 struct nrf5_device_spec
{
128 const char *build_code
;
129 unsigned int flash_size_kb
;
132 #define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize) \
137 .build_code = bcode, \
138 .flash_size_kb = (fsize), \
141 /* The known devices table below is derived from the "nRF51 Series
142 * Compatibility Matrix" document, which can be found by searching for
143 * ATTN-51 on the Nordic Semi website:
145 * http://www.nordicsemi.com/eng/content/search?SearchText=ATTN-51
147 * Up to date with Matrix v2.0, plus some additional HWIDs.
149 * The additional HWIDs apply where the build code in the matrix is
150 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
151 * for x==0, x!=0 means different (unspecified) HWIDs.
153 static const struct nrf5_device_spec nrf5_known_devices_table
[] = {
154 /* nRF51822 Devices (IC rev 1). */
155 NRF5_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
156 NRF5_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
157 NRF5_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
158 NRF5_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
159 NRF5_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
161 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
162 with built-in jlink seem to use engineering samples not listed
163 in the nRF51 Series Compatibility Matrix V1.0. */
164 NRF5_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
166 /* nRF51822 Devices (IC rev 2). */
167 NRF5_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
168 NRF5_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
169 NRF5_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
170 NRF5_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
171 NRF5_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
172 NRF5_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
173 NRF5_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
174 NRF5_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
175 NRF5_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
177 /* nRF51822 Devices (IC rev 3). */
178 NRF5_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
179 NRF5_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
180 NRF5_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
181 NRF5_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
182 NRF5_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
183 NRF5_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
184 NRF5_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
185 NRF5_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
186 NRF5_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
188 /* nRF51422 Devices (IC rev 1). */
189 NRF5_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
190 NRF5_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
191 NRF5_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
193 /* nRF51422 Devices (IC rev 2). */
194 NRF5_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
195 NRF5_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
196 NRF5_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
197 NRF5_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
199 /* nRF51422 Devices (IC rev 3). */
200 NRF5_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
201 NRF5_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
202 NRF5_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
203 NRF5_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
204 NRF5_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
205 NRF5_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
206 NRF5_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
208 /* nRF52810 Devices */
209 NRF5_DEVICE_DEF(0x0142, "52810", "QFAA", "B0", 192),
210 NRF5_DEVICE_DEF(0x0143, "52810", "QCAA", "C0", 192),
212 /* nRF52832 Devices */
213 NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0", 512),
214 NRF5_DEVICE_DEF(0x0139, "52832", "QFAA", "E0", 512),
215 NRF5_DEVICE_DEF(0x00E3, "52832", "CIAA", "B0", 512),
217 /* nRF52840 Devices */
218 NRF5_DEVICE_DEF(0x0150, "52840", "QIAA", "C0", 1024),
221 static int nrf5_bank_is_probed(struct flash_bank
*bank
)
223 struct nrf5_bank
*nbank
= bank
->driver_priv
;
225 assert(nbank
!= NULL
);
227 return nbank
->probed
;
229 static int nrf5_probe(struct flash_bank
*bank
);
231 static int nrf5_get_probed_chip_if_halted(struct flash_bank
*bank
, struct nrf5_info
**chip
)
233 if (bank
->target
->state
!= TARGET_HALTED
) {
234 LOG_ERROR("Target not halted");
235 return ERROR_TARGET_NOT_HALTED
;
238 struct nrf5_bank
*nbank
= bank
->driver_priv
;
241 int probed
= nrf5_bank_is_probed(bank
);
245 return nrf5_probe(bank
);
250 static int nrf5_wait_for_nvmc(struct nrf5_info
*chip
)
254 int timeout_ms
= 340;
255 int64_t ts_start
= timeval_ms();
258 res
= target_read_u32(chip
->target
, NRF5_NVMC_READY
, &ready
);
259 if (res
!= ERROR_OK
) {
260 LOG_ERROR("Couldn't read NVMC_READY register");
264 if (ready
== 0x00000001)
269 } while ((timeval_ms()-ts_start
) < timeout_ms
);
271 LOG_DEBUG("Timed out waiting for NVMC_READY");
272 return ERROR_FLASH_BUSY
;
275 static int nrf5_nvmc_erase_enable(struct nrf5_info
*chip
)
278 res
= target_write_u32(chip
->target
,
280 NRF5_NVMC_CONFIG_EEN
);
282 if (res
!= ERROR_OK
) {
283 LOG_ERROR("Failed to enable erase operation");
288 According to NVMC examples in Nordic SDK busy status must be
289 checked after writing to NVMC_CONFIG
291 res
= nrf5_wait_for_nvmc(chip
);
293 LOG_ERROR("Erase enable did not complete");
298 static int nrf5_nvmc_write_enable(struct nrf5_info
*chip
)
301 res
= target_write_u32(chip
->target
,
303 NRF5_NVMC_CONFIG_WEN
);
305 if (res
!= ERROR_OK
) {
306 LOG_ERROR("Failed to enable write operation");
311 According to NVMC examples in Nordic SDK busy status must be
312 checked after writing to NVMC_CONFIG
314 res
= nrf5_wait_for_nvmc(chip
);
316 LOG_ERROR("Write enable did not complete");
321 static int nrf5_nvmc_read_only(struct nrf5_info
*chip
)
324 res
= target_write_u32(chip
->target
,
326 NRF5_NVMC_CONFIG_REN
);
328 if (res
!= ERROR_OK
) {
329 LOG_ERROR("Failed to enable read-only operation");
333 According to NVMC examples in Nordic SDK busy status must be
334 checked after writing to NVMC_CONFIG
336 res
= nrf5_wait_for_nvmc(chip
);
338 LOG_ERROR("Read only enable did not complete");
343 static int nrf5_nvmc_generic_erase(struct nrf5_info
*chip
,
344 uint32_t erase_register
, uint32_t erase_value
)
348 res
= nrf5_nvmc_erase_enable(chip
);
352 res
= target_write_u32(chip
->target
,
358 res
= nrf5_wait_for_nvmc(chip
);
362 return nrf5_nvmc_read_only(chip
);
365 nrf5_nvmc_read_only(chip
);
367 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32
" val: 0x%08"PRIx32
,
368 erase_register
, erase_value
);
372 static int nrf5_protect_check(struct flash_bank
*bank
)
377 /* UICR cannot be write protected so just return early */
378 if (bank
->base
== NRF5_UICR_BASE
)
381 struct nrf5_bank
*nbank
= bank
->driver_priv
;
382 struct nrf5_info
*chip
= nbank
->chip
;
384 assert(chip
!= NULL
);
386 res
= target_read_u32(chip
->target
, NRF5_FICR_CLENR0
,
388 if (res
!= ERROR_OK
) {
389 LOG_ERROR("Couldn't read code region 0 size[FICR]");
393 if (clenr0
== 0xFFFFFFFF) {
394 res
= target_read_u32(chip
->target
, NRF5_UICR_CLENR0
,
396 if (res
!= ERROR_OK
) {
397 LOG_ERROR("Couldn't read code region 0 size[UICR]");
402 for (int i
= 0; i
< bank
->num_sectors
; i
++)
403 bank
->sectors
[i
].is_protected
=
404 clenr0
!= 0xFFFFFFFF && bank
->sectors
[i
].offset
< clenr0
;
409 static int nrf5_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
412 uint32_t clenr0
, ppfc
;
413 struct nrf5_info
*chip
;
415 /* UICR cannot be write protected so just bail out early */
416 if (bank
->base
== NRF5_UICR_BASE
)
419 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
424 LOG_ERROR("Code region 0 must start at the begining of the bank");
428 res
= target_read_u32(chip
->target
, NRF5_FICR_PPFC
,
430 if (res
!= ERROR_OK
) {
431 LOG_ERROR("Couldn't read PPFC register");
435 if ((ppfc
& 0xFF) == 0x00) {
436 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
440 res
= target_read_u32(chip
->target
, NRF5_UICR_CLENR0
,
442 if (res
!= ERROR_OK
) {
443 LOG_ERROR("Couldn't read code region 0 size[UICR]");
447 if (clenr0
== 0xFFFFFFFF) {
448 res
= target_write_u32(chip
->target
, NRF5_UICR_CLENR0
,
450 if (res
!= ERROR_OK
) {
451 LOG_ERROR("Couldn't write code region 0 size[UICR]");
456 LOG_ERROR("You need to perform chip erase before changing the protection settings");
459 nrf5_protect_check(bank
);
464 static int nrf5_probe(struct flash_bank
*bank
)
468 struct nrf5_bank
*nbank
= bank
->driver_priv
;
469 struct nrf5_info
*chip
= nbank
->chip
;
471 res
= target_read_u32(chip
->target
, NRF5_FICR_CONFIGID
, &hwid
);
472 if (res
!= ERROR_OK
) {
473 LOG_ERROR("Couldn't read CONFIGID register");
477 hwid
&= 0xFFFF; /* HWID is stored in the lower two
478 * bytes of the CONFIGID register */
480 const struct nrf5_device_spec
*spec
= NULL
;
481 for (size_t i
= 0; i
< ARRAY_SIZE(nrf5_known_devices_table
); i
++) {
482 if (hwid
== nrf5_known_devices_table
[i
].hwid
) {
483 spec
= &nrf5_known_devices_table
[i
];
488 if (!chip
->bank
[0].probed
&& !chip
->bank
[1].probed
) {
490 LOG_INFO("nRF%s-%s(build code: %s) %ukB Flash",
491 spec
->part
, spec
->variant
, spec
->build_code
,
492 spec
->flash_size_kb
);
494 LOG_WARNING("Unknown device (HWID 0x%08" PRIx32
")", hwid
);
497 if (bank
->base
== NRF5_FLASH_BASE
) {
498 /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
499 res
= target_read_u32(chip
->target
, NRF5_FICR_CODEPAGESIZE
,
500 &chip
->code_page_size
);
501 if (res
!= ERROR_OK
) {
502 LOG_ERROR("Couldn't read code page size");
506 /* Note the register name is misleading,
507 * NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
508 uint32_t num_sectors
;
509 res
= target_read_u32(chip
->target
, NRF5_FICR_CODESIZE
, &num_sectors
);
510 if (res
!= ERROR_OK
) {
511 LOG_ERROR("Couldn't read code memory size");
515 bank
->num_sectors
= num_sectors
;
516 bank
->size
= num_sectors
* chip
->code_page_size
;
518 if (spec
&& bank
->size
/ 1024 != spec
->flash_size_kb
)
519 LOG_WARNING("Chip's reported Flash capacity does not match expected one");
521 bank
->sectors
= calloc(bank
->num_sectors
,
522 sizeof((bank
->sectors
)[0]));
524 return ERROR_FLASH_BANK_NOT_PROBED
;
526 /* Fill out the sector information: all NRF5 sectors are the same size and
527 * there is always a fixed number of them. */
528 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
529 bank
->sectors
[i
].size
= chip
->code_page_size
;
530 bank
->sectors
[i
].offset
= i
* chip
->code_page_size
;
532 /* mark as unknown */
533 bank
->sectors
[i
].is_erased
= -1;
534 bank
->sectors
[i
].is_protected
= -1;
537 nrf5_protect_check(bank
);
539 chip
->bank
[0].probed
= true;
541 bank
->size
= NRF5_UICR_SIZE
;
542 bank
->num_sectors
= 1;
543 bank
->sectors
= calloc(bank
->num_sectors
,
544 sizeof((bank
->sectors
)[0]));
546 return ERROR_FLASH_BANK_NOT_PROBED
;
548 bank
->sectors
[0].size
= bank
->size
;
549 bank
->sectors
[0].offset
= 0;
551 bank
->sectors
[0].is_erased
= 0;
552 bank
->sectors
[0].is_protected
= 0;
554 chip
->bank
[1].probed
= true;
560 static int nrf5_auto_probe(struct flash_bank
*bank
)
562 int probed
= nrf5_bank_is_probed(bank
);
569 return nrf5_probe(bank
);
572 static int nrf5_erase_all(struct nrf5_info
*chip
)
574 LOG_DEBUG("Erasing all non-volatile memory");
575 return nrf5_nvmc_generic_erase(chip
,
580 static int nrf5_erase_page(struct flash_bank
*bank
,
581 struct nrf5_info
*chip
,
582 struct flash_sector
*sector
)
586 LOG_DEBUG("Erasing page at 0x%"PRIx32
, sector
->offset
);
587 if (sector
->is_protected
) {
588 LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32
, sector
->offset
);
592 if (bank
->base
== NRF5_UICR_BASE
) {
594 res
= target_read_u32(chip
->target
, NRF5_FICR_PPFC
,
596 if (res
!= ERROR_OK
) {
597 LOG_ERROR("Couldn't read PPFC register");
601 if ((ppfc
& 0xFF) == 0xFF) {
602 /* We can't erase the UICR. Double-check to
603 see if it's already erased before complaining. */
604 default_flash_blank_check(bank
);
605 if (sector
->is_erased
== 1)
608 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
612 res
= nrf5_nvmc_generic_erase(chip
,
618 res
= nrf5_nvmc_generic_erase(chip
,
626 static const uint8_t nrf5_flash_write_code
[] = {
627 /* See contrib/loaders/flash/cortex-m0.S */
629 0x0d, 0x68, /* ldr r5, [r1, #0] */
630 0x00, 0x2d, /* cmp r5, #0 */
631 0x0b, 0xd0, /* beq.n 1e <exit> */
632 0x4c, 0x68, /* ldr r4, [r1, #4] */
633 0xac, 0x42, /* cmp r4, r5 */
634 0xf9, 0xd0, /* beq.n 0 <wait_fifo> */
635 0x20, 0xcc, /* ldmia r4!, {r5} */
636 0x20, 0xc3, /* stmia r3!, {r5} */
637 0x94, 0x42, /* cmp r4, r2 */
638 0x01, 0xd3, /* bcc.n 18 <no_wrap> */
639 0x0c, 0x46, /* mov r4, r1 */
640 0x08, 0x34, /* adds r4, #8 */
642 0x4c, 0x60, /* str r4, [r1, #4] */
643 0x04, 0x38, /* subs r0, #4 */
644 0xf0, 0xd1, /* bne.n 0 <wait_fifo> */
646 0x00, 0xbe /* bkpt 0x0000 */
650 /* Start a low level flash write for the specified region */
651 static int nrf5_ll_flash_write(struct nrf5_info
*chip
, uint32_t offset
, const uint8_t *buffer
, uint32_t bytes
)
653 struct target
*target
= chip
->target
;
654 uint32_t buffer_size
= 8192;
655 struct working_area
*write_algorithm
;
656 struct working_area
*source
;
657 uint32_t address
= NRF5_FLASH_BASE
+ offset
;
658 struct reg_param reg_params
[4];
659 struct armv7m_algorithm armv7m_info
;
660 int retval
= ERROR_OK
;
663 LOG_DEBUG("Writing buffer to flash offset=0x%"PRIx32
" bytes=0x%"PRIx32
, offset
, bytes
);
664 assert(bytes
% 4 == 0);
666 /* allocate working area with flash programming code */
667 if (target_alloc_working_area(target
, sizeof(nrf5_flash_write_code
),
668 &write_algorithm
) != ERROR_OK
) {
669 LOG_WARNING("no working area available, falling back to slow memory writes");
671 for (; bytes
> 0; bytes
-= 4) {
672 retval
= target_write_memory(chip
->target
, offset
, 4, 1, buffer
);
673 if (retval
!= ERROR_OK
)
676 retval
= nrf5_wait_for_nvmc(chip
);
677 if (retval
!= ERROR_OK
)
687 LOG_WARNING("using fast async flash loader. This is currently supported");
688 LOG_WARNING("only with ST-Link and CMSIS-DAP. If you have issues, add");
689 LOG_WARNING("\"set WORKAREASIZE 0\" before sourcing nrf51.cfg/nrf52.cfg to disable it");
691 retval
= target_write_buffer(target
, write_algorithm
->address
,
692 sizeof(nrf5_flash_write_code
),
693 nrf5_flash_write_code
);
694 if (retval
!= ERROR_OK
)
698 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
) {
700 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
701 if (buffer_size
<= 256) {
702 /* free working area, write algorithm already allocated */
703 target_free_working_area(target
, write_algorithm
);
705 LOG_WARNING("No large enough working area available, can't do block memory writes");
706 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
710 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
711 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
713 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* byte count */
714 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer start */
715 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer end */
716 init_reg_param(®_params
[3], "r3", 32, PARAM_IN_OUT
); /* target address */
718 buf_set_u32(reg_params
[0].value
, 0, 32, bytes
);
719 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
720 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
+ source
->size
);
721 buf_set_u32(reg_params
[3].value
, 0, 32, address
);
723 retval
= target_run_flash_async_algorithm(target
, buffer
, bytes
/4, 4,
726 source
->address
, source
->size
,
727 write_algorithm
->address
, 0,
730 target_free_working_area(target
, source
);
731 target_free_working_area(target
, write_algorithm
);
733 destroy_reg_param(®_params
[0]);
734 destroy_reg_param(®_params
[1]);
735 destroy_reg_param(®_params
[2]);
736 destroy_reg_param(®_params
[3]);
741 /* Check and erase flash sectors in specified range then start a low level page write.
742 start/end must be sector aligned.
744 static int nrf5_write_pages(struct flash_bank
*bank
, uint32_t start
, uint32_t end
, const uint8_t *buffer
)
746 int res
= ERROR_FAIL
;
747 struct nrf5_bank
*nbank
= bank
->driver_priv
;
748 struct nrf5_info
*chip
= nbank
->chip
;
750 assert(start
% chip
->code_page_size
== 0);
751 assert(end
% chip
->code_page_size
== 0);
753 res
= nrf5_nvmc_write_enable(chip
);
757 res
= nrf5_ll_flash_write(chip
, start
, buffer
, (end
- start
));
761 return nrf5_nvmc_read_only(chip
);
764 nrf5_nvmc_read_only(chip
);
765 LOG_ERROR("Failed to write to nrf5 flash");
769 static int nrf5_erase(struct flash_bank
*bank
, int first
, int last
)
772 struct nrf5_info
*chip
;
774 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
778 /* For each sector to be erased */
779 for (int s
= first
; s
<= last
&& res
== ERROR_OK
; s
++)
780 res
= nrf5_erase_page(bank
, chip
, &bank
->sectors
[s
]);
785 static int nrf5_code_flash_write(struct flash_bank
*bank
,
786 struct nrf5_info
*chip
,
787 const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
791 /* Need to perform reads to fill any gaps we need to preserve in the first page,
792 before the start of buffer, or in the last page, after the end of buffer */
793 uint32_t first_page
= offset
/chip
->code_page_size
;
794 uint32_t last_page
= DIV_ROUND_UP(offset
+count
, chip
->code_page_size
);
796 uint32_t first_page_offset
= first_page
* chip
->code_page_size
;
797 uint32_t last_page_offset
= last_page
* chip
->code_page_size
;
799 LOG_DEBUG("Padding write from 0x%08"PRIx32
"-0x%08"PRIx32
" as 0x%08"PRIx32
"-0x%08"PRIx32
,
800 offset
, offset
+count
, first_page_offset
, last_page_offset
);
802 uint32_t page_cnt
= last_page
- first_page
;
803 uint8_t buffer_to_flash
[page_cnt
*chip
->code_page_size
];
805 /* Fill in any space between start of first page and start of buffer */
806 uint32_t pre
= offset
- first_page_offset
;
808 res
= target_read_memory(bank
->target
,
817 /* Fill in main contents of buffer */
818 memcpy(buffer_to_flash
+pre
, buffer
, count
);
820 /* Fill in any space between end of buffer and end of last page */
821 uint32_t post
= last_page_offset
- (offset
+count
);
823 /* Retrieve the full row contents from Flash */
824 res
= target_read_memory(bank
->target
,
828 buffer_to_flash
+pre
+count
);
833 return nrf5_write_pages(bank
, first_page_offset
, last_page_offset
, buffer_to_flash
);
836 static int nrf5_uicr_flash_write(struct flash_bank
*bank
,
837 struct nrf5_info
*chip
,
838 const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
841 uint8_t uicr
[NRF5_UICR_SIZE
];
842 struct flash_sector
*sector
= &bank
->sectors
[0];
844 if ((offset
+ count
) > NRF5_UICR_SIZE
)
847 res
= target_read_memory(bank
->target
,
856 res
= nrf5_erase_page(bank
, chip
, sector
);
860 res
= nrf5_nvmc_write_enable(chip
);
864 memcpy(&uicr
[offset
], buffer
, count
);
866 res
= nrf5_ll_flash_write(chip
, NRF5_UICR_BASE
, uicr
, NRF5_UICR_SIZE
);
867 if (res
!= ERROR_OK
) {
868 nrf5_nvmc_read_only(chip
);
872 return nrf5_nvmc_read_only(chip
);
876 static int nrf5_write(struct flash_bank
*bank
, const uint8_t *buffer
,
877 uint32_t offset
, uint32_t count
)
880 struct nrf5_bank
*nbank
= bank
->driver_priv
;
881 struct nrf5_info
*chip
;
883 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
887 return nbank
->write(bank
, chip
, buffer
, offset
, count
);
890 static void nrf5_free_driver_priv(struct flash_bank
*bank
)
892 struct nrf5_bank
*nbank
= bank
->driver_priv
;
893 struct nrf5_info
*chip
= nbank
->chip
;
898 if (chip
->refcount
== 0) {
900 bank
->driver_priv
= NULL
;
904 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command
)
906 static struct nrf5_info
*chip
;
907 struct nrf5_bank
*nbank
= NULL
;
909 switch (bank
->base
) {
910 case NRF5_FLASH_BASE
:
914 LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT
, bank
->base
);
919 /* Create a new chip */
920 chip
= calloc(1, sizeof(*chip
));
924 chip
->target
= bank
->target
;
927 switch (bank
->base
) {
928 case NRF5_FLASH_BASE
:
929 nbank
= &chip
->bank
[0];
930 nbank
->write
= nrf5_code_flash_write
;
933 nbank
= &chip
->bank
[1];
934 nbank
->write
= nrf5_uicr_flash_write
;
937 assert(nbank
!= NULL
);
941 nbank
->probed
= false;
942 bank
->driver_priv
= nbank
;
947 COMMAND_HANDLER(nrf5_handle_mass_erase_command
)
950 struct flash_bank
*bank
= NULL
;
951 struct target
*target
= get_current_target(CMD_CTX
);
953 res
= get_flash_bank_by_addr(target
, NRF5_FLASH_BASE
, true, &bank
);
957 assert(bank
!= NULL
);
959 struct nrf5_info
*chip
;
961 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
967 res
= target_read_u32(target
, NRF5_FICR_PPFC
,
969 if (res
!= ERROR_OK
) {
970 LOG_ERROR("Couldn't read PPFC register");
974 if ((ppfc
& 0xFF) == 0x00) {
975 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
976 "mass erase command won't work.");
980 res
= nrf5_erase_all(chip
);
981 if (res
!= ERROR_OK
) {
982 LOG_ERROR("Failed to erase the chip");
983 nrf5_protect_check(bank
);
987 res
= nrf5_protect_check(bank
);
988 if (res
!= ERROR_OK
) {
989 LOG_ERROR("Failed to check chip's write protection");
993 res
= get_flash_bank_by_addr(target
, NRF5_UICR_BASE
, true, &bank
);
1000 static int nrf5_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1004 struct nrf5_info
*chip
;
1006 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
1007 if (res
!= ERROR_OK
)
1011 const uint32_t address
;
1014 { .address
= NRF5_FICR_CODEPAGESIZE
},
1015 { .address
= NRF5_FICR_CODESIZE
},
1016 { .address
= NRF5_FICR_CLENR0
},
1017 { .address
= NRF5_FICR_PPFC
},
1018 { .address
= NRF5_FICR_NUMRAMBLOCK
},
1019 { .address
= NRF5_FICR_SIZERAMBLOCK0
},
1020 { .address
= NRF5_FICR_SIZERAMBLOCK1
},
1021 { .address
= NRF5_FICR_SIZERAMBLOCK2
},
1022 { .address
= NRF5_FICR_SIZERAMBLOCK3
},
1023 { .address
= NRF5_FICR_CONFIGID
},
1024 { .address
= NRF5_FICR_DEVICEID0
},
1025 { .address
= NRF5_FICR_DEVICEID1
},
1026 { .address
= NRF5_FICR_ER0
},
1027 { .address
= NRF5_FICR_ER1
},
1028 { .address
= NRF5_FICR_ER2
},
1029 { .address
= NRF5_FICR_ER3
},
1030 { .address
= NRF5_FICR_IR0
},
1031 { .address
= NRF5_FICR_IR1
},
1032 { .address
= NRF5_FICR_IR2
},
1033 { .address
= NRF5_FICR_IR3
},
1034 { .address
= NRF5_FICR_DEVICEADDRTYPE
},
1035 { .address
= NRF5_FICR_DEVICEADDR0
},
1036 { .address
= NRF5_FICR_DEVICEADDR1
},
1037 { .address
= NRF5_FICR_OVERRIDEN
},
1038 { .address
= NRF5_FICR_NRF_1MBIT0
},
1039 { .address
= NRF5_FICR_NRF_1MBIT1
},
1040 { .address
= NRF5_FICR_NRF_1MBIT2
},
1041 { .address
= NRF5_FICR_NRF_1MBIT3
},
1042 { .address
= NRF5_FICR_NRF_1MBIT4
},
1043 { .address
= NRF5_FICR_BLE_1MBIT0
},
1044 { .address
= NRF5_FICR_BLE_1MBIT1
},
1045 { .address
= NRF5_FICR_BLE_1MBIT2
},
1046 { .address
= NRF5_FICR_BLE_1MBIT3
},
1047 { .address
= NRF5_FICR_BLE_1MBIT4
},
1049 { .address
= NRF5_UICR_CLENR0
, },
1050 { .address
= NRF5_UICR_RBPCONF
},
1051 { .address
= NRF5_UICR_XTALFREQ
},
1052 { .address
= NRF5_UICR_FWID
},
1055 for (size_t i
= 0; i
< ARRAY_SIZE(ficr
); i
++) {
1056 res
= target_read_u32(chip
->target
, ficr
[i
].address
,
1058 if (res
!= ERROR_OK
) {
1059 LOG_ERROR("Couldn't read %" PRIx32
, ficr
[i
].address
);
1064 for (size_t i
= 0; i
< ARRAY_SIZE(uicr
); i
++) {
1065 res
= target_read_u32(chip
->target
, uicr
[i
].address
,
1067 if (res
!= ERROR_OK
) {
1068 LOG_ERROR("Couldn't read %" PRIx32
, uicr
[i
].address
);
1073 snprintf(buf
, buf_size
,
1074 "\n[factory information control block]\n\n"
1075 "code page size: %"PRIu32
"B\n"
1076 "code memory size: %"PRIu32
"kB\n"
1077 "code region 0 size: %"PRIu32
"kB\n"
1078 "pre-programmed code: %s\n"
1079 "number of ram blocks: %"PRIu32
"\n"
1080 "ram block 0 size: %"PRIu32
"B\n"
1081 "ram block 1 size: %"PRIu32
"B\n"
1082 "ram block 2 size: %"PRIu32
"B\n"
1083 "ram block 3 size: %"PRIu32
"B\n"
1084 "config id: %" PRIx32
"\n"
1085 "device id: 0x%"PRIx32
"%08"PRIx32
"\n"
1086 "encryption root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1087 "identity root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1088 "device address type: 0x%"PRIx32
"\n"
1089 "device address: 0x%"PRIx32
"%08"PRIx32
"\n"
1090 "override enable: %"PRIx32
"\n"
1091 "NRF_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1092 "BLE_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1093 "\n[user information control block]\n\n"
1094 "code region 0 size: %"PRIu32
"kB\n"
1095 "read back protection configuration: %"PRIx32
"\n"
1096 "reset value for XTALFREQ: %"PRIx32
"\n"
1097 "firmware id: 0x%04"PRIx32
,
1099 (ficr
[1].value
* ficr
[0].value
) / 1024,
1100 (ficr
[2].value
== 0xFFFFFFFF) ? 0 : ficr
[2].value
/ 1024,
1101 ((ficr
[3].value
& 0xFF) == 0x00) ? "present" : "not present",
1104 (ficr
[6].value
== 0xFFFFFFFF) ? 0 : ficr
[6].value
,
1105 (ficr
[7].value
== 0xFFFFFFFF) ? 0 : ficr
[7].value
,
1106 (ficr
[8].value
== 0xFFFFFFFF) ? 0 : ficr
[8].value
,
1108 ficr
[10].value
, ficr
[11].value
,
1109 ficr
[12].value
, ficr
[13].value
, ficr
[14].value
, ficr
[15].value
,
1110 ficr
[16].value
, ficr
[17].value
, ficr
[18].value
, ficr
[19].value
,
1112 ficr
[21].value
, ficr
[22].value
,
1114 ficr
[24].value
, ficr
[25].value
, ficr
[26].value
, ficr
[27].value
, ficr
[28].value
,
1115 ficr
[29].value
, ficr
[30].value
, ficr
[31].value
, ficr
[32].value
, ficr
[33].value
,
1116 (uicr
[0].value
== 0xFFFFFFFF) ? 0 : uicr
[0].value
/ 1024,
1117 uicr
[1].value
& 0xFFFF,
1118 uicr
[2].value
& 0xFF,
1119 uicr
[3].value
& 0xFFFF);
1124 static const struct command_registration nrf5_exec_command_handlers
[] = {
1126 .name
= "mass_erase",
1127 .handler
= nrf5_handle_mass_erase_command
,
1128 .mode
= COMMAND_EXEC
,
1129 .help
= "Erase all flash contents of the chip.",
1132 COMMAND_REGISTRATION_DONE
1135 static const struct command_registration nrf5_command_handlers
[] = {
1138 .mode
= COMMAND_ANY
,
1139 .help
= "nrf5 flash command group",
1141 .chain
= nrf5_exec_command_handlers
,
1145 .mode
= COMMAND_ANY
,
1146 .help
= "nrf51 flash command group",
1148 .chain
= nrf5_exec_command_handlers
,
1150 COMMAND_REGISTRATION_DONE
1153 const struct flash_driver nrf5_flash
= {
1155 .commands
= nrf5_command_handlers
,
1156 .flash_bank_command
= nrf5_flash_bank_command
,
1158 .erase
= nrf5_erase
,
1159 .protect
= nrf5_protect
,
1160 .write
= nrf5_write
,
1161 .read
= default_flash_read
,
1162 .probe
= nrf5_probe
,
1163 .auto_probe
= nrf5_auto_probe
,
1164 .erase_check
= default_flash_blank_check
,
1165 .protect_check
= nrf5_protect_check
,
1166 .free_driver_priv
= nrf5_free_driver_priv
,
1169 /* We need to retain the flash-driver name as well as the commands
1170 * for backwards compatability */
1171 const struct flash_driver nrf51_flash
= {
1173 .commands
= nrf5_command_handlers
,
1174 .flash_bank_command
= nrf5_flash_bank_command
,
1176 .erase
= nrf5_erase
,
1177 .protect
= nrf5_protect
,
1178 .write
= nrf5_write
,
1179 .read
= default_flash_read
,
1180 .probe
= nrf5_probe
,
1181 .auto_probe
= nrf5_auto_probe
,
1182 .erase_check
= default_flash_blank_check
,
1183 .protect_check
= nrf5_protect_check
,
1184 .free_driver_priv
= nrf5_free_driver_priv
,
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