1 /***************************************************************************
2 * Copyright (C) 2013 Synapse Product Development *
3 * Andrey Smirnov <andrew.smironv@gmail.com> *
4 * Angus Gratton <gus@projectgus.com> *
5 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
19 ***************************************************************************/
26 #include <target/algorithm.h>
27 #include <target/armv7m.h>
28 #include <helper/types.h>
29 #include <helper/time_support.h>
32 NRF5_FLASH_BASE
= 0x00000000,
35 enum nrf5_ficr_registers
{
36 NRF5_FICR_BASE
= 0x10000000, /* Factory Information Configuration Registers */
38 #define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
40 NRF5_FICR_CODEPAGESIZE
= NRF5_FICR_REG(0x010),
41 NRF5_FICR_CODESIZE
= NRF5_FICR_REG(0x014),
42 NRF5_FICR_CLENR0
= NRF5_FICR_REG(0x028),
43 NRF5_FICR_PPFC
= NRF5_FICR_REG(0x02C),
44 NRF5_FICR_NUMRAMBLOCK
= NRF5_FICR_REG(0x034),
45 NRF5_FICR_SIZERAMBLOCK0
= NRF5_FICR_REG(0x038),
46 NRF5_FICR_SIZERAMBLOCK1
= NRF5_FICR_REG(0x03C),
47 NRF5_FICR_SIZERAMBLOCK2
= NRF5_FICR_REG(0x040),
48 NRF5_FICR_SIZERAMBLOCK3
= NRF5_FICR_REG(0x044),
49 NRF5_FICR_CONFIGID
= NRF5_FICR_REG(0x05C),
50 NRF5_FICR_DEVICEID0
= NRF5_FICR_REG(0x060),
51 NRF5_FICR_DEVICEID1
= NRF5_FICR_REG(0x064),
52 NRF5_FICR_ER0
= NRF5_FICR_REG(0x080),
53 NRF5_FICR_ER1
= NRF5_FICR_REG(0x084),
54 NRF5_FICR_ER2
= NRF5_FICR_REG(0x088),
55 NRF5_FICR_ER3
= NRF5_FICR_REG(0x08C),
56 NRF5_FICR_IR0
= NRF5_FICR_REG(0x090),
57 NRF5_FICR_IR1
= NRF5_FICR_REG(0x094),
58 NRF5_FICR_IR2
= NRF5_FICR_REG(0x098),
59 NRF5_FICR_IR3
= NRF5_FICR_REG(0x09C),
60 NRF5_FICR_DEVICEADDRTYPE
= NRF5_FICR_REG(0x0A0),
61 NRF5_FICR_DEVICEADDR0
= NRF5_FICR_REG(0x0A4),
62 NRF5_FICR_DEVICEADDR1
= NRF5_FICR_REG(0x0A8),
63 NRF5_FICR_OVERRIDEN
= NRF5_FICR_REG(0x0AC),
64 NRF5_FICR_NRF_1MBIT0
= NRF5_FICR_REG(0x0B0),
65 NRF5_FICR_NRF_1MBIT1
= NRF5_FICR_REG(0x0B4),
66 NRF5_FICR_NRF_1MBIT2
= NRF5_FICR_REG(0x0B8),
67 NRF5_FICR_NRF_1MBIT3
= NRF5_FICR_REG(0x0BC),
68 NRF5_FICR_NRF_1MBIT4
= NRF5_FICR_REG(0x0C0),
69 NRF5_FICR_BLE_1MBIT0
= NRF5_FICR_REG(0x0EC),
70 NRF5_FICR_BLE_1MBIT1
= NRF5_FICR_REG(0x0F0),
71 NRF5_FICR_BLE_1MBIT2
= NRF5_FICR_REG(0x0F4),
72 NRF5_FICR_BLE_1MBIT3
= NRF5_FICR_REG(0x0F8),
73 NRF5_FICR_BLE_1MBIT4
= NRF5_FICR_REG(0x0FC),
76 enum nrf5_uicr_registers
{
77 NRF5_UICR_BASE
= 0x10001000, /* User Information
78 * Configuration Regsters */
80 NRF5_UICR_SIZE
= 0x100,
82 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
84 NRF5_UICR_CLENR0
= NRF5_UICR_REG(0x000),
85 NRF5_UICR_RBPCONF
= NRF5_UICR_REG(0x004),
86 NRF5_UICR_XTALFREQ
= NRF5_UICR_REG(0x008),
87 NRF5_UICR_FWID
= NRF5_UICR_REG(0x010),
90 enum nrf5_nvmc_registers
{
91 NRF5_NVMC_BASE
= 0x4001E000, /* Non-Volatile Memory
92 * Controller Regsters */
94 #define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
96 NRF5_NVMC_READY
= NRF5_NVMC_REG(0x400),
97 NRF5_NVMC_CONFIG
= NRF5_NVMC_REG(0x504),
98 NRF5_NVMC_ERASEPAGE
= NRF5_NVMC_REG(0x508),
99 NRF5_NVMC_ERASEALL
= NRF5_NVMC_REG(0x50C),
100 NRF5_NVMC_ERASEUICR
= NRF5_NVMC_REG(0x514),
103 enum nrf5_nvmc_config_bits
{
104 NRF5_NVMC_CONFIG_REN
= 0x00,
105 NRF5_NVMC_CONFIG_WEN
= 0x01,
106 NRF5_NVMC_CONFIG_EEN
= 0x02,
111 uint32_t code_page_size
;
115 struct nrf5_info
*chip
;
117 int (*write
) (struct flash_bank
*bank
,
118 struct nrf5_info
*chip
,
119 const uint8_t *buffer
, uint32_t offset
, uint32_t count
);
121 struct target
*target
;
124 struct nrf5_device_spec
{
128 const char *build_code
;
129 unsigned int flash_size_kb
;
132 #define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize) \
137 .build_code = bcode, \
138 .flash_size_kb = (fsize), \
141 /* The known devices table below is derived from the "nRF5x series
142 * compatibility matrix" documents, which can be found in the "DocLib" of
145 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51422_ic_revision_overview
146 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51822_ic_revision_overview
147 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51824_ic_revision_overview
148 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52810/latest/COMP/nrf52810/nRF52810_ic_revision_overview
149 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52832/latest/COMP/nrf52832/ic_revision_overview
150 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52840/latest/COMP/nrf52840/nRF52840_ic_revision_overview
152 * Up to date with Matrix v2.0, plus some additional HWIDs.
154 * The additional HWIDs apply where the build code in the matrix is
155 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
156 * for x==0, x!=0 means different (unspecified) HWIDs.
158 static const struct nrf5_device_spec nrf5_known_devices_table
[] = {
159 /* nRF51822 Devices (IC rev 1). */
160 NRF5_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
161 NRF5_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
162 NRF5_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
163 NRF5_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
164 NRF5_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
166 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
167 with built-in jlink seem to use engineering samples not listed
168 in the nRF51 Series Compatibility Matrix V1.0. */
169 NRF5_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
171 /* nRF51822 Devices (IC rev 2). */
172 NRF5_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
173 NRF5_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
174 NRF5_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
175 NRF5_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
176 NRF5_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
177 NRF5_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
178 NRF5_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
179 NRF5_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
180 NRF5_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
182 /* nRF51822 Devices (IC rev 3). */
183 NRF5_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
184 NRF5_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
185 NRF5_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
186 NRF5_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
187 NRF5_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
188 NRF5_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
189 NRF5_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
190 NRF5_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
191 NRF5_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
193 /* nRF51422 Devices (IC rev 1). */
194 NRF5_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
195 NRF5_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
196 NRF5_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
198 /* nRF51422 Devices (IC rev 2). */
199 NRF5_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
200 NRF5_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
201 NRF5_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
202 NRF5_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
204 /* nRF51422 Devices (IC rev 3). */
205 NRF5_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
206 NRF5_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
207 NRF5_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
208 NRF5_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
209 NRF5_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
210 NRF5_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
211 NRF5_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
213 /* nRF52810 Devices */
214 NRF5_DEVICE_DEF(0x0142, "52810", "QFAA", "B0", 192),
215 NRF5_DEVICE_DEF(0x0143, "52810", "QCAA", "C0", 192),
217 /* nRF52832 Devices */
218 NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0", 512),
219 NRF5_DEVICE_DEF(0x0139, "52832", "QFAA", "E0", 512),
220 NRF5_DEVICE_DEF(0x00E3, "52832", "CIAA", "B0", 512),
222 /* nRF52840 Devices */
223 NRF5_DEVICE_DEF(0x0150, "52840", "QIAA", "C0", 1024),
226 static int nrf5_bank_is_probed(struct flash_bank
*bank
)
228 struct nrf5_bank
*nbank
= bank
->driver_priv
;
230 assert(nbank
!= NULL
);
232 return nbank
->probed
;
234 static int nrf5_probe(struct flash_bank
*bank
);
236 static int nrf5_get_probed_chip_if_halted(struct flash_bank
*bank
, struct nrf5_info
**chip
)
238 if (bank
->target
->state
!= TARGET_HALTED
) {
239 LOG_ERROR("Target not halted");
240 return ERROR_TARGET_NOT_HALTED
;
243 struct nrf5_bank
*nbank
= bank
->driver_priv
;
246 int probed
= nrf5_bank_is_probed(bank
);
250 return nrf5_probe(bank
);
255 static int nrf5_wait_for_nvmc(struct nrf5_info
*chip
)
259 int timeout_ms
= 340;
260 int64_t ts_start
= timeval_ms();
263 res
= target_read_u32(chip
->target
, NRF5_NVMC_READY
, &ready
);
264 if (res
!= ERROR_OK
) {
265 LOG_ERROR("Couldn't read NVMC_READY register");
269 if (ready
== 0x00000001)
274 } while ((timeval_ms()-ts_start
) < timeout_ms
);
276 LOG_DEBUG("Timed out waiting for NVMC_READY");
277 return ERROR_FLASH_BUSY
;
280 static int nrf5_nvmc_erase_enable(struct nrf5_info
*chip
)
283 res
= target_write_u32(chip
->target
,
285 NRF5_NVMC_CONFIG_EEN
);
287 if (res
!= ERROR_OK
) {
288 LOG_ERROR("Failed to enable erase operation");
293 According to NVMC examples in Nordic SDK busy status must be
294 checked after writing to NVMC_CONFIG
296 res
= nrf5_wait_for_nvmc(chip
);
298 LOG_ERROR("Erase enable did not complete");
303 static int nrf5_nvmc_write_enable(struct nrf5_info
*chip
)
306 res
= target_write_u32(chip
->target
,
308 NRF5_NVMC_CONFIG_WEN
);
310 if (res
!= ERROR_OK
) {
311 LOG_ERROR("Failed to enable write operation");
316 According to NVMC examples in Nordic SDK busy status must be
317 checked after writing to NVMC_CONFIG
319 res
= nrf5_wait_for_nvmc(chip
);
321 LOG_ERROR("Write enable did not complete");
326 static int nrf5_nvmc_read_only(struct nrf5_info
*chip
)
329 res
= target_write_u32(chip
->target
,
331 NRF5_NVMC_CONFIG_REN
);
333 if (res
!= ERROR_OK
) {
334 LOG_ERROR("Failed to enable read-only operation");
338 According to NVMC examples in Nordic SDK busy status must be
339 checked after writing to NVMC_CONFIG
341 res
= nrf5_wait_for_nvmc(chip
);
343 LOG_ERROR("Read only enable did not complete");
348 static int nrf5_nvmc_generic_erase(struct nrf5_info
*chip
,
349 uint32_t erase_register
, uint32_t erase_value
)
353 res
= nrf5_nvmc_erase_enable(chip
);
357 res
= target_write_u32(chip
->target
,
363 res
= nrf5_wait_for_nvmc(chip
);
367 return nrf5_nvmc_read_only(chip
);
370 nrf5_nvmc_read_only(chip
);
372 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32
" val: 0x%08"PRIx32
,
373 erase_register
, erase_value
);
377 static int nrf5_protect_check(struct flash_bank
*bank
)
382 /* UICR cannot be write protected so just return early */
383 if (bank
->base
== NRF5_UICR_BASE
)
386 struct nrf5_bank
*nbank
= bank
->driver_priv
;
387 struct nrf5_info
*chip
= nbank
->chip
;
389 assert(chip
!= NULL
);
391 res
= target_read_u32(chip
->target
, NRF5_FICR_CLENR0
,
393 if (res
!= ERROR_OK
) {
394 LOG_ERROR("Couldn't read code region 0 size[FICR]");
398 if (clenr0
== 0xFFFFFFFF) {
399 res
= target_read_u32(chip
->target
, NRF5_UICR_CLENR0
,
401 if (res
!= ERROR_OK
) {
402 LOG_ERROR("Couldn't read code region 0 size[UICR]");
407 for (int i
= 0; i
< bank
->num_sectors
; i
++)
408 bank
->sectors
[i
].is_protected
=
409 clenr0
!= 0xFFFFFFFF && bank
->sectors
[i
].offset
< clenr0
;
414 static int nrf5_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
417 uint32_t clenr0
, ppfc
;
418 struct nrf5_info
*chip
;
420 /* UICR cannot be write protected so just bail out early */
421 if (bank
->base
== NRF5_UICR_BASE
)
424 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
429 LOG_ERROR("Code region 0 must start at the begining of the bank");
433 res
= target_read_u32(chip
->target
, NRF5_FICR_PPFC
,
435 if (res
!= ERROR_OK
) {
436 LOG_ERROR("Couldn't read PPFC register");
440 if ((ppfc
& 0xFF) == 0x00) {
441 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
445 res
= target_read_u32(chip
->target
, NRF5_UICR_CLENR0
,
447 if (res
!= ERROR_OK
) {
448 LOG_ERROR("Couldn't read code region 0 size[UICR]");
452 if (clenr0
== 0xFFFFFFFF) {
453 res
= target_write_u32(chip
->target
, NRF5_UICR_CLENR0
,
455 if (res
!= ERROR_OK
) {
456 LOG_ERROR("Couldn't write code region 0 size[UICR]");
461 LOG_ERROR("You need to perform chip erase before changing the protection settings");
464 nrf5_protect_check(bank
);
469 static int nrf5_probe(struct flash_bank
*bank
)
473 struct nrf5_bank
*nbank
= bank
->driver_priv
;
474 struct nrf5_info
*chip
= nbank
->chip
;
476 res
= target_read_u32(chip
->target
, NRF5_FICR_CONFIGID
, &hwid
);
477 if (res
!= ERROR_OK
) {
478 LOG_ERROR("Couldn't read CONFIGID register");
482 hwid
&= 0xFFFF; /* HWID is stored in the lower two
483 * bytes of the CONFIGID register */
485 const struct nrf5_device_spec
*spec
= NULL
;
486 for (size_t i
= 0; i
< ARRAY_SIZE(nrf5_known_devices_table
); i
++) {
487 if (hwid
== nrf5_known_devices_table
[i
].hwid
) {
488 spec
= &nrf5_known_devices_table
[i
];
493 if (!chip
->bank
[0].probed
&& !chip
->bank
[1].probed
) {
495 LOG_INFO("nRF%s-%s(build code: %s) %ukB Flash",
496 spec
->part
, spec
->variant
, spec
->build_code
,
497 spec
->flash_size_kb
);
499 LOG_WARNING("Unknown device (HWID 0x%08" PRIx32
")", hwid
);
502 if (bank
->base
== NRF5_FLASH_BASE
) {
503 /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
504 res
= target_read_u32(chip
->target
, NRF5_FICR_CODEPAGESIZE
,
505 &chip
->code_page_size
);
506 if (res
!= ERROR_OK
) {
507 LOG_ERROR("Couldn't read code page size");
511 /* Note the register name is misleading,
512 * NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
513 uint32_t num_sectors
;
514 res
= target_read_u32(chip
->target
, NRF5_FICR_CODESIZE
, &num_sectors
);
515 if (res
!= ERROR_OK
) {
516 LOG_ERROR("Couldn't read code memory size");
520 bank
->num_sectors
= num_sectors
;
521 bank
->size
= num_sectors
* chip
->code_page_size
;
523 if (spec
&& bank
->size
/ 1024 != spec
->flash_size_kb
)
524 LOG_WARNING("Chip's reported Flash capacity does not match expected one");
526 bank
->sectors
= calloc(bank
->num_sectors
,
527 sizeof((bank
->sectors
)[0]));
529 return ERROR_FLASH_BANK_NOT_PROBED
;
531 /* Fill out the sector information: all NRF5 sectors are the same size and
532 * there is always a fixed number of them. */
533 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
534 bank
->sectors
[i
].size
= chip
->code_page_size
;
535 bank
->sectors
[i
].offset
= i
* chip
->code_page_size
;
537 /* mark as unknown */
538 bank
->sectors
[i
].is_erased
= -1;
539 bank
->sectors
[i
].is_protected
= -1;
542 nrf5_protect_check(bank
);
544 chip
->bank
[0].probed
= true;
546 bank
->size
= NRF5_UICR_SIZE
;
547 bank
->num_sectors
= 1;
548 bank
->sectors
= calloc(bank
->num_sectors
,
549 sizeof((bank
->sectors
)[0]));
551 return ERROR_FLASH_BANK_NOT_PROBED
;
553 bank
->sectors
[0].size
= bank
->size
;
554 bank
->sectors
[0].offset
= 0;
556 bank
->sectors
[0].is_erased
= 0;
557 bank
->sectors
[0].is_protected
= 0;
559 chip
->bank
[1].probed
= true;
565 static int nrf5_auto_probe(struct flash_bank
*bank
)
567 int probed
= nrf5_bank_is_probed(bank
);
574 return nrf5_probe(bank
);
577 static int nrf5_erase_all(struct nrf5_info
*chip
)
579 LOG_DEBUG("Erasing all non-volatile memory");
580 return nrf5_nvmc_generic_erase(chip
,
585 static int nrf5_erase_page(struct flash_bank
*bank
,
586 struct nrf5_info
*chip
,
587 struct flash_sector
*sector
)
591 LOG_DEBUG("Erasing page at 0x%"PRIx32
, sector
->offset
);
592 if (sector
->is_protected
) {
593 LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32
, sector
->offset
);
597 if (bank
->base
== NRF5_UICR_BASE
) {
599 res
= target_read_u32(chip
->target
, NRF5_FICR_PPFC
,
601 if (res
!= ERROR_OK
) {
602 LOG_ERROR("Couldn't read PPFC register");
606 if ((ppfc
& 0xFF) == 0xFF) {
607 /* We can't erase the UICR. Double-check to
608 see if it's already erased before complaining. */
609 default_flash_blank_check(bank
);
610 if (sector
->is_erased
== 1)
613 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
617 res
= nrf5_nvmc_generic_erase(chip
,
623 res
= nrf5_nvmc_generic_erase(chip
,
631 static const uint8_t nrf5_flash_write_code
[] = {
632 /* See contrib/loaders/flash/cortex-m0.S */
634 0x0d, 0x68, /* ldr r5, [r1, #0] */
635 0x00, 0x2d, /* cmp r5, #0 */
636 0x0b, 0xd0, /* beq.n 1e <exit> */
637 0x4c, 0x68, /* ldr r4, [r1, #4] */
638 0xac, 0x42, /* cmp r4, r5 */
639 0xf9, 0xd0, /* beq.n 0 <wait_fifo> */
640 0x20, 0xcc, /* ldmia r4!, {r5} */
641 0x20, 0xc3, /* stmia r3!, {r5} */
642 0x94, 0x42, /* cmp r4, r2 */
643 0x01, 0xd3, /* bcc.n 18 <no_wrap> */
644 0x0c, 0x46, /* mov r4, r1 */
645 0x08, 0x34, /* adds r4, #8 */
647 0x4c, 0x60, /* str r4, [r1, #4] */
648 0x04, 0x38, /* subs r0, #4 */
649 0xf0, 0xd1, /* bne.n 0 <wait_fifo> */
651 0x00, 0xbe /* bkpt 0x0000 */
655 /* Start a low level flash write for the specified region */
656 static int nrf5_ll_flash_write(struct nrf5_info
*chip
, uint32_t offset
, const uint8_t *buffer
, uint32_t bytes
)
658 struct target
*target
= chip
->target
;
659 uint32_t buffer_size
= 8192;
660 struct working_area
*write_algorithm
;
661 struct working_area
*source
;
662 uint32_t address
= NRF5_FLASH_BASE
+ offset
;
663 struct reg_param reg_params
[4];
664 struct armv7m_algorithm armv7m_info
;
665 int retval
= ERROR_OK
;
668 LOG_DEBUG("Writing buffer to flash offset=0x%"PRIx32
" bytes=0x%"PRIx32
, offset
, bytes
);
669 assert(bytes
% 4 == 0);
671 /* allocate working area with flash programming code */
672 if (target_alloc_working_area(target
, sizeof(nrf5_flash_write_code
),
673 &write_algorithm
) != ERROR_OK
) {
674 LOG_WARNING("no working area available, falling back to slow memory writes");
676 for (; bytes
> 0; bytes
-= 4) {
677 retval
= target_write_memory(chip
->target
, offset
, 4, 1, buffer
);
678 if (retval
!= ERROR_OK
)
681 retval
= nrf5_wait_for_nvmc(chip
);
682 if (retval
!= ERROR_OK
)
692 LOG_WARNING("using fast async flash loader. This is currently supported");
693 LOG_WARNING("only with ST-Link and CMSIS-DAP. If you have issues, add");
694 LOG_WARNING("\"set WORKAREASIZE 0\" before sourcing nrf51.cfg/nrf52.cfg to disable it");
696 retval
= target_write_buffer(target
, write_algorithm
->address
,
697 sizeof(nrf5_flash_write_code
),
698 nrf5_flash_write_code
);
699 if (retval
!= ERROR_OK
)
703 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
) {
705 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
706 if (buffer_size
<= 256) {
707 /* free working area, write algorithm already allocated */
708 target_free_working_area(target
, write_algorithm
);
710 LOG_WARNING("No large enough working area available, can't do block memory writes");
711 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
715 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
716 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
718 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* byte count */
719 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer start */
720 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer end */
721 init_reg_param(®_params
[3], "r3", 32, PARAM_IN_OUT
); /* target address */
723 buf_set_u32(reg_params
[0].value
, 0, 32, bytes
);
724 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
725 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
+ source
->size
);
726 buf_set_u32(reg_params
[3].value
, 0, 32, address
);
728 retval
= target_run_flash_async_algorithm(target
, buffer
, bytes
/4, 4,
731 source
->address
, source
->size
,
732 write_algorithm
->address
, 0,
735 target_free_working_area(target
, source
);
736 target_free_working_area(target
, write_algorithm
);
738 destroy_reg_param(®_params
[0]);
739 destroy_reg_param(®_params
[1]);
740 destroy_reg_param(®_params
[2]);
741 destroy_reg_param(®_params
[3]);
746 /* Check and erase flash sectors in specified range then start a low level page write.
747 start/end must be sector aligned.
749 static int nrf5_write_pages(struct flash_bank
*bank
, uint32_t start
, uint32_t end
, const uint8_t *buffer
)
751 int res
= ERROR_FAIL
;
752 struct nrf5_bank
*nbank
= bank
->driver_priv
;
753 struct nrf5_info
*chip
= nbank
->chip
;
755 assert(start
% chip
->code_page_size
== 0);
756 assert(end
% chip
->code_page_size
== 0);
758 res
= nrf5_nvmc_write_enable(chip
);
762 res
= nrf5_ll_flash_write(chip
, start
, buffer
, (end
- start
));
766 return nrf5_nvmc_read_only(chip
);
769 nrf5_nvmc_read_only(chip
);
770 LOG_ERROR("Failed to write to nrf5 flash");
774 static int nrf5_erase(struct flash_bank
*bank
, int first
, int last
)
777 struct nrf5_info
*chip
;
779 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
783 /* For each sector to be erased */
784 for (int s
= first
; s
<= last
&& res
== ERROR_OK
; s
++)
785 res
= nrf5_erase_page(bank
, chip
, &bank
->sectors
[s
]);
790 static int nrf5_code_flash_write(struct flash_bank
*bank
,
791 struct nrf5_info
*chip
,
792 const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
796 /* Need to perform reads to fill any gaps we need to preserve in the first page,
797 before the start of buffer, or in the last page, after the end of buffer */
798 uint32_t first_page
= offset
/chip
->code_page_size
;
799 uint32_t last_page
= DIV_ROUND_UP(offset
+count
, chip
->code_page_size
);
801 uint32_t first_page_offset
= first_page
* chip
->code_page_size
;
802 uint32_t last_page_offset
= last_page
* chip
->code_page_size
;
804 LOG_DEBUG("Padding write from 0x%08"PRIx32
"-0x%08"PRIx32
" as 0x%08"PRIx32
"-0x%08"PRIx32
,
805 offset
, offset
+count
, first_page_offset
, last_page_offset
);
807 uint32_t page_cnt
= last_page
- first_page
;
808 uint8_t buffer_to_flash
[page_cnt
*chip
->code_page_size
];
810 /* Fill in any space between start of first page and start of buffer */
811 uint32_t pre
= offset
- first_page_offset
;
813 res
= target_read_memory(bank
->target
,
822 /* Fill in main contents of buffer */
823 memcpy(buffer_to_flash
+pre
, buffer
, count
);
825 /* Fill in any space between end of buffer and end of last page */
826 uint32_t post
= last_page_offset
- (offset
+count
);
828 /* Retrieve the full row contents from Flash */
829 res
= target_read_memory(bank
->target
,
833 buffer_to_flash
+pre
+count
);
838 return nrf5_write_pages(bank
, first_page_offset
, last_page_offset
, buffer_to_flash
);
841 static int nrf5_uicr_flash_write(struct flash_bank
*bank
,
842 struct nrf5_info
*chip
,
843 const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
846 uint8_t uicr
[NRF5_UICR_SIZE
];
847 struct flash_sector
*sector
= &bank
->sectors
[0];
849 if ((offset
+ count
) > NRF5_UICR_SIZE
)
852 res
= target_read_memory(bank
->target
,
861 res
= nrf5_erase_page(bank
, chip
, sector
);
865 res
= nrf5_nvmc_write_enable(chip
);
869 memcpy(&uicr
[offset
], buffer
, count
);
871 res
= nrf5_ll_flash_write(chip
, NRF5_UICR_BASE
, uicr
, NRF5_UICR_SIZE
);
872 if (res
!= ERROR_OK
) {
873 nrf5_nvmc_read_only(chip
);
877 return nrf5_nvmc_read_only(chip
);
881 static int nrf5_write(struct flash_bank
*bank
, const uint8_t *buffer
,
882 uint32_t offset
, uint32_t count
)
885 struct nrf5_bank
*nbank
= bank
->driver_priv
;
886 struct nrf5_info
*chip
;
888 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
892 return nbank
->write(bank
, chip
, buffer
, offset
, count
);
895 static void nrf5_free_driver_priv(struct flash_bank
*bank
)
897 struct nrf5_bank
*nbank
= bank
->driver_priv
;
898 struct nrf5_info
*chip
= nbank
->chip
;
903 if (chip
->refcount
== 0) {
905 bank
->driver_priv
= NULL
;
909 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command
)
911 static struct nrf5_info
*chip
;
912 struct nrf5_bank
*nbank
= NULL
;
914 switch (bank
->base
) {
915 case NRF5_FLASH_BASE
:
919 LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT
, bank
->base
);
924 /* Create a new chip */
925 chip
= calloc(1, sizeof(*chip
));
929 chip
->target
= bank
->target
;
932 switch (bank
->base
) {
933 case NRF5_FLASH_BASE
:
934 nbank
= &chip
->bank
[0];
935 nbank
->write
= nrf5_code_flash_write
;
938 nbank
= &chip
->bank
[1];
939 nbank
->write
= nrf5_uicr_flash_write
;
942 assert(nbank
!= NULL
);
946 nbank
->probed
= false;
947 bank
->driver_priv
= nbank
;
952 COMMAND_HANDLER(nrf5_handle_mass_erase_command
)
955 struct flash_bank
*bank
= NULL
;
956 struct target
*target
= get_current_target(CMD_CTX
);
958 res
= get_flash_bank_by_addr(target
, NRF5_FLASH_BASE
, true, &bank
);
962 assert(bank
!= NULL
);
964 struct nrf5_info
*chip
;
966 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
972 res
= target_read_u32(target
, NRF5_FICR_PPFC
,
974 if (res
!= ERROR_OK
) {
975 LOG_ERROR("Couldn't read PPFC register");
979 if ((ppfc
& 0xFF) == 0x00) {
980 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
981 "mass erase command won't work.");
985 res
= nrf5_erase_all(chip
);
986 if (res
!= ERROR_OK
) {
987 LOG_ERROR("Failed to erase the chip");
988 nrf5_protect_check(bank
);
992 res
= nrf5_protect_check(bank
);
993 if (res
!= ERROR_OK
) {
994 LOG_ERROR("Failed to check chip's write protection");
998 res
= get_flash_bank_by_addr(target
, NRF5_UICR_BASE
, true, &bank
);
1005 static int nrf5_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1009 struct nrf5_info
*chip
;
1011 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
1012 if (res
!= ERROR_OK
)
1016 const uint32_t address
;
1019 { .address
= NRF5_FICR_CODEPAGESIZE
},
1020 { .address
= NRF5_FICR_CODESIZE
},
1021 { .address
= NRF5_FICR_CLENR0
},
1022 { .address
= NRF5_FICR_PPFC
},
1023 { .address
= NRF5_FICR_NUMRAMBLOCK
},
1024 { .address
= NRF5_FICR_SIZERAMBLOCK0
},
1025 { .address
= NRF5_FICR_SIZERAMBLOCK1
},
1026 { .address
= NRF5_FICR_SIZERAMBLOCK2
},
1027 { .address
= NRF5_FICR_SIZERAMBLOCK3
},
1028 { .address
= NRF5_FICR_CONFIGID
},
1029 { .address
= NRF5_FICR_DEVICEID0
},
1030 { .address
= NRF5_FICR_DEVICEID1
},
1031 { .address
= NRF5_FICR_ER0
},
1032 { .address
= NRF5_FICR_ER1
},
1033 { .address
= NRF5_FICR_ER2
},
1034 { .address
= NRF5_FICR_ER3
},
1035 { .address
= NRF5_FICR_IR0
},
1036 { .address
= NRF5_FICR_IR1
},
1037 { .address
= NRF5_FICR_IR2
},
1038 { .address
= NRF5_FICR_IR3
},
1039 { .address
= NRF5_FICR_DEVICEADDRTYPE
},
1040 { .address
= NRF5_FICR_DEVICEADDR0
},
1041 { .address
= NRF5_FICR_DEVICEADDR1
},
1042 { .address
= NRF5_FICR_OVERRIDEN
},
1043 { .address
= NRF5_FICR_NRF_1MBIT0
},
1044 { .address
= NRF5_FICR_NRF_1MBIT1
},
1045 { .address
= NRF5_FICR_NRF_1MBIT2
},
1046 { .address
= NRF5_FICR_NRF_1MBIT3
},
1047 { .address
= NRF5_FICR_NRF_1MBIT4
},
1048 { .address
= NRF5_FICR_BLE_1MBIT0
},
1049 { .address
= NRF5_FICR_BLE_1MBIT1
},
1050 { .address
= NRF5_FICR_BLE_1MBIT2
},
1051 { .address
= NRF5_FICR_BLE_1MBIT3
},
1052 { .address
= NRF5_FICR_BLE_1MBIT4
},
1054 { .address
= NRF5_UICR_CLENR0
, },
1055 { .address
= NRF5_UICR_RBPCONF
},
1056 { .address
= NRF5_UICR_XTALFREQ
},
1057 { .address
= NRF5_UICR_FWID
},
1060 for (size_t i
= 0; i
< ARRAY_SIZE(ficr
); i
++) {
1061 res
= target_read_u32(chip
->target
, ficr
[i
].address
,
1063 if (res
!= ERROR_OK
) {
1064 LOG_ERROR("Couldn't read %" PRIx32
, ficr
[i
].address
);
1069 for (size_t i
= 0; i
< ARRAY_SIZE(uicr
); i
++) {
1070 res
= target_read_u32(chip
->target
, uicr
[i
].address
,
1072 if (res
!= ERROR_OK
) {
1073 LOG_ERROR("Couldn't read %" PRIx32
, uicr
[i
].address
);
1078 snprintf(buf
, buf_size
,
1079 "\n[factory information control block]\n\n"
1080 "code page size: %"PRIu32
"B\n"
1081 "code memory size: %"PRIu32
"kB\n"
1082 "code region 0 size: %"PRIu32
"kB\n"
1083 "pre-programmed code: %s\n"
1084 "number of ram blocks: %"PRIu32
"\n"
1085 "ram block 0 size: %"PRIu32
"B\n"
1086 "ram block 1 size: %"PRIu32
"B\n"
1087 "ram block 2 size: %"PRIu32
"B\n"
1088 "ram block 3 size: %"PRIu32
"B\n"
1089 "config id: %" PRIx32
"\n"
1090 "device id: 0x%"PRIx32
"%08"PRIx32
"\n"
1091 "encryption root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1092 "identity root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1093 "device address type: 0x%"PRIx32
"\n"
1094 "device address: 0x%"PRIx32
"%08"PRIx32
"\n"
1095 "override enable: %"PRIx32
"\n"
1096 "NRF_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1097 "BLE_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1098 "\n[user information control block]\n\n"
1099 "code region 0 size: %"PRIu32
"kB\n"
1100 "read back protection configuration: %"PRIx32
"\n"
1101 "reset value for XTALFREQ: %"PRIx32
"\n"
1102 "firmware id: 0x%04"PRIx32
,
1104 (ficr
[1].value
* ficr
[0].value
) / 1024,
1105 (ficr
[2].value
== 0xFFFFFFFF) ? 0 : ficr
[2].value
/ 1024,
1106 ((ficr
[3].value
& 0xFF) == 0x00) ? "present" : "not present",
1109 (ficr
[6].value
== 0xFFFFFFFF) ? 0 : ficr
[6].value
,
1110 (ficr
[7].value
== 0xFFFFFFFF) ? 0 : ficr
[7].value
,
1111 (ficr
[8].value
== 0xFFFFFFFF) ? 0 : ficr
[8].value
,
1113 ficr
[10].value
, ficr
[11].value
,
1114 ficr
[12].value
, ficr
[13].value
, ficr
[14].value
, ficr
[15].value
,
1115 ficr
[16].value
, ficr
[17].value
, ficr
[18].value
, ficr
[19].value
,
1117 ficr
[21].value
, ficr
[22].value
,
1119 ficr
[24].value
, ficr
[25].value
, ficr
[26].value
, ficr
[27].value
, ficr
[28].value
,
1120 ficr
[29].value
, ficr
[30].value
, ficr
[31].value
, ficr
[32].value
, ficr
[33].value
,
1121 (uicr
[0].value
== 0xFFFFFFFF) ? 0 : uicr
[0].value
/ 1024,
1122 uicr
[1].value
& 0xFFFF,
1123 uicr
[2].value
& 0xFF,
1124 uicr
[3].value
& 0xFFFF);
1129 static const struct command_registration nrf5_exec_command_handlers
[] = {
1131 .name
= "mass_erase",
1132 .handler
= nrf5_handle_mass_erase_command
,
1133 .mode
= COMMAND_EXEC
,
1134 .help
= "Erase all flash contents of the chip.",
1137 COMMAND_REGISTRATION_DONE
1140 static const struct command_registration nrf5_command_handlers
[] = {
1143 .mode
= COMMAND_ANY
,
1144 .help
= "nrf5 flash command group",
1146 .chain
= nrf5_exec_command_handlers
,
1150 .mode
= COMMAND_ANY
,
1151 .help
= "nrf51 flash command group",
1153 .chain
= nrf5_exec_command_handlers
,
1155 COMMAND_REGISTRATION_DONE
1158 const struct flash_driver nrf5_flash
= {
1160 .commands
= nrf5_command_handlers
,
1161 .flash_bank_command
= nrf5_flash_bank_command
,
1163 .erase
= nrf5_erase
,
1164 .protect
= nrf5_protect
,
1165 .write
= nrf5_write
,
1166 .read
= default_flash_read
,
1167 .probe
= nrf5_probe
,
1168 .auto_probe
= nrf5_auto_probe
,
1169 .erase_check
= default_flash_blank_check
,
1170 .protect_check
= nrf5_protect_check
,
1171 .free_driver_priv
= nrf5_free_driver_priv
,
1174 /* We need to retain the flash-driver name as well as the commands
1175 * for backwards compatability */
1176 const struct flash_driver nrf51_flash
= {
1178 .commands
= nrf5_command_handlers
,
1179 .flash_bank_command
= nrf5_flash_bank_command
,
1181 .erase
= nrf5_erase
,
1182 .protect
= nrf5_protect
,
1183 .write
= nrf5_write
,
1184 .read
= default_flash_read
,
1185 .probe
= nrf5_probe
,
1186 .auto_probe
= nrf5_auto_probe
,
1187 .erase_check
= default_flash_blank_check
,
1188 .protect_check
= nrf5_protect_check
,
1189 .free_driver_priv
= nrf5_free_driver_priv
,
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