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flash/nor/nrf5: refactor sector allocation to use alloc_block_array()
[openocd.git] / src / flash / nor / nrf5.c
1 /***************************************************************************
2 * Copyright (C) 2013 Synapse Product Development *
3 * Andrey Smirnov <andrew.smironv@gmail.com> *
4 * Angus Gratton <gus@projectgus.com> *
5 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
19 ***************************************************************************/
20
21 #ifdef HAVE_CONFIG_H
22 #include "config.h"
23 #endif
24
25 #include "imp.h"
26 #include <target/algorithm.h>
27 #include <target/armv7m.h>
28 #include <helper/types.h>
29 #include <helper/time_support.h>
30
31 enum {
32 NRF5_FLASH_BASE = 0x00000000,
33 };
34
35 enum nrf5_ficr_registers {
36 NRF5_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
37
38 #define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
39
40 NRF5_FICR_CODEPAGESIZE = NRF5_FICR_REG(0x010),
41 NRF5_FICR_CODESIZE = NRF5_FICR_REG(0x014),
42 NRF5_FICR_CLENR0 = NRF5_FICR_REG(0x028),
43 NRF5_FICR_PPFC = NRF5_FICR_REG(0x02C),
44 NRF5_FICR_NUMRAMBLOCK = NRF5_FICR_REG(0x034),
45 NRF5_FICR_SIZERAMBLOCK0 = NRF5_FICR_REG(0x038),
46 NRF5_FICR_SIZERAMBLOCK1 = NRF5_FICR_REG(0x03C),
47 NRF5_FICR_SIZERAMBLOCK2 = NRF5_FICR_REG(0x040),
48 NRF5_FICR_SIZERAMBLOCK3 = NRF5_FICR_REG(0x044),
49 NRF5_FICR_CONFIGID = NRF5_FICR_REG(0x05C),
50 NRF5_FICR_DEVICEID0 = NRF5_FICR_REG(0x060),
51 NRF5_FICR_DEVICEID1 = NRF5_FICR_REG(0x064),
52 NRF5_FICR_ER0 = NRF5_FICR_REG(0x080),
53 NRF5_FICR_ER1 = NRF5_FICR_REG(0x084),
54 NRF5_FICR_ER2 = NRF5_FICR_REG(0x088),
55 NRF5_FICR_ER3 = NRF5_FICR_REG(0x08C),
56 NRF5_FICR_IR0 = NRF5_FICR_REG(0x090),
57 NRF5_FICR_IR1 = NRF5_FICR_REG(0x094),
58 NRF5_FICR_IR2 = NRF5_FICR_REG(0x098),
59 NRF5_FICR_IR3 = NRF5_FICR_REG(0x09C),
60 NRF5_FICR_DEVICEADDRTYPE = NRF5_FICR_REG(0x0A0),
61 NRF5_FICR_DEVICEADDR0 = NRF5_FICR_REG(0x0A4),
62 NRF5_FICR_DEVICEADDR1 = NRF5_FICR_REG(0x0A8),
63 NRF5_FICR_OVERRIDEN = NRF5_FICR_REG(0x0AC),
64 NRF5_FICR_NRF_1MBIT0 = NRF5_FICR_REG(0x0B0),
65 NRF5_FICR_NRF_1MBIT1 = NRF5_FICR_REG(0x0B4),
66 NRF5_FICR_NRF_1MBIT2 = NRF5_FICR_REG(0x0B8),
67 NRF5_FICR_NRF_1MBIT3 = NRF5_FICR_REG(0x0BC),
68 NRF5_FICR_NRF_1MBIT4 = NRF5_FICR_REG(0x0C0),
69 NRF5_FICR_BLE_1MBIT0 = NRF5_FICR_REG(0x0EC),
70 NRF5_FICR_BLE_1MBIT1 = NRF5_FICR_REG(0x0F0),
71 NRF5_FICR_BLE_1MBIT2 = NRF5_FICR_REG(0x0F4),
72 NRF5_FICR_BLE_1MBIT3 = NRF5_FICR_REG(0x0F8),
73 NRF5_FICR_BLE_1MBIT4 = NRF5_FICR_REG(0x0FC),
74
75 /* Following registers are available on nRF52 and on nRF51 since rev 3 */
76 NRF5_FICR_INFO_PART = NRF5_FICR_REG(0x100),
77 NRF5_FICR_INFO_VARIANT = NRF5_FICR_REG(0x104),
78 NRF5_FICR_INFO_PACKAGE = NRF5_FICR_REG(0x108),
79 NRF5_FICR_INFO_RAM = NRF5_FICR_REG(0x10C),
80 NRF5_FICR_INFO_FLASH = NRF5_FICR_REG(0x110),
81 };
82
83 enum nrf5_uicr_registers {
84 NRF5_UICR_BASE = 0x10001000, /* User Information
85 * Configuration Regsters */
86
87 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
88
89 NRF5_UICR_CLENR0 = NRF5_UICR_REG(0x000),
90 NRF5_UICR_RBPCONF = NRF5_UICR_REG(0x004),
91 NRF5_UICR_XTALFREQ = NRF5_UICR_REG(0x008),
92 NRF5_UICR_FWID = NRF5_UICR_REG(0x010),
93 };
94
95 enum nrf5_nvmc_registers {
96 NRF5_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
97 * Controller Registers */
98
99 #define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
100
101 NRF5_NVMC_READY = NRF5_NVMC_REG(0x400),
102 NRF5_NVMC_CONFIG = NRF5_NVMC_REG(0x504),
103 NRF5_NVMC_ERASEPAGE = NRF5_NVMC_REG(0x508),
104 NRF5_NVMC_ERASEALL = NRF5_NVMC_REG(0x50C),
105 NRF5_NVMC_ERASEUICR = NRF5_NVMC_REG(0x514),
106
107 NRF5_BPROT_BASE = 0x40000000,
108 };
109
110 enum nrf5_nvmc_config_bits {
111 NRF5_NVMC_CONFIG_REN = 0x00,
112 NRF5_NVMC_CONFIG_WEN = 0x01,
113 NRF5_NVMC_CONFIG_EEN = 0x02,
114
115 };
116
117 struct nrf52_ficr_info {
118 uint32_t part;
119 uint32_t variant;
120 uint32_t package;
121 uint32_t ram;
122 uint32_t flash;
123 };
124
125 enum nrf5_features {
126 NRF5_FEATURE_SERIES_51 = 1 << 0,
127 NRF5_FEATURE_SERIES_52 = 1 << 1,
128 NRF5_FEATURE_BPROT = 1 << 2,
129 NRF5_FEATURE_ACL_PROT = 1 << 3,
130 };
131
132 struct nrf5_device_spec {
133 uint16_t hwid;
134 const char *part;
135 const char *variant;
136 const char *build_code;
137 unsigned int flash_size_kb;
138 enum nrf5_features features;
139 };
140
141 struct nrf5_info {
142 uint32_t refcount;
143
144 struct nrf5_bank {
145 struct nrf5_info *chip;
146 bool probed;
147 } bank[2];
148 struct target *target;
149
150 /* chip identification stored in nrf5_probe() for use in nrf5_info() */
151 bool ficr_info_valid;
152 struct nrf52_ficr_info ficr_info;
153 const struct nrf5_device_spec *spec;
154 uint32_t hwid;
155 enum nrf5_features features;
156 unsigned int flash_size_kb;
157 };
158
159 #define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize) \
160 { \
161 .hwid = (id), \
162 .part = pt, \
163 .variant = var, \
164 .build_code = bcode, \
165 .flash_size_kb = (fsize), \
166 .features = NRF5_FEATURE_SERIES_51, \
167 }
168
169 #define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize, features) \
170 { \
171 .hwid = (id), \
172 .part = pt, \
173 .variant = var, \
174 .build_code = bcode, \
175 .flash_size_kb = (fsize), \
176 .features = features, \
177 }
178
179 /* The known devices table below is derived from the "nRF5x series
180 * compatibility matrix" documents, which can be found in the "DocLib" of
181 * nordic:
182 *
183 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51422_ic_revision_overview
184 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51822_ic_revision_overview
185 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51824_ic_revision_overview
186 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52810/latest/COMP/nrf52810/nRF52810_ic_revision_overview
187 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52832/latest/COMP/nrf52832/ic_revision_overview
188 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52840/latest/COMP/nrf52840/nRF52840_ic_revision_overview
189 *
190 * Up to date with Matrix v2.0, plus some additional HWIDs.
191 *
192 * The additional HWIDs apply where the build code in the matrix is
193 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
194 * for x==0, x!=0 means different (unspecified) HWIDs.
195 */
196 static const struct nrf5_device_spec nrf5_known_devices_table[] = {
197 /* nRF51822 Devices (IC rev 1). */
198 NRF51_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
199 NRF51_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
200 NRF51_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
201 NRF51_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
202 NRF51_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
203
204 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
205 with built-in jlink seem to use engineering samples not listed
206 in the nRF51 Series Compatibility Matrix V1.0. */
207 NRF51_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
208
209 /* nRF51822 Devices (IC rev 2). */
210 NRF51_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
211 NRF51_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
212 NRF51_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
213 NRF51_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
214 NRF51_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
215 NRF51_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
216 NRF51_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
217 NRF51_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
218 NRF51_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
219
220 /* nRF51822 Devices (IC rev 3). */
221 NRF51_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
222 NRF51_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
223 NRF51_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
224 NRF51_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
225 NRF51_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
226 NRF51_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
227 NRF51_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
228 NRF51_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
229 NRF51_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
230
231 /* nRF51422 Devices (IC rev 1). */
232 NRF51_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
233 NRF51_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
234 NRF51_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
235
236 /* nRF51422 Devices (IC rev 2). */
237 NRF51_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
238 NRF51_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
239 NRF51_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
240 NRF51_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
241
242 /* nRF51422 Devices (IC rev 3). */
243 NRF51_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
244 NRF51_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
245 NRF51_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
246 NRF51_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
247 NRF51_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
248 NRF51_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
249 NRF51_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
250
251 /* The driver fully autodects nRF52 series devices by FICR INFO,
252 * no need for nRF52xxx HWIDs in this table */
253 #if 0
254 /* nRF52810 Devices */
255 NRF5_DEVICE_DEF(0x0142, "52810", "QFAA", "B0", 192, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
256 NRF5_DEVICE_DEF(0x0143, "52810", "QCAA", "C0", 192, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
257
258 /* nRF52832 Devices */
259 NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
260 NRF5_DEVICE_DEF(0x0139, "52832", "QFAA", "E0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
261 NRF5_DEVICE_DEF(0x00E3, "52832", "CIAA", "B0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
262
263 /* nRF52840 Devices */
264 NRF5_DEVICE_DEF(0x0150, "52840", "QIAA", "C0", 1024, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_ACL_PROT),
265 #endif
266 };
267
268 struct nrf5_device_package {
269 uint32_t package;
270 const char *code;
271 };
272
273 /* Newer devices have FICR INFO.PACKAGE.
274 * This table converts its value to two character code */
275 static const struct nrf5_device_package nrf5_packages_table[] = {
276 { 0x2000, "QF" },
277 { 0x2001, "CH" },
278 { 0x2002, "CI" },
279 { 0x2005, "CK" },
280 };
281
282 static int nrf5_bank_is_probed(struct flash_bank *bank)
283 {
284 struct nrf5_bank *nbank = bank->driver_priv;
285
286 assert(nbank != NULL);
287
288 return nbank->probed;
289 }
290 static int nrf5_probe(struct flash_bank *bank);
291
292 static int nrf5_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf5_info **chip)
293 {
294 if (bank->target->state != TARGET_HALTED) {
295 LOG_ERROR("Target not halted");
296 return ERROR_TARGET_NOT_HALTED;
297 }
298
299 struct nrf5_bank *nbank = bank->driver_priv;
300 *chip = nbank->chip;
301
302 int probed = nrf5_bank_is_probed(bank);
303 if (probed < 0)
304 return probed;
305 else if (!probed)
306 return nrf5_probe(bank);
307 else
308 return ERROR_OK;
309 }
310
311 static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
312 {
313 uint32_t ready;
314 int res;
315 int timeout_ms = 340;
316 int64_t ts_start = timeval_ms();
317
318 do {
319 res = target_read_u32(chip->target, NRF5_NVMC_READY, &ready);
320 if (res != ERROR_OK) {
321 LOG_ERROR("Couldn't read NVMC_READY register");
322 return res;
323 }
324
325 if (ready == 0x00000001)
326 return ERROR_OK;
327
328 keep_alive();
329
330 } while ((timeval_ms()-ts_start) < timeout_ms);
331
332 LOG_DEBUG("Timed out waiting for NVMC_READY");
333 return ERROR_FLASH_BUSY;
334 }
335
336 static int nrf5_nvmc_erase_enable(struct nrf5_info *chip)
337 {
338 int res;
339 res = target_write_u32(chip->target,
340 NRF5_NVMC_CONFIG,
341 NRF5_NVMC_CONFIG_EEN);
342
343 if (res != ERROR_OK) {
344 LOG_ERROR("Failed to enable erase operation");
345 return res;
346 }
347
348 /*
349 According to NVMC examples in Nordic SDK busy status must be
350 checked after writing to NVMC_CONFIG
351 */
352 res = nrf5_wait_for_nvmc(chip);
353 if (res != ERROR_OK)
354 LOG_ERROR("Erase enable did not complete");
355
356 return res;
357 }
358
359 static int nrf5_nvmc_write_enable(struct nrf5_info *chip)
360 {
361 int res;
362 res = target_write_u32(chip->target,
363 NRF5_NVMC_CONFIG,
364 NRF5_NVMC_CONFIG_WEN);
365
366 if (res != ERROR_OK) {
367 LOG_ERROR("Failed to enable write operation");
368 return res;
369 }
370
371 /*
372 According to NVMC examples in Nordic SDK busy status must be
373 checked after writing to NVMC_CONFIG
374 */
375 res = nrf5_wait_for_nvmc(chip);
376 if (res != ERROR_OK)
377 LOG_ERROR("Write enable did not complete");
378
379 return res;
380 }
381
382 static int nrf5_nvmc_read_only(struct nrf5_info *chip)
383 {
384 int res;
385 res = target_write_u32(chip->target,
386 NRF5_NVMC_CONFIG,
387 NRF5_NVMC_CONFIG_REN);
388
389 if (res != ERROR_OK) {
390 LOG_ERROR("Failed to enable read-only operation");
391 return res;
392 }
393 /*
394 According to NVMC examples in Nordic SDK busy status must be
395 checked after writing to NVMC_CONFIG
396 */
397 res = nrf5_wait_for_nvmc(chip);
398 if (res != ERROR_OK)
399 LOG_ERROR("Read only enable did not complete");
400
401 return res;
402 }
403
404 static int nrf5_nvmc_generic_erase(struct nrf5_info *chip,
405 uint32_t erase_register, uint32_t erase_value)
406 {
407 int res;
408
409 res = nrf5_nvmc_erase_enable(chip);
410 if (res != ERROR_OK)
411 goto error;
412
413 res = target_write_u32(chip->target,
414 erase_register,
415 erase_value);
416 if (res != ERROR_OK)
417 goto set_read_only;
418
419 res = nrf5_wait_for_nvmc(chip);
420 if (res != ERROR_OK)
421 goto set_read_only;
422
423 return nrf5_nvmc_read_only(chip);
424
425 set_read_only:
426 nrf5_nvmc_read_only(chip);
427 error:
428 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
429 erase_register, erase_value);
430 return ERROR_FAIL;
431 }
432
433 static int nrf5_protect_check_bprot(struct flash_bank *bank)
434 {
435 struct nrf5_bank *nbank = bank->driver_priv;
436 struct nrf5_info *chip = nbank->chip;
437
438 assert(chip != NULL);
439
440 static uint32_t nrf5_bprot_offsets[4] = { 0x600, 0x604, 0x610, 0x614 };
441 uint32_t bprot_reg = 0;
442 int res;
443
444 for (int i = 0; i < bank->num_sectors; i++) {
445 unsigned int bit = i % 32;
446 if (bit == 0) {
447 unsigned int n_reg = i / 32;
448 if (n_reg >= ARRAY_SIZE(nrf5_bprot_offsets))
449 break;
450
451 res = target_read_u32(chip->target, NRF5_BPROT_BASE + nrf5_bprot_offsets[n_reg], &bprot_reg);
452 if (res != ERROR_OK)
453 return res;
454 }
455 bank->sectors[i].is_protected = (bprot_reg & (1 << bit)) ? 1 : 0;
456 }
457 return ERROR_OK;
458 }
459
460 static int nrf5_protect_check(struct flash_bank *bank)
461 {
462 int res;
463 uint32_t clenr0;
464
465 /* UICR cannot be write protected so just return early */
466 if (bank->base == NRF5_UICR_BASE)
467 return ERROR_OK;
468
469 struct nrf5_bank *nbank = bank->driver_priv;
470 struct nrf5_info *chip = nbank->chip;
471
472 assert(chip != NULL);
473
474 if (chip->features & NRF5_FEATURE_BPROT)
475 return nrf5_protect_check_bprot(bank);
476
477 if (!(chip->features & NRF5_FEATURE_SERIES_51)) {
478 LOG_WARNING("Flash protection of this nRF device is not supported");
479 return ERROR_FLASH_OPER_UNSUPPORTED;
480 }
481
482 res = target_read_u32(chip->target, NRF5_FICR_CLENR0,
483 &clenr0);
484 if (res != ERROR_OK) {
485 LOG_ERROR("Couldn't read code region 0 size[FICR]");
486 return res;
487 }
488
489 if (clenr0 == 0xFFFFFFFF) {
490 res = target_read_u32(chip->target, NRF5_UICR_CLENR0,
491 &clenr0);
492 if (res != ERROR_OK) {
493 LOG_ERROR("Couldn't read code region 0 size[UICR]");
494 return res;
495 }
496 }
497
498 for (int i = 0; i < bank->num_sectors; i++)
499 bank->sectors[i].is_protected =
500 clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
501
502 return ERROR_OK;
503 }
504
505 static int nrf5_protect(struct flash_bank *bank, int set, int first, int last)
506 {
507 int res;
508 uint32_t clenr0, ppfc;
509 struct nrf5_info *chip;
510
511 /* UICR cannot be write protected so just bail out early */
512 if (bank->base == NRF5_UICR_BASE)
513 return ERROR_FAIL;
514
515 res = nrf5_get_probed_chip_if_halted(bank, &chip);
516 if (res != ERROR_OK)
517 return res;
518
519 if (!(chip->features & NRF5_FEATURE_SERIES_51)) {
520 LOG_ERROR("Flash protection setting of this nRF device is not supported");
521 return ERROR_FLASH_OPER_UNSUPPORTED;
522 }
523
524 if (first != 0) {
525 LOG_ERROR("Code region 0 must start at the begining of the bank");
526 return ERROR_FAIL;
527 }
528
529 res = target_read_u32(chip->target, NRF5_FICR_PPFC,
530 &ppfc);
531 if (res != ERROR_OK) {
532 LOG_ERROR("Couldn't read PPFC register");
533 return res;
534 }
535
536 if ((ppfc & 0xFF) == 0x00) {
537 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
538 return ERROR_FAIL;
539 }
540
541 res = target_read_u32(chip->target, NRF5_UICR_CLENR0,
542 &clenr0);
543 if (res != ERROR_OK) {
544 LOG_ERROR("Couldn't read code region 0 size[UICR]");
545 return res;
546 }
547
548 if (clenr0 == 0xFFFFFFFF) {
549 res = target_write_u32(chip->target, NRF5_UICR_CLENR0,
550 clenr0);
551 if (res != ERROR_OK) {
552 LOG_ERROR("Couldn't write code region 0 size[UICR]");
553 return res;
554 }
555
556 } else {
557 LOG_ERROR("You need to perform chip erase before changing the protection settings");
558 }
559
560 nrf5_protect_check(bank);
561
562 return ERROR_OK;
563 }
564
565 static bool nrf5_info_variant_to_str(uint32_t variant, char *bf)
566 {
567 h_u32_to_be((uint8_t *)bf, variant);
568 bf[4] = '\0';
569 if (isalnum(bf[0]) && isalnum(bf[1]) && isalnum(bf[2]) && isalnum(bf[3]))
570 return true;
571
572 strcpy(bf, "xxxx");
573 return false;
574 }
575
576 static const char *nrf5_decode_info_package(uint32_t package)
577 {
578 for (size_t i = 0; i < ARRAY_SIZE(nrf5_packages_table); i++) {
579 if (nrf5_packages_table[i].package == package)
580 return nrf5_packages_table[i].code;
581 }
582 return "xx";
583 }
584
585 static int nrf5_info(struct flash_bank *bank, char *buf, int buf_size)
586 {
587 struct nrf5_bank *nbank = bank->driver_priv;
588 struct nrf5_info *chip = nbank->chip;
589
590 if (chip->spec) {
591 snprintf(buf, buf_size,
592 "nRF%s-%s(build code: %s) %ukB Flash",
593 chip->spec->part, chip->spec->variant, chip->spec->build_code,
594 chip->flash_size_kb);
595
596 } else if (chip->ficr_info_valid) {
597 char variant[5];
598 nrf5_info_variant_to_str(chip->ficr_info.variant, variant);
599 snprintf(buf, buf_size,
600 "nRF%" PRIx32 "-%s%.2s(build code: %s) %" PRIu32
601 "kB Flash, %" PRIu32 "kB RAM",
602 chip->ficr_info.part,
603 nrf5_decode_info_package(chip->ficr_info.package),
604 variant, &variant[2],
605 chip->flash_size_kb,
606 chip->ficr_info.ram);
607
608 } else {
609 snprintf(buf, buf_size, "nRF51xxx (HWID 0x%04" PRIx16 ") %ukB Flash",
610 chip->hwid, chip->flash_size_kb);
611 }
612 return ERROR_OK;
613 }
614
615 static int nrf5_read_ficr_info(struct nrf5_info *chip)
616 {
617 int res;
618 struct target *target = chip->target;
619
620 chip->ficr_info_valid = false;
621
622 res = target_read_u32(target, NRF5_FICR_INFO_PART, &chip->ficr_info.part);
623 if (res != ERROR_OK) {
624 LOG_DEBUG("Couldn't read FICR INFO.PART register");
625 return res;
626 }
627
628 uint32_t series = chip->ficr_info.part & 0xfffff000;
629 switch (series) {
630 case 0x51000:
631 chip->features = NRF5_FEATURE_SERIES_51;
632 break;
633
634 case 0x52000:
635 chip->features = NRF5_FEATURE_SERIES_52;
636
637 switch (chip->ficr_info.part) {
638 case 0x52810:
639 case 0x52832:
640 chip->features |= NRF5_FEATURE_BPROT;
641 break;
642
643 case 0x52840:
644 chip->features |= NRF5_FEATURE_ACL_PROT;
645 break;
646 }
647 break;
648
649 default:
650 LOG_DEBUG("FICR INFO likely not implemented. Invalid PART value 0x%08"
651 PRIx32, chip->ficr_info.part);
652 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
653 }
654
655 /* Now we know the device has FICR INFO filled by something relevant:
656 * Although it is not documented, the tested nRF51 rev 3 devices
657 * have FICR INFO.PART, RAM and FLASH of the same format as nRF52.
658 * VARIANT and PACKAGE coding is unknown for a nRF51 device.
659 * nRF52 devices have FICR INFO documented and always filled. */
660
661 res = target_read_u32(target, NRF5_FICR_INFO_VARIANT, &chip->ficr_info.variant);
662 if (res != ERROR_OK)
663 return res;
664
665 res = target_read_u32(target, NRF5_FICR_INFO_PACKAGE, &chip->ficr_info.package);
666 if (res != ERROR_OK)
667 return res;
668
669 res = target_read_u32(target, NRF5_FICR_INFO_RAM, &chip->ficr_info.ram);
670 if (res != ERROR_OK)
671 return res;
672
673 res = target_read_u32(target, NRF5_FICR_INFO_FLASH, &chip->ficr_info.flash);
674 if (res != ERROR_OK)
675 return res;
676
677 chip->ficr_info_valid = true;
678 return ERROR_OK;
679 }
680
681 static int nrf5_probe(struct flash_bank *bank)
682 {
683 int res;
684 struct nrf5_bank *nbank = bank->driver_priv;
685 struct nrf5_info *chip = nbank->chip;
686 struct target *target = chip->target;
687
688 res = target_read_u32(target, NRF5_FICR_CONFIGID, &chip->hwid);
689 if (res != ERROR_OK) {
690 LOG_ERROR("Couldn't read CONFIGID register");
691 return res;
692 }
693
694 chip->hwid &= 0xFFFF; /* HWID is stored in the lower two
695 * bytes of the CONFIGID register */
696
697 /* guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
698 chip->features = NRF5_FEATURE_SERIES_51;
699
700 /* Don't bail out on error for the case that some old engineering
701 * sample has FICR INFO registers unreadable. We can proceed anyway. */
702 (void)nrf5_read_ficr_info(chip);
703
704 chip->spec = NULL;
705 for (size_t i = 0; i < ARRAY_SIZE(nrf5_known_devices_table); i++) {
706 if (chip->hwid == nrf5_known_devices_table[i].hwid) {
707 chip->spec = &nrf5_known_devices_table[i];
708 chip->features = chip->spec->features;
709 break;
710 }
711 }
712
713 if (chip->spec && chip->ficr_info_valid) {
714 /* check if HWID table gives the same part as FICR INFO */
715 if (chip->ficr_info.part != strtoul(chip->spec->part, NULL, 16))
716 LOG_WARNING("HWID 0x%04" PRIx32 " mismatch: FICR INFO.PART %"
717 PRIx32, chip->hwid, chip->ficr_info.part);
718 }
719
720 /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
721 uint32_t flash_page_size;
722 res = target_read_u32(chip->target, NRF5_FICR_CODEPAGESIZE,
723 &flash_page_size);
724 if (res != ERROR_OK) {
725 LOG_ERROR("Couldn't read code page size");
726 return res;
727 }
728
729 /* Note the register name is misleading,
730 * NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
731 uint32_t num_sectors;
732 res = target_read_u32(chip->target, NRF5_FICR_CODESIZE, &num_sectors);
733 if (res != ERROR_OK) {
734 LOG_ERROR("Couldn't read code memory size");
735 return res;
736 }
737
738 chip->flash_size_kb = num_sectors * flash_page_size / 1024;
739
740 if (!chip->bank[0].probed && !chip->bank[1].probed) {
741 char buf[80];
742 nrf5_info(bank, buf, sizeof(buf));
743 if (!chip->spec && !chip->ficr_info_valid) {
744 LOG_INFO("Unknown device: %s", buf);
745 } else {
746 LOG_INFO("%s", buf);
747 }
748 }
749
750 if (bank->base == NRF5_FLASH_BASE) {
751 /* Sanity check */
752 if (chip->spec && chip->flash_size_kb != chip->spec->flash_size_kb)
753 LOG_WARNING("Chip's reported Flash capacity does not match expected one");
754 if (chip->ficr_info_valid && chip->flash_size_kb != chip->ficr_info.flash)
755 LOG_WARNING("Chip's reported Flash capacity does not match FICR INFO.FLASH");
756
757 bank->num_sectors = num_sectors;
758 bank->size = num_sectors * flash_page_size;
759
760 bank->sectors = alloc_block_array(0, flash_page_size, num_sectors);
761 if (!bank->sectors)
762 return ERROR_FAIL;
763
764 nrf5_protect_check(bank);
765
766 chip->bank[0].probed = true;
767
768 } else {
769 bank->num_sectors = 1;
770 bank->size = flash_page_size;
771
772 bank->sectors = alloc_block_array(0, flash_page_size, num_sectors);
773 if (!bank->sectors)
774 return ERROR_FAIL;
775
776 bank->sectors[0].is_protected = 0;
777
778 chip->bank[1].probed = true;
779 }
780
781 return ERROR_OK;
782 }
783
784 static int nrf5_auto_probe(struct flash_bank *bank)
785 {
786 int probed = nrf5_bank_is_probed(bank);
787
788 if (probed < 0)
789 return probed;
790 else if (probed)
791 return ERROR_OK;
792 else
793 return nrf5_probe(bank);
794 }
795
796 static int nrf5_erase_all(struct nrf5_info *chip)
797 {
798 LOG_DEBUG("Erasing all non-volatile memory");
799 return nrf5_nvmc_generic_erase(chip,
800 NRF5_NVMC_ERASEALL,
801 0x00000001);
802 }
803
804 static int nrf5_erase_page(struct flash_bank *bank,
805 struct nrf5_info *chip,
806 struct flash_sector *sector)
807 {
808 int res;
809
810 LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
811 if (sector->is_protected) {
812 LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32, sector->offset);
813 return ERROR_FAIL;
814 }
815
816 if (bank->base == NRF5_UICR_BASE) {
817 uint32_t ppfc;
818 res = target_read_u32(chip->target, NRF5_FICR_PPFC,
819 &ppfc);
820 if (res != ERROR_OK) {
821 LOG_ERROR("Couldn't read PPFC register");
822 return res;
823 }
824
825 if ((ppfc & 0xFF) == 0xFF) {
826 /* We can't erase the UICR. Double-check to
827 see if it's already erased before complaining. */
828 default_flash_blank_check(bank);
829 if (sector->is_erased == 1)
830 return ERROR_OK;
831
832 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
833 return ERROR_FAIL;
834 }
835
836 res = nrf5_nvmc_generic_erase(chip,
837 NRF5_NVMC_ERASEUICR,
838 0x00000001);
839
840
841 } else {
842 res = nrf5_nvmc_generic_erase(chip,
843 NRF5_NVMC_ERASEPAGE,
844 sector->offset);
845 }
846
847 return res;
848 }
849
850 static const uint8_t nrf5_flash_write_code[] = {
851 /* See contrib/loaders/flash/cortex-m0.S */
852 /* <wait_fifo>: */
853 0x0d, 0x68, /* ldr r5, [r1, #0] */
854 0x00, 0x2d, /* cmp r5, #0 */
855 0x0b, 0xd0, /* beq.n 1e <exit> */
856 0x4c, 0x68, /* ldr r4, [r1, #4] */
857 0xac, 0x42, /* cmp r4, r5 */
858 0xf9, 0xd0, /* beq.n 0 <wait_fifo> */
859 0x20, 0xcc, /* ldmia r4!, {r5} */
860 0x20, 0xc3, /* stmia r3!, {r5} */
861 0x94, 0x42, /* cmp r4, r2 */
862 0x01, 0xd3, /* bcc.n 18 <no_wrap> */
863 0x0c, 0x46, /* mov r4, r1 */
864 0x08, 0x34, /* adds r4, #8 */
865 /* <no_wrap>: */
866 0x4c, 0x60, /* str r4, [r1, #4] */
867 0x04, 0x38, /* subs r0, #4 */
868 0xf0, 0xd1, /* bne.n 0 <wait_fifo> */
869 /* <exit>: */
870 0x00, 0xbe /* bkpt 0x0000 */
871 };
872
873
874 /* Start a low level flash write for the specified region */
875 static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const uint8_t *buffer, uint32_t bytes)
876 {
877 struct target *target = chip->target;
878 uint32_t buffer_size = 8192;
879 struct working_area *write_algorithm;
880 struct working_area *source;
881 struct reg_param reg_params[4];
882 struct armv7m_algorithm armv7m_info;
883 int retval = ERROR_OK;
884
885 LOG_DEBUG("Writing buffer to flash address=0x%"PRIx32" bytes=0x%"PRIx32, address, bytes);
886 assert(bytes % 4 == 0);
887
888 /* allocate working area with flash programming code */
889 if (target_alloc_working_area(target, sizeof(nrf5_flash_write_code),
890 &write_algorithm) != ERROR_OK) {
891 LOG_WARNING("no working area available, falling back to slow memory writes");
892
893 for (; bytes > 0; bytes -= 4) {
894 retval = target_write_memory(target, address, 4, 1, buffer);
895 if (retval != ERROR_OK)
896 return retval;
897
898 retval = nrf5_wait_for_nvmc(chip);
899 if (retval != ERROR_OK)
900 return retval;
901
902 address += 4;
903 buffer += 4;
904 }
905
906 return ERROR_OK;
907 }
908
909 retval = target_write_buffer(target, write_algorithm->address,
910 sizeof(nrf5_flash_write_code),
911 nrf5_flash_write_code);
912 if (retval != ERROR_OK)
913 return retval;
914
915 /* memory buffer */
916 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
917 buffer_size /= 2;
918 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
919 if (buffer_size <= 256) {
920 /* free working area, write algorithm already allocated */
921 target_free_working_area(target, write_algorithm);
922
923 LOG_WARNING("No large enough working area available, can't do block memory writes");
924 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
925 }
926 }
927
928 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
929 armv7m_info.core_mode = ARM_MODE_THREAD;
930
931 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* byte count */
932 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer start */
933 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer end */
934 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT); /* target address */
935
936 buf_set_u32(reg_params[0].value, 0, 32, bytes);
937 buf_set_u32(reg_params[1].value, 0, 32, source->address);
938 buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
939 buf_set_u32(reg_params[3].value, 0, 32, address);
940
941 retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
942 0, NULL,
943 4, reg_params,
944 source->address, source->size,
945 write_algorithm->address, 0,
946 &armv7m_info);
947
948 target_free_working_area(target, source);
949 target_free_working_area(target, write_algorithm);
950
951 destroy_reg_param(&reg_params[0]);
952 destroy_reg_param(&reg_params[1]);
953 destroy_reg_param(&reg_params[2]);
954 destroy_reg_param(&reg_params[3]);
955
956 return retval;
957 }
958
959 static int nrf5_write(struct flash_bank *bank, const uint8_t *buffer,
960 uint32_t offset, uint32_t count)
961 {
962 struct nrf5_info *chip;
963
964 int res = nrf5_get_probed_chip_if_halted(bank, &chip);
965 if (res != ERROR_OK)
966 return res;
967
968 assert(offset % 4 == 0);
969 assert(count % 4 == 0);
970
971 res = nrf5_nvmc_write_enable(chip);
972 if (res != ERROR_OK)
973 goto error;
974
975 res = nrf5_ll_flash_write(chip, bank->base + offset, buffer, count);
976 if (res != ERROR_OK)
977 goto error;
978
979 return nrf5_nvmc_read_only(chip);
980
981 error:
982 nrf5_nvmc_read_only(chip);
983 LOG_ERROR("Failed to write to nrf5 flash");
984 return res;
985 }
986
987 static int nrf5_erase(struct flash_bank *bank, int first, int last)
988 {
989 int res;
990 struct nrf5_info *chip;
991
992 res = nrf5_get_probed_chip_if_halted(bank, &chip);
993 if (res != ERROR_OK)
994 return res;
995
996 /* For each sector to be erased */
997 for (int s = first; s <= last && res == ERROR_OK; s++)
998 res = nrf5_erase_page(bank, chip, &bank->sectors[s]);
999
1000 return res;
1001 }
1002
1003 static void nrf5_free_driver_priv(struct flash_bank *bank)
1004 {
1005 struct nrf5_bank *nbank = bank->driver_priv;
1006 struct nrf5_info *chip = nbank->chip;
1007 if (chip == NULL)
1008 return;
1009
1010 chip->refcount--;
1011 if (chip->refcount == 0) {
1012 free(chip);
1013 bank->driver_priv = NULL;
1014 }
1015 }
1016
1017 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
1018 {
1019 static struct nrf5_info *chip;
1020 struct nrf5_bank *nbank = NULL;
1021
1022 switch (bank->base) {
1023 case NRF5_FLASH_BASE:
1024 case NRF5_UICR_BASE:
1025 break;
1026 default:
1027 LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base);
1028 return ERROR_FAIL;
1029 }
1030
1031 if (!chip) {
1032 /* Create a new chip */
1033 chip = calloc(1, sizeof(*chip));
1034 if (!chip)
1035 return ERROR_FAIL;
1036
1037 chip->target = bank->target;
1038 }
1039
1040 switch (bank->base) {
1041 case NRF5_FLASH_BASE:
1042 nbank = &chip->bank[0];
1043 break;
1044 case NRF5_UICR_BASE:
1045 nbank = &chip->bank[1];
1046 break;
1047 }
1048 assert(nbank != NULL);
1049
1050 chip->refcount++;
1051 nbank->chip = chip;
1052 nbank->probed = false;
1053 bank->driver_priv = nbank;
1054 bank->write_start_alignment = bank->write_end_alignment = 4;
1055
1056 return ERROR_OK;
1057 }
1058
1059 COMMAND_HANDLER(nrf5_handle_mass_erase_command)
1060 {
1061 int res;
1062 struct flash_bank *bank = NULL;
1063 struct target *target = get_current_target(CMD_CTX);
1064
1065 res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank);
1066 if (res != ERROR_OK)
1067 return res;
1068
1069 assert(bank != NULL);
1070
1071 struct nrf5_info *chip;
1072
1073 res = nrf5_get_probed_chip_if_halted(bank, &chip);
1074 if (res != ERROR_OK)
1075 return res;
1076
1077 uint32_t ppfc;
1078
1079 res = target_read_u32(target, NRF5_FICR_PPFC,
1080 &ppfc);
1081 if (res != ERROR_OK) {
1082 LOG_ERROR("Couldn't read PPFC register");
1083 return res;
1084 }
1085
1086 if ((ppfc & 0xFF) == 0x00) {
1087 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1088 "mass erase command won't work.");
1089 return ERROR_FAIL;
1090 }
1091
1092 res = nrf5_erase_all(chip);
1093 if (res != ERROR_OK) {
1094 LOG_ERROR("Failed to erase the chip");
1095 nrf5_protect_check(bank);
1096 return res;
1097 }
1098
1099 res = nrf5_protect_check(bank);
1100 if (res != ERROR_OK) {
1101 LOG_ERROR("Failed to check chip's write protection");
1102 return res;
1103 }
1104
1105 res = get_flash_bank_by_addr(target, NRF5_UICR_BASE, true, &bank);
1106 if (res != ERROR_OK)
1107 return res;
1108
1109 return ERROR_OK;
1110 }
1111
1112 COMMAND_HANDLER(nrf5_handle_info_command)
1113 {
1114 int res;
1115 struct flash_bank *bank = NULL;
1116 struct target *target = get_current_target(CMD_CTX);
1117
1118 res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank);
1119 if (res != ERROR_OK)
1120 return res;
1121
1122 assert(bank != NULL);
1123
1124 struct nrf5_info *chip;
1125
1126 res = nrf5_get_probed_chip_if_halted(bank, &chip);
1127 if (res != ERROR_OK)
1128 return res;
1129
1130 static struct {
1131 const uint32_t address;
1132 uint32_t value;
1133 } ficr[] = {
1134 { .address = NRF5_FICR_CODEPAGESIZE },
1135 { .address = NRF5_FICR_CODESIZE },
1136 { .address = NRF5_FICR_CLENR0 },
1137 { .address = NRF5_FICR_PPFC },
1138 { .address = NRF5_FICR_NUMRAMBLOCK },
1139 { .address = NRF5_FICR_SIZERAMBLOCK0 },
1140 { .address = NRF5_FICR_SIZERAMBLOCK1 },
1141 { .address = NRF5_FICR_SIZERAMBLOCK2 },
1142 { .address = NRF5_FICR_SIZERAMBLOCK3 },
1143 { .address = NRF5_FICR_CONFIGID },
1144 { .address = NRF5_FICR_DEVICEID0 },
1145 { .address = NRF5_FICR_DEVICEID1 },
1146 { .address = NRF5_FICR_ER0 },
1147 { .address = NRF5_FICR_ER1 },
1148 { .address = NRF5_FICR_ER2 },
1149 { .address = NRF5_FICR_ER3 },
1150 { .address = NRF5_FICR_IR0 },
1151 { .address = NRF5_FICR_IR1 },
1152 { .address = NRF5_FICR_IR2 },
1153 { .address = NRF5_FICR_IR3 },
1154 { .address = NRF5_FICR_DEVICEADDRTYPE },
1155 { .address = NRF5_FICR_DEVICEADDR0 },
1156 { .address = NRF5_FICR_DEVICEADDR1 },
1157 { .address = NRF5_FICR_OVERRIDEN },
1158 { .address = NRF5_FICR_NRF_1MBIT0 },
1159 { .address = NRF5_FICR_NRF_1MBIT1 },
1160 { .address = NRF5_FICR_NRF_1MBIT2 },
1161 { .address = NRF5_FICR_NRF_1MBIT3 },
1162 { .address = NRF5_FICR_NRF_1MBIT4 },
1163 { .address = NRF5_FICR_BLE_1MBIT0 },
1164 { .address = NRF5_FICR_BLE_1MBIT1 },
1165 { .address = NRF5_FICR_BLE_1MBIT2 },
1166 { .address = NRF5_FICR_BLE_1MBIT3 },
1167 { .address = NRF5_FICR_BLE_1MBIT4 },
1168 }, uicr[] = {
1169 { .address = NRF5_UICR_CLENR0, },
1170 { .address = NRF5_UICR_RBPCONF },
1171 { .address = NRF5_UICR_XTALFREQ },
1172 { .address = NRF5_UICR_FWID },
1173 };
1174
1175 for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
1176 res = target_read_u32(chip->target, ficr[i].address,
1177 &ficr[i].value);
1178 if (res != ERROR_OK) {
1179 LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address);
1180 return res;
1181 }
1182 }
1183
1184 for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) {
1185 res = target_read_u32(chip->target, uicr[i].address,
1186 &uicr[i].value);
1187 if (res != ERROR_OK) {
1188 LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address);
1189 return res;
1190 }
1191 }
1192
1193 command_print(CMD,
1194 "\n[factory information control block]\n\n"
1195 "code page size: %"PRIu32"B\n"
1196 "code memory size: %"PRIu32"kB\n"
1197 "code region 0 size: %"PRIu32"kB\n"
1198 "pre-programmed code: %s\n"
1199 "number of ram blocks: %"PRIu32"\n"
1200 "ram block 0 size: %"PRIu32"B\n"
1201 "ram block 1 size: %"PRIu32"B\n"
1202 "ram block 2 size: %"PRIu32"B\n"
1203 "ram block 3 size: %"PRIu32 "B\n"
1204 "config id: %" PRIx32 "\n"
1205 "device id: 0x%"PRIx32"%08"PRIx32"\n"
1206 "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1207 "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1208 "device address type: 0x%"PRIx32"\n"
1209 "device address: 0x%"PRIx32"%08"PRIx32"\n"
1210 "override enable: %"PRIx32"\n"
1211 "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1212 "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1213 "\n[user information control block]\n\n"
1214 "code region 0 size: %"PRIu32"kB\n"
1215 "read back protection configuration: %"PRIx32"\n"
1216 "reset value for XTALFREQ: %"PRIx32"\n"
1217 "firmware id: 0x%04"PRIx32,
1218 ficr[0].value,
1219 (ficr[1].value * ficr[0].value) / 1024,
1220 (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
1221 ((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
1222 ficr[4].value,
1223 ficr[5].value,
1224 (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
1225 (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
1226 (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
1227 ficr[9].value,
1228 ficr[10].value, ficr[11].value,
1229 ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
1230 ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
1231 ficr[20].value,
1232 ficr[21].value, ficr[22].value,
1233 ficr[23].value,
1234 ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
1235 ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
1236 (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
1237 uicr[1].value & 0xFFFF,
1238 uicr[2].value & 0xFF,
1239 uicr[3].value & 0xFFFF);
1240
1241 return ERROR_OK;
1242 }
1243
1244 static const struct command_registration nrf5_exec_command_handlers[] = {
1245 {
1246 .name = "mass_erase",
1247 .handler = nrf5_handle_mass_erase_command,
1248 .mode = COMMAND_EXEC,
1249 .help = "Erase all flash contents of the chip.",
1250 .usage = "",
1251 },
1252 {
1253 .name = "info",
1254 .handler = nrf5_handle_info_command,
1255 .mode = COMMAND_EXEC,
1256 .help = "Show FICR and UICR info.",
1257 .usage = "",
1258 },
1259 COMMAND_REGISTRATION_DONE
1260 };
1261
1262 static const struct command_registration nrf5_command_handlers[] = {
1263 {
1264 .name = "nrf5",
1265 .mode = COMMAND_ANY,
1266 .help = "nrf5 flash command group",
1267 .usage = "",
1268 .chain = nrf5_exec_command_handlers,
1269 },
1270 {
1271 .name = "nrf51",
1272 .mode = COMMAND_ANY,
1273 .help = "nrf51 flash command group",
1274 .usage = "",
1275 .chain = nrf5_exec_command_handlers,
1276 },
1277 COMMAND_REGISTRATION_DONE
1278 };
1279
1280 const struct flash_driver nrf5_flash = {
1281 .name = "nrf5",
1282 .commands = nrf5_command_handlers,
1283 .flash_bank_command = nrf5_flash_bank_command,
1284 .info = nrf5_info,
1285 .erase = nrf5_erase,
1286 .protect = nrf5_protect,
1287 .write = nrf5_write,
1288 .read = default_flash_read,
1289 .probe = nrf5_probe,
1290 .auto_probe = nrf5_auto_probe,
1291 .erase_check = default_flash_blank_check,
1292 .protect_check = nrf5_protect_check,
1293 .free_driver_priv = nrf5_free_driver_priv,
1294 };
1295
1296 /* We need to retain the flash-driver name as well as the commands
1297 * for backwards compatability */
1298 const struct flash_driver nrf51_flash = {
1299 .name = "nrf51",
1300 .commands = nrf5_command_handlers,
1301 .flash_bank_command = nrf5_flash_bank_command,
1302 .info = nrf5_info,
1303 .erase = nrf5_erase,
1304 .protect = nrf5_protect,
1305 .write = nrf5_write,
1306 .read = default_flash_read,
1307 .probe = nrf5_probe,
1308 .auto_probe = nrf5_auto_probe,
1309 .erase_check = default_flash_blank_check,
1310 .protect_check = nrf5_protect_check,
1311 .free_driver_priv = nrf5_free_driver_priv,
1312 };
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