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flash/nor: consolidate flash protect/protect_check
[openocd.git] / src / flash / nor / lpc288x.c
1 /***************************************************************************
2 * Copyright (C) 2008 by *
3 * Karl RobinSod <karl.robinsod@gmail.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18
19 /***************************************************************************
20 * There are some things to notice
21 *
22 * You need to unprotect flash sectors each time you connect the OpenOCD
23 * Dumping 1MB takes about 60 Seconds
24 * Full erase (sectors 0-22 inclusive) takes 2-4 seconds
25 * Writing 1MB takes 88 seconds
26 *
27 ***************************************************************************/
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "imp.h"
33 #include <helper/binarybuffer.h>
34
35 #define LOAD_TIMER_ERASE 0
36 #define LOAD_TIMER_WRITE 1
37
38 #define FLASH_PAGE_SIZE 512
39
40 /* LPC288X control registers */
41 #define DBGU_CIDR 0x8000507C
42 /* LPC288X flash registers */
43 #define F_CTRL 0x80102000 /* Flash control register R/W 0x5 */
44 #define F_STAT 0x80102004 /* Flash status register RO 0x45 */
45 #define F_PROG_TIME 0x80102008 /* Flash program time register R/W 0 */
46 #define F_WAIT 0x80102010 /* Flash read wait state register R/W 0xC004 */
47 #define F_CLK_TIME 0x8010201C /* Flash clock divider for 66 kHz generation R/W 0
48 **/
49 #define F_INTEN_CLR 0x80102FD8 /* Clear interrupt enable bits WO - */
50 #define F_INTEN_SET 0x80102FDC /* Set interrupt enable bits WO - */
51 #define F_INT_STAT 0x80102FE0 /* Interrupt status bits RO 0 */
52 #define F_INTEN 0x80102FE4 /* Interrupt enable bits RO 0 */
53 #define F_INT_CLR 0x80102FE8 /* Clear interrupt status bits WO */
54 #define F_INT_SET 0x80102FEC /* Set interrupt status bits WO - */
55 #define FLASH_PD 0x80005030 /* Allows turning off the Flash memory for power
56 *savings. R/W 1*/
57 #define FLASH_INIT 0x80005034 /* Monitors Flash readiness, such as recovery from
58 *Power Down mode. R/W -*/
59
60 /* F_CTRL bits */
61 #define FC_CS 0x0001
62 #define FC_FUNC 0x0002
63 #define FC_WEN 0x0004
64 #define FC_RD_LATCH 0x0020
65 #define FC_PROTECT 0x0080
66 #define FC_SET_DATA 0x0400
67 #define FC_RSSL 0x0800
68 #define FC_PROG_REQ 0x1000
69 #define FC_CLR_BUF 0x4000
70 #define FC_LOAD_REQ 0x8000
71 /* F_STAT bits */
72 #define FS_DONE 0x0001
73 #define FS_PROGGNT 0x0002
74 #define FS_RDY 0x0004
75 #define FS_ERR 0x0020
76 /* F_PROG_TIME */
77 #define FPT_TIME_MASK 0x7FFF
78
79 #define FPT_ENABLE 0x8000
80 /* F_WAIT */
81 #define FW_WAIT_STATES_MASK 0x00FF
82 #define FW_SET_MASK 0xC000
83
84 /* F_CLK_TIME */
85 #define FCT_CLK_DIV_MASK 0x0FFF
86
87 struct lpc288x_flash_bank {
88 uint32_t working_area;
89 uint32_t working_area_size;
90
91 /* chip id register */
92 uint32_t cidr;
93 const char *target_name;
94 uint32_t cclk;
95
96 uint32_t sector_size_break;
97 };
98
99 static uint32_t lpc288x_wait_status_busy(struct flash_bank *bank, int timeout);
100 static void lpc288x_load_timer(int erase, struct target *target);
101 static void lpc288x_set_flash_clk(struct flash_bank *bank);
102 static uint32_t lpc288x_system_ready(struct flash_bank *bank);
103
104 static uint32_t lpc288x_wait_status_busy(struct flash_bank *bank, int timeout)
105 {
106 uint32_t status;
107 struct target *target = bank->target;
108 do {
109 alive_sleep(1);
110 timeout--;
111 target_read_u32(target, F_STAT, &status);
112 } while (((status & FS_DONE) == 0) && timeout);
113
114 if (timeout == 0) {
115 LOG_DEBUG("Timedout!");
116 return ERROR_FLASH_OPERATION_FAILED;
117 }
118 return ERROR_OK;
119 }
120
121 /* Read device id register and fill in driver info structure */
122 static int lpc288x_read_part_info(struct flash_bank *bank)
123 {
124 struct lpc288x_flash_bank *lpc288x_info = bank->driver_priv;
125 struct target *target = bank->target;
126 uint32_t cidr;
127
128 int i = 0;
129 uint32_t offset;
130
131 if (lpc288x_info->cidr == 0x0102100A)
132 return ERROR_OK;/* already probed, multiple probes may cause memory leak, not
133 *allowed */
134
135 /* Read and parse chip identification register */
136 target_read_u32(target, DBGU_CIDR, &cidr);
137
138 if (cidr != 0x0102100A) {
139 LOG_WARNING("Cannot identify target as an LPC288X (%08" PRIx32 ")", cidr);
140 return ERROR_FLASH_OPERATION_FAILED;
141 }
142
143 lpc288x_info->cidr = cidr;
144 lpc288x_info->sector_size_break = 0x000F0000;
145 lpc288x_info->target_name = "LPC288x";
146
147 /* setup the sector info... */
148 offset = bank->base;
149 bank->num_sectors = 23;
150 bank->sectors = malloc(sizeof(struct flash_sector) * 23);
151
152 for (i = 0; i < 15; i++) {
153 bank->sectors[i].offset = offset;
154 bank->sectors[i].size = 64 * 1024;
155 offset += bank->sectors[i].size;
156 bank->sectors[i].is_erased = -1;
157 bank->sectors[i].is_protected = 1;
158 }
159 for (i = 15; i < 23; i++) {
160 bank->sectors[i].offset = offset;
161 bank->sectors[i].size = 8 * 1024;
162 offset += bank->sectors[i].size;
163 bank->sectors[i].is_erased = -1;
164 bank->sectors[i].is_protected = 1;
165 }
166
167 return ERROR_OK;
168 }
169
170 /* TODO: Revisit! Is it impossible to read protection status? */
171 static int lpc288x_protect_check(struct flash_bank *bank)
172 {
173 return ERROR_OK;
174 }
175
176 /* flash_bank LPC288x 0 0 0 0 <target#> <cclk> */
177 FLASH_BANK_COMMAND_HANDLER(lpc288x_flash_bank_command)
178 {
179 struct lpc288x_flash_bank *lpc288x_info;
180
181 if (CMD_ARGC < 6)
182 return ERROR_COMMAND_SYNTAX_ERROR;
183
184 lpc288x_info = malloc(sizeof(struct lpc288x_flash_bank));
185 bank->driver_priv = lpc288x_info;
186
187 /* part wasn't probed for info yet */
188 lpc288x_info->cidr = 0;
189 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], lpc288x_info->cclk);
190
191 return ERROR_OK;
192 }
193
194 /* The frequency is the AHB clock frequency divided by (CLK_DIV ×3) + 1.
195 * This must be programmed such that the Flash Programming clock frequency is 66 kHz ± 20%.
196 * AHB = 12 MHz ?
197 * 12000000/66000 = 182
198 * CLK_DIV = 60 ? */
199 static void lpc288x_set_flash_clk(struct flash_bank *bank)
200 {
201 uint32_t clk_time;
202 struct lpc288x_flash_bank *lpc288x_info = bank->driver_priv;
203 clk_time = (lpc288x_info->cclk / 66000) / 3;
204 target_write_u32(bank->target, F_CTRL, FC_CS | FC_WEN);
205 target_write_u32(bank->target, F_CLK_TIME, clk_time);
206 }
207
208 /* AHB tcyc (in ns) 83 ns
209 * LOAD_TIMER_ERASE FPT_TIME = ((400,000,000 / AHB tcyc (in ns)) - 2) / 512
210 * = 9412 (9500) (AN10548 9375)
211 * LOAD_TIMER_WRITE FPT_TIME = ((1,000,000 / AHB tcyc (in ns)) - 2) / 512
212 * = 23 (75) (AN10548 72 - is this wrong?)
213 * TODO: Sort out timing calcs ;) */
214 static void lpc288x_load_timer(int erase, struct target *target)
215 {
216 if (erase == LOAD_TIMER_ERASE)
217 target_write_u32(target, F_PROG_TIME, FPT_ENABLE | 9500);
218 else
219 target_write_u32(target, F_PROG_TIME, FPT_ENABLE | 75);
220 }
221
222 static uint32_t lpc288x_system_ready(struct flash_bank *bank)
223 {
224 struct lpc288x_flash_bank *lpc288x_info = bank->driver_priv;
225 if (lpc288x_info->cidr == 0)
226 return ERROR_FLASH_BANK_NOT_PROBED;
227
228 if (bank->target->state != TARGET_HALTED) {
229 LOG_ERROR("Target not halted");
230 return ERROR_TARGET_NOT_HALTED;
231 }
232 return ERROR_OK;
233 }
234
235 static int lpc288x_erase_check(struct flash_bank *bank)
236 {
237 uint32_t status = lpc288x_system_ready(bank); /* probed? halted? */
238 if (status != ERROR_OK) {
239 LOG_INFO("Processor not halted/not probed");
240 return status;
241 }
242
243 return ERROR_OK;
244 }
245
246 static int lpc288x_erase(struct flash_bank *bank, int first, int last)
247 {
248 uint32_t status;
249 int sector;
250 struct target *target = bank->target;
251
252 status = lpc288x_system_ready(bank); /* probed? halted? */
253 if (status != ERROR_OK)
254 return status;
255
256 if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
257 LOG_INFO("Bad sector range");
258 return ERROR_FLASH_SECTOR_INVALID;
259 }
260
261 /* Configure the flash controller timing */
262 lpc288x_set_flash_clk(bank);
263
264 for (sector = first; sector <= last; sector++) {
265 if (lpc288x_wait_status_busy(bank, 1000) != ERROR_OK)
266 return ERROR_FLASH_OPERATION_FAILED;
267
268 lpc288x_load_timer(LOAD_TIMER_ERASE, target);
269
270 target_write_u32(target, bank->sectors[sector].offset, 0x00);
271
272 target_write_u32(target, F_CTRL, FC_PROG_REQ | FC_PROTECT | FC_CS);
273 }
274 if (lpc288x_wait_status_busy(bank, 1000) != ERROR_OK)
275 return ERROR_FLASH_OPERATION_FAILED;
276 return ERROR_OK;
277 }
278
279 static int lpc288x_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
280 {
281 uint8_t page_buffer[FLASH_PAGE_SIZE];
282 uint32_t status, source_offset, dest_offset;
283 struct target *target = bank->target;
284 uint32_t bytes_remaining = count;
285 uint32_t first_sector, last_sector, sector, page;
286 int i;
287
288 /* probed? halted? */
289 status = lpc288x_system_ready(bank);
290 if (status != ERROR_OK)
291 return status;
292
293 /* Initialise search indices */
294 first_sector = last_sector = 0xffffffff;
295
296 /* validate the write range... */
297 for (i = 0; i < bank->num_sectors; i++) {
298 if ((offset >= bank->sectors[i].offset) &&
299 (offset < (bank->sectors[i].offset + bank->sectors[i].size)) &&
300 (first_sector == 0xffffffff)) {
301 first_sector = i;
302 /* all writes must start on a sector boundary... */
303 if (offset % bank->sectors[i].size) {
304 LOG_INFO(
305 "offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "",
306 offset,
307 bank->sectors[i].size);
308 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
309 }
310 }
311 if (((offset + count) > bank->sectors[i].offset) &&
312 ((offset + count) <= (bank->sectors[i].offset + bank->sectors[i].size)) &&
313 (last_sector == 0xffffffff))
314 last_sector = i;
315 }
316
317 /* Range check... */
318 if (first_sector == 0xffffffff || last_sector == 0xffffffff) {
319 LOG_INFO("Range check failed %" PRIx32 " %" PRIx32 "", offset, count);
320 return ERROR_FLASH_DST_OUT_OF_BANK;
321 }
322
323 /* Configure the flash controller timing */
324 lpc288x_set_flash_clk(bank);
325
326 /* initialise the offsets */
327 source_offset = 0;
328 dest_offset = 0;
329
330 for (sector = first_sector; sector <= last_sector; sector++) {
331 for (page = 0; page < bank->sectors[sector].size / FLASH_PAGE_SIZE; page++) {
332 if (bytes_remaining == 0) {
333 count = 0;
334 memset(page_buffer, 0xFF, FLASH_PAGE_SIZE);
335 } else if (bytes_remaining < FLASH_PAGE_SIZE) {
336 count = bytes_remaining;
337 memset(page_buffer, 0xFF, FLASH_PAGE_SIZE);
338 memcpy(page_buffer, &buffer[source_offset], count);
339 } else {
340 count = FLASH_PAGE_SIZE;
341 memcpy(page_buffer, &buffer[source_offset], count);
342 }
343
344 /* Wait for flash to become ready */
345 if (lpc288x_wait_status_busy(bank, 1000) != ERROR_OK)
346 return ERROR_FLASH_OPERATION_FAILED;
347
348 /* fill flash data latches with 1's */
349 target_write_u32(target, F_CTRL, FC_CS | FC_SET_DATA | FC_WEN | FC_FUNC);
350
351 target_write_u32(target, F_CTRL, FC_CS | FC_WEN | FC_FUNC);
352
353 if (target_write_buffer(target, offset + dest_offset, FLASH_PAGE_SIZE,
354 page_buffer) != ERROR_OK) {
355 LOG_INFO("Write to flash buffer failed");
356 return ERROR_FLASH_OPERATION_FAILED;
357 }
358
359 dest_offset += FLASH_PAGE_SIZE;
360 source_offset += count;
361 bytes_remaining -= count;
362
363 lpc288x_load_timer(LOAD_TIMER_WRITE, target);
364
365 target_write_u32(target, F_CTRL, FC_PROG_REQ | FC_PROTECT | FC_FUNC |
366 FC_CS);
367 }
368 }
369
370 return ERROR_OK;
371 }
372
373 static int lpc288x_probe(struct flash_bank *bank)
374 {
375 /* we only deal with LPC2888 so flash config is fixed */
376 struct lpc288x_flash_bank *lpc288x_info = bank->driver_priv;
377 int retval;
378
379 if (lpc288x_info->cidr != 0)
380 return ERROR_OK;/* already probed */
381
382 if (bank->target->state != TARGET_HALTED) {
383 LOG_ERROR("Target not halted");
384 return ERROR_TARGET_NOT_HALTED;
385 }
386
387 retval = lpc288x_read_part_info(bank);
388 if (retval != ERROR_OK)
389 return retval;
390 return ERROR_OK;
391 }
392
393 static int lpc288x_protect(struct flash_bank *bank, int set, int first, int last)
394 {
395 int lockregion, status;
396 uint32_t value;
397 struct target *target = bank->target;
398
399 /* probed? halted? */
400 status = lpc288x_system_ready(bank);
401 if (status != ERROR_OK)
402 return status;
403
404 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
405 return ERROR_FLASH_SECTOR_INVALID;
406
407 /* Configure the flash controller timing */
408 lpc288x_set_flash_clk(bank);
409
410 for (lockregion = first; lockregion <= last; lockregion++) {
411 if (set) {
412 /* write an odd value to base addy to protect... */
413 value = 0x01;
414 } else {
415 /* write an even value to base addy to unprotect... */
416 value = 0x00;
417 }
418 target_write_u32(target, bank->sectors[lockregion].offset, value);
419 target_write_u32(target, F_CTRL, FC_LOAD_REQ | FC_PROTECT | FC_WEN | FC_FUNC |
420 FC_CS);
421 }
422
423 return ERROR_OK;
424 }
425
426 struct flash_driver lpc288x_flash = {
427 .name = "lpc288x",
428 .flash_bank_command = lpc288x_flash_bank_command,
429 .erase = lpc288x_erase,
430 .protect = lpc288x_protect,
431 .write = lpc288x_write,
432 .read = default_flash_read,
433 .probe = lpc288x_probe,
434 .auto_probe = lpc288x_probe,
435 .erase_check = lpc288x_erase_check,
436 .protect_check = lpc288x_protect_check,
437 .free_driver_priv = default_flash_free_driver_priv,
438 };
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