target algo: do not write reg_param if direction is PARAM_IN
[openocd.git] / src / flash / nor / kinetis.c
1 /***************************************************************************
2 * Copyright (C) 2011 by Mathias Kuester *
3 * kesmtp@freenet.de *
4 * *
5 * Copyright (C) 2011 sleep(5) ltd *
6 * tomas@sleepfive.com *
7 * *
8 * Copyright (C) 2012 by Christopher D. Kilgour *
9 * techie at whiterocker.com *
10 * *
11 * Copyright (C) 2013 Nemui Trinomius *
12 * nemuisan_kawausogasuki@live.jp *
13 * *
14 * Copyright (C) 2015 Tomas Vanek *
15 * vanekt@fbl.cz *
16 * *
17 * This program is free software; you can redistribute it and/or modify *
18 * it under the terms of the GNU General Public License as published by *
19 * the Free Software Foundation; either version 2 of the License, or *
20 * (at your option) any later version. *
21 * *
22 * This program is distributed in the hope that it will be useful, *
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
25 * GNU General Public License for more details. *
26 * *
27 * You should have received a copy of the GNU General Public License *
28 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
29 ***************************************************************************/
30
31 #ifdef HAVE_CONFIG_H
32 #include "config.h"
33 #endif
34
35 #include "jtag/interface.h"
36 #include "imp.h"
37 #include <helper/binarybuffer.h>
38 #include <helper/time_support.h>
39 #include <target/target_type.h>
40 #include <target/algorithm.h>
41 #include <target/armv7m.h>
42 #include <target/cortex_m.h>
43
44 /*
45 * Implementation Notes
46 *
47 * The persistent memories in the Kinetis chip families K10 through
48 * K70 are all manipulated with the Flash Memory Module. Some
49 * variants call this module the FTFE, others call it the FTFL. To
50 * indicate that both are considered here, we use FTFX.
51 *
52 * Within the module, according to the chip variant, the persistent
53 * memory is divided into what Freescale terms Program Flash, FlexNVM,
54 * and FlexRAM. All chip variants have Program Flash. Some chip
55 * variants also have FlexNVM and FlexRAM, which always appear
56 * together.
57 *
58 * A given Kinetis chip may have 1, 2 or 4 blocks of flash. Here we map
59 * each block to a separate bank. Each block size varies by chip and
60 * may be determined by the read-only SIM_FCFG1 register. The sector
61 * size within each bank/block varies by chip, and may be 1, 2 or 4k.
62 * The sector size may be different for flash and FlexNVM.
63 *
64 * The first half of the flash (1 or 2 blocks) is always Program Flash
65 * and always starts at address 0x00000000. The "PFLSH" flag, bit 23
66 * of the read-only SIM_FCFG2 register, determines whether the second
67 * half of the flash is also Program Flash or FlexNVM+FlexRAM. When
68 * PFLSH is set, the second from the first half. When PFLSH is clear,
69 * the second half of flash is FlexNVM and always starts at address
70 * 0x10000000. FlexRAM, which is also present when PFLSH is clear,
71 * always starts at address 0x14000000.
72 *
73 * The Flash Memory Module provides a register set where flash
74 * commands are loaded to perform flash operations like erase and
75 * program. Different commands are available depending on whether
76 * Program Flash or FlexNVM/FlexRAM is being manipulated. Although
77 * the commands used are quite consistent between flash blocks, the
78 * parameters they accept differ according to the flash sector size.
79 *
80 */
81
82 /* Addressess */
83 #define FCF_ADDRESS 0x00000400
84 #define FCF_FPROT 0x8
85 #define FCF_FSEC 0xc
86 #define FCF_FOPT 0xd
87 #define FCF_FDPROT 0xf
88 #define FCF_SIZE 0x10
89
90 #define FLEXRAM 0x14000000
91
92 #define MSCM_OCMDR0 0x40001400
93 #define FMC_PFB01CR 0x4001f004
94 #define FTFx_FSTAT 0x40020000
95 #define FTFx_FCNFG 0x40020001
96 #define FTFx_FCCOB3 0x40020004
97 #define FTFx_FPROT3 0x40020010
98 #define FTFx_FDPROT 0x40020017
99 #define SIM_BASE 0x40047000
100 #define SIM_BASE_KL28 0x40074000
101 #define SIM_COPC 0x40048100
102 /* SIM_COPC does not exist on devices with changed SIM_BASE */
103 #define WDOG_BASE 0x40052000
104 #define WDOG32_KE1X 0x40052000
105 #define WDOG32_KL28 0x40076000
106 #define SMC_PMCTRL 0x4007E001
107 #define SMC_PMSTAT 0x4007E003
108 #define SMC32_PMCTRL 0x4007E00C
109 #define SMC32_PMSTAT 0x4007E014
110 #define MCM_PLACR 0xF000300C
111
112 /* Offsets */
113 #define SIM_SOPT1_OFFSET 0x0000
114 #define SIM_SDID_OFFSET 0x1024
115 #define SIM_FCFG1_OFFSET 0x104c
116 #define SIM_FCFG2_OFFSET 0x1050
117
118 #define WDOG_STCTRLH_OFFSET 0
119 #define WDOG32_CS_OFFSET 0
120
121 /* Values */
122 #define PM_STAT_RUN 0x01
123 #define PM_STAT_VLPR 0x04
124 #define PM_CTRL_RUNM_RUN 0x00
125
126 /* Commands */
127 #define FTFx_CMD_BLOCKSTAT 0x00
128 #define FTFx_CMD_SECTSTAT 0x01
129 #define FTFx_CMD_LWORDPROG 0x06
130 #define FTFx_CMD_SECTERASE 0x09
131 #define FTFx_CMD_SECTWRITE 0x0b
132 #define FTFx_CMD_MASSERASE 0x44
133 #define FTFx_CMD_PGMPART 0x80
134 #define FTFx_CMD_SETFLEXRAM 0x81
135
136 /* The older Kinetis K series uses the following SDID layout :
137 * Bit 31-16 : 0
138 * Bit 15-12 : REVID
139 * Bit 11-7 : DIEID
140 * Bit 6-4 : FAMID
141 * Bit 3-0 : PINID
142 *
143 * The newer Kinetis series uses the following SDID layout :
144 * Bit 31-28 : FAMID
145 * Bit 27-24 : SUBFAMID
146 * Bit 23-20 : SERIESID
147 * Bit 19-16 : SRAMSIZE
148 * Bit 15-12 : REVID
149 * Bit 6-4 : Reserved (0)
150 * Bit 3-0 : PINID
151 *
152 * We assume that if bits 31-16 are 0 then it's an older
153 * K-series MCU.
154 */
155
156 #define KINETIS_SOPT1_RAMSIZE_MASK 0x0000F000
157 #define KINETIS_SOPT1_RAMSIZE_K24FN1M 0x0000B000
158
159 #define KINETIS_SDID_K_SERIES_MASK 0x0000FFFF
160
161 #define KINETIS_SDID_DIEID_MASK 0x00000F80
162
163 #define KINETIS_SDID_DIEID_K22FN128 0x00000680 /* smaller pflash with FTFA */
164 #define KINETIS_SDID_DIEID_K22FN256 0x00000A80
165 #define KINETIS_SDID_DIEID_K22FN512 0x00000E80
166 #define KINETIS_SDID_DIEID_K24FN256 0x00000700
167
168 #define KINETIS_SDID_DIEID_K24FN1M 0x00000300 /* Detect Errata 7534 */
169
170 /* We can't rely solely on the FAMID field to determine the MCU
171 * type since some FAMID values identify multiple MCUs with
172 * different flash sector sizes (K20 and K22 for instance).
173 * Therefore we combine it with the DIEID bits which may possibly
174 * break if Freescale bumps the DIEID for a particular MCU. */
175 #define KINETIS_K_SDID_TYPE_MASK 0x00000FF0
176 #define KINETIS_K_SDID_K10_M50 0x00000000
177 #define KINETIS_K_SDID_K10_M72 0x00000080
178 #define KINETIS_K_SDID_K10_M100 0x00000100
179 #define KINETIS_K_SDID_K10_M120 0x00000180
180 #define KINETIS_K_SDID_K11 0x00000220
181 #define KINETIS_K_SDID_K12 0x00000200
182 #define KINETIS_K_SDID_K20_M50 0x00000010
183 #define KINETIS_K_SDID_K20_M72 0x00000090
184 #define KINETIS_K_SDID_K20_M100 0x00000110
185 #define KINETIS_K_SDID_K20_M120 0x00000190
186 #define KINETIS_K_SDID_K21_M50 0x00000230
187 #define KINETIS_K_SDID_K21_M120 0x00000330
188 #define KINETIS_K_SDID_K22_M50 0x00000210
189 #define KINETIS_K_SDID_K22_M120 0x00000310
190 #define KINETIS_K_SDID_K30_M72 0x000000A0
191 #define KINETIS_K_SDID_K30_M100 0x00000120
192 #define KINETIS_K_SDID_K40_M72 0x000000B0
193 #define KINETIS_K_SDID_K40_M100 0x00000130
194 #define KINETIS_K_SDID_K50_M72 0x000000E0
195 #define KINETIS_K_SDID_K51_M72 0x000000F0
196 #define KINETIS_K_SDID_K53 0x00000170
197 #define KINETIS_K_SDID_K60_M100 0x00000140
198 #define KINETIS_K_SDID_K60_M150 0x000001C0
199 #define KINETIS_K_SDID_K70_M150 0x000001D0
200
201 #define KINETIS_SDID_SERIESID_MASK 0x00F00000
202 #define KINETIS_SDID_SERIESID_K 0x00000000
203 #define KINETIS_SDID_SERIESID_KL 0x00100000
204 #define KINETIS_SDID_SERIESID_KE 0x00200000
205 #define KINETIS_SDID_SERIESID_KW 0x00500000
206 #define KINETIS_SDID_SERIESID_KV 0x00600000
207
208 #define KINETIS_SDID_SUBFAMID_SHIFT 24
209 #define KINETIS_SDID_SUBFAMID_MASK 0x0F000000
210 #define KINETIS_SDID_SUBFAMID_KX0 0x00000000
211 #define KINETIS_SDID_SUBFAMID_KX1 0x01000000
212 #define KINETIS_SDID_SUBFAMID_KX2 0x02000000
213 #define KINETIS_SDID_SUBFAMID_KX3 0x03000000
214 #define KINETIS_SDID_SUBFAMID_KX4 0x04000000
215 #define KINETIS_SDID_SUBFAMID_KX5 0x05000000
216 #define KINETIS_SDID_SUBFAMID_KX6 0x06000000
217 #define KINETIS_SDID_SUBFAMID_KX7 0x07000000
218 #define KINETIS_SDID_SUBFAMID_KX8 0x08000000
219
220 #define KINETIS_SDID_FAMILYID_SHIFT 28
221 #define KINETIS_SDID_FAMILYID_MASK 0xF0000000
222 #define KINETIS_SDID_FAMILYID_K0X 0x00000000
223 #define KINETIS_SDID_FAMILYID_K1X 0x10000000
224 #define KINETIS_SDID_FAMILYID_K2X 0x20000000
225 #define KINETIS_SDID_FAMILYID_K3X 0x30000000
226 #define KINETIS_SDID_FAMILYID_K4X 0x40000000
227 #define KINETIS_SDID_FAMILYID_K5X 0x50000000
228 #define KINETIS_SDID_FAMILYID_K6X 0x60000000
229 #define KINETIS_SDID_FAMILYID_K7X 0x70000000
230 #define KINETIS_SDID_FAMILYID_K8X 0x80000000
231 #define KINETIS_SDID_FAMILYID_KL8X 0x90000000
232
233 /* The field originally named DIEID has new name/meaning on KE1x */
234 #define KINETIS_SDID_PROJECTID_MASK KINETIS_SDID_DIEID_MASK
235 #define KINETIS_SDID_PROJECTID_KE1xF 0x00000080
236 #define KINETIS_SDID_PROJECTID_KE1xZ 0x00000100
237
238 struct kinetis_flash_bank {
239 struct kinetis_chip *k_chip;
240 bool probed;
241 unsigned bank_number; /* bank number in particular chip */
242 struct flash_bank *bank;
243
244 uint32_t sector_size;
245 uint32_t protection_size;
246 uint32_t prog_base; /* base address for FTFx operations */
247 /* usually same as bank->base for pflash, differs for FlexNVM */
248 uint32_t protection_block; /* number of first protection block in this bank */
249
250 enum {
251 FC_AUTO = 0,
252 FC_PFLASH,
253 FC_FLEX_NVM,
254 FC_FLEX_RAM,
255 } flash_class;
256 };
257
258 #define KINETIS_MAX_BANKS 4u
259
260 struct kinetis_chip {
261 struct target *target;
262 bool probed;
263
264 uint32_t sim_sdid;
265 uint32_t sim_fcfg1;
266 uint32_t sim_fcfg2;
267 uint32_t fcfg2_maxaddr0_shifted;
268 uint32_t fcfg2_maxaddr1_shifted;
269
270 unsigned num_pflash_blocks, num_nvm_blocks;
271 unsigned pflash_sector_size, nvm_sector_size;
272 unsigned max_flash_prog_size;
273
274 uint32_t pflash_base;
275 uint32_t pflash_size;
276 uint32_t nvm_base;
277 uint32_t nvm_size; /* whole FlexNVM */
278 uint32_t dflash_size; /* accessible rest of FlexNVM if EEPROM backup uses part of FlexNVM */
279
280 uint32_t progr_accel_ram;
281 uint32_t sim_base;
282
283 enum {
284 FS_PROGRAM_SECTOR = 1,
285 FS_PROGRAM_LONGWORD = 2,
286 FS_PROGRAM_PHRASE = 4, /* Unsupported */
287
288 FS_NO_CMD_BLOCKSTAT = 0x40,
289 FS_WIDTH_256BIT = 0x80,
290 FS_ECC = 0x100,
291 } flash_support;
292
293 enum {
294 KINETIS_CACHE_NONE,
295 KINETIS_CACHE_K, /* invalidate using FMC->PFB0CR/PFB01CR */
296 KINETIS_CACHE_L, /* invalidate using MCM->PLACR */
297 KINETIS_CACHE_MSCM, /* devices like KE1xF, invalidate MSCM->OCMDR0 */
298 } cache_type;
299
300 enum {
301 KINETIS_WDOG_NONE,
302 KINETIS_WDOG_K,
303 KINETIS_WDOG_COP,
304 KINETIS_WDOG32_KE1X,
305 KINETIS_WDOG32_KL28,
306 } watchdog_type;
307
308 enum {
309 KINETIS_SMC,
310 KINETIS_SMC32,
311 } sysmodectrlr_type;
312
313 char name[40];
314
315 unsigned num_banks;
316 struct kinetis_flash_bank banks[KINETIS_MAX_BANKS];
317 };
318
319 struct kinetis_type {
320 uint32_t sdid;
321 char *name;
322 };
323
324 static const struct kinetis_type kinetis_types_old[] = {
325 { KINETIS_K_SDID_K10_M50, "MK10D%s5" },
326 { KINETIS_K_SDID_K10_M72, "MK10D%s7" },
327 { KINETIS_K_SDID_K10_M100, "MK10D%s10" },
328 { KINETIS_K_SDID_K10_M120, "MK10F%s12" },
329 { KINETIS_K_SDID_K11, "MK11D%s5" },
330 { KINETIS_K_SDID_K12, "MK12D%s5" },
331
332 { KINETIS_K_SDID_K20_M50, "MK20D%s5" },
333 { KINETIS_K_SDID_K20_M72, "MK20D%s7" },
334 { KINETIS_K_SDID_K20_M100, "MK20D%s10" },
335 { KINETIS_K_SDID_K20_M120, "MK20F%s12" },
336 { KINETIS_K_SDID_K21_M50, "MK21D%s5" },
337 { KINETIS_K_SDID_K21_M120, "MK21F%s12" },
338 { KINETIS_K_SDID_K22_M50, "MK22D%s5" },
339 { KINETIS_K_SDID_K22_M120, "MK22F%s12" },
340
341 { KINETIS_K_SDID_K30_M72, "MK30D%s7" },
342 { KINETIS_K_SDID_K30_M100, "MK30D%s10" },
343
344 { KINETIS_K_SDID_K40_M72, "MK40D%s7" },
345 { KINETIS_K_SDID_K40_M100, "MK40D%s10" },
346
347 { KINETIS_K_SDID_K50_M72, "MK50D%s7" },
348 { KINETIS_K_SDID_K51_M72, "MK51D%s7" },
349 { KINETIS_K_SDID_K53, "MK53D%s10" },
350
351 { KINETIS_K_SDID_K60_M100, "MK60D%s10" },
352 { KINETIS_K_SDID_K60_M150, "MK60F%s15" },
353
354 { KINETIS_K_SDID_K70_M150, "MK70F%s15" },
355 };
356
357
358 #define MDM_AP 1
359
360 #define MDM_REG_STAT 0x00
361 #define MDM_REG_CTRL 0x04
362 #define MDM_REG_ID 0xfc
363
364 #define MDM_STAT_FMEACK (1<<0)
365 #define MDM_STAT_FREADY (1<<1)
366 #define MDM_STAT_SYSSEC (1<<2)
367 #define MDM_STAT_SYSRES (1<<3)
368 #define MDM_STAT_FMEEN (1<<5)
369 #define MDM_STAT_BACKDOOREN (1<<6)
370 #define MDM_STAT_LPEN (1<<7)
371 #define MDM_STAT_VLPEN (1<<8)
372 #define MDM_STAT_LLSMODEXIT (1<<9)
373 #define MDM_STAT_VLLSXMODEXIT (1<<10)
374 #define MDM_STAT_CORE_HALTED (1<<16)
375 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
376 #define MDM_STAT_CORESLEEPING (1<<18)
377
378 #define MDM_CTRL_FMEIP (1<<0)
379 #define MDM_CTRL_DBG_DIS (1<<1)
380 #define MDM_CTRL_DBG_REQ (1<<2)
381 #define MDM_CTRL_SYS_RES_REQ (1<<3)
382 #define MDM_CTRL_CORE_HOLD_RES (1<<4)
383 #define MDM_CTRL_VLLSX_DBG_REQ (1<<5)
384 #define MDM_CTRL_VLLSX_DBG_ACK (1<<6)
385 #define MDM_CTRL_VLLSX_STAT_ACK (1<<7)
386
387 #define MDM_ACCESS_TIMEOUT 500 /* msec */
388
389
390 static bool allow_fcf_writes;
391 static uint8_t fcf_fopt = 0xff;
392 static bool fcf_fopt_configured;
393 static bool create_banks;
394
395
396 struct flash_driver kinetis_flash;
397 static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
398 uint32_t offset, uint32_t count);
399 static int kinetis_probe_chip(struct kinetis_chip *k_chip);
400 static int kinetis_auto_probe(struct flash_bank *bank);
401
402
403 static int kinetis_mdm_write_register(struct adiv5_dap *dap, unsigned reg, uint32_t value)
404 {
405 int retval;
406 LOG_DEBUG("MDM_REG[0x%02x] <- %08" PRIX32, reg, value);
407
408 retval = dap_queue_ap_write(dap_ap(dap, MDM_AP), reg, value);
409 if (retval != ERROR_OK) {
410 LOG_DEBUG("MDM: failed to queue a write request");
411 return retval;
412 }
413
414 retval = dap_run(dap);
415 if (retval != ERROR_OK) {
416 LOG_DEBUG("MDM: dap_run failed");
417 return retval;
418 }
419
420
421 return ERROR_OK;
422 }
423
424 static int kinetis_mdm_read_register(struct adiv5_dap *dap, unsigned reg, uint32_t *result)
425 {
426 int retval;
427
428 retval = dap_queue_ap_read(dap_ap(dap, MDM_AP), reg, result);
429 if (retval != ERROR_OK) {
430 LOG_DEBUG("MDM: failed to queue a read request");
431 return retval;
432 }
433
434 retval = dap_run(dap);
435 if (retval != ERROR_OK) {
436 LOG_DEBUG("MDM: dap_run failed");
437 return retval;
438 }
439
440 LOG_DEBUG("MDM_REG[0x%02x]: %08" PRIX32, reg, *result);
441 return ERROR_OK;
442 }
443
444 static int kinetis_mdm_poll_register(struct adiv5_dap *dap, unsigned reg,
445 uint32_t mask, uint32_t value, uint32_t timeout_ms)
446 {
447 uint32_t val;
448 int retval;
449 int64_t ms_timeout = timeval_ms() + timeout_ms;
450
451 do {
452 retval = kinetis_mdm_read_register(dap, reg, &val);
453 if (retval != ERROR_OK || (val & mask) == value)
454 return retval;
455
456 alive_sleep(1);
457 } while (timeval_ms() < ms_timeout);
458
459 LOG_DEBUG("MDM: polling timed out");
460 return ERROR_FAIL;
461 }
462
463 /*
464 * This command can be used to break a watchdog reset loop when
465 * connecting to an unsecured target. Unlike other commands, halt will
466 * automatically retry as it does not know how far into the boot process
467 * it is when the command is called.
468 */
469 COMMAND_HANDLER(kinetis_mdm_halt)
470 {
471 struct target *target = get_current_target(CMD_CTX);
472 struct cortex_m_common *cortex_m = target_to_cm(target);
473 struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
474 int retval;
475 int tries = 0;
476 uint32_t stat;
477 int64_t ms_timeout = timeval_ms() + MDM_ACCESS_TIMEOUT;
478
479 if (!dap) {
480 LOG_ERROR("Cannot perform halt with a high-level adapter");
481 return ERROR_FAIL;
482 }
483
484 while (true) {
485 tries++;
486
487 kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_CORE_HOLD_RES);
488
489 alive_sleep(1);
490
491 retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &stat);
492 if (retval != ERROR_OK) {
493 LOG_DEBUG("MDM: failed to read MDM_REG_STAT");
494 continue;
495 }
496
497 /* Repeat setting MDM_CTRL_CORE_HOLD_RES until system is out of
498 * reset with flash ready and without security
499 */
500 if ((stat & (MDM_STAT_FREADY | MDM_STAT_SYSSEC | MDM_STAT_SYSRES))
501 == (MDM_STAT_FREADY | MDM_STAT_SYSRES))
502 break;
503
504 if (timeval_ms() >= ms_timeout) {
505 LOG_ERROR("MDM: halt timed out");
506 return ERROR_FAIL;
507 }
508 }
509
510 LOG_DEBUG("MDM: halt succeded after %d attempts.", tries);
511
512 target_poll(target);
513 /* enable polling in case kinetis_check_flash_security_status disabled it */
514 jtag_poll_set_enabled(true);
515
516 alive_sleep(100);
517
518 target->reset_halt = true;
519 target->type->assert_reset(target);
520
521 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
522 if (retval != ERROR_OK) {
523 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
524 return retval;
525 }
526
527 target->type->deassert_reset(target);
528
529 return ERROR_OK;
530 }
531
532 COMMAND_HANDLER(kinetis_mdm_reset)
533 {
534 struct target *target = get_current_target(CMD_CTX);
535 struct cortex_m_common *cortex_m = target_to_cm(target);
536 struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
537 int retval;
538
539 if (!dap) {
540 LOG_ERROR("Cannot perform reset with a high-level adapter");
541 return ERROR_FAIL;
542 }
543
544 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_SYS_RES_REQ);
545 if (retval != ERROR_OK) {
546 LOG_ERROR("MDM: failed to write MDM_REG_CTRL");
547 return retval;
548 }
549
550 retval = kinetis_mdm_poll_register(dap, MDM_REG_STAT, MDM_STAT_SYSRES, 0, 500);
551 if (retval != ERROR_OK) {
552 LOG_ERROR("MDM: failed to assert reset");
553 return retval;
554 }
555
556 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
557 if (retval != ERROR_OK) {
558 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
559 return retval;
560 }
561
562 return ERROR_OK;
563 }
564
565 /*
566 * This function implements the procedure to mass erase the flash via
567 * SWD/JTAG on Kinetis K and L series of devices as it is described in
568 * AN4835 "Production Flash Programming Best Practices for Kinetis K-
569 * and L-series MCUs" Section 4.2.1. To prevent a watchdog reset loop,
570 * the core remains halted after this function completes as suggested
571 * by the application note.
572 */
573 COMMAND_HANDLER(kinetis_mdm_mass_erase)
574 {
575 struct target *target = get_current_target(CMD_CTX);
576 struct cortex_m_common *cortex_m = target_to_cm(target);
577 struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
578
579 if (!dap) {
580 LOG_ERROR("Cannot perform mass erase with a high-level adapter");
581 return ERROR_FAIL;
582 }
583
584 int retval;
585
586 /*
587 * ... Power on the processor, or if power has already been
588 * applied, assert the RESET pin to reset the processor. For
589 * devices that do not have a RESET pin, write the System
590 * Reset Request bit in the MDM-AP control register after
591 * establishing communication...
592 */
593
594 /* assert SRST if configured */
595 bool has_srst = jtag_get_reset_config() & RESET_HAS_SRST;
596 if (has_srst)
597 adapter_assert_reset();
598
599 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_SYS_RES_REQ);
600 if (retval != ERROR_OK && !has_srst) {
601 LOG_ERROR("MDM: failed to assert reset");
602 goto deassert_reset_and_exit;
603 }
604
605 /*
606 * ... Read the MDM-AP status register repeatedly and wait for
607 * stable conditions suitable for mass erase:
608 * - mass erase is enabled
609 * - flash is ready
610 * - reset is finished
611 *
612 * Mass erase is started as soon as all conditions are met in 32
613 * subsequent status reads.
614 *
615 * In case of not stable conditions (RESET/WDOG loop in secured device)
616 * the user is asked for manual pressing of RESET button
617 * as a last resort.
618 */
619 int cnt_mass_erase_disabled = 0;
620 int cnt_ready = 0;
621 int64_t ms_start = timeval_ms();
622 bool man_reset_requested = false;
623
624 do {
625 uint32_t stat = 0;
626 int64_t ms_elapsed = timeval_ms() - ms_start;
627
628 if (!man_reset_requested && ms_elapsed > 100) {
629 LOG_INFO("MDM: Press RESET button now if possible.");
630 man_reset_requested = true;
631 }
632
633 if (ms_elapsed > 3000) {
634 LOG_ERROR("MDM: waiting for mass erase conditions timed out.");
635 LOG_INFO("Mass erase of a secured MCU is not possible without hardware reset.");
636 LOG_INFO("Connect SRST, use 'reset_config srst_only' and retry.");
637 goto deassert_reset_and_exit;
638 }
639 retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &stat);
640 if (retval != ERROR_OK) {
641 cnt_ready = 0;
642 continue;
643 }
644
645 if (!(stat & MDM_STAT_FMEEN)) {
646 cnt_ready = 0;
647 cnt_mass_erase_disabled++;
648 if (cnt_mass_erase_disabled > 10) {
649 LOG_ERROR("MDM: mass erase is disabled");
650 goto deassert_reset_and_exit;
651 }
652 continue;
653 }
654
655 if ((stat & (MDM_STAT_FREADY | MDM_STAT_SYSRES)) == MDM_STAT_FREADY)
656 cnt_ready++;
657 else
658 cnt_ready = 0;
659
660 } while (cnt_ready < 32);
661
662 /*
663 * ... Write the MDM-AP control register to set the Flash Mass
664 * Erase in Progress bit. This will start the mass erase
665 * process...
666 */
667 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_SYS_RES_REQ | MDM_CTRL_FMEIP);
668 if (retval != ERROR_OK) {
669 LOG_ERROR("MDM: failed to start mass erase");
670 goto deassert_reset_and_exit;
671 }
672
673 /*
674 * ... Read the MDM-AP control register until the Flash Mass
675 * Erase in Progress bit clears...
676 * Data sheed defines erase time <3.6 sec/512kB flash block.
677 * The biggest device has 4 pflash blocks => timeout 16 sec.
678 */
679 retval = kinetis_mdm_poll_register(dap, MDM_REG_CTRL, MDM_CTRL_FMEIP, 0, 16000);
680 if (retval != ERROR_OK) {
681 LOG_ERROR("MDM: mass erase timeout");
682 goto deassert_reset_and_exit;
683 }
684
685 target_poll(target);
686 /* enable polling in case kinetis_check_flash_security_status disabled it */
687 jtag_poll_set_enabled(true);
688
689 alive_sleep(100);
690
691 target->reset_halt = true;
692 target->type->assert_reset(target);
693
694 /*
695 * ... Negate the RESET signal or clear the System Reset Request
696 * bit in the MDM-AP control register.
697 */
698 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
699 if (retval != ERROR_OK)
700 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
701
702 target->type->deassert_reset(target);
703
704 return retval;
705
706 deassert_reset_and_exit:
707 kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
708 if (has_srst)
709 adapter_deassert_reset();
710 return retval;
711 }
712
713 static const uint32_t kinetis_known_mdm_ids[] = {
714 0x001C0000, /* Kinetis-K Series */
715 0x001C0020, /* Kinetis-L/M/V/E Series */
716 0x001C0030, /* Kinetis with a Cortex-M7, in time of writing KV58 */
717 };
718
719 /*
720 * This function implements the procedure to connect to
721 * SWD/JTAG on Kinetis K and L series of devices as it is described in
722 * AN4835 "Production Flash Programming Best Practices for Kinetis K-
723 * and L-series MCUs" Section 4.1.1
724 */
725 COMMAND_HANDLER(kinetis_check_flash_security_status)
726 {
727 struct target *target = get_current_target(CMD_CTX);
728 struct cortex_m_common *cortex_m = target_to_cm(target);
729 struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
730
731 if (!dap) {
732 LOG_WARNING("Cannot check flash security status with a high-level adapter");
733 return ERROR_OK;
734 }
735
736 if (!dap->ops)
737 return ERROR_OK; /* too early to check, in JTAG mode ops may not be initialised */
738
739 uint32_t val;
740 int retval;
741
742 /*
743 * ... The MDM-AP ID register can be read to verify that the
744 * connection is working correctly...
745 */
746 retval = kinetis_mdm_read_register(dap, MDM_REG_ID, &val);
747 if (retval != ERROR_OK) {
748 LOG_ERROR("MDM: failed to read ID register");
749 return ERROR_OK;
750 }
751
752 if (val == 0)
753 return ERROR_OK; /* dap not yet initialised */
754
755 bool found = false;
756 for (size_t i = 0; i < ARRAY_SIZE(kinetis_known_mdm_ids); i++) {
757 if (val == kinetis_known_mdm_ids[i]) {
758 found = true;
759 break;
760 }
761 }
762
763 if (!found)
764 LOG_WARNING("MDM: unknown ID %08" PRIX32, val);
765
766 /*
767 * ... Read the System Security bit to determine if security is enabled.
768 * If System Security = 0, then proceed. If System Security = 1, then
769 * communication with the internals of the processor, including the
770 * flash, will not be possible without issuing a mass erase command or
771 * unsecuring the part through other means (backdoor key unlock)...
772 */
773 retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &val);
774 if (retval != ERROR_OK) {
775 LOG_ERROR("MDM: failed to read MDM_REG_STAT");
776 return ERROR_OK;
777 }
778
779 /*
780 * System Security bit is also active for short time during reset.
781 * If a MCU has blank flash and runs in RESET/WDOG loop,
782 * System Security bit is active most of time!
783 * We should observe Flash Ready bit and read status several times
784 * to avoid false detection of secured MCU
785 */
786 int secured_score = 0, flash_not_ready_score = 0;
787
788 if ((val & (MDM_STAT_SYSSEC | MDM_STAT_FREADY)) != MDM_STAT_FREADY) {
789 uint32_t stats[32];
790 int i;
791
792 for (i = 0; i < 32; i++) {
793 stats[i] = MDM_STAT_FREADY;
794 dap_queue_ap_read(dap_ap(dap, MDM_AP), MDM_REG_STAT, &stats[i]);
795 }
796 retval = dap_run(dap);
797 if (retval != ERROR_OK) {
798 LOG_DEBUG("MDM: dap_run failed when validating secured state");
799 return ERROR_OK;
800 }
801 for (i = 0; i < 32; i++) {
802 if (stats[i] & MDM_STAT_SYSSEC)
803 secured_score++;
804 if (!(stats[i] & MDM_STAT_FREADY))
805 flash_not_ready_score++;
806 }
807 }
808
809 if (flash_not_ready_score <= 8 && secured_score > 24) {
810 jtag_poll_set_enabled(false);
811
812 LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
813 LOG_WARNING("**** ****");
814 LOG_WARNING("**** Your Kinetis MCU is in secured state, which means that, ****");
815 LOG_WARNING("**** with exception for very basic communication, JTAG/SWD ****");
816 LOG_WARNING("**** interface will NOT work. In order to restore its ****");
817 LOG_WARNING("**** functionality please issue 'kinetis mdm mass_erase' ****");
818 LOG_WARNING("**** command, power cycle the MCU and restart OpenOCD. ****");
819 LOG_WARNING("**** ****");
820 LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
821
822 } else if (flash_not_ready_score > 24) {
823 jtag_poll_set_enabled(false);
824 LOG_WARNING("**** Your Kinetis MCU is probably locked-up in RESET/WDOG loop. ****");
825 LOG_WARNING("**** Common reason is a blank flash (at least a reset vector). ****");
826 LOG_WARNING("**** Issue 'kinetis mdm halt' command or if SRST is connected ****");
827 LOG_WARNING("**** and configured, use 'reset halt' ****");
828 LOG_WARNING("**** If MCU cannot be halted, it is likely secured and running ****");
829 LOG_WARNING("**** in RESET/WDOG loop. Issue 'kinetis mdm mass_erase' ****");
830
831 } else {
832 LOG_INFO("MDM: Chip is unsecured. Continuing.");
833 jtag_poll_set_enabled(true);
834 }
835
836 return ERROR_OK;
837 }
838
839
840 static struct kinetis_chip *kinetis_get_chip(struct target *target)
841 {
842 struct flash_bank *bank_iter;
843 struct kinetis_flash_bank *k_bank;
844
845 /* iterate over all kinetis banks */
846 for (bank_iter = flash_bank_list(); bank_iter; bank_iter = bank_iter->next) {
847 if (bank_iter->driver != &kinetis_flash
848 || bank_iter->target != target)
849 continue;
850
851 k_bank = bank_iter->driver_priv;
852 if (!k_bank)
853 continue;
854
855 if (k_bank->k_chip)
856 return k_bank->k_chip;
857 }
858 return NULL;
859 }
860
861 static int kinetis_chip_options(struct kinetis_chip *k_chip, int argc, const char *argv[])
862 {
863 int i;
864 for (i = 0; i < argc; i++) {
865 if (strcmp(argv[i], "-sim-base") == 0) {
866 if (i + 1 < argc)
867 k_chip->sim_base = strtoul(argv[++i], NULL, 0);
868 } else
869 LOG_ERROR("Unsupported flash bank option %s", argv[i]);
870 }
871 return ERROR_OK;
872 }
873
874 FLASH_BANK_COMMAND_HANDLER(kinetis_flash_bank_command)
875 {
876 struct target *target = bank->target;
877 struct kinetis_chip *k_chip;
878 struct kinetis_flash_bank *k_bank;
879 int retval;
880
881 if (CMD_ARGC < 6)
882 return ERROR_COMMAND_SYNTAX_ERROR;
883
884 LOG_INFO("add flash_bank kinetis %s", bank->name);
885
886 k_chip = kinetis_get_chip(target);
887
888 if (k_chip == NULL) {
889 k_chip = calloc(sizeof(struct kinetis_chip), 1);
890 if (k_chip == NULL) {
891 LOG_ERROR("No memory");
892 return ERROR_FAIL;
893 }
894
895 k_chip->target = target;
896
897 /* only the first defined bank can define chip options */
898 retval = kinetis_chip_options(k_chip, CMD_ARGC - 6, CMD_ARGV + 6);
899 if (retval != ERROR_OK)
900 return retval;
901 }
902
903 if (k_chip->num_banks >= KINETIS_MAX_BANKS) {
904 LOG_ERROR("Only %u Kinetis flash banks are supported", KINETIS_MAX_BANKS);
905 return ERROR_FAIL;
906 }
907
908 bank->driver_priv = k_bank = &(k_chip->banks[k_chip->num_banks]);
909 k_bank->k_chip = k_chip;
910 k_bank->bank_number = k_chip->num_banks;
911 k_bank->bank = bank;
912 k_chip->num_banks++;
913
914 return ERROR_OK;
915 }
916
917
918 static void kinetis_free_driver_priv(struct flash_bank *bank)
919 {
920 struct kinetis_flash_bank *k_bank = bank->driver_priv;
921 if (k_bank == NULL)
922 return;
923
924 struct kinetis_chip *k_chip = k_bank->k_chip;
925 if (k_chip == NULL)
926 return;
927
928 k_chip->num_banks--;
929 if (k_chip->num_banks == 0)
930 free(k_chip);
931 }
932
933
934 static int kinetis_create_missing_banks(struct kinetis_chip *k_chip)
935 {
936 unsigned bank_idx;
937 unsigned num_blocks;
938 struct kinetis_flash_bank *k_bank;
939 struct flash_bank *bank;
940 char base_name[69], name[80], num[4];
941 char *class, *p;
942
943 num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
944 if (num_blocks > KINETIS_MAX_BANKS) {
945 LOG_ERROR("Only %u Kinetis flash banks are supported", KINETIS_MAX_BANKS);
946 return ERROR_FAIL;
947 }
948
949 bank = k_chip->banks[0].bank;
950 if (bank && bank->name) {
951 strncpy(base_name, bank->name, sizeof(base_name) - 1);
952 base_name[sizeof(base_name) - 1] = '\0';
953 p = strstr(base_name, ".pflash");
954 if (p) {
955 *p = '\0';
956 if (k_chip->num_pflash_blocks > 1) {
957 /* rename first bank if numbering is needed */
958 snprintf(name, sizeof(name), "%s.pflash0", base_name);
959 free(bank->name);
960 bank->name = strdup(name);
961 }
962 }
963 } else {
964 strncpy(base_name, target_name(k_chip->target), sizeof(base_name) - 1);
965 base_name[sizeof(base_name) - 1] = '\0';
966 p = strstr(base_name, ".cpu");
967 if (p)
968 *p = '\0';
969 }
970
971 for (bank_idx = 1; bank_idx < num_blocks; bank_idx++) {
972 k_bank = &(k_chip->banks[bank_idx]);
973 bank = k_bank->bank;
974
975 if (bank)
976 continue;
977
978 num[0] = '\0';
979
980 if (bank_idx < k_chip->num_pflash_blocks) {
981 class = "pflash";
982 if (k_chip->num_pflash_blocks > 1)
983 snprintf(num, sizeof(num), "%u", bank_idx);
984 } else {
985 class = "flexnvm";
986 if (k_chip->num_nvm_blocks > 1)
987 snprintf(num, sizeof(num), "%u",
988 bank_idx - k_chip->num_pflash_blocks);
989 }
990
991 bank = calloc(sizeof(struct flash_bank), 1);
992 if (bank == NULL)
993 return ERROR_FAIL;
994
995 bank->target = k_chip->target;
996 bank->driver = &kinetis_flash;
997 bank->default_padded_value = bank->erased_value = 0xff;
998
999 snprintf(name, sizeof(name), "%s.%s%s",
1000 base_name, class, num);
1001 bank->name = strdup(name);
1002
1003 bank->driver_priv = k_bank = &(k_chip->banks[k_chip->num_banks]);
1004 k_bank->k_chip = k_chip;
1005 k_bank->bank_number = bank_idx;
1006 k_bank->bank = bank;
1007 if (k_chip->num_banks <= bank_idx)
1008 k_chip->num_banks = bank_idx + 1;
1009
1010 flash_bank_add(bank);
1011 }
1012 return ERROR_OK;
1013 }
1014
1015
1016 static int kinetis_disable_wdog_algo(struct target *target, size_t code_size, const uint8_t *code, uint32_t wdog_base)
1017 {
1018 struct working_area *wdog_algorithm;
1019 struct armv7m_algorithm armv7m_info;
1020 struct reg_param reg_params[1];
1021 int retval;
1022
1023 if (target->state != TARGET_HALTED) {
1024 LOG_ERROR("Target not halted");
1025 return ERROR_TARGET_NOT_HALTED;
1026 }
1027
1028 retval = target_alloc_working_area(target, code_size, &wdog_algorithm);
1029 if (retval != ERROR_OK)
1030 return retval;
1031
1032 retval = target_write_buffer(target, wdog_algorithm->address,
1033 code_size, code);
1034 if (retval == ERROR_OK) {
1035 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1036 armv7m_info.core_mode = ARM_MODE_THREAD;
1037
1038 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1039 buf_set_u32(reg_params[0].value, 0, 32, wdog_base);
1040
1041 retval = target_run_algorithm(target, 0, NULL, 1, reg_params,
1042 wdog_algorithm->address,
1043 wdog_algorithm->address + code_size - 2,
1044 500, &armv7m_info);
1045
1046 destroy_reg_param(&reg_params[0]);
1047
1048 if (retval != ERROR_OK)
1049 LOG_ERROR("Error executing Kinetis WDOG unlock algorithm");
1050 }
1051
1052 target_free_working_area(target, wdog_algorithm);
1053
1054 return retval;
1055 }
1056
1057 /* Disable the watchdog on Kinetis devices
1058 * Standard Kx WDOG peripheral checks timing and therefore requires to run algo.
1059 */
1060 static int kinetis_disable_wdog_kx(struct target *target)
1061 {
1062 const uint32_t wdog_base = WDOG_BASE;
1063 uint16_t wdog;
1064 int retval;
1065
1066 static const uint8_t kinetis_unlock_wdog_code[] = {
1067 #include "../../../contrib/loaders/watchdog/armv7m_kinetis_wdog.inc"
1068 };
1069
1070 retval = target_read_u16(target, wdog_base + WDOG_STCTRLH_OFFSET, &wdog);
1071 if (retval != ERROR_OK)
1072 return retval;
1073
1074 if ((wdog & 0x1) == 0) {
1075 /* watchdog already disabled */
1076 return ERROR_OK;
1077 }
1078 LOG_INFO("Disabling Kinetis watchdog (initial WDOG_STCTRLH = 0x%04" PRIx16 ")", wdog);
1079
1080 retval = kinetis_disable_wdog_algo(target, sizeof(kinetis_unlock_wdog_code), kinetis_unlock_wdog_code, wdog_base);
1081 if (retval != ERROR_OK)
1082 return retval;
1083
1084 retval = target_read_u16(target, wdog_base + WDOG_STCTRLH_OFFSET, &wdog);
1085 if (retval != ERROR_OK)
1086 return retval;
1087
1088 LOG_INFO("WDOG_STCTRLH = 0x%04" PRIx16, wdog);
1089 return (wdog & 0x1) ? ERROR_FAIL : ERROR_OK;
1090 }
1091
1092 static int kinetis_disable_wdog32(struct target *target, uint32_t wdog_base)
1093 {
1094 uint32_t wdog_cs;
1095 int retval;
1096
1097 static const uint8_t kinetis_unlock_wdog_code[] = {
1098 #include "../../../contrib/loaders/watchdog/armv7m_kinetis_wdog32.inc"
1099 };
1100
1101 retval = target_read_u32(target, wdog_base + WDOG32_CS_OFFSET, &wdog_cs);
1102 if (retval != ERROR_OK)
1103 return retval;
1104
1105 if ((wdog_cs & 0x80) == 0)
1106 return ERROR_OK; /* watchdog already disabled */
1107
1108 LOG_INFO("Disabling Kinetis watchdog (initial WDOG_CS 0x%08" PRIx32 ")", wdog_cs);
1109
1110 retval = kinetis_disable_wdog_algo(target, sizeof(kinetis_unlock_wdog_code), kinetis_unlock_wdog_code, wdog_base);
1111 if (retval != ERROR_OK)
1112 return retval;
1113
1114 retval = target_read_u32(target, wdog_base + WDOG32_CS_OFFSET, &wdog_cs);
1115 if (retval != ERROR_OK)
1116 return retval;
1117
1118 if ((wdog_cs & 0x80) == 0)
1119 return ERROR_OK; /* watchdog disabled successfully */
1120
1121 LOG_ERROR("Cannot disable Kinetis watchdog (WDOG_CS 0x%08" PRIx32 "), issue 'reset init'", wdog_cs);
1122 return ERROR_FAIL;
1123 }
1124
1125 static int kinetis_disable_wdog(struct kinetis_chip *k_chip)
1126 {
1127 struct target *target = k_chip->target;
1128 uint8_t sim_copc;
1129 int retval;
1130
1131 if (!k_chip->probed) {
1132 retval = kinetis_probe_chip(k_chip);
1133 if (retval != ERROR_OK)
1134 return retval;
1135 }
1136
1137 switch (k_chip->watchdog_type) {
1138 case KINETIS_WDOG_K:
1139 return kinetis_disable_wdog_kx(target);
1140
1141 case KINETIS_WDOG_COP:
1142 retval = target_read_u8(target, SIM_COPC, &sim_copc);
1143 if (retval != ERROR_OK)
1144 return retval;
1145
1146 if ((sim_copc & 0xc) == 0)
1147 return ERROR_OK; /* watchdog already disabled */
1148
1149 LOG_INFO("Disabling Kinetis watchdog (initial SIM_COPC 0x%02" PRIx8 ")", sim_copc);
1150 retval = target_write_u8(target, SIM_COPC, sim_copc & ~0xc);
1151 if (retval != ERROR_OK)
1152 return retval;
1153
1154 retval = target_read_u8(target, SIM_COPC, &sim_copc);
1155 if (retval != ERROR_OK)
1156 return retval;
1157
1158 if ((sim_copc & 0xc) == 0)
1159 return ERROR_OK; /* watchdog disabled successfully */
1160
1161 LOG_ERROR("Cannot disable Kinetis watchdog (SIM_COPC 0x%02" PRIx8 "), issue 'reset init'", sim_copc);
1162 return ERROR_FAIL;
1163
1164 case KINETIS_WDOG32_KE1X:
1165 return kinetis_disable_wdog32(target, WDOG32_KE1X);
1166
1167 case KINETIS_WDOG32_KL28:
1168 return kinetis_disable_wdog32(target, WDOG32_KL28);
1169
1170 default:
1171 return ERROR_OK;
1172 }
1173 }
1174
1175 COMMAND_HANDLER(kinetis_disable_wdog_handler)
1176 {
1177 int result;
1178 struct target *target = get_current_target(CMD_CTX);
1179 struct kinetis_chip *k_chip = kinetis_get_chip(target);
1180
1181 if (k_chip == NULL)
1182 return ERROR_FAIL;
1183
1184 if (CMD_ARGC > 0)
1185 return ERROR_COMMAND_SYNTAX_ERROR;
1186
1187 result = kinetis_disable_wdog(k_chip);
1188 return result;
1189 }
1190
1191
1192 static int kinetis_ftfx_decode_error(uint8_t fstat)
1193 {
1194 if (fstat & 0x20) {
1195 LOG_ERROR("Flash operation failed, illegal command");
1196 return ERROR_FLASH_OPER_UNSUPPORTED;
1197
1198 } else if (fstat & 0x10)
1199 LOG_ERROR("Flash operation failed, protection violated");
1200
1201 else if (fstat & 0x40)
1202 LOG_ERROR("Flash operation failed, read collision");
1203
1204 else if (fstat & 0x80)
1205 return ERROR_OK;
1206
1207 else
1208 LOG_ERROR("Flash operation timed out");
1209
1210 return ERROR_FLASH_OPERATION_FAILED;
1211 }
1212
1213 static int kinetis_ftfx_clear_error(struct target *target)
1214 {
1215 /* reset error flags */
1216 return target_write_u8(target, FTFx_FSTAT, 0x70);
1217 }
1218
1219
1220 static int kinetis_ftfx_prepare(struct target *target)
1221 {
1222 int result, i;
1223 uint8_t fstat;
1224
1225 /* wait until busy */
1226 for (i = 0; i < 50; i++) {
1227 result = target_read_u8(target, FTFx_FSTAT, &fstat);
1228 if (result != ERROR_OK)
1229 return result;
1230
1231 if (fstat & 0x80)
1232 break;
1233 }
1234
1235 if ((fstat & 0x80) == 0) {
1236 LOG_ERROR("Flash controller is busy");
1237 return ERROR_FLASH_OPERATION_FAILED;
1238 }
1239 if (fstat != 0x80) {
1240 /* reset error flags */
1241 result = kinetis_ftfx_clear_error(target);
1242 }
1243 return result;
1244 }
1245
1246 /* Kinetis Program-LongWord Microcodes */
1247 static const uint8_t kinetis_flash_write_code[] = {
1248 #include "../../../contrib/loaders/flash/kinetis/kinetis_flash.inc"
1249 };
1250
1251 /* Program LongWord Block Write */
1252 static int kinetis_write_block(struct flash_bank *bank, const uint8_t *buffer,
1253 uint32_t offset, uint32_t wcount)
1254 {
1255 struct target *target = bank->target;
1256 uint32_t buffer_size = 2048; /* Default minimum value */
1257 struct working_area *write_algorithm;
1258 struct working_area *source;
1259 struct kinetis_flash_bank *k_bank = bank->driver_priv;
1260 uint32_t address = k_bank->prog_base + offset;
1261 uint32_t end_address;
1262 struct reg_param reg_params[5];
1263 struct armv7m_algorithm armv7m_info;
1264 int retval;
1265 uint8_t fstat;
1266
1267 /* Increase buffer_size if needed */
1268 if (buffer_size < (target->working_area_size/2))
1269 buffer_size = (target->working_area_size/2);
1270
1271 /* allocate working area with flash programming code */
1272 if (target_alloc_working_area(target, sizeof(kinetis_flash_write_code),
1273 &write_algorithm) != ERROR_OK) {
1274 LOG_WARNING("no working area available, can't do block memory writes");
1275 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1276 }
1277
1278 retval = target_write_buffer(target, write_algorithm->address,
1279 sizeof(kinetis_flash_write_code), kinetis_flash_write_code);
1280 if (retval != ERROR_OK)
1281 return retval;
1282
1283 /* memory buffer */
1284 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
1285 buffer_size /= 4;
1286 if (buffer_size <= 256) {
1287 /* free working area, write algorithm already allocated */
1288 target_free_working_area(target, write_algorithm);
1289
1290 LOG_WARNING("No large enough working area available, can't do block memory writes");
1291 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1292 }
1293 }
1294
1295 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1296 armv7m_info.core_mode = ARM_MODE_THREAD;
1297
1298 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* address */
1299 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* word count */
1300 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1301 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1302 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1303
1304 buf_set_u32(reg_params[0].value, 0, 32, address);
1305 buf_set_u32(reg_params[1].value, 0, 32, wcount);
1306 buf_set_u32(reg_params[2].value, 0, 32, source->address);
1307 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
1308 buf_set_u32(reg_params[4].value, 0, 32, FTFx_FSTAT);
1309
1310 retval = target_run_flash_async_algorithm(target, buffer, wcount, 4,
1311 0, NULL,
1312 5, reg_params,
1313 source->address, source->size,
1314 write_algorithm->address, 0,
1315 &armv7m_info);
1316
1317 if (retval == ERROR_FLASH_OPERATION_FAILED) {
1318 end_address = buf_get_u32(reg_params[0].value, 0, 32);
1319
1320 LOG_ERROR("Error writing flash at %08" PRIx32, end_address);
1321
1322 retval = target_read_u8(target, FTFx_FSTAT, &fstat);
1323 if (retval == ERROR_OK) {
1324 retval = kinetis_ftfx_decode_error(fstat);
1325
1326 /* reset error flags */
1327 target_write_u8(target, FTFx_FSTAT, 0x70);
1328 }
1329 } else if (retval != ERROR_OK)
1330 LOG_ERROR("Error executing kinetis Flash programming algorithm");
1331
1332 target_free_working_area(target, source);
1333 target_free_working_area(target, write_algorithm);
1334
1335 destroy_reg_param(&reg_params[0]);
1336 destroy_reg_param(&reg_params[1]);
1337 destroy_reg_param(&reg_params[2]);
1338 destroy_reg_param(&reg_params[3]);
1339 destroy_reg_param(&reg_params[4]);
1340
1341 return retval;
1342 }
1343
1344 static int kinetis_protect(struct flash_bank *bank, int set, int first, int last)
1345 {
1346 int i;
1347
1348 if (allow_fcf_writes) {
1349 LOG_ERROR("Protection setting is possible with 'kinetis fcf_source protection' only!");
1350 return ERROR_FAIL;
1351 }
1352
1353 if (!bank->prot_blocks || bank->num_prot_blocks == 0) {
1354 LOG_ERROR("No protection possible for current bank!");
1355 return ERROR_FLASH_BANK_INVALID;
1356 }
1357
1358 for (i = first; i < bank->num_prot_blocks && i <= last; i++)
1359 bank->prot_blocks[i].is_protected = set;
1360
1361 LOG_INFO("Protection bits will be written at the next FCF sector erase or write.");
1362 LOG_INFO("Do not issue 'flash info' command until protection is written,");
1363 LOG_INFO("doing so would re-read protection status from MCU.");
1364
1365 return ERROR_OK;
1366 }
1367
1368 static int kinetis_protect_check(struct flash_bank *bank)
1369 {
1370 struct kinetis_flash_bank *k_bank = bank->driver_priv;
1371 int result;
1372 int i, b;
1373 uint32_t fprot;
1374
1375 if (k_bank->flash_class == FC_PFLASH) {
1376
1377 /* read protection register */
1378 result = target_read_u32(bank->target, FTFx_FPROT3, &fprot);
1379 if (result != ERROR_OK)
1380 return result;
1381
1382 /* Every bit protects 1/32 of the full flash (not necessarily just this bank) */
1383
1384 } else if (k_bank->flash_class == FC_FLEX_NVM) {
1385 uint8_t fdprot;
1386
1387 /* read protection register */
1388 result = target_read_u8(bank->target, FTFx_FDPROT, &fdprot);
1389 if (result != ERROR_OK)
1390 return result;
1391
1392 fprot = fdprot;
1393
1394 } else {
1395 LOG_ERROR("Protection checks for FlexRAM not supported");
1396 return ERROR_FLASH_BANK_INVALID;
1397 }
1398
1399 b = k_bank->protection_block;
1400 for (i = 0; i < bank->num_prot_blocks; i++) {
1401 if ((fprot >> b) & 1)
1402 bank->prot_blocks[i].is_protected = 0;
1403 else
1404 bank->prot_blocks[i].is_protected = 1;
1405
1406 b++;
1407 }
1408
1409 return ERROR_OK;
1410 }
1411
1412
1413 static int kinetis_fill_fcf(struct flash_bank *bank, uint8_t *fcf)
1414 {
1415 uint32_t fprot = 0xffffffff;
1416 uint8_t fsec = 0xfe; /* set MCU unsecure */
1417 uint8_t fdprot = 0xff;
1418 int i;
1419 unsigned bank_idx;
1420 unsigned num_blocks;
1421 uint32_t pflash_bit;
1422 uint8_t dflash_bit;
1423 struct flash_bank *bank_iter;
1424 struct kinetis_flash_bank *k_bank = bank->driver_priv;
1425 struct kinetis_chip *k_chip = k_bank->k_chip;
1426
1427 memset(fcf, 0xff, FCF_SIZE);
1428
1429 pflash_bit = 1;
1430 dflash_bit = 1;
1431
1432 /* iterate over all kinetis banks */
1433 /* current bank is bank 0, it contains FCF */
1434 num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
1435 for (bank_idx = 0; bank_idx < num_blocks; bank_idx++) {
1436 k_bank = &(k_chip->banks[bank_idx]);
1437 bank_iter = k_bank->bank;
1438
1439 if (bank_iter == NULL) {
1440 LOG_WARNING("Missing bank %u configuration, FCF protection flags may be incomplette", bank_idx);
1441 continue;
1442 }
1443
1444 kinetis_auto_probe(bank_iter);
1445
1446 if (k_bank->flash_class == FC_PFLASH) {
1447 for (i = 0; i < bank_iter->num_prot_blocks; i++) {
1448 if (bank_iter->prot_blocks[i].is_protected == 1)
1449 fprot &= ~pflash_bit;
1450
1451 pflash_bit <<= 1;
1452 }
1453
1454 } else if (k_bank->flash_class == FC_FLEX_NVM) {
1455 for (i = 0; i < bank_iter->num_prot_blocks; i++) {
1456 if (bank_iter->prot_blocks[i].is_protected == 1)
1457 fdprot &= ~dflash_bit;
1458
1459 dflash_bit <<= 1;
1460 }
1461
1462 }
1463 }
1464
1465 target_buffer_set_u32(bank->target, fcf + FCF_FPROT, fprot);
1466 fcf[FCF_FSEC] = fsec;
1467 fcf[FCF_FOPT] = fcf_fopt;
1468 fcf[FCF_FDPROT] = fdprot;
1469 return ERROR_OK;
1470 }
1471
1472 static int kinetis_ftfx_command(struct target *target, uint8_t fcmd, uint32_t faddr,
1473 uint8_t fccob4, uint8_t fccob5, uint8_t fccob6, uint8_t fccob7,
1474 uint8_t fccob8, uint8_t fccob9, uint8_t fccoba, uint8_t fccobb,
1475 uint8_t *ftfx_fstat)
1476 {
1477 uint8_t command[12] = {faddr & 0xff, (faddr >> 8) & 0xff, (faddr >> 16) & 0xff, fcmd,
1478 fccob7, fccob6, fccob5, fccob4,
1479 fccobb, fccoba, fccob9, fccob8};
1480 int result;
1481 uint8_t fstat;
1482 int64_t ms_timeout = timeval_ms() + 250;
1483
1484 result = target_write_memory(target, FTFx_FCCOB3, 4, 3, command);
1485 if (result != ERROR_OK)
1486 return result;
1487
1488 /* start command */
1489 result = target_write_u8(target, FTFx_FSTAT, 0x80);
1490 if (result != ERROR_OK)
1491 return result;
1492
1493 /* wait for done */
1494 do {
1495 result = target_read_u8(target, FTFx_FSTAT, &fstat);
1496
1497 if (result != ERROR_OK)
1498 return result;
1499
1500 if (fstat & 0x80)
1501 break;
1502
1503 } while (timeval_ms() < ms_timeout);
1504
1505 if (ftfx_fstat)
1506 *ftfx_fstat = fstat;
1507
1508 if ((fstat & 0xf0) != 0x80) {
1509 LOG_DEBUG("ftfx command failed FSTAT: %02X FCCOB: %02X%02X%02X%02X %02X%02X%02X%02X %02X%02X%02X%02X",
1510 fstat, command[3], command[2], command[1], command[0],
1511 command[7], command[6], command[5], command[4],
1512 command[11], command[10], command[9], command[8]);
1513
1514 return kinetis_ftfx_decode_error(fstat);
1515 }
1516
1517 return ERROR_OK;
1518 }
1519
1520
1521 static int kinetis_read_pmstat(struct kinetis_chip *k_chip, uint8_t *pmstat)
1522 {
1523 int result;
1524 uint32_t stat32;
1525 struct target *target = k_chip->target;
1526
1527 switch (k_chip->sysmodectrlr_type) {
1528 case KINETIS_SMC:
1529 result = target_read_u8(target, SMC_PMSTAT, pmstat);
1530 return result;
1531
1532 case KINETIS_SMC32:
1533 result = target_read_u32(target, SMC32_PMSTAT, &stat32);
1534 if (result == ERROR_OK)
1535 *pmstat = stat32 & 0xff;
1536 return result;
1537 }
1538 return ERROR_FAIL;
1539 }
1540
1541 static int kinetis_check_run_mode(struct kinetis_chip *k_chip)
1542 {
1543 int result, i;
1544 uint8_t pmstat;
1545 struct target *target;
1546
1547 if (k_chip == NULL) {
1548 LOG_ERROR("Chip not probed.");
1549 return ERROR_FAIL;
1550 }
1551 target = k_chip->target;
1552
1553 if (target->state != TARGET_HALTED) {
1554 LOG_ERROR("Target not halted");
1555 return ERROR_TARGET_NOT_HALTED;
1556 }
1557
1558 result = kinetis_read_pmstat(k_chip, &pmstat);
1559 if (result != ERROR_OK)
1560 return result;
1561
1562 if (pmstat == PM_STAT_RUN)
1563 return ERROR_OK;
1564
1565 if (pmstat == PM_STAT_VLPR) {
1566 /* It is safe to switch from VLPR to RUN mode without changing clock */
1567 LOG_INFO("Switching from VLPR to RUN mode.");
1568
1569 switch (k_chip->sysmodectrlr_type) {
1570 case KINETIS_SMC:
1571 result = target_write_u8(target, SMC_PMCTRL, PM_CTRL_RUNM_RUN);
1572 break;
1573
1574 case KINETIS_SMC32:
1575 result = target_write_u32(target, SMC32_PMCTRL, PM_CTRL_RUNM_RUN);
1576 break;
1577 }
1578 if (result != ERROR_OK)
1579 return result;
1580
1581 for (i = 100; i; i--) {
1582 result = kinetis_read_pmstat(k_chip, &pmstat);
1583 if (result != ERROR_OK)
1584 return result;
1585
1586 if (pmstat == PM_STAT_RUN)
1587 return ERROR_OK;
1588 }
1589 }
1590
1591 LOG_ERROR("Flash operation not possible in current run mode: SMC_PMSTAT: 0x%x", pmstat);
1592 LOG_ERROR("Issue a 'reset init' command.");
1593 return ERROR_TARGET_NOT_HALTED;
1594 }
1595
1596
1597 static void kinetis_invalidate_flash_cache(struct kinetis_chip *k_chip)
1598 {
1599 struct target *target = k_chip->target;
1600
1601 switch (k_chip->cache_type) {
1602 case KINETIS_CACHE_K:
1603 target_write_u8(target, FMC_PFB01CR + 2, 0xf0);
1604 /* Set CINV_WAY bits - request invalidate of all cache ways */
1605 /* FMC_PFB0CR has same address and CINV_WAY bits as FMC_PFB01CR */
1606 break;
1607
1608 case KINETIS_CACHE_L:
1609 target_write_u8(target, MCM_PLACR + 1, 0x04);
1610 /* set bit CFCC - Clear Flash Controller Cache */
1611 break;
1612
1613 case KINETIS_CACHE_MSCM:
1614 target_write_u32(target, MSCM_OCMDR0, 0x30);
1615 /* disable data prefetch and flash speculate */
1616 break;
1617
1618 default:
1619 break;
1620 }
1621 }
1622
1623
1624 static int kinetis_erase(struct flash_bank *bank, int first, int last)
1625 {
1626 int result, i;
1627 struct kinetis_flash_bank *k_bank = bank->driver_priv;
1628 struct kinetis_chip *k_chip = k_bank->k_chip;
1629
1630 result = kinetis_check_run_mode(k_chip);
1631 if (result != ERROR_OK)
1632 return result;
1633
1634 /* reset error flags */
1635 result = kinetis_ftfx_prepare(bank->target);
1636 if (result != ERROR_OK)
1637 return result;
1638
1639 if ((first > bank->num_sectors) || (last > bank->num_sectors))
1640 return ERROR_FLASH_OPERATION_FAILED;
1641
1642 /*
1643 * FIXME: TODO: use the 'Erase Flash Block' command if the
1644 * requested erase is PFlash or NVM and encompasses the entire
1645 * block. Should be quicker.
1646 */
1647 for (i = first; i <= last; i++) {
1648 /* set command and sector address */
1649 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTERASE, k_bank->prog_base + bank->sectors[i].offset,
1650 0, 0, 0, 0, 0, 0, 0, 0, NULL);
1651
1652 if (result != ERROR_OK) {
1653 LOG_WARNING("erase sector %d failed", i);
1654 return ERROR_FLASH_OPERATION_FAILED;
1655 }
1656
1657 bank->sectors[i].is_erased = 1;
1658
1659 if (k_bank->prog_base == 0
1660 && bank->sectors[i].offset <= FCF_ADDRESS
1661 && bank->sectors[i].offset + bank->sectors[i].size > FCF_ADDRESS + FCF_SIZE) {
1662 if (allow_fcf_writes) {
1663 LOG_WARNING("Flash Configuration Field erased, DO NOT reset or power off the device");
1664 LOG_WARNING("until correct FCF is programmed or MCU gets security lock.");
1665 } else {
1666 uint8_t fcf_buffer[FCF_SIZE];
1667
1668 kinetis_fill_fcf(bank, fcf_buffer);
1669 result = kinetis_write_inner(bank, fcf_buffer, FCF_ADDRESS, FCF_SIZE);
1670 if (result != ERROR_OK)
1671 LOG_WARNING("Flash Configuration Field write failed");
1672 bank->sectors[i].is_erased = 0;
1673 }
1674 }
1675 }
1676
1677 kinetis_invalidate_flash_cache(k_bank->k_chip);
1678
1679 return ERROR_OK;
1680 }
1681
1682 static int kinetis_make_ram_ready(struct target *target)
1683 {
1684 int result;
1685 uint8_t ftfx_fcnfg;
1686
1687 /* check if ram ready */
1688 result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
1689 if (result != ERROR_OK)
1690 return result;
1691
1692 if (ftfx_fcnfg & (1 << 1))
1693 return ERROR_OK; /* ram ready */
1694
1695 /* make flex ram available */
1696 result = kinetis_ftfx_command(target, FTFx_CMD_SETFLEXRAM, 0x00ff0000,
1697 0, 0, 0, 0, 0, 0, 0, 0, NULL);
1698 if (result != ERROR_OK)
1699 return ERROR_FLASH_OPERATION_FAILED;
1700
1701 /* check again */
1702 result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
1703 if (result != ERROR_OK)
1704 return result;
1705
1706 if (ftfx_fcnfg & (1 << 1))
1707 return ERROR_OK; /* ram ready */
1708
1709 return ERROR_FLASH_OPERATION_FAILED;
1710 }
1711
1712
1713 static int kinetis_write_sections(struct flash_bank *bank, const uint8_t *buffer,
1714 uint32_t offset, uint32_t count)
1715 {
1716 int result = ERROR_OK;
1717 struct kinetis_flash_bank *k_bank = bank->driver_priv;
1718 struct kinetis_chip *k_chip = k_bank->k_chip;
1719 uint8_t *buffer_aligned = NULL;
1720 /*
1721 * Kinetis uses different terms for the granularity of
1722 * sector writes, e.g. "phrase" or "128 bits". We use
1723 * the generic term "chunk". The largest possible
1724 * Kinetis "chunk" is 16 bytes (128 bits).
1725 */
1726 uint32_t prog_section_chunk_bytes = k_bank->sector_size >> 8;
1727 uint32_t prog_size_bytes = k_chip->max_flash_prog_size;
1728
1729 while (count > 0) {
1730 uint32_t size = prog_size_bytes - offset % prog_size_bytes;
1731 uint32_t align_begin = offset % prog_section_chunk_bytes;
1732 uint32_t align_end;
1733 uint32_t size_aligned;
1734 uint16_t chunk_count;
1735 uint8_t ftfx_fstat;
1736
1737 if (size > count)
1738 size = count;
1739
1740 align_end = (align_begin + size) % prog_section_chunk_bytes;
1741 if (align_end)
1742 align_end = prog_section_chunk_bytes - align_end;
1743
1744 size_aligned = align_begin + size + align_end;
1745 chunk_count = size_aligned / prog_section_chunk_bytes;
1746
1747 if (size != size_aligned) {
1748 /* aligned section: the first, the last or the only */
1749 if (!buffer_aligned)
1750 buffer_aligned = malloc(prog_size_bytes);
1751
1752 memset(buffer_aligned, 0xff, size_aligned);
1753 memcpy(buffer_aligned + align_begin, buffer, size);
1754
1755 result = target_write_memory(bank->target, k_chip->progr_accel_ram,
1756 4, size_aligned / 4, buffer_aligned);
1757
1758 LOG_DEBUG("section @ %08" PRIx32 " aligned begin %" PRIu32 ", end %" PRIu32,
1759 bank->base + offset, align_begin, align_end);
1760 } else
1761 result = target_write_memory(bank->target, k_chip->progr_accel_ram,
1762 4, size_aligned / 4, buffer);
1763
1764 LOG_DEBUG("write section @ %08" PRIx32 " with length %" PRIu32 " bytes",
1765 bank->base + offset, size);
1766
1767 if (result != ERROR_OK) {
1768 LOG_ERROR("target_write_memory failed");
1769 break;
1770 }
1771
1772 /* execute section-write command */
1773 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTWRITE,
1774 k_bank->prog_base + offset - align_begin,
1775 chunk_count>>8, chunk_count, 0, 0,
1776 0, 0, 0, 0, &ftfx_fstat);
1777
1778 if (result != ERROR_OK) {
1779 LOG_ERROR("Error writing section at %08" PRIx32, bank->base + offset);
1780 break;
1781 }
1782
1783 if (ftfx_fstat & 0x01) {
1784 LOG_ERROR("Flash write error at %08" PRIx32, bank->base + offset);
1785 if (k_bank->prog_base == 0 && offset == FCF_ADDRESS + FCF_SIZE
1786 && (k_chip->flash_support & FS_WIDTH_256BIT)) {
1787 LOG_ERROR("Flash write immediately after the end of Flash Config Field shows error");
1788 LOG_ERROR("because the flash memory is 256 bits wide (data were written correctly).");
1789 LOG_ERROR("Either change the linker script to add a gap of 16 bytes after FCF");
1790 LOG_ERROR("or set 'kinetis fcf_source write'");
1791 }
1792 }
1793
1794 buffer += size;
1795 offset += size;
1796 count -= size;
1797 }
1798
1799 free(buffer_aligned);
1800 return result;
1801 }
1802
1803
1804 static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
1805 uint32_t offset, uint32_t count)
1806 {
1807 int result, fallback = 0;
1808 struct kinetis_flash_bank *k_bank = bank->driver_priv;
1809 struct kinetis_chip *k_chip = k_bank->k_chip;
1810
1811 if (!(k_chip->flash_support & FS_PROGRAM_SECTOR)) {
1812 /* fallback to longword write */
1813 fallback = 1;
1814 LOG_INFO("This device supports Program Longword execution only.");
1815 } else {
1816 result = kinetis_make_ram_ready(bank->target);
1817 if (result != ERROR_OK) {
1818 fallback = 1;
1819 LOG_WARNING("FlexRAM not ready, fallback to slow longword write.");
1820 }
1821 }
1822
1823 LOG_DEBUG("flash write @ %08" PRIx32, bank->base + offset);
1824
1825 if (fallback == 0) {
1826 /* program section command */
1827 kinetis_write_sections(bank, buffer, offset, count);
1828 } else if (k_chip->flash_support & FS_PROGRAM_LONGWORD) {
1829 /* program longword command, not supported in FTFE */
1830 uint8_t *new_buffer = NULL;
1831
1832 /* check word alignment */
1833 if (offset & 0x3) {
1834 LOG_ERROR("offset 0x%" PRIx32 " breaks the required alignment", offset);
1835 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
1836 }
1837
1838 if (count & 0x3) {
1839 uint32_t old_count = count;
1840 count = (old_count | 3) + 1;
1841 new_buffer = malloc(count);
1842 if (new_buffer == NULL) {
1843 LOG_ERROR("odd number of bytes to write and no memory "
1844 "for padding buffer");
1845 return ERROR_FAIL;
1846 }
1847 LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
1848 "and padding with 0xff", old_count, count);
1849 memset(new_buffer + old_count, 0xff, count - old_count);
1850 buffer = memcpy(new_buffer, buffer, old_count);
1851 }
1852
1853 uint32_t words_remaining = count / 4;
1854
1855 kinetis_disable_wdog(k_chip);
1856
1857 /* try using a block write */
1858 result = kinetis_write_block(bank, buffer, offset, words_remaining);
1859
1860 if (result == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1861 /* if block write failed (no sufficient working area),
1862 * we use normal (slow) single word accesses */
1863 LOG_WARNING("couldn't use block writes, falling back to single "
1864 "memory accesses");
1865
1866 while (words_remaining) {
1867 uint8_t ftfx_fstat;
1868
1869 LOG_DEBUG("write longword @ %08" PRIx32, (uint32_t)(bank->base + offset));
1870
1871 result = kinetis_ftfx_command(bank->target, FTFx_CMD_LWORDPROG, k_bank->prog_base + offset,
1872 buffer[3], buffer[2], buffer[1], buffer[0],
1873 0, 0, 0, 0, &ftfx_fstat);
1874
1875 if (result != ERROR_OK) {
1876 LOG_ERROR("Error writing longword at %08" PRIx32, bank->base + offset);
1877 break;
1878 }
1879
1880 if (ftfx_fstat & 0x01)
1881 LOG_ERROR("Flash write error at %08" PRIx32, bank->base + offset);
1882
1883 buffer += 4;
1884 offset += 4;
1885 words_remaining--;
1886 }
1887 }
1888 free(new_buffer);
1889 } else {
1890 LOG_ERROR("Flash write strategy not implemented");
1891 return ERROR_FLASH_OPERATION_FAILED;
1892 }
1893
1894 kinetis_invalidate_flash_cache(k_chip);
1895 return result;
1896 }
1897
1898
1899 static int kinetis_write(struct flash_bank *bank, const uint8_t *buffer,
1900 uint32_t offset, uint32_t count)
1901 {
1902 int result;
1903 bool set_fcf = false;
1904 bool fcf_in_data_valid = false;
1905 int sect = 0;
1906 struct kinetis_flash_bank *k_bank = bank->driver_priv;
1907 struct kinetis_chip *k_chip = k_bank->k_chip;
1908 uint8_t fcf_buffer[FCF_SIZE];
1909 uint8_t fcf_current[FCF_SIZE];
1910 uint8_t fcf_in_data[FCF_SIZE];
1911
1912 result = kinetis_check_run_mode(k_chip);
1913 if (result != ERROR_OK)
1914 return result;
1915
1916 /* reset error flags */
1917 result = kinetis_ftfx_prepare(bank->target);
1918 if (result != ERROR_OK)
1919 return result;
1920
1921 if (k_bank->prog_base == 0 && !allow_fcf_writes) {
1922 if (bank->sectors[1].offset <= FCF_ADDRESS)
1923 sect = 1; /* 1kb sector, FCF in 2nd sector */
1924
1925 if (offset < bank->sectors[sect].offset + bank->sectors[sect].size
1926 && offset + count > bank->sectors[sect].offset)
1927 set_fcf = true; /* write to any part of sector with FCF */
1928 }
1929
1930 if (set_fcf) {
1931 kinetis_fill_fcf(bank, fcf_buffer);
1932
1933 fcf_in_data_valid = offset <= FCF_ADDRESS
1934 && offset + count >= FCF_ADDRESS + FCF_SIZE;
1935 if (fcf_in_data_valid) {
1936 memcpy(fcf_in_data, buffer + FCF_ADDRESS - offset, FCF_SIZE);
1937 if (memcmp(fcf_in_data + FCF_FPROT, fcf_buffer, 4)) {
1938 fcf_in_data_valid = false;
1939 LOG_INFO("Flash protection requested in programmed file differs from current setting.");
1940 }
1941 if (fcf_in_data[FCF_FDPROT] != fcf_buffer[FCF_FDPROT]) {
1942 fcf_in_data_valid = false;
1943 LOG_INFO("Data flash protection requested in programmed file differs from current setting.");
1944 }
1945 if ((fcf_in_data[FCF_FSEC] & 3) != 2) {
1946 fcf_in_data_valid = false;
1947 LOG_INFO("Device security requested in programmed file!");
1948 } else if (k_chip->flash_support & FS_ECC
1949 && fcf_in_data[FCF_FSEC] != fcf_buffer[FCF_FSEC]) {
1950 fcf_in_data_valid = false;
1951 LOG_INFO("Strange unsecure mode 0x%02" PRIx8
1952 "requested in programmed file!",
1953 fcf_in_data[FCF_FSEC]);
1954 }
1955 if ((k_chip->flash_support & FS_ECC || fcf_fopt_configured)
1956 && fcf_in_data[FCF_FOPT] != fcf_fopt) {
1957 fcf_in_data_valid = false;
1958 LOG_INFO("FOPT requested in programmed file differs from current setting.");
1959 }
1960 if (!fcf_in_data_valid)
1961 LOG_INFO("Expect verify errors at FCF (0x408-0x40f).");
1962 }
1963 }
1964
1965 if (set_fcf && !fcf_in_data_valid) {
1966 if (offset < FCF_ADDRESS) {
1967 /* write part preceding FCF */
1968 result = kinetis_write_inner(bank, buffer, offset, FCF_ADDRESS - offset);
1969 if (result != ERROR_OK)
1970 return result;
1971 }
1972
1973 result = target_read_memory(bank->target, bank->base + FCF_ADDRESS, 4, FCF_SIZE / 4, fcf_current);
1974 if (result == ERROR_OK && memcmp(fcf_current, fcf_buffer, FCF_SIZE) == 0)
1975 set_fcf = false;
1976
1977 if (set_fcf) {
1978 /* write FCF if differs from flash - eliminate multiple writes */
1979 result = kinetis_write_inner(bank, fcf_buffer, FCF_ADDRESS, FCF_SIZE);
1980 if (result != ERROR_OK)
1981 return result;
1982 }
1983
1984 LOG_WARNING("Flash Configuration Field written.");
1985 LOG_WARNING("Reset or power off the device to make settings effective.");
1986
1987 if (offset + count > FCF_ADDRESS + FCF_SIZE) {
1988 uint32_t delta = FCF_ADDRESS + FCF_SIZE - offset;
1989 /* write part after FCF */
1990 result = kinetis_write_inner(bank, buffer + delta, FCF_ADDRESS + FCF_SIZE, count - delta);
1991 }
1992 return result;
1993
1994 } else {
1995 /* no FCF fiddling, normal write */
1996 return kinetis_write_inner(bank, buffer, offset, count);
1997 }
1998 }
1999
2000
2001 static int kinetis_probe_chip(struct kinetis_chip *k_chip)
2002 {
2003 int result;
2004 uint8_t fcfg1_nvmsize, fcfg1_pfsize, fcfg1_eesize, fcfg1_depart;
2005 uint8_t fcfg2_pflsh;
2006 uint32_t ee_size = 0;
2007 uint32_t pflash_size_k, nvm_size_k, dflash_size_k;
2008 uint32_t pflash_size_m;
2009 unsigned num_blocks = 0;
2010 unsigned maxaddr_shift = 13;
2011 struct target *target = k_chip->target;
2012
2013 unsigned familyid = 0, subfamid = 0;
2014 unsigned cpu_mhz = 120;
2015 unsigned idx;
2016 bool use_nvm_marking = false;
2017 char flash_marking[12], nvm_marking[2];
2018 char name[40];
2019
2020 k_chip->probed = false;
2021 k_chip->pflash_sector_size = 0;
2022 k_chip->pflash_base = 0;
2023 k_chip->nvm_base = 0x10000000;
2024 k_chip->progr_accel_ram = FLEXRAM;
2025
2026 name[0] = '\0';
2027
2028 if (k_chip->sim_base)
2029 result = target_read_u32(target, k_chip->sim_base + SIM_SDID_OFFSET, &k_chip->sim_sdid);
2030 else {
2031 result = target_read_u32(target, SIM_BASE + SIM_SDID_OFFSET, &k_chip->sim_sdid);
2032 if (result == ERROR_OK)
2033 k_chip->sim_base = SIM_BASE;
2034 else {
2035 result = target_read_u32(target, SIM_BASE_KL28 + SIM_SDID_OFFSET, &k_chip->sim_sdid);
2036 if (result == ERROR_OK)
2037 k_chip->sim_base = SIM_BASE_KL28;
2038 }
2039 }
2040 if (result != ERROR_OK)
2041 return result;
2042
2043 if ((k_chip->sim_sdid & (~KINETIS_SDID_K_SERIES_MASK)) == 0) {
2044 /* older K-series MCU */
2045 uint32_t mcu_type = k_chip->sim_sdid & KINETIS_K_SDID_TYPE_MASK;
2046 k_chip->cache_type = KINETIS_CACHE_K;
2047 k_chip->watchdog_type = KINETIS_WDOG_K;
2048
2049 switch (mcu_type) {
2050 case KINETIS_K_SDID_K10_M50:
2051 case KINETIS_K_SDID_K20_M50:
2052 /* 1kB sectors */
2053 k_chip->pflash_sector_size = 1<<10;
2054 k_chip->nvm_sector_size = 1<<10;
2055 num_blocks = 2;
2056 k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
2057 break;
2058 case KINETIS_K_SDID_K10_M72:
2059 case KINETIS_K_SDID_K20_M72:
2060 case KINETIS_K_SDID_K30_M72:
2061 case KINETIS_K_SDID_K30_M100:
2062 case KINETIS_K_SDID_K40_M72:
2063 case KINETIS_K_SDID_K40_M100:
2064 case KINETIS_K_SDID_K50_M72:
2065 /* 2kB sectors, 1kB FlexNVM sectors */
2066 k_chip->pflash_sector_size = 2<<10;
2067 k_chip->nvm_sector_size = 1<<10;
2068 num_blocks = 2;
2069 k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
2070 k_chip->max_flash_prog_size = 1<<10;
2071 break;
2072 case KINETIS_K_SDID_K10_M100:
2073 case KINETIS_K_SDID_K20_M100:
2074 case KINETIS_K_SDID_K11:
2075 case KINETIS_K_SDID_K12:
2076 case KINETIS_K_SDID_K21_M50:
2077 case KINETIS_K_SDID_K22_M50:
2078 case KINETIS_K_SDID_K51_M72:
2079 case KINETIS_K_SDID_K53:
2080 case KINETIS_K_SDID_K60_M100:
2081 /* 2kB sectors */
2082 k_chip->pflash_sector_size = 2<<10;
2083 k_chip->nvm_sector_size = 2<<10;
2084 num_blocks = 2;
2085 k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
2086 break;
2087 case KINETIS_K_SDID_K21_M120:
2088 case KINETIS_K_SDID_K22_M120:
2089 /* 4kB sectors (MK21FN1M0, MK21FX512, MK22FN1M0, MK22FX512) */
2090 k_chip->pflash_sector_size = 4<<10;
2091 k_chip->max_flash_prog_size = 1<<10;
2092 k_chip->nvm_sector_size = 4<<10;
2093 num_blocks = 2;
2094 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2095 break;
2096 case KINETIS_K_SDID_K10_M120:
2097 case KINETIS_K_SDID_K20_M120:
2098 case KINETIS_K_SDID_K60_M150:
2099 case KINETIS_K_SDID_K70_M150:
2100 /* 4kB sectors */
2101 k_chip->pflash_sector_size = 4<<10;
2102 k_chip->nvm_sector_size = 4<<10;
2103 num_blocks = 4;
2104 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2105 break;
2106 default:
2107 LOG_ERROR("Unsupported K-family FAMID");
2108 }
2109
2110 for (idx = 0; idx < ARRAY_SIZE(kinetis_types_old); idx++) {
2111 if (kinetis_types_old[idx].sdid == mcu_type) {
2112 strcpy(name, kinetis_types_old[idx].name);
2113 use_nvm_marking = true;
2114 break;
2115 }
2116 }
2117
2118 } else {
2119 /* Newer K-series or KL series MCU */
2120 familyid = (k_chip->sim_sdid & KINETIS_SDID_FAMILYID_MASK) >> KINETIS_SDID_FAMILYID_SHIFT;
2121 subfamid = (k_chip->sim_sdid & KINETIS_SDID_SUBFAMID_MASK) >> KINETIS_SDID_SUBFAMID_SHIFT;
2122
2123 switch (k_chip->sim_sdid & KINETIS_SDID_SERIESID_MASK) {
2124 case KINETIS_SDID_SERIESID_K:
2125 use_nvm_marking = true;
2126 k_chip->cache_type = KINETIS_CACHE_K;
2127 k_chip->watchdog_type = KINETIS_WDOG_K;
2128
2129 switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
2130 case KINETIS_SDID_FAMILYID_K0X | KINETIS_SDID_SUBFAMID_KX2:
2131 /* K02FN64, K02FN128: FTFA, 2kB sectors */
2132 k_chip->pflash_sector_size = 2<<10;
2133 num_blocks = 1;
2134 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2135 cpu_mhz = 100;
2136 break;
2137
2138 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX2: {
2139 /* MK24FN1M reports as K22, this should detect it (according to errata note 1N83J) */
2140 uint32_t sopt1;
2141 result = target_read_u32(target, k_chip->sim_base + SIM_SOPT1_OFFSET, &sopt1);
2142 if (result != ERROR_OK)
2143 return result;
2144
2145 if (((k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K24FN1M) &&
2146 ((sopt1 & KINETIS_SOPT1_RAMSIZE_MASK) == KINETIS_SOPT1_RAMSIZE_K24FN1M)) {
2147 /* MK24FN1M */
2148 k_chip->pflash_sector_size = 4<<10;
2149 num_blocks = 2;
2150 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2151 k_chip->max_flash_prog_size = 1<<10;
2152 subfamid = 4; /* errata 1N83J fix */
2153 break;
2154 }
2155 if ((k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN128
2156 || (k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN256
2157 || (k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN512) {
2158 /* K22 with new-style SDID - smaller pflash with FTFA, 2kB sectors */
2159 k_chip->pflash_sector_size = 2<<10;
2160 /* autodetect 1 or 2 blocks */
2161 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2162 break;
2163 }
2164 LOG_ERROR("Unsupported Kinetis K22 DIEID");
2165 break;
2166 }
2167 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX4:
2168 k_chip->pflash_sector_size = 4<<10;
2169 if ((k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K24FN256) {
2170 /* K24FN256 - smaller pflash with FTFA */
2171 num_blocks = 1;
2172 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2173 break;
2174 }
2175 /* K24FN1M without errata 7534 */
2176 num_blocks = 2;
2177 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2178 k_chip->max_flash_prog_size = 1<<10;
2179 break;
2180
2181 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX1: /* errata 7534 - should be K63 */
2182 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX2: /* errata 7534 - should be K64 */
2183 subfamid += 2; /* errata 7534 fix */
2184 /* fallthrough */
2185 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX3:
2186 /* K63FN1M0 */
2187 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX4:
2188 /* K64FN1M0, K64FX512 */
2189 k_chip->pflash_sector_size = 4<<10;
2190 k_chip->nvm_sector_size = 4<<10;
2191 k_chip->max_flash_prog_size = 1<<10;
2192 num_blocks = 2;
2193 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2194 break;
2195
2196 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX6:
2197 /* K26FN2M0 */
2198 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX6:
2199 /* K66FN2M0, K66FX1M0 */
2200 k_chip->pflash_sector_size = 4<<10;
2201 k_chip->nvm_sector_size = 4<<10;
2202 k_chip->max_flash_prog_size = 1<<10;
2203 num_blocks = 4;
2204 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_ECC;
2205 cpu_mhz = 180;
2206 break;
2207
2208 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX7:
2209 /* K27FN2M0 */
2210 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX8:
2211 /* K28FN2M0 */
2212 k_chip->pflash_sector_size = 4<<10;
2213 k_chip->max_flash_prog_size = 1<<10;
2214 num_blocks = 4;
2215 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_ECC;
2216 cpu_mhz = 150;
2217 break;
2218
2219 case KINETIS_SDID_FAMILYID_K8X | KINETIS_SDID_SUBFAMID_KX0:
2220 case KINETIS_SDID_FAMILYID_K8X | KINETIS_SDID_SUBFAMID_KX1:
2221 case KINETIS_SDID_FAMILYID_K8X | KINETIS_SDID_SUBFAMID_KX2:
2222 /* K80FN256, K81FN256, K82FN256 */
2223 k_chip->pflash_sector_size = 4<<10;
2224 num_blocks = 1;
2225 k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_NO_CMD_BLOCKSTAT;
2226 cpu_mhz = 150;
2227 break;
2228
2229 case KINETIS_SDID_FAMILYID_KL8X | KINETIS_SDID_SUBFAMID_KX1:
2230 case KINETIS_SDID_FAMILYID_KL8X | KINETIS_SDID_SUBFAMID_KX2:
2231 /* KL81Z128, KL82Z128 */
2232 k_chip->pflash_sector_size = 2<<10;
2233 num_blocks = 1;
2234 k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_NO_CMD_BLOCKSTAT;
2235 k_chip->cache_type = KINETIS_CACHE_L;
2236
2237 use_nvm_marking = false;
2238 snprintf(name, sizeof(name), "MKL8%uZ%%s7",
2239 subfamid);
2240 break;
2241
2242 default:
2243 LOG_ERROR("Unsupported Kinetis FAMILYID SUBFAMID");
2244 }
2245
2246 if (name[0] == '\0')
2247 snprintf(name, sizeof(name), "MK%u%uF%%s%u",
2248 familyid, subfamid, cpu_mhz / 10);
2249 break;
2250
2251 case KINETIS_SDID_SERIESID_KL:
2252 /* KL-series */
2253 k_chip->pflash_sector_size = 1<<10;
2254 k_chip->nvm_sector_size = 1<<10;
2255 /* autodetect 1 or 2 blocks */
2256 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2257 k_chip->cache_type = KINETIS_CACHE_L;
2258 k_chip->watchdog_type = KINETIS_WDOG_COP;
2259
2260 cpu_mhz = 48;
2261 switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
2262 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX3:
2263 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX3:
2264 subfamid = 7;
2265 break;
2266
2267 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX8:
2268 cpu_mhz = 72;
2269 k_chip->pflash_sector_size = 2<<10;
2270 num_blocks = 2;
2271 k_chip->watchdog_type = KINETIS_WDOG32_KL28;
2272 k_chip->sysmodectrlr_type = KINETIS_SMC32;
2273 break;
2274 }
2275
2276 snprintf(name, sizeof(name), "MKL%u%uZ%%s%u",
2277 familyid, subfamid, cpu_mhz / 10);
2278 break;
2279
2280 case KINETIS_SDID_SERIESID_KW:
2281 /* Newer KW-series (all KW series except KW2xD, KW01Z) */
2282 cpu_mhz = 48;
2283 switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
2284 case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX0:
2285 /* KW40Z */
2286 case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX0:
2287 /* KW30Z */
2288 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX0:
2289 /* KW20Z */
2290 /* FTFA, 1kB sectors */
2291 k_chip->pflash_sector_size = 1<<10;
2292 k_chip->nvm_sector_size = 1<<10;
2293 /* autodetect 1 or 2 blocks */
2294 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2295 k_chip->cache_type = KINETIS_CACHE_L;
2296 k_chip->watchdog_type = KINETIS_WDOG_COP;
2297 break;
2298 case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX1:
2299 /* KW41Z */
2300 case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX1:
2301 /* KW31Z */
2302 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX1:
2303 /* KW21Z */
2304 /* FTFA, 2kB sectors */
2305 k_chip->pflash_sector_size = 2<<10;
2306 k_chip->nvm_sector_size = 2<<10;
2307 /* autodetect 1 or 2 blocks */
2308 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2309 k_chip->cache_type = KINETIS_CACHE_L;
2310 k_chip->watchdog_type = KINETIS_WDOG_COP;
2311 break;
2312 default:
2313 LOG_ERROR("Unsupported KW FAMILYID SUBFAMID");
2314 }
2315 snprintf(name, sizeof(name), "MKW%u%uZ%%s%u",
2316 familyid, subfamid, cpu_mhz / 10);
2317 break;
2318
2319 case KINETIS_SDID_SERIESID_KV:
2320 /* KV-series */
2321 k_chip->watchdog_type = KINETIS_WDOG_K;
2322 switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
2323 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX0:
2324 /* KV10: FTFA, 1kB sectors */
2325 k_chip->pflash_sector_size = 1<<10;
2326 num_blocks = 1;
2327 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2328 k_chip->cache_type = KINETIS_CACHE_L;
2329 strcpy(name, "MKV10Z%s7");
2330 break;
2331
2332 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX1:
2333 /* KV11: FTFA, 2kB sectors */
2334 k_chip->pflash_sector_size = 2<<10;
2335 num_blocks = 1;
2336 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2337 k_chip->cache_type = KINETIS_CACHE_L;
2338 strcpy(name, "MKV11Z%s7");
2339 break;
2340
2341 case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX0:
2342 /* KV30: FTFA, 2kB sectors, 1 block */
2343 case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX1:
2344 /* KV31: FTFA, 2kB sectors, 2 blocks */
2345 k_chip->pflash_sector_size = 2<<10;
2346 /* autodetect 1 or 2 blocks */
2347 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2348 k_chip->cache_type = KINETIS_CACHE_K;
2349 break;
2350
2351 case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX2:
2352 case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX4:
2353 case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX6:
2354 /* KV4x: FTFA, 4kB sectors */
2355 k_chip->pflash_sector_size = 4<<10;
2356 num_blocks = 1;
2357 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2358 k_chip->cache_type = KINETIS_CACHE_K;
2359 cpu_mhz = 168;
2360 break;
2361
2362 case KINETIS_SDID_FAMILYID_K5X | KINETIS_SDID_SUBFAMID_KX6:
2363 case KINETIS_SDID_FAMILYID_K5X | KINETIS_SDID_SUBFAMID_KX8:
2364 /* KV5x: FTFE, 8kB sectors */
2365 k_chip->pflash_sector_size = 8<<10;
2366 k_chip->max_flash_prog_size = 1<<10;
2367 num_blocks = 1;
2368 maxaddr_shift = 14;
2369 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_WIDTH_256BIT | FS_ECC;
2370 k_chip->pflash_base = 0x10000000;
2371 k_chip->progr_accel_ram = 0x18000000;
2372 cpu_mhz = 240;
2373 break;
2374
2375 default:
2376 LOG_ERROR("Unsupported KV FAMILYID SUBFAMID");
2377 }
2378
2379 if (name[0] == '\0')
2380 snprintf(name, sizeof(name), "MKV%u%uF%%s%u",
2381 familyid, subfamid, cpu_mhz / 10);
2382 break;
2383
2384 case KINETIS_SDID_SERIESID_KE:
2385 /* KE1x-series */
2386 k_chip->watchdog_type = KINETIS_WDOG32_KE1X;
2387 switch (k_chip->sim_sdid &
2388 (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK | KINETIS_SDID_PROJECTID_MASK)) {
2389 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1xZ:
2390 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX5 | KINETIS_SDID_PROJECTID_KE1xZ:
2391 /* KE1xZ: FTFE, 2kB sectors */
2392 k_chip->pflash_sector_size = 2<<10;
2393 k_chip->nvm_sector_size = 2<<10;
2394 k_chip->max_flash_prog_size = 1<<9;
2395 num_blocks = 2;
2396 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2397 k_chip->cache_type = KINETIS_CACHE_L;
2398
2399 cpu_mhz = 72;
2400 snprintf(name, sizeof(name), "MKE%u%uZ%%s%u",
2401 familyid, subfamid, cpu_mhz / 10);
2402 break;
2403
2404 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1xF:
2405 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX6 | KINETIS_SDID_PROJECTID_KE1xF:
2406 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX8 | KINETIS_SDID_PROJECTID_KE1xF:
2407 /* KE1xF: FTFE, 4kB sectors */
2408 k_chip->pflash_sector_size = 4<<10;
2409 k_chip->nvm_sector_size = 2<<10;
2410 k_chip->max_flash_prog_size = 1<<10;
2411 num_blocks = 2;
2412 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2413 k_chip->cache_type = KINETIS_CACHE_MSCM;
2414
2415 cpu_mhz = 168;
2416 snprintf(name, sizeof(name), "MKE%u%uF%%s%u",
2417 familyid, subfamid, cpu_mhz / 10);
2418 break;
2419
2420 default:
2421 LOG_ERROR("Unsupported KE FAMILYID SUBFAMID");
2422 }
2423 break;
2424
2425 default:
2426 LOG_ERROR("Unsupported K-series");
2427 }
2428 }
2429
2430 if (k_chip->pflash_sector_size == 0) {
2431 LOG_ERROR("MCU is unsupported, SDID 0x%08" PRIx32, k_chip->sim_sdid);
2432 return ERROR_FLASH_OPER_UNSUPPORTED;
2433 }
2434
2435 result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &k_chip->sim_fcfg1);
2436 if (result != ERROR_OK)
2437 return result;
2438
2439 result = target_read_u32(target, k_chip->sim_base + SIM_FCFG2_OFFSET, &k_chip->sim_fcfg2);
2440 if (result != ERROR_OK)
2441 return result;
2442
2443 LOG_DEBUG("SDID: 0x%08" PRIX32 " FCFG1: 0x%08" PRIX32 " FCFG2: 0x%08" PRIX32, k_chip->sim_sdid,
2444 k_chip->sim_fcfg1, k_chip->sim_fcfg2);
2445
2446 fcfg1_nvmsize = (uint8_t)((k_chip->sim_fcfg1 >> 28) & 0x0f);
2447 fcfg1_pfsize = (uint8_t)((k_chip->sim_fcfg1 >> 24) & 0x0f);
2448 fcfg1_eesize = (uint8_t)((k_chip->sim_fcfg1 >> 16) & 0x0f);
2449 fcfg1_depart = (uint8_t)((k_chip->sim_fcfg1 >> 8) & 0x0f);
2450
2451 fcfg2_pflsh = (uint8_t)((k_chip->sim_fcfg2 >> 23) & 0x01);
2452 k_chip->fcfg2_maxaddr0_shifted = ((k_chip->sim_fcfg2 >> 24) & 0x7f) << maxaddr_shift;
2453 k_chip->fcfg2_maxaddr1_shifted = ((k_chip->sim_fcfg2 >> 16) & 0x7f) << maxaddr_shift;
2454
2455 if (num_blocks == 0)
2456 num_blocks = k_chip->fcfg2_maxaddr1_shifted ? 2 : 1;
2457 else if (k_chip->fcfg2_maxaddr1_shifted == 0 && num_blocks >= 2 && fcfg2_pflsh) {
2458 /* fcfg2_maxaddr1 may be zero due to partitioning whole NVM as EEPROM backup
2459 * Do not adjust block count in this case! */
2460 num_blocks = 1;
2461 LOG_WARNING("MAXADDR1 is zero, number of flash banks adjusted to 1");
2462 } else if (k_chip->fcfg2_maxaddr1_shifted != 0 && num_blocks == 1) {
2463 num_blocks = 2;
2464 LOG_WARNING("MAXADDR1 is non zero, number of flash banks adjusted to 2");
2465 }
2466
2467 /* when the PFLSH bit is set, there is no FlexNVM/FlexRAM */
2468 if (!fcfg2_pflsh) {
2469 switch (fcfg1_nvmsize) {
2470 case 0x03:
2471 case 0x05:
2472 case 0x07:
2473 case 0x09:
2474 case 0x0b:
2475 k_chip->nvm_size = 1 << (14 + (fcfg1_nvmsize >> 1));
2476 break;
2477 case 0x0f:
2478 if (k_chip->pflash_sector_size >= 4<<10)
2479 k_chip->nvm_size = 512<<10;
2480 else
2481 /* K20_100 */
2482 k_chip->nvm_size = 256<<10;
2483 break;
2484 default:
2485 k_chip->nvm_size = 0;
2486 break;
2487 }
2488
2489 switch (fcfg1_eesize) {
2490 case 0x00:
2491 case 0x01:
2492 case 0x02:
2493 case 0x03:
2494 case 0x04:
2495 case 0x05:
2496 case 0x06:
2497 case 0x07:
2498 case 0x08:
2499 case 0x09:
2500 ee_size = (16 << (10 - fcfg1_eesize));
2501 break;
2502 default:
2503 ee_size = 0;
2504 break;
2505 }
2506
2507 switch (fcfg1_depart) {
2508 case 0x01:
2509 case 0x02:
2510 case 0x03:
2511 case 0x04:
2512 case 0x05:
2513 case 0x06:
2514 k_chip->dflash_size = k_chip->nvm_size - (4096 << fcfg1_depart);
2515 break;
2516 case 0x07:
2517 case 0x08:
2518 k_chip->dflash_size = 0;
2519 break;
2520 case 0x09:
2521 case 0x0a:
2522 case 0x0b:
2523 case 0x0c:
2524 case 0x0d:
2525 k_chip->dflash_size = 4096 << (fcfg1_depart & 0x7);
2526 break;
2527 default:
2528 k_chip->dflash_size = k_chip->nvm_size;
2529 break;
2530 }
2531 }
2532
2533 switch (fcfg1_pfsize) {
2534 case 0x00:
2535 k_chip->pflash_size = 8192;
2536 break;
2537 case 0x01:
2538 case 0x03:
2539 case 0x05:
2540 case 0x07:
2541 case 0x09:
2542 case 0x0b:
2543 case 0x0d:
2544 k_chip->pflash_size = 1 << (14 + (fcfg1_pfsize >> 1));
2545 break;
2546 case 0x0f:
2547 /* a peculiar case: Freescale states different sizes for 0xf
2548 * KL03P24M48SF0RM 32 KB .... duplicate of code 0x3
2549 * K02P64M100SFARM 128 KB ... duplicate of code 0x7
2550 * K22P121M120SF8RM 256 KB ... duplicate of code 0x9
2551 * K22P121M120SF7RM 512 KB ... duplicate of code 0xb
2552 * K22P100M120SF5RM 1024 KB ... duplicate of code 0xd
2553 * K26P169M180SF5RM 2048 KB ... the only unique value
2554 * fcfg2_maxaddr0 seems to be the only clue to pflash_size
2555 * Checking fcfg2_maxaddr0 in bank probe is pointless then
2556 */
2557 if (fcfg2_pflsh)
2558 k_chip->pflash_size = k_chip->fcfg2_maxaddr0_shifted * num_blocks;
2559 else
2560 k_chip->pflash_size = k_chip->fcfg2_maxaddr0_shifted * num_blocks / 2;
2561 if (k_chip->pflash_size != 2048<<10)
2562 LOG_WARNING("SIM_FCFG1 PFSIZE = 0xf: please check if pflash is %u KB", k_chip->pflash_size>>10);
2563
2564 break;
2565 default:
2566 k_chip->pflash_size = 0;
2567 break;
2568 }
2569
2570 if (k_chip->flash_support & FS_PROGRAM_SECTOR && k_chip->max_flash_prog_size == 0) {
2571 k_chip->max_flash_prog_size = k_chip->pflash_sector_size;
2572 /* Program section size is equal to sector size by default */
2573 }
2574
2575 if (fcfg2_pflsh) {
2576 k_chip->num_pflash_blocks = num_blocks;
2577 k_chip->num_nvm_blocks = 0;
2578 } else {
2579 k_chip->num_pflash_blocks = (num_blocks + 1) / 2;
2580 k_chip->num_nvm_blocks = num_blocks - k_chip->num_pflash_blocks;
2581 }
2582
2583 if (use_nvm_marking) {
2584 nvm_marking[0] = k_chip->num_nvm_blocks ? 'X' : 'N';
2585 nvm_marking[1] = '\0';
2586 } else
2587 nvm_marking[0] = '\0';
2588
2589 pflash_size_k = k_chip->pflash_size / 1024;
2590 pflash_size_m = pflash_size_k / 1024;
2591 if (pflash_size_m)
2592 snprintf(flash_marking, sizeof(flash_marking), "%s%" PRIu32 "M0xxx", nvm_marking, pflash_size_m);
2593 else
2594 snprintf(flash_marking, sizeof(flash_marking), "%s%" PRIu32 "xxx", nvm_marking, pflash_size_k);
2595
2596 snprintf(k_chip->name, sizeof(k_chip->name), name, flash_marking);
2597 LOG_INFO("Kinetis %s detected: %u flash blocks", k_chip->name, num_blocks);
2598 LOG_INFO("%u PFlash banks: %" PRIu32 "k total", k_chip->num_pflash_blocks, pflash_size_k);
2599 if (k_chip->num_nvm_blocks) {
2600 nvm_size_k = k_chip->nvm_size / 1024;
2601 dflash_size_k = k_chip->dflash_size / 1024;
2602 LOG_INFO("%u FlexNVM banks: %" PRIu32 "k total, %" PRIu32 "k available as data flash, %" PRIu32 "bytes FlexRAM",
2603 k_chip->num_nvm_blocks, nvm_size_k, dflash_size_k, ee_size);
2604 }
2605
2606 k_chip->probed = true;
2607
2608 if (create_banks)
2609 kinetis_create_missing_banks(k_chip);
2610
2611 return ERROR_OK;
2612 }
2613
2614 static int kinetis_probe(struct flash_bank *bank)
2615 {
2616 int result, i;
2617 uint8_t fcfg2_maxaddr0, fcfg2_pflsh, fcfg2_maxaddr1;
2618 unsigned num_blocks, first_nvm_bank;
2619 uint32_t size_k;
2620 struct kinetis_flash_bank *k_bank = bank->driver_priv;
2621 struct kinetis_chip *k_chip = k_bank->k_chip;
2622
2623 k_bank->probed = false;
2624
2625 if (!k_chip->probed) {
2626 result = kinetis_probe_chip(k_chip);
2627 if (result != ERROR_OK)
2628 return result;
2629 }
2630
2631 num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
2632 first_nvm_bank = k_chip->num_pflash_blocks;
2633
2634 if (k_bank->bank_number < k_chip->num_pflash_blocks) {
2635 /* pflash, banks start at address zero */
2636 k_bank->flash_class = FC_PFLASH;
2637 bank->size = (k_chip->pflash_size / k_chip->num_pflash_blocks);
2638 bank->base = k_chip->pflash_base + bank->size * k_bank->bank_number;
2639 k_bank->prog_base = 0x00000000 + bank->size * k_bank->bank_number;
2640 k_bank->sector_size = k_chip->pflash_sector_size;
2641 /* pflash is divided into 32 protection areas for
2642 * parts with more than 32K of PFlash. For parts with
2643 * less the protection unit is set to 1024 bytes */
2644 k_bank->protection_size = MAX(k_chip->pflash_size / 32, 1024);
2645 bank->num_prot_blocks = bank->size / k_bank->protection_size;
2646 k_bank->protection_block = bank->num_prot_blocks * k_bank->bank_number;
2647
2648 size_k = bank->size / 1024;
2649 LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k PFlash, FTFx base 0x%08" PRIx32 ", sect %u",
2650 k_bank->bank_number, size_k, k_bank->prog_base, k_bank->sector_size);
2651
2652 } else if (k_bank->bank_number < num_blocks) {
2653 /* nvm, banks start at address 0x10000000 */
2654 unsigned nvm_ord = k_bank->bank_number - first_nvm_bank;
2655 uint32_t limit;
2656
2657 k_bank->flash_class = FC_FLEX_NVM;
2658 bank->size = k_chip->nvm_size / k_chip->num_nvm_blocks;
2659 bank->base = k_chip->nvm_base + bank->size * nvm_ord;
2660 k_bank->prog_base = 0x00800000 + bank->size * nvm_ord;
2661 k_bank->sector_size = k_chip->nvm_sector_size;
2662 if (k_chip->dflash_size == 0) {
2663 k_bank->protection_size = 0;
2664 } else {
2665 for (i = k_chip->dflash_size; ~i & 1; i >>= 1)
2666 ;
2667 if (i == 1)
2668 k_bank->protection_size = k_chip->dflash_size / 8; /* data flash size = 2^^n */
2669 else
2670 k_bank->protection_size = k_chip->nvm_size / 8; /* TODO: verify on SF1, not documented in RM */
2671 }
2672 bank->num_prot_blocks = 8 / k_chip->num_nvm_blocks;
2673 k_bank->protection_block = bank->num_prot_blocks * nvm_ord;
2674
2675 /* EEPROM backup part of FlexNVM is not accessible, use dflash_size as a limit */
2676 if (k_chip->dflash_size > bank->size * nvm_ord)
2677 limit = k_chip->dflash_size - bank->size * nvm_ord;
2678 else
2679 limit = 0;
2680
2681 if (bank->size > limit) {
2682 bank->size = limit;
2683 LOG_DEBUG("FlexNVM bank %d limited to 0x%08" PRIx32 " due to active EEPROM backup",
2684 k_bank->bank_number, limit);
2685 }
2686
2687 size_k = bank->size / 1024;
2688 LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k FlexNVM, FTFx base 0x%08" PRIx32 ", sect %u",
2689 k_bank->bank_number, size_k, k_bank->prog_base, k_bank->sector_size);
2690
2691 } else {
2692 LOG_ERROR("Cannot determine parameters for bank %d, only %d banks on device",
2693 k_bank->bank_number, num_blocks);
2694 return ERROR_FLASH_BANK_INVALID;
2695 }
2696
2697 fcfg2_pflsh = (uint8_t)((k_chip->sim_fcfg2 >> 23) & 0x01);
2698 fcfg2_maxaddr0 = (uint8_t)((k_chip->sim_fcfg2 >> 24) & 0x7f);
2699 fcfg2_maxaddr1 = (uint8_t)((k_chip->sim_fcfg2 >> 16) & 0x7f);
2700
2701 if (k_bank->bank_number == 0 && k_chip->fcfg2_maxaddr0_shifted != bank->size)
2702 LOG_WARNING("MAXADDR0 0x%02" PRIx8 " check failed,"
2703 " please report to OpenOCD mailing list", fcfg2_maxaddr0);
2704
2705 if (fcfg2_pflsh) {
2706 if (k_bank->bank_number == 1 && k_chip->fcfg2_maxaddr1_shifted != bank->size)
2707 LOG_WARNING("MAXADDR1 0x%02" PRIx8 " check failed,"
2708 " please report to OpenOCD mailing list", fcfg2_maxaddr1);
2709 } else {
2710 if (k_bank->bank_number == first_nvm_bank
2711 && k_chip->fcfg2_maxaddr1_shifted != k_chip->dflash_size)
2712 LOG_WARNING("FlexNVM MAXADDR1 0x%02" PRIx8 " check failed,"
2713 " please report to OpenOCD mailing list", fcfg2_maxaddr1);
2714 }
2715
2716 if (bank->sectors) {
2717 free(bank->sectors);
2718 bank->sectors = NULL;
2719 }
2720 if (bank->prot_blocks) {
2721 free(bank->prot_blocks);
2722 bank->prot_blocks = NULL;
2723 }
2724
2725 if (k_bank->sector_size == 0) {
2726 LOG_ERROR("Unknown sector size for bank %d", bank->bank_number);
2727 return ERROR_FLASH_BANK_INVALID;
2728 }
2729
2730 bank->num_sectors = bank->size / k_bank->sector_size;
2731
2732 if (bank->num_sectors > 0) {
2733 /* FlexNVM bank can be used for EEPROM backup therefore zero sized */
2734 bank->sectors = alloc_block_array(0, k_bank->sector_size, bank->num_sectors);
2735 if (!bank->sectors)
2736 return ERROR_FAIL;
2737
2738 bank->prot_blocks = alloc_block_array(0, k_bank->protection_size, bank->num_prot_blocks);
2739 if (!bank->prot_blocks)
2740 return ERROR_FAIL;
2741
2742 } else {
2743 bank->num_prot_blocks = 0;
2744 }
2745
2746 k_bank->probed = true;
2747
2748 return ERROR_OK;
2749 }
2750
2751 static int kinetis_auto_probe(struct flash_bank *bank)
2752 {
2753 struct kinetis_flash_bank *k_bank = bank->driver_priv;
2754
2755 if (k_bank && k_bank->probed)
2756 return ERROR_OK;
2757
2758 return kinetis_probe(bank);
2759 }
2760
2761 static int kinetis_info(struct flash_bank *bank, char *buf, int buf_size)
2762 {
2763 const char *bank_class_names[] = {
2764 "(ANY)", "PFlash", "FlexNVM", "FlexRAM"
2765 };
2766
2767 struct kinetis_flash_bank *k_bank = bank->driver_priv;
2768 struct kinetis_chip *k_chip = k_bank->k_chip;
2769 uint32_t size_k = bank->size / 1024;
2770
2771 snprintf(buf, buf_size,
2772 "%s %s: %" PRIu32 "k %s bank %s at 0x%08" PRIx32,
2773 bank->driver->name, k_chip->name,
2774 size_k, bank_class_names[k_bank->flash_class],
2775 bank->name, bank->base);
2776
2777 return ERROR_OK;
2778 }
2779
2780 static int kinetis_blank_check(struct flash_bank *bank)
2781 {
2782 struct kinetis_flash_bank *k_bank = bank->driver_priv;
2783 struct kinetis_chip *k_chip = k_bank->k_chip;
2784 int result;
2785
2786 /* suprisingly blank check does not work in VLPR and HSRUN modes */
2787 result = kinetis_check_run_mode(k_chip);
2788 if (result != ERROR_OK)
2789 return result;
2790
2791 /* reset error flags */
2792 result = kinetis_ftfx_prepare(bank->target);
2793 if (result != ERROR_OK)
2794 return result;
2795
2796 if (k_bank->flash_class == FC_PFLASH || k_bank->flash_class == FC_FLEX_NVM) {
2797 bool block_dirty = true;
2798 bool use_block_cmd = !(k_chip->flash_support & FS_NO_CMD_BLOCKSTAT);
2799 uint8_t ftfx_fstat;
2800
2801 if (use_block_cmd && k_bank->flash_class == FC_FLEX_NVM) {
2802 uint8_t fcfg1_depart = (uint8_t)((k_chip->sim_fcfg1 >> 8) & 0x0f);
2803 /* block operation cannot be used on FlexNVM when EEPROM backup partition is set */
2804 if (fcfg1_depart != 0xf && fcfg1_depart != 0)
2805 use_block_cmd = false;
2806 }
2807
2808 if (use_block_cmd) {
2809 /* check if whole bank is blank */
2810 result = kinetis_ftfx_command(bank->target, FTFx_CMD_BLOCKSTAT, k_bank->prog_base,
2811 0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
2812
2813 if (result != ERROR_OK)
2814 kinetis_ftfx_clear_error(bank->target);
2815 else if ((ftfx_fstat & 0x01) == 0)
2816 block_dirty = false;
2817 }
2818
2819 if (block_dirty) {
2820 /* the whole bank is not erased, check sector-by-sector */
2821 int i;
2822 for (i = 0; i < bank->num_sectors; i++) {
2823 /* normal margin */
2824 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTSTAT,
2825 k_bank->prog_base + bank->sectors[i].offset,
2826 1, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
2827
2828 if (result == ERROR_OK) {
2829 bank->sectors[i].is_erased = !(ftfx_fstat & 0x01);
2830 } else {
2831 LOG_DEBUG("Ignoring errored PFlash sector blank-check");
2832 kinetis_ftfx_clear_error(bank->target);
2833 bank->sectors[i].is_erased = -1;
2834 }
2835 }
2836 } else {
2837 /* the whole bank is erased, update all sectors */
2838 int i;
2839 for (i = 0; i < bank->num_sectors; i++)
2840 bank->sectors[i].is_erased = 1;
2841 }
2842 } else {
2843 LOG_WARNING("kinetis_blank_check not supported yet for FlexRAM");
2844 return ERROR_FLASH_OPERATION_FAILED;
2845 }
2846
2847 return ERROR_OK;
2848 }
2849
2850
2851 COMMAND_HANDLER(kinetis_nvm_partition)
2852 {
2853 int result;
2854 unsigned bank_idx;
2855 unsigned num_blocks, first_nvm_bank;
2856 unsigned long par, log2 = 0, ee1 = 0, ee2 = 0;
2857 enum { SHOW_INFO, DF_SIZE, EEBKP_SIZE } sz_type = SHOW_INFO;
2858 bool enable;
2859 uint8_t load_flex_ram = 1;
2860 uint8_t ee_size_code = 0x3f;
2861 uint8_t flex_nvm_partition_code = 0;
2862 uint8_t ee_split = 3;
2863 struct target *target = get_current_target(CMD_CTX);
2864 struct kinetis_chip *k_chip;
2865 uint32_t sim_fcfg1;
2866
2867 k_chip = kinetis_get_chip(target);
2868
2869 if (CMD_ARGC >= 2) {
2870 if (strcmp(CMD_ARGV[0], "dataflash") == 0)
2871 sz_type = DF_SIZE;
2872 else if (strcmp(CMD_ARGV[0], "eebkp") == 0)
2873 sz_type = EEBKP_SIZE;
2874
2875 par = strtoul(CMD_ARGV[1], NULL, 10);
2876 while (par >> (log2 + 3))
2877 log2++;
2878 }
2879 switch (sz_type) {
2880 case SHOW_INFO:
2881 if (k_chip == NULL) {
2882 LOG_ERROR("Chip not probed.");
2883 return ERROR_FAIL;
2884 }
2885 result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &sim_fcfg1);
2886 if (result != ERROR_OK)
2887 return result;
2888
2889 flex_nvm_partition_code = (uint8_t)((sim_fcfg1 >> 8) & 0x0f);
2890 switch (flex_nvm_partition_code) {
2891 case 0:
2892 command_print(CMD_CTX, "No EEPROM backup, data flash only");
2893 break;
2894 case 1:
2895 case 2:
2896 case 3:
2897 case 4:
2898 case 5:
2899 case 6:
2900 command_print(CMD_CTX, "EEPROM backup %d KB", 4 << flex_nvm_partition_code);
2901 break;
2902 case 8:
2903 command_print(CMD_CTX, "No data flash, EEPROM backup only");
2904 break;
2905 case 0x9:
2906 case 0xA:
2907 case 0xB:
2908 case 0xC:
2909 case 0xD:
2910 case 0xE:
2911 command_print(CMD_CTX, "data flash %d KB", 4 << (flex_nvm_partition_code & 7));
2912 break;
2913 case 0xf:
2914 command_print(CMD_CTX, "No EEPROM backup, data flash only (DEPART not set)");
2915 break;
2916 default:
2917 command_print(CMD_CTX, "Unsupported EEPROM backup size code 0x%02" PRIx8, flex_nvm_partition_code);
2918 }
2919 return ERROR_OK;
2920
2921 case DF_SIZE:
2922 flex_nvm_partition_code = 0x8 | log2;
2923 break;
2924
2925 case EEBKP_SIZE:
2926 flex_nvm_partition_code = log2;
2927 break;
2928 }
2929
2930 if (CMD_ARGC == 3)
2931 ee1 = ee2 = strtoul(CMD_ARGV[2], NULL, 10) / 2;
2932 else if (CMD_ARGC >= 4) {
2933 ee1 = strtoul(CMD_ARGV[2], NULL, 10);
2934 ee2 = strtoul(CMD_ARGV[3], NULL, 10);
2935 }
2936
2937 enable = ee1 + ee2 > 0;
2938 if (enable) {
2939 for (log2 = 2; ; log2++) {
2940 if (ee1 + ee2 == (16u << 10) >> log2)
2941 break;
2942 if (ee1 + ee2 > (16u << 10) >> log2 || log2 >= 9) {
2943 LOG_ERROR("Unsupported EEPROM size");
2944 return ERROR_FLASH_OPERATION_FAILED;
2945 }
2946 }
2947
2948 if (ee1 * 3 == ee2)
2949 ee_split = 1;
2950 else if (ee1 * 7 == ee2)
2951 ee_split = 0;
2952 else if (ee1 != ee2) {
2953 LOG_ERROR("Unsupported EEPROM sizes ratio");
2954 return ERROR_FLASH_OPERATION_FAILED;
2955 }
2956
2957 ee_size_code = log2 | ee_split << 4;
2958 }
2959
2960 if (CMD_ARGC >= 5)
2961 COMMAND_PARSE_ON_OFF(CMD_ARGV[4], enable);
2962 if (enable)
2963 load_flex_ram = 0;
2964
2965 LOG_INFO("DEPART 0x%" PRIx8 ", EEPROM size code 0x%" PRIx8,
2966 flex_nvm_partition_code, ee_size_code);
2967
2968 result = kinetis_check_run_mode(k_chip);
2969 if (result != ERROR_OK)
2970 return result;
2971
2972 /* reset error flags */
2973 result = kinetis_ftfx_prepare(target);
2974 if (result != ERROR_OK)
2975 return result;
2976
2977 result = kinetis_ftfx_command(target, FTFx_CMD_PGMPART, load_flex_ram,
2978 ee_size_code, flex_nvm_partition_code, 0, 0,
2979 0, 0, 0, 0, NULL);
2980 if (result != ERROR_OK)
2981 return result;
2982
2983 command_print(CMD_CTX, "FlexNVM partition set. Please reset MCU.");
2984
2985 if (k_chip) {
2986 first_nvm_bank = k_chip->num_pflash_blocks;
2987 num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
2988 for (bank_idx = first_nvm_bank; bank_idx < num_blocks; bank_idx++)
2989 k_chip->banks[bank_idx].probed = false; /* re-probe before next use */
2990 k_chip->probed = false;
2991 }
2992
2993 command_print(CMD_CTX, "FlexNVM banks will be re-probed to set new data flash size.");
2994 return ERROR_OK;
2995 }
2996
2997 COMMAND_HANDLER(kinetis_fcf_source_handler)
2998 {
2999 if (CMD_ARGC > 1)
3000 return ERROR_COMMAND_SYNTAX_ERROR;
3001
3002 if (CMD_ARGC == 1) {
3003 if (strcmp(CMD_ARGV[0], "write") == 0)
3004 allow_fcf_writes = true;
3005 else if (strcmp(CMD_ARGV[0], "protection") == 0)
3006 allow_fcf_writes = false;
3007 else
3008 return ERROR_COMMAND_SYNTAX_ERROR;
3009 }
3010
3011 if (allow_fcf_writes) {
3012 command_print(CMD_CTX, "Arbitrary Flash Configuration Field writes enabled.");
3013 command_print(CMD_CTX, "Protection info writes to FCF disabled.");
3014 LOG_WARNING("BEWARE: incorrect flash configuration may permanently lock the device.");
3015 } else {
3016 command_print(CMD_CTX, "Protection info writes to Flash Configuration Field enabled.");
3017 command_print(CMD_CTX, "Arbitrary FCF writes disabled. Mode safe from unwanted locking of the device.");
3018 }
3019
3020 return ERROR_OK;
3021 }
3022
3023 COMMAND_HANDLER(kinetis_fopt_handler)
3024 {
3025 if (CMD_ARGC > 1)
3026 return ERROR_COMMAND_SYNTAX_ERROR;
3027
3028 if (CMD_ARGC == 1) {
3029 fcf_fopt = (uint8_t)strtoul(CMD_ARGV[0], NULL, 0);
3030 fcf_fopt_configured = true;
3031 } else {
3032 command_print(CMD_CTX, "FCF_FOPT 0x%02" PRIx8, fcf_fopt);
3033 }
3034
3035 return ERROR_OK;
3036 }
3037
3038 COMMAND_HANDLER(kinetis_create_banks_handler)
3039 {
3040 if (CMD_ARGC > 0)
3041 return ERROR_COMMAND_SYNTAX_ERROR;
3042
3043 create_banks = true;
3044
3045 return ERROR_OK;
3046 }
3047
3048
3049 static const struct command_registration kinetis_security_command_handlers[] = {
3050 {
3051 .name = "check_security",
3052 .mode = COMMAND_EXEC,
3053 .help = "Check status of device security lock",
3054 .usage = "",
3055 .handler = kinetis_check_flash_security_status,
3056 },
3057 {
3058 .name = "halt",
3059 .mode = COMMAND_EXEC,
3060 .help = "Issue a halt via the MDM-AP",
3061 .usage = "",
3062 .handler = kinetis_mdm_halt,
3063 },
3064 {
3065 .name = "mass_erase",
3066 .mode = COMMAND_EXEC,
3067 .help = "Issue a complete flash erase via the MDM-AP",
3068 .usage = "",
3069 .handler = kinetis_mdm_mass_erase,
3070 },
3071 { .name = "reset",
3072 .mode = COMMAND_EXEC,
3073 .help = "Issue a reset via the MDM-AP",
3074 .usage = "",
3075 .handler = kinetis_mdm_reset,
3076 },
3077 COMMAND_REGISTRATION_DONE
3078 };
3079
3080 static const struct command_registration kinetis_exec_command_handlers[] = {
3081 {
3082 .name = "mdm",
3083 .mode = COMMAND_ANY,
3084 .help = "MDM-AP command group",
3085 .usage = "",
3086 .chain = kinetis_security_command_handlers,
3087 },
3088 {
3089 .name = "disable_wdog",
3090 .mode = COMMAND_EXEC,
3091 .help = "Disable the watchdog timer",
3092 .usage = "",
3093 .handler = kinetis_disable_wdog_handler,
3094 },
3095 {
3096 .name = "nvm_partition",
3097 .mode = COMMAND_EXEC,
3098 .help = "Show/set data flash or EEPROM backup size in kilobytes,"
3099 " set two EEPROM sizes in bytes and FlexRAM loading during reset",
3100 .usage = "('info'|'dataflash' size|'eebkp' size) [eesize1 eesize2] ['on'|'off']",
3101 .handler = kinetis_nvm_partition,
3102 },
3103 {
3104 .name = "fcf_source",