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Make OpenOCD build using -Og.
[openocd.git] / src / flash / nor / kinetis.c
1 /***************************************************************************
2 * Copyright (C) 2011 by Mathias Kuester *
3 * kesmtp@freenet.de *
4 * *
5 * Copyright (C) 2011 sleep(5) ltd *
6 * tomas@sleepfive.com *
7 * *
8 * Copyright (C) 2012 by Christopher D. Kilgour *
9 * techie at whiterocker.com *
10 * *
11 * Copyright (C) 2013 Nemui Trinomius *
12 * nemuisan_kawausogasuki@live.jp *
13 * *
14 * Copyright (C) 2015 Tomas Vanek *
15 * vanekt@fbl.cz *
16 * *
17 * This program is free software; you can redistribute it and/or modify *
18 * it under the terms of the GNU General Public License as published by *
19 * the Free Software Foundation; either version 2 of the License, or *
20 * (at your option) any later version. *
21 * *
22 * This program is distributed in the hope that it will be useful, *
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
25 * GNU General Public License for more details. *
26 * *
27 * You should have received a copy of the GNU General Public License *
28 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
29 ***************************************************************************/
30
31 #ifdef HAVE_CONFIG_H
32 #include "config.h"
33 #endif
34
35 #include "jtag/interface.h"
36 #include "imp.h"
37 #include <helper/binarybuffer.h>
38 #include <helper/time_support.h>
39 #include <target/target_type.h>
40 #include <target/algorithm.h>
41 #include <target/armv7m.h>
42 #include <target/cortex_m.h>
43
44 /*
45 * Implementation Notes
46 *
47 * The persistent memories in the Kinetis chip families K10 through
48 * K70 are all manipulated with the Flash Memory Module. Some
49 * variants call this module the FTFE, others call it the FTFL. To
50 * indicate that both are considered here, we use FTFX.
51 *
52 * Within the module, according to the chip variant, the persistent
53 * memory is divided into what Freescale terms Program Flash, FlexNVM,
54 * and FlexRAM. All chip variants have Program Flash. Some chip
55 * variants also have FlexNVM and FlexRAM, which always appear
56 * together.
57 *
58 * A given Kinetis chip may have 1, 2 or 4 blocks of flash. Here we map
59 * each block to a separate bank. Each block size varies by chip and
60 * may be determined by the read-only SIM_FCFG1 register. The sector
61 * size within each bank/block varies by chip, and may be 1, 2 or 4k.
62 * The sector size may be different for flash and FlexNVM.
63 *
64 * The first half of the flash (1 or 2 blocks) is always Program Flash
65 * and always starts at address 0x00000000. The "PFLSH" flag, bit 23
66 * of the read-only SIM_FCFG2 register, determines whether the second
67 * half of the flash is also Program Flash or FlexNVM+FlexRAM. When
68 * PFLSH is set, the second from the first half. When PFLSH is clear,
69 * the second half of flash is FlexNVM and always starts at address
70 * 0x10000000. FlexRAM, which is also present when PFLSH is clear,
71 * always starts at address 0x14000000.
72 *
73 * The Flash Memory Module provides a register set where flash
74 * commands are loaded to perform flash operations like erase and
75 * program. Different commands are available depending on whether
76 * Program Flash or FlexNVM/FlexRAM is being manipulated. Although
77 * the commands used are quite consistent between flash blocks, the
78 * parameters they accept differ according to the flash sector size.
79 *
80 */
81
82 /* Addressess */
83 #define FCF_ADDRESS 0x00000400
84 #define FCF_FPROT 0x8
85 #define FCF_FSEC 0xc
86 #define FCF_FOPT 0xd
87 #define FCF_FDPROT 0xf
88 #define FCF_SIZE 0x10
89
90 #define FLEXRAM 0x14000000
91
92 #define FMC_PFB01CR 0x4001f004
93 #define FTFx_FSTAT 0x40020000
94 #define FTFx_FCNFG 0x40020001
95 #define FTFx_FCCOB3 0x40020004
96 #define FTFx_FPROT3 0x40020010
97 #define FTFx_FDPROT 0x40020017
98 #define SIM_SDID 0x40048024
99 #define SIM_SOPT1 0x40047000
100 #define SIM_FCFG1 0x4004804c
101 #define SIM_FCFG2 0x40048050
102 #define WDOG_STCTRH 0x40052000
103 #define SMC_PMCTRL 0x4007E001
104 #define SMC_PMSTAT 0x4007E003
105
106 /* Values */
107 #define PM_STAT_RUN 0x01
108 #define PM_STAT_VLPR 0x04
109 #define PM_CTRL_RUNM_RUN 0x00
110
111 /* Commands */
112 #define FTFx_CMD_BLOCKSTAT 0x00
113 #define FTFx_CMD_SECTSTAT 0x01
114 #define FTFx_CMD_LWORDPROG 0x06
115 #define FTFx_CMD_SECTERASE 0x09
116 #define FTFx_CMD_SECTWRITE 0x0b
117 #define FTFx_CMD_MASSERASE 0x44
118 #define FTFx_CMD_PGMPART 0x80
119 #define FTFx_CMD_SETFLEXRAM 0x81
120
121 /* The older Kinetis K series uses the following SDID layout :
122 * Bit 31-16 : 0
123 * Bit 15-12 : REVID
124 * Bit 11-7 : DIEID
125 * Bit 6-4 : FAMID
126 * Bit 3-0 : PINID
127 *
128 * The newer Kinetis series uses the following SDID layout :
129 * Bit 31-28 : FAMID
130 * Bit 27-24 : SUBFAMID
131 * Bit 23-20 : SERIESID
132 * Bit 19-16 : SRAMSIZE
133 * Bit 15-12 : REVID
134 * Bit 6-4 : Reserved (0)
135 * Bit 3-0 : PINID
136 *
137 * We assume that if bits 31-16 are 0 then it's an older
138 * K-series MCU.
139 */
140
141 #define KINETIS_SOPT1_RAMSIZE_MASK 0x0000F000
142 #define KINETIS_SOPT1_RAMSIZE_K24FN1M 0x0000B000
143
144 #define KINETIS_SDID_K_SERIES_MASK 0x0000FFFF
145
146 #define KINETIS_SDID_DIEID_MASK 0x00000F80
147
148 #define KINETIS_SDID_DIEID_K22FN128 0x00000680 /* smaller pflash with FTFA */
149 #define KINETIS_SDID_DIEID_K22FN256 0x00000A80
150 #define KINETIS_SDID_DIEID_K22FN512 0x00000E80
151 #define KINETIS_SDID_DIEID_K24FN256 0x00000700
152
153 #define KINETIS_SDID_DIEID_K24FN1M 0x00000300 /* Detect Errata 7534 */
154
155 /* We can't rely solely on the FAMID field to determine the MCU
156 * type since some FAMID values identify multiple MCUs with
157 * different flash sector sizes (K20 and K22 for instance).
158 * Therefore we combine it with the DIEID bits which may possibly
159 * break if Freescale bumps the DIEID for a particular MCU. */
160 #define KINETIS_K_SDID_TYPE_MASK 0x00000FF0
161 #define KINETIS_K_SDID_K10_M50 0x00000000
162 #define KINETIS_K_SDID_K10_M72 0x00000080
163 #define KINETIS_K_SDID_K10_M100 0x00000100
164 #define KINETIS_K_SDID_K10_M120 0x00000180
165 #define KINETIS_K_SDID_K11 0x00000220
166 #define KINETIS_K_SDID_K12 0x00000200
167 #define KINETIS_K_SDID_K20_M50 0x00000010
168 #define KINETIS_K_SDID_K20_M72 0x00000090
169 #define KINETIS_K_SDID_K20_M100 0x00000110
170 #define KINETIS_K_SDID_K20_M120 0x00000190
171 #define KINETIS_K_SDID_K21_M50 0x00000230
172 #define KINETIS_K_SDID_K21_M120 0x00000330
173 #define KINETIS_K_SDID_K22_M50 0x00000210
174 #define KINETIS_K_SDID_K22_M120 0x00000310
175 #define KINETIS_K_SDID_K30_M72 0x000000A0
176 #define KINETIS_K_SDID_K30_M100 0x00000120
177 #define KINETIS_K_SDID_K40_M72 0x000000B0
178 #define KINETIS_K_SDID_K40_M100 0x00000130
179 #define KINETIS_K_SDID_K50_M72 0x000000E0
180 #define KINETIS_K_SDID_K51_M72 0x000000F0
181 #define KINETIS_K_SDID_K53 0x00000170
182 #define KINETIS_K_SDID_K60_M100 0x00000140
183 #define KINETIS_K_SDID_K60_M150 0x000001C0
184 #define KINETIS_K_SDID_K70_M150 0x000001D0
185
186 #define KINETIS_SDID_SERIESID_MASK 0x00F00000
187 #define KINETIS_SDID_SERIESID_K 0x00000000
188 #define KINETIS_SDID_SERIESID_KL 0x00100000
189 #define KINETIS_SDID_SERIESID_KW 0x00500000
190 #define KINETIS_SDID_SERIESID_KV 0x00600000
191
192 #define KINETIS_SDID_SUBFAMID_MASK 0x0F000000
193 #define KINETIS_SDID_SUBFAMID_KX0 0x00000000
194 #define KINETIS_SDID_SUBFAMID_KX1 0x01000000
195 #define KINETIS_SDID_SUBFAMID_KX2 0x02000000
196 #define KINETIS_SDID_SUBFAMID_KX3 0x03000000
197 #define KINETIS_SDID_SUBFAMID_KX4 0x04000000
198 #define KINETIS_SDID_SUBFAMID_KX5 0x05000000
199 #define KINETIS_SDID_SUBFAMID_KX6 0x06000000
200
201 #define KINETIS_SDID_FAMILYID_MASK 0xF0000000
202 #define KINETIS_SDID_FAMILYID_K0X 0x00000000
203 #define KINETIS_SDID_FAMILYID_K1X 0x10000000
204 #define KINETIS_SDID_FAMILYID_K2X 0x20000000
205 #define KINETIS_SDID_FAMILYID_K3X 0x30000000
206 #define KINETIS_SDID_FAMILYID_K4X 0x40000000
207 #define KINETIS_SDID_FAMILYID_K6X 0x60000000
208 #define KINETIS_SDID_FAMILYID_K7X 0x70000000
209
210 struct kinetis_flash_bank {
211 bool probed;
212 uint32_t sector_size;
213 uint32_t max_flash_prog_size;
214 uint32_t protection_size;
215 uint32_t prog_base; /* base address for FTFx operations */
216 /* same as bank->base for pflash, differs for FlexNVM */
217 uint32_t protection_block; /* number of first protection block in this bank */
218
219 uint32_t sim_sdid;
220 uint32_t sim_fcfg1;
221 uint32_t sim_fcfg2;
222
223 enum {
224 FC_AUTO = 0,
225 FC_PFLASH,
226 FC_FLEX_NVM,
227 FC_FLEX_RAM,
228 } flash_class;
229
230 enum {
231 FS_PROGRAM_SECTOR = 1,
232 FS_PROGRAM_LONGWORD = 2,
233 FS_PROGRAM_PHRASE = 4, /* Unsupported */
234 FS_INVALIDATE_CACHE = 8,
235 } flash_support;
236 };
237
238 #define MDM_AP 1
239
240 #define MDM_REG_STAT 0x00
241 #define MDM_REG_CTRL 0x04
242 #define MDM_REG_ID 0xfc
243
244 #define MDM_STAT_FMEACK (1<<0)
245 #define MDM_STAT_FREADY (1<<1)
246 #define MDM_STAT_SYSSEC (1<<2)
247 #define MDM_STAT_SYSRES (1<<3)
248 #define MDM_STAT_FMEEN (1<<5)
249 #define MDM_STAT_BACKDOOREN (1<<6)
250 #define MDM_STAT_LPEN (1<<7)
251 #define MDM_STAT_VLPEN (1<<8)
252 #define MDM_STAT_LLSMODEXIT (1<<9)
253 #define MDM_STAT_VLLSXMODEXIT (1<<10)
254 #define MDM_STAT_CORE_HALTED (1<<16)
255 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
256 #define MDM_STAT_CORESLEEPING (1<<18)
257
258 #define MDM_CTRL_FMEIP (1<<0)
259 #define MDM_CTRL_DBG_DIS (1<<1)
260 #define MDM_CTRL_DBG_REQ (1<<2)
261 #define MDM_CTRL_SYS_RES_REQ (1<<3)
262 #define MDM_CTRL_CORE_HOLD_RES (1<<4)
263 #define MDM_CTRL_VLLSX_DBG_REQ (1<<5)
264 #define MDM_CTRL_VLLSX_DBG_ACK (1<<6)
265 #define MDM_CTRL_VLLSX_STAT_ACK (1<<7)
266
267 #define MDM_ACCESS_TIMEOUT 500 /* msec */
268
269
270 static bool allow_fcf_writes;
271 static uint8_t fcf_fopt = 0xff;
272
273
274 struct flash_driver kinetis_flash;
275 static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
276 uint32_t offset, uint32_t count);
277 static int kinetis_auto_probe(struct flash_bank *bank);
278
279
280 static int kinetis_mdm_write_register(struct adiv5_dap *dap, unsigned reg, uint32_t value)
281 {
282 int retval;
283 LOG_DEBUG("MDM_REG[0x%02x] <- %08" PRIX32, reg, value);
284
285 retval = dap_queue_ap_write(dap_ap(dap, MDM_AP), reg, value);
286 if (retval != ERROR_OK) {
287 LOG_DEBUG("MDM: failed to queue a write request");
288 return retval;
289 }
290
291 retval = dap_run(dap);
292 if (retval != ERROR_OK) {
293 LOG_DEBUG("MDM: dap_run failed");
294 return retval;
295 }
296
297
298 return ERROR_OK;
299 }
300
301 static int kinetis_mdm_read_register(struct adiv5_dap *dap, unsigned reg, uint32_t *result)
302 {
303 int retval;
304
305 retval = dap_queue_ap_read(dap_ap(dap, MDM_AP), reg, result);
306 if (retval != ERROR_OK) {
307 LOG_DEBUG("MDM: failed to queue a read request");
308 return retval;
309 }
310
311 retval = dap_run(dap);
312 if (retval != ERROR_OK) {
313 LOG_DEBUG("MDM: dap_run failed");
314 return retval;
315 }
316
317 LOG_DEBUG("MDM_REG[0x%02x]: %08" PRIX32, reg, *result);
318 return ERROR_OK;
319 }
320
321 static int kinetis_mdm_poll_register(struct adiv5_dap *dap, unsigned reg,
322 uint32_t mask, uint32_t value, uint32_t timeout_ms)
323 {
324 uint32_t val;
325 int retval;
326 int64_t ms_timeout = timeval_ms() + timeout_ms;
327
328 do {
329 retval = kinetis_mdm_read_register(dap, reg, &val);
330 if (retval != ERROR_OK || (val & mask) == value)
331 return retval;
332
333 alive_sleep(1);
334 } while (timeval_ms() < ms_timeout);
335
336 LOG_DEBUG("MDM: polling timed out");
337 return ERROR_FAIL;
338 }
339
340 /*
341 * This command can be used to break a watchdog reset loop when
342 * connecting to an unsecured target. Unlike other commands, halt will
343 * automatically retry as it does not know how far into the boot process
344 * it is when the command is called.
345 */
346 COMMAND_HANDLER(kinetis_mdm_halt)
347 {
348 struct target *target = get_current_target(CMD_CTX);
349 struct cortex_m_common *cortex_m = target_to_cm(target);
350 struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
351 int retval;
352 int tries = 0;
353 uint32_t stat;
354 int64_t ms_timeout = timeval_ms() + MDM_ACCESS_TIMEOUT;
355
356 if (!dap) {
357 LOG_ERROR("Cannot perform halt with a high-level adapter");
358 return ERROR_FAIL;
359 }
360
361 while (true) {
362 tries++;
363
364 kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_CORE_HOLD_RES);
365
366 alive_sleep(1);
367
368 retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &stat);
369 if (retval != ERROR_OK) {
370 LOG_DEBUG("MDM: failed to read MDM_REG_STAT");
371 continue;
372 }
373
374 /* Repeat setting MDM_CTRL_CORE_HOLD_RES until system is out of
375 * reset with flash ready and without security
376 */
377 if ((stat & (MDM_STAT_FREADY | MDM_STAT_SYSSEC | MDM_STAT_SYSRES))
378 == (MDM_STAT_FREADY | MDM_STAT_SYSRES))
379 break;
380
381 if (timeval_ms() >= ms_timeout) {
382 LOG_ERROR("MDM: halt timed out");
383 return ERROR_FAIL;
384 }
385 }
386
387 LOG_DEBUG("MDM: halt succeded after %d attempts.", tries);
388
389 target_poll(target);
390 /* enable polling in case kinetis_check_flash_security_status disabled it */
391 jtag_poll_set_enabled(true);
392
393 alive_sleep(100);
394
395 target->reset_halt = true;
396 target->type->assert_reset(target);
397
398 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
399 if (retval != ERROR_OK) {
400 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
401 return retval;
402 }
403
404 target->type->deassert_reset(target);
405
406 return ERROR_OK;
407 }
408
409 COMMAND_HANDLER(kinetis_mdm_reset)
410 {
411 struct target *target = get_current_target(CMD_CTX);
412 struct cortex_m_common *cortex_m = target_to_cm(target);
413 struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
414 int retval;
415
416 if (!dap) {
417 LOG_ERROR("Cannot perform reset with a high-level adapter");
418 return ERROR_FAIL;
419 }
420
421 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_SYS_RES_REQ);
422 if (retval != ERROR_OK) {
423 LOG_ERROR("MDM: failed to write MDM_REG_CTRL");
424 return retval;
425 }
426
427 retval = kinetis_mdm_poll_register(dap, MDM_REG_STAT, MDM_STAT_SYSRES, 0, 500);
428 if (retval != ERROR_OK) {
429 LOG_ERROR("MDM: failed to assert reset");
430 return retval;
431 }
432
433 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
434 if (retval != ERROR_OK) {
435 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
436 return retval;
437 }
438
439 return ERROR_OK;
440 }
441
442 /*
443 * This function implements the procedure to mass erase the flash via
444 * SWD/JTAG on Kinetis K and L series of devices as it is described in
445 * AN4835 "Production Flash Programming Best Practices for Kinetis K-
446 * and L-series MCUs" Section 4.2.1. To prevent a watchdog reset loop,
447 * the core remains halted after this function completes as suggested
448 * by the application note.
449 */
450 COMMAND_HANDLER(kinetis_mdm_mass_erase)
451 {
452 struct target *target = get_current_target(CMD_CTX);
453 struct cortex_m_common *cortex_m = target_to_cm(target);
454 struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
455
456 if (!dap) {
457 LOG_ERROR("Cannot perform mass erase with a high-level adapter");
458 return ERROR_FAIL;
459 }
460
461 int retval;
462
463 /*
464 * ... Power on the processor, or if power has already been
465 * applied, assert the RESET pin to reset the processor. For
466 * devices that do not have a RESET pin, write the System
467 * Reset Request bit in the MDM-AP control register after
468 * establishing communication...
469 */
470
471 /* assert SRST if configured */
472 bool has_srst = jtag_get_reset_config() & RESET_HAS_SRST;
473 if (has_srst)
474 adapter_assert_reset();
475
476 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_SYS_RES_REQ);
477 if (retval != ERROR_OK && !has_srst) {
478 LOG_ERROR("MDM: failed to assert reset");
479 goto deassert_reset_and_exit;
480 }
481
482 /*
483 * ... Read the MDM-AP status register repeatedly and wait for
484 * stable conditions suitable for mass erase:
485 * - mass erase is enabled
486 * - flash is ready
487 * - reset is finished
488 *
489 * Mass erase is started as soon as all conditions are met in 32
490 * subsequent status reads.
491 *
492 * In case of not stable conditions (RESET/WDOG loop in secured device)
493 * the user is asked for manual pressing of RESET button
494 * as a last resort.
495 */
496 int cnt_mass_erase_disabled = 0;
497 int cnt_ready = 0;
498 int64_t ms_start = timeval_ms();
499 bool man_reset_requested = false;
500
501 do {
502 uint32_t stat = 0;
503 int64_t ms_elapsed = timeval_ms() - ms_start;
504
505 if (!man_reset_requested && ms_elapsed > 100) {
506 LOG_INFO("MDM: Press RESET button now if possible.");
507 man_reset_requested = true;
508 }
509
510 if (ms_elapsed > 3000) {
511 LOG_ERROR("MDM: waiting for mass erase conditions timed out.");
512 LOG_INFO("Mass erase of a secured MCU is not possible without hardware reset.");
513 LOG_INFO("Connect SRST, use 'reset_config srst_only' and retry.");
514 goto deassert_reset_and_exit;
515 }
516 retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &stat);
517 if (retval != ERROR_OK) {
518 cnt_ready = 0;
519 continue;
520 }
521
522 if (!(stat & MDM_STAT_FMEEN)) {
523 cnt_ready = 0;
524 cnt_mass_erase_disabled++;
525 if (cnt_mass_erase_disabled > 10) {
526 LOG_ERROR("MDM: mass erase is disabled");
527 goto deassert_reset_and_exit;
528 }
529 continue;
530 }
531
532 if ((stat & (MDM_STAT_FREADY | MDM_STAT_SYSRES)) == MDM_STAT_FREADY)
533 cnt_ready++;
534 else
535 cnt_ready = 0;
536
537 } while (cnt_ready < 32);
538
539 /*
540 * ... Write the MDM-AP control register to set the Flash Mass
541 * Erase in Progress bit. This will start the mass erase
542 * process...
543 */
544 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_SYS_RES_REQ | MDM_CTRL_FMEIP);
545 if (retval != ERROR_OK) {
546 LOG_ERROR("MDM: failed to start mass erase");
547 goto deassert_reset_and_exit;
548 }
549
550 /*
551 * ... Read the MDM-AP control register until the Flash Mass
552 * Erase in Progress bit clears...
553 * Data sheed defines erase time <3.6 sec/512kB flash block.
554 * The biggest device has 4 pflash blocks => timeout 16 sec.
555 */
556 retval = kinetis_mdm_poll_register(dap, MDM_REG_CTRL, MDM_CTRL_FMEIP, 0, 16000);
557 if (retval != ERROR_OK) {
558 LOG_ERROR("MDM: mass erase timeout");
559 goto deassert_reset_and_exit;
560 }
561
562 target_poll(target);
563 /* enable polling in case kinetis_check_flash_security_status disabled it */
564 jtag_poll_set_enabled(true);
565
566 alive_sleep(100);
567
568 target->reset_halt = true;
569 target->type->assert_reset(target);
570
571 /*
572 * ... Negate the RESET signal or clear the System Reset Request
573 * bit in the MDM-AP control register.
574 */
575 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
576 if (retval != ERROR_OK)
577 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
578
579 target->type->deassert_reset(target);
580
581 return retval;
582
583 deassert_reset_and_exit:
584 kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
585 if (has_srst)
586 adapter_deassert_reset();
587 return retval;
588 }
589
590 static const uint32_t kinetis_known_mdm_ids[] = {
591 0x001C0000, /* Kinetis-K Series */
592 0x001C0020, /* Kinetis-L/M/V/E Series */
593 };
594
595 /*
596 * This function implements the procedure to connect to
597 * SWD/JTAG on Kinetis K and L series of devices as it is described in
598 * AN4835 "Production Flash Programming Best Practices for Kinetis K-
599 * and L-series MCUs" Section 4.1.1
600 */
601 COMMAND_HANDLER(kinetis_check_flash_security_status)
602 {
603 struct target *target = get_current_target(CMD_CTX);
604 struct cortex_m_common *cortex_m = target_to_cm(target);
605 struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
606
607 if (!dap) {
608 LOG_WARNING("Cannot check flash security status with a high-level adapter");
609 return ERROR_OK;
610 }
611
612 if (!dap->ops)
613 return ERROR_OK; /* too early to check, in JTAG mode ops may not be initialised */
614
615 uint32_t val;
616 int retval;
617
618 /*
619 * ... The MDM-AP ID register can be read to verify that the
620 * connection is working correctly...
621 */
622 retval = kinetis_mdm_read_register(dap, MDM_REG_ID, &val);
623 if (retval != ERROR_OK) {
624 LOG_ERROR("MDM: failed to read ID register");
625 return ERROR_OK;
626 }
627
628 if (val == 0)
629 return ERROR_OK; /* dap not yet initialised */
630
631 bool found = false;
632 for (size_t i = 0; i < ARRAY_SIZE(kinetis_known_mdm_ids); i++) {
633 if (val == kinetis_known_mdm_ids[i]) {
634 found = true;
635 break;
636 }
637 }
638
639 if (!found)
640 LOG_WARNING("MDM: unknown ID %08" PRIX32, val);
641
642 /*
643 * ... Read the System Security bit to determine if security is enabled.
644 * If System Security = 0, then proceed. If System Security = 1, then
645 * communication with the internals of the processor, including the
646 * flash, will not be possible without issuing a mass erase command or
647 * unsecuring the part through other means (backdoor key unlock)...
648 */
649 retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &val);
650 if (retval != ERROR_OK) {
651 LOG_ERROR("MDM: failed to read MDM_REG_STAT");
652 return ERROR_OK;
653 }
654
655 /*
656 * System Security bit is also active for short time during reset.
657 * If a MCU has blank flash and runs in RESET/WDOG loop,
658 * System Security bit is active most of time!
659 * We should observe Flash Ready bit and read status several times
660 * to avoid false detection of secured MCU
661 */
662 int secured_score = 0, flash_not_ready_score = 0;
663
664 if ((val & (MDM_STAT_SYSSEC | MDM_STAT_FREADY)) != MDM_STAT_FREADY) {
665 uint32_t stats[32];
666 int i;
667
668 for (i = 0; i < 32; i++) {
669 stats[i] = MDM_STAT_FREADY;
670 dap_queue_ap_read(dap_ap(dap, MDM_AP), MDM_REG_STAT, &stats[i]);
671 }
672 retval = dap_run(dap);
673 if (retval != ERROR_OK) {
674 LOG_DEBUG("MDM: dap_run failed when validating secured state");
675 return ERROR_OK;
676 }
677 for (i = 0; i < 32; i++) {
678 if (stats[i] & MDM_STAT_SYSSEC)
679 secured_score++;
680 if (!(stats[i] & MDM_STAT_FREADY))
681 flash_not_ready_score++;
682 }
683 }
684
685 if (flash_not_ready_score <= 8 && secured_score > 24) {
686 jtag_poll_set_enabled(false);
687
688 LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
689 LOG_WARNING("**** ****");
690 LOG_WARNING("**** Your Kinetis MCU is in secured state, which means that, ****");
691 LOG_WARNING("**** with exception for very basic communication, JTAG/SWD ****");
692 LOG_WARNING("**** interface will NOT work. In order to restore its ****");
693 LOG_WARNING("**** functionality please issue 'kinetis mdm mass_erase' ****");
694 LOG_WARNING("**** command, power cycle the MCU and restart OpenOCD. ****");
695 LOG_WARNING("**** ****");
696 LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
697
698 } else if (flash_not_ready_score > 24) {
699 jtag_poll_set_enabled(false);
700 LOG_WARNING("**** Your Kinetis MCU is probably locked-up in RESET/WDOG loop. ****");
701 LOG_WARNING("**** Common reason is a blank flash (at least a reset vector). ****");
702 LOG_WARNING("**** Issue 'kinetis mdm halt' command or if SRST is connected ****");
703 LOG_WARNING("**** and configured, use 'reset halt' ****");
704 LOG_WARNING("**** If MCU cannot be halted, it is likely secured and running ****");
705 LOG_WARNING("**** in RESET/WDOG loop. Issue 'kinetis mdm mass_erase' ****");
706
707 } else {
708 LOG_INFO("MDM: Chip is unsecured. Continuing.");
709 jtag_poll_set_enabled(true);
710 }
711
712 return ERROR_OK;
713 }
714
715 FLASH_BANK_COMMAND_HANDLER(kinetis_flash_bank_command)
716 {
717 struct kinetis_flash_bank *bank_info;
718
719 if (CMD_ARGC < 6)
720 return ERROR_COMMAND_SYNTAX_ERROR;
721
722 LOG_INFO("add flash_bank kinetis %s", bank->name);
723
724 bank_info = malloc(sizeof(struct kinetis_flash_bank));
725
726 memset(bank_info, 0, sizeof(struct kinetis_flash_bank));
727
728 bank->driver_priv = bank_info;
729
730 return ERROR_OK;
731 }
732
733 /* Disable the watchdog on Kinetis devices */
734 int kinetis_disable_wdog(struct target *target, uint32_t sim_sdid)
735 {
736 struct working_area *wdog_algorithm;
737 struct armv7m_algorithm armv7m_info;
738 uint16_t wdog;
739 int retval;
740
741 static const uint8_t kinetis_unlock_wdog_code[] = {
742 #include "../../../contrib/loaders/watchdog/armv7m_kinetis_wdog.inc"
743 };
744
745 /* Decide whether the connected device needs watchdog disabling.
746 * Disable for all Kx and KVx devices, return if it is a KLx */
747
748 if ((sim_sdid & KINETIS_SDID_SERIESID_MASK) == KINETIS_SDID_SERIESID_KL)
749 return ERROR_OK;
750
751 /* The connected device requires watchdog disabling. */
752 retval = target_read_u16(target, WDOG_STCTRH, &wdog);
753 if (retval != ERROR_OK)
754 return retval;
755
756 if ((wdog & 0x1) == 0) {
757 /* watchdog already disabled */
758 return ERROR_OK;
759 }
760 LOG_INFO("Disabling Kinetis watchdog (initial WDOG_STCTRLH = 0x%x)", wdog);
761
762 if (target->state != TARGET_HALTED) {
763 LOG_ERROR("Target not halted");
764 return ERROR_TARGET_NOT_HALTED;
765 }
766
767 retval = target_alloc_working_area(target, sizeof(kinetis_unlock_wdog_code), &wdog_algorithm);
768 if (retval != ERROR_OK)
769 return retval;
770
771 retval = target_write_buffer(target, wdog_algorithm->address,
772 sizeof(kinetis_unlock_wdog_code), (uint8_t *)kinetis_unlock_wdog_code);
773 if (retval != ERROR_OK) {
774 target_free_working_area(target, wdog_algorithm);
775 return retval;
776 }
777
778 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
779 armv7m_info.core_mode = ARM_MODE_THREAD;
780
781 retval = target_run_algorithm(target, 0, NULL, 0, NULL, wdog_algorithm->address,
782 wdog_algorithm->address + (sizeof(kinetis_unlock_wdog_code) - 2),
783 10000, &armv7m_info);
784
785 if (retval != ERROR_OK)
786 LOG_ERROR("error executing kinetis wdog unlock algorithm");
787
788 retval = target_read_u16(target, WDOG_STCTRH, &wdog);
789 if (retval != ERROR_OK)
790 return retval;
791 LOG_INFO("WDOG_STCTRLH = 0x%x", wdog);
792
793 target_free_working_area(target, wdog_algorithm);
794
795 return retval;
796 }
797
798 COMMAND_HANDLER(kinetis_disable_wdog_handler)
799 {
800 int result;
801 uint32_t sim_sdid;
802 struct target *target = get_current_target(CMD_CTX);
803
804 if (CMD_ARGC > 0)
805 return ERROR_COMMAND_SYNTAX_ERROR;
806
807 result = target_read_u32(target, SIM_SDID, &sim_sdid);
808 if (result != ERROR_OK) {
809 LOG_ERROR("Failed to read SIMSDID");
810 return result;
811 }
812
813 result = kinetis_disable_wdog(target, sim_sdid);
814 return result;
815 }
816
817
818 static int kinetis_ftfx_decode_error(uint8_t fstat)
819 {
820 if (fstat & 0x20) {
821 LOG_ERROR("Flash operation failed, illegal command");
822 return ERROR_FLASH_OPER_UNSUPPORTED;
823
824 } else if (fstat & 0x10)
825 LOG_ERROR("Flash operation failed, protection violated");
826
827 else if (fstat & 0x40)
828 LOG_ERROR("Flash operation failed, read collision");
829
830 else if (fstat & 0x80)
831 return ERROR_OK;
832
833 else
834 LOG_ERROR("Flash operation timed out");
835
836 return ERROR_FLASH_OPERATION_FAILED;
837 }
838
839
840 static int kinetis_ftfx_prepare(struct target *target)
841 {
842 int result, i;
843 uint8_t fstat;
844
845 /* wait until busy */
846 for (i = 0; i < 50; i++) {
847 result = target_read_u8(target, FTFx_FSTAT, &fstat);
848 if (result != ERROR_OK)
849 return result;
850
851 if (fstat & 0x80)
852 break;
853 }
854
855 if ((fstat & 0x80) == 0) {
856 LOG_ERROR("Flash controller is busy");
857 return ERROR_FLASH_OPERATION_FAILED;
858 }
859 if (fstat != 0x80) {
860 /* reset error flags */
861 result = target_write_u8(target, FTFx_FSTAT, 0x70);
862 }
863 return result;
864 }
865
866 /* Kinetis Program-LongWord Microcodes */
867 static const uint8_t kinetis_flash_write_code[] = {
868 /* Params:
869 * r0 - workarea buffer
870 * r1 - target address
871 * r2 - wordcount
872 * Clobbered:
873 * r4 - tmp
874 * r5 - tmp
875 * r6 - tmp
876 * r7 - tmp
877 */
878
879 /* .L1: */
880 /* for(register uint32_t i=0;i<wcount;i++){ */
881 0x04, 0x1C, /* mov r4, r0 */
882 0x00, 0x23, /* mov r3, #0 */
883 /* .L2: */
884 0x0E, 0x1A, /* sub r6, r1, r0 */
885 0xA6, 0x19, /* add r6, r4, r6 */
886 0x93, 0x42, /* cmp r3, r2 */
887 0x16, 0xD0, /* beq .L9 */
888 /* .L5: */
889 /* while((FTFx_FSTAT&FTFA_FSTAT_CCIF_MASK) != FTFA_FSTAT_CCIF_MASK){}; */
890 0x0B, 0x4D, /* ldr r5, .L10 */
891 0x2F, 0x78, /* ldrb r7, [r5] */
892 0x7F, 0xB2, /* sxtb r7, r7 */
893 0x00, 0x2F, /* cmp r7, #0 */
894 0xFA, 0xDA, /* bge .L5 */
895 /* FTFx_FSTAT = FTFA_FSTAT_ACCERR_MASK|FTFA_FSTAT_FPVIOL_MASK|FTFA_FSTAT_RDCO */
896 0x70, 0x27, /* mov r7, #112 */
897 0x2F, 0x70, /* strb r7, [r5] */
898 /* FTFx_FCCOB3 = faddr; */
899 0x09, 0x4F, /* ldr r7, .L10+4 */
900 0x3E, 0x60, /* str r6, [r7] */
901 0x06, 0x27, /* mov r7, #6 */
902 /* FTFx_FCCOB0 = 0x06; */
903 0x08, 0x4E, /* ldr r6, .L10+8 */
904 0x37, 0x70, /* strb r7, [r6] */
905 /* FTFx_FCCOB7 = *pLW; */
906 0x80, 0xCC, /* ldmia r4!, {r7} */
907 0x08, 0x4E, /* ldr r6, .L10+12 */
908 0x37, 0x60, /* str r7, [r6] */
909 /* FTFx_FSTAT = FTFA_FSTAT_CCIF_MASK; */
910 0x80, 0x27, /* mov r7, #128 */
911 0x2F, 0x70, /* strb r7, [r5] */
912 /* .L4: */
913 /* while((FTFx_FSTAT&FTFA_FSTAT_CCIF_MASK) != FTFA_FSTAT_CCIF_MASK){}; */
914 0x2E, 0x78, /* ldrb r6, [r5] */
915 0x77, 0xB2, /* sxtb r7, r6 */
916 0x00, 0x2F, /* cmp r7, #0 */
917 0xFB, 0xDA, /* bge .L4 */
918 0x01, 0x33, /* add r3, r3, #1 */
919 0xE4, 0xE7, /* b .L2 */
920 /* .L9: */
921 0x00, 0xBE, /* bkpt #0 */
922 /* .L10: */
923 0x00, 0x00, 0x02, 0x40, /* .word 1073872896 */
924 0x04, 0x00, 0x02, 0x40, /* .word 1073872900 */
925 0x07, 0x00, 0x02, 0x40, /* .word 1073872903 */
926 0x08, 0x00, 0x02, 0x40, /* .word 1073872904 */
927 };
928
929 /* Program LongWord Block Write */
930 static int kinetis_write_block(struct flash_bank *bank, const uint8_t *buffer,
931 uint32_t offset, uint32_t wcount)
932 {
933 struct target *target = bank->target;
934 uint32_t buffer_size = 2048; /* Default minimum value */
935 struct working_area *write_algorithm;
936 struct working_area *source;
937 struct kinetis_flash_bank *kinfo = bank->driver_priv;
938 uint32_t address = kinfo->prog_base + offset;
939 struct reg_param reg_params[3];
940 struct armv7m_algorithm armv7m_info;
941 int retval = ERROR_OK;
942
943 /* Params:
944 * r0 - workarea buffer
945 * r1 - target address
946 * r2 - wordcount
947 * Clobbered:
948 * r4 - tmp
949 * r5 - tmp
950 * r6 - tmp
951 * r7 - tmp
952 */
953
954 /* Increase buffer_size if needed */
955 if (buffer_size < (target->working_area_size/2))
956 buffer_size = (target->working_area_size/2);
957
958 /* allocate working area with flash programming code */
959 if (target_alloc_working_area(target, sizeof(kinetis_flash_write_code),
960 &write_algorithm) != ERROR_OK) {
961 LOG_WARNING("no working area available, can't do block memory writes");
962 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
963 }
964
965 retval = target_write_buffer(target, write_algorithm->address,
966 sizeof(kinetis_flash_write_code), kinetis_flash_write_code);
967 if (retval != ERROR_OK)
968 return retval;
969
970 /* memory buffer */
971 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
972 buffer_size /= 4;
973 if (buffer_size <= 256) {
974 /* free working area, write algorithm already allocated */
975 target_free_working_area(target, write_algorithm);
976
977 LOG_WARNING("No large enough working area available, can't do block memory writes");
978 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
979 }
980 }
981
982 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
983 armv7m_info.core_mode = ARM_MODE_THREAD;
984
985 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT); /* *pLW (*buffer) */
986 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* faddr */
987 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* number of words to program */
988
989 /* write code buffer and use Flash programming code within kinetis */
990 /* Set breakpoint to 0 with time-out of 1000 ms */
991 while (wcount > 0) {
992 uint32_t thisrun_count = (wcount > (buffer_size / 4)) ? (buffer_size / 4) : wcount;
993
994 retval = target_write_buffer(target, source->address, thisrun_count * 4, buffer);
995 if (retval != ERROR_OK)
996 break;
997
998 buf_set_u32(reg_params[0].value, 0, 32, source->address);
999 buf_set_u32(reg_params[1].value, 0, 32, address);
1000 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
1001
1002 retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
1003 write_algorithm->address, 0, 100000, &armv7m_info);
1004 if (retval != ERROR_OK) {
1005 LOG_ERROR("Error executing kinetis Flash programming algorithm");
1006 retval = ERROR_FLASH_OPERATION_FAILED;
1007 break;
1008 }
1009
1010 buffer += thisrun_count * 4;
1011 address += thisrun_count * 4;
1012 wcount -= thisrun_count;
1013 }
1014
1015 target_free_working_area(target, source);
1016 target_free_working_area(target, write_algorithm);
1017
1018 destroy_reg_param(&reg_params[0]);
1019 destroy_reg_param(&reg_params[1]);
1020 destroy_reg_param(&reg_params[2]);
1021
1022 return retval;
1023 }
1024
1025 static int kinetis_protect(struct flash_bank *bank, int set, int first, int last)
1026 {
1027 int i;
1028
1029 if (allow_fcf_writes) {
1030 LOG_ERROR("Protection setting is possible with 'kinetis fcf_source protection' only!");
1031 return ERROR_FAIL;
1032 }
1033
1034 if (!bank->prot_blocks || bank->num_prot_blocks == 0) {
1035 LOG_ERROR("No protection possible for current bank!");
1036 return ERROR_FLASH_BANK_INVALID;
1037 }
1038
1039 for (i = first; i < bank->num_prot_blocks && i <= last; i++)
1040 bank->prot_blocks[i].is_protected = set;
1041
1042 LOG_INFO("Protection bits will be written at the next FCF sector erase or write.");
1043 LOG_INFO("Do not issue 'flash info' command until protection is written,");
1044 LOG_INFO("doing so would re-read protection status from MCU.");
1045
1046 return ERROR_OK;
1047 }
1048
1049 static int kinetis_protect_check(struct flash_bank *bank)
1050 {
1051 struct kinetis_flash_bank *kinfo = bank->driver_priv;
1052 int result;
1053 int i, b;
1054 uint32_t fprot;
1055
1056 if (kinfo->flash_class == FC_PFLASH) {
1057
1058 /* read protection register */
1059 result = target_read_u32(bank->target, FTFx_FPROT3, &fprot);
1060 if (result != ERROR_OK)
1061 return result;
1062
1063 /* Every bit protects 1/32 of the full flash (not necessarily just this bank) */
1064
1065 } else if (kinfo->flash_class == FC_FLEX_NVM) {
1066 uint8_t fdprot;
1067
1068 /* read protection register */
1069 result = target_read_u8(bank->target, FTFx_FDPROT, &fdprot);
1070 if (result != ERROR_OK)
1071 return result;
1072
1073 fprot = fdprot;
1074
1075 } else {
1076 LOG_ERROR("Protection checks for FlexRAM not supported");
1077 return ERROR_FLASH_BANK_INVALID;
1078 }
1079
1080 b = kinfo->protection_block;
1081 for (i = 0; i < bank->num_prot_blocks; i++) {
1082 if ((fprot >> b) & 1)
1083 bank->prot_blocks[i].is_protected = 0;
1084 else
1085 bank->prot_blocks[i].is_protected = 1;
1086
1087 b++;
1088 }
1089
1090 return ERROR_OK;
1091 }
1092
1093
1094 static int kinetis_fill_fcf(struct flash_bank *bank, uint8_t *fcf)
1095 {
1096 uint32_t fprot = 0xffffffff;
1097 uint8_t fsec = 0xfe; /* set MCU unsecure */
1098 uint8_t fdprot = 0xff;
1099 int i;
1100 uint32_t pflash_bit;
1101 uint8_t dflash_bit;
1102 struct flash_bank *bank_iter;
1103 struct kinetis_flash_bank *kinfo;
1104
1105 memset(fcf, 0xff, FCF_SIZE);
1106
1107 pflash_bit = 1;
1108 dflash_bit = 1;
1109
1110 /* iterate over all kinetis banks */
1111 /* current bank is bank 0, it contains FCF */
1112 for (bank_iter = bank; bank_iter; bank_iter = bank_iter->next) {
1113 if (bank_iter->driver != &kinetis_flash
1114 || bank_iter->target != bank->target)
1115 continue;
1116
1117 kinetis_auto_probe(bank_iter);
1118
1119 kinfo = bank->driver_priv;
1120 if (!kinfo)
1121 continue;
1122
1123 if (kinfo->flash_class == FC_PFLASH) {
1124 for (i = 0; i < bank_iter->num_prot_blocks; i++) {
1125 if (bank_iter->prot_blocks[i].is_protected == 1)
1126 fprot &= ~pflash_bit;
1127
1128 pflash_bit <<= 1;
1129 }
1130
1131 } else if (kinfo->flash_class == FC_FLEX_NVM) {
1132 for (i = 0; i < bank_iter->num_prot_blocks; i++) {
1133 if (bank_iter->prot_blocks[i].is_protected == 1)
1134 fdprot &= ~dflash_bit;
1135
1136 dflash_bit <<= 1;
1137 }
1138
1139 }
1140 }
1141
1142 target_buffer_set_u32(bank->target, fcf + FCF_FPROT, fprot);
1143 fcf[FCF_FSEC] = fsec;
1144 fcf[FCF_FOPT] = fcf_fopt;
1145 fcf[FCF_FDPROT] = fdprot;
1146 return ERROR_OK;
1147 }
1148
1149 static int kinetis_ftfx_command(struct target *target, uint8_t fcmd, uint32_t faddr,
1150 uint8_t fccob4, uint8_t fccob5, uint8_t fccob6, uint8_t fccob7,
1151 uint8_t fccob8, uint8_t fccob9, uint8_t fccoba, uint8_t fccobb,
1152 uint8_t *ftfx_fstat)
1153 {
1154 uint8_t command[12] = {faddr & 0xff, (faddr >> 8) & 0xff, (faddr >> 16) & 0xff, fcmd,
1155 fccob7, fccob6, fccob5, fccob4,
1156 fccobb, fccoba, fccob9, fccob8};
1157 int result;
1158 uint8_t fstat;
1159 int64_t ms_timeout = timeval_ms() + 250;
1160
1161 result = target_write_memory(target, FTFx_FCCOB3, 4, 3, command);
1162 if (result != ERROR_OK)
1163 return result;
1164
1165 /* start command */
1166 result = target_write_u8(target, FTFx_FSTAT, 0x80);
1167 if (result != ERROR_OK)
1168 return result;
1169
1170 /* wait for done */
1171 do {
1172 result = target_read_u8(target, FTFx_FSTAT, &fstat);
1173
1174 if (result != ERROR_OK)
1175 return result;
1176
1177 if (fstat & 0x80)
1178 break;
1179
1180 } while (timeval_ms() < ms_timeout);
1181
1182 if (ftfx_fstat)
1183 *ftfx_fstat = fstat;
1184
1185 if ((fstat & 0xf0) != 0x80) {
1186 LOG_DEBUG("ftfx command failed FSTAT: %02X FCCOB: %02X%02X%02X%02X %02X%02X%02X%02X %02X%02X%02X%02X",
1187 fstat, command[3], command[2], command[1], command[0],
1188 command[7], command[6], command[5], command[4],
1189 command[11], command[10], command[9], command[8]);
1190
1191 return kinetis_ftfx_decode_error(fstat);
1192 }
1193
1194 return ERROR_OK;
1195 }
1196
1197
1198 static int kinetis_check_run_mode(struct target *target)
1199 {
1200 int result, i;
1201 uint8_t pmctrl, pmstat;
1202
1203 if (target->state != TARGET_HALTED) {
1204 LOG_ERROR("Target not halted");
1205 return ERROR_TARGET_NOT_HALTED;
1206 }
1207
1208 result = target_read_u8(target, SMC_PMSTAT, &pmstat);
1209 if (result != ERROR_OK)
1210 return result;
1211
1212 if (pmstat == PM_STAT_RUN)
1213 return ERROR_OK;
1214
1215 if (pmstat == PM_STAT_VLPR) {
1216 /* It is safe to switch from VLPR to RUN mode without changing clock */
1217 LOG_INFO("Switching from VLPR to RUN mode.");
1218 pmctrl = PM_CTRL_RUNM_RUN;
1219 result = target_write_u8(target, SMC_PMCTRL, pmctrl);
1220 if (result != ERROR_OK)
1221 return result;
1222
1223 for (i = 100; i; i--) {
1224 result = target_read_u8(target, SMC_PMSTAT, &pmstat);
1225 if (result != ERROR_OK)
1226 return result;
1227
1228 if (pmstat == PM_STAT_RUN)
1229 return ERROR_OK;
1230 }
1231 }
1232
1233 LOG_ERROR("Flash operation not possible in current run mode: SMC_PMSTAT: 0x%x", pmstat);
1234 LOG_ERROR("Issue a 'reset init' command.");
1235 return ERROR_TARGET_NOT_HALTED;
1236 }
1237
1238
1239 static void kinetis_invalidate_flash_cache(struct flash_bank *bank)
1240 {
1241 struct kinetis_flash_bank *kinfo = bank->driver_priv;
1242 uint8_t pfb01cr_byte2 = 0xf0;
1243
1244 if (!(kinfo->flash_support & FS_INVALIDATE_CACHE))
1245 return;
1246
1247 target_write_memory(bank->target, FMC_PFB01CR + 2, 1, 1, &pfb01cr_byte2);
1248 return;
1249 }
1250
1251
1252 static int kinetis_erase(struct flash_bank *bank, int first, int last)
1253 {
1254 int result, i;
1255 struct kinetis_flash_bank *kinfo = bank->driver_priv;
1256
1257 result = kinetis_check_run_mode(bank->target);
1258 if (result != ERROR_OK)
1259 return result;
1260
1261 /* reset error flags */
1262 result = kinetis_ftfx_prepare(bank->target);
1263 if (result != ERROR_OK)
1264 return result;
1265
1266 if ((first > bank->num_sectors) || (last > bank->num_sectors))
1267 return ERROR_FLASH_OPERATION_FAILED;
1268
1269 /*
1270 * FIXME: TODO: use the 'Erase Flash Block' command if the
1271 * requested erase is PFlash or NVM and encompasses the entire
1272 * block. Should be quicker.
1273 */
1274 for (i = first; i <= last; i++) {
1275 /* set command and sector address */
1276 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTERASE, kinfo->prog_base + bank->sectors[i].offset,
1277 0, 0, 0, 0, 0, 0, 0, 0, NULL);
1278
1279 if (result != ERROR_OK) {
1280 LOG_WARNING("erase sector %d failed", i);
1281 return ERROR_FLASH_OPERATION_FAILED;
1282 }
1283
1284 bank->sectors[i].is_erased = 1;
1285
1286 if (bank->base == 0
1287 && bank->sectors[i].offset <= FCF_ADDRESS
1288 && bank->sectors[i].offset + bank->sectors[i].size > FCF_ADDRESS + FCF_SIZE) {
1289 if (allow_fcf_writes) {
1290 LOG_WARNING("Flash Configuration Field erased, DO NOT reset or power off the device");
1291 LOG_WARNING("until correct FCF is programmed or MCU gets security lock.");
1292 } else {
1293 uint8_t fcf_buffer[FCF_SIZE];
1294
1295 kinetis_fill_fcf(bank, fcf_buffer);
1296 result = kinetis_write_inner(bank, fcf_buffer, FCF_ADDRESS, FCF_SIZE);
1297 if (result != ERROR_OK)
1298 LOG_WARNING("Flash Configuration Field write failed");
1299 bank->sectors[i].is_erased = 0;
1300 }
1301 }
1302 }
1303
1304 kinetis_invalidate_flash_cache(bank);
1305
1306 return ERROR_OK;
1307 }
1308
1309 static int kinetis_make_ram_ready(struct target *target)
1310 {
1311 int result;
1312 uint8_t ftfx_fcnfg;
1313
1314 /* check if ram ready */
1315 result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
1316 if (result != ERROR_OK)
1317 return result;
1318
1319 if (ftfx_fcnfg & (1 << 1))
1320 return ERROR_OK; /* ram ready */
1321
1322 /* make flex ram available */
1323 result = kinetis_ftfx_command(target, FTFx_CMD_SETFLEXRAM, 0x00ff0000,
1324 0, 0, 0, 0, 0, 0, 0, 0, NULL);
1325 if (result != ERROR_OK)
1326 return ERROR_FLASH_OPERATION_FAILED;
1327
1328 /* check again */
1329 result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
1330 if (result != ERROR_OK)
1331 return result;
1332
1333 if (ftfx_fcnfg & (1 << 1))
1334 return ERROR_OK; /* ram ready */
1335
1336 return ERROR_FLASH_OPERATION_FAILED;
1337 }
1338
1339
1340 static int kinetis_write_sections(struct flash_bank *bank, const uint8_t *buffer,
1341 uint32_t offset, uint32_t count)
1342 {
1343 int result = ERROR_OK;
1344 struct kinetis_flash_bank *kinfo = bank->driver_priv;
1345 uint8_t *buffer_aligned = NULL;
1346 /*
1347 * Kinetis uses different terms for the granularity of
1348 * sector writes, e.g. "phrase" or "128 bits". We use
1349 * the generic term "chunk". The largest possible
1350 * Kinetis "chunk" is 16 bytes (128 bits).
1351 */
1352 uint32_t prog_section_chunk_bytes = kinfo->sector_size >> 8;
1353 uint32_t prog_size_bytes = kinfo->max_flash_prog_size;
1354
1355 while (count > 0) {
1356 uint32_t size = prog_size_bytes - offset % prog_size_bytes;
1357 uint32_t align_begin = offset % prog_section_chunk_bytes;
1358 uint32_t align_end;
1359 uint32_t size_aligned;
1360 uint16_t chunk_count;
1361 uint8_t ftfx_fstat;
1362
1363 if (size > count)
1364 size = count;
1365
1366 align_end = (align_begin + size) % prog_section_chunk_bytes;
1367 if (align_end)
1368 align_end = prog_section_chunk_bytes - align_end;
1369
1370 size_aligned = align_begin + size + align_end;
1371 chunk_count = size_aligned / prog_section_chunk_bytes;
1372
1373 if (size != size_aligned) {
1374 /* aligned section: the first, the last or the only */
1375 if (!buffer_aligned)
1376 buffer_aligned = malloc(prog_size_bytes);
1377
1378 memset(buffer_aligned, 0xff, size_aligned);
1379 memcpy(buffer_aligned + align_begin, buffer, size);
1380
1381 result = target_write_memory(bank->target, FLEXRAM,
1382 4, size_aligned / 4, buffer_aligned);
1383
1384 LOG_DEBUG("section @ %08" PRIx32 " aligned begin %" PRIu32 ", end %" PRIu32,
1385 bank->base + offset, align_begin, align_end);
1386 } else
1387 result = target_write_memory(bank->target, FLEXRAM,
1388 4, size_aligned / 4, buffer);
1389
1390 LOG_DEBUG("write section @ %08" PRIx32 " with length %" PRIu32 " bytes",
1391 bank->base + offset, size);
1392
1393 if (result != ERROR_OK) {
1394 LOG_ERROR("target_write_memory failed");
1395 break;
1396 }
1397
1398 /* execute section-write command */
1399 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTWRITE,
1400 kinfo->prog_base + offset - align_begin,
1401 chunk_count>>8, chunk_count, 0, 0,
1402 0, 0, 0, 0, &ftfx_fstat);
1403
1404 if (result != ERROR_OK) {
1405 LOG_ERROR("Error writing section at %08" PRIx32, bank->base + offset);
1406 break;
1407 }
1408
1409 if (ftfx_fstat & 0x01)
1410 LOG_ERROR("Flash write error at %08" PRIx32, bank->base + offset);
1411
1412 buffer += size;
1413 offset += size;
1414 count -= size;
1415 }
1416
1417 free(buffer_aligned);
1418 return result;
1419 }
1420
1421
1422 static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
1423 uint32_t offset, uint32_t count)
1424 {
1425 int result, fallback = 0;
1426 struct kinetis_flash_bank *kinfo = bank->driver_priv;
1427
1428 if (!(kinfo->flash_support & FS_PROGRAM_SECTOR)) {
1429 /* fallback to longword write */
1430 fallback = 1;
1431 LOG_WARNING("This device supports Program Longword execution only.");
1432 } else {
1433 result = kinetis_make_ram_ready(bank->target);
1434 if (result != ERROR_OK) {
1435 fallback = 1;
1436 LOG_WARNING("FlexRAM not ready, fallback to slow longword write.");
1437 }
1438 }
1439
1440 LOG_DEBUG("flash write @08%" PRIx32, bank->base + offset);
1441
1442 if (fallback == 0) {
1443 /* program section command */
1444 kinetis_write_sections(bank, buffer, offset, count);
1445 }
1446 else if (kinfo->flash_support & FS_PROGRAM_LONGWORD) {
1447 /* program longword command, not supported in FTFE */
1448 uint8_t *new_buffer = NULL;
1449
1450 /* check word alignment */
1451 if (offset & 0x3) {
1452 LOG_ERROR("offset 0x%" PRIx32 " breaks the required alignment", offset);
1453 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
1454 }
1455
1456 if (count & 0x3) {
1457 uint32_t old_count = count;
1458 count = (old_count | 3) + 1;
1459 new_buffer = malloc(count);
1460 if (new_buffer == NULL) {
1461 LOG_ERROR("odd number of bytes to write and no memory "
1462 "for padding buffer");
1463 return ERROR_FAIL;
1464 }
1465 LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
1466 "and padding with 0xff", old_count, count);
1467 memset(new_buffer + old_count, 0xff, count - old_count);
1468 buffer = memcpy(new_buffer, buffer, old_count);
1469 }
1470
1471 uint32_t words_remaining = count / 4;
1472
1473 kinetis_disable_wdog(bank->target, kinfo->sim_sdid);
1474
1475 /* try using a block write */
1476 result = kinetis_write_block(bank, buffer, offset, words_remaining);
1477
1478 if (result == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1479 /* if block write failed (no sufficient working area),
1480 * we use normal (slow) single word accesses */
1481 LOG_WARNING("couldn't use block writes, falling back to single "
1482 "memory accesses");
1483
1484 while (words_remaining) {
1485 uint8_t ftfx_fstat;
1486
1487 LOG_DEBUG("write longword @ %08" PRIx32, (uint32_t)(bank->base + offset));
1488
1489 result = kinetis_ftfx_command(bank->target, FTFx_CMD_LWORDPROG, kinfo->prog_base + offset,
1490 buffer[3], buffer[2], buffer[1], buffer[0],
1491 0, 0, 0, 0, &ftfx_fstat);
1492
1493 if (result != ERROR_OK) {
1494 LOG_ERROR("Error writing longword at %08" PRIx32, bank->base + offset);
1495 break;
1496 }
1497
1498 if (ftfx_fstat & 0x01)
1499 LOG_ERROR("Flash write error at %08" PRIx32, bank->base + offset);
1500
1501 buffer += 4;
1502 offset += 4;
1503 words_remaining--;
1504 }
1505 }
1506 free(new_buffer);
1507 } else {
1508 LOG_ERROR("Flash write strategy not implemented");
1509 return ERROR_FLASH_OPERATION_FAILED;
1510 }
1511
1512 kinetis_invalidate_flash_cache(bank);
1513 return result;
1514 }
1515
1516
1517 static int kinetis_write(struct flash_bank *bank, const uint8_t *buffer,
1518 uint32_t offset, uint32_t count)
1519 {
1520 int result;
1521 bool set_fcf = false;
1522 int sect = 0;
1523
1524 result = kinetis_check_run_mode(bank->target);
1525 if (result != ERROR_OK)
1526 return result;
1527
1528 /* reset error flags */
1529 result = kinetis_ftfx_prepare(bank->target);
1530 if (result != ERROR_OK)
1531 return result;
1532
1533 if (bank->base == 0 && !allow_fcf_writes) {
1534 if (bank->sectors[1].offset <= FCF_ADDRESS)
1535 sect = 1; /* 1kb sector, FCF in 2nd sector */
1536
1537 if (offset < bank->sectors[sect].offset + bank->sectors[sect].size
1538 && offset + count > bank->sectors[sect].offset)
1539 set_fcf = true; /* write to any part of sector with FCF */
1540 }
1541
1542 if (set_fcf) {
1543 uint8_t fcf_buffer[FCF_SIZE];
1544 uint8_t fcf_current[FCF_SIZE];
1545
1546 kinetis_fill_fcf(bank, fcf_buffer);
1547
1548 if (offset < FCF_ADDRESS) {
1549 /* write part preceding FCF */
1550 result = kinetis_write_inner(bank, buffer, offset, FCF_ADDRESS - offset);
1551 if (result != ERROR_OK)
1552 return result;
1553 }
1554
1555 result = target_read_memory(bank->target, FCF_ADDRESS, 4, FCF_SIZE / 4, fcf_current);
1556 if (result == ERROR_OK && memcmp(fcf_current, fcf_buffer, FCF_SIZE) == 0)
1557 set_fcf = false;
1558
1559 if (set_fcf) {
1560 /* write FCF if differs from flash - eliminate multiple writes */
1561 result = kinetis_write_inner(bank, fcf_buffer, FCF_ADDRESS, FCF_SIZE);
1562 if (result != ERROR_OK)
1563 return result;
1564 }
1565
1566 LOG_WARNING("Flash Configuration Field written.");
1567 LOG_WARNING("Reset or power off the device to make settings effective.");
1568
1569 if (offset + count > FCF_ADDRESS + FCF_SIZE) {
1570 uint32_t delta = FCF_ADDRESS + FCF_SIZE - offset;
1571 /* write part after FCF */
1572 result = kinetis_write_inner(bank, buffer + delta, FCF_ADDRESS + FCF_SIZE, count - delta);
1573 }
1574 return result;
1575
1576 } else
1577 /* no FCF fiddling, normal write */
1578 return kinetis_write_inner(bank, buffer, offset, count);
1579 }
1580
1581
1582 static int kinetis_probe(struct flash_bank *bank)
1583 {
1584 int result, i;
1585 uint8_t fcfg1_nvmsize, fcfg1_pfsize, fcfg1_eesize, fcfg1_depart;
1586 uint8_t fcfg2_maxaddr0, fcfg2_pflsh, fcfg2_maxaddr1;
1587 uint32_t nvm_size = 0, pf_size = 0, df_size = 0, ee_size = 0;
1588 unsigned num_blocks = 0, num_pflash_blocks = 0, num_nvm_blocks = 0, first_nvm_bank = 0,
1589 pflash_sector_size_bytes = 0, nvm_sector_size_bytes = 0;
1590 struct target *target = bank->target;
1591 struct kinetis_flash_bank *kinfo = bank->driver_priv;
1592
1593 kinfo->probed = false;
1594
1595 result = target_read_u32(target, SIM_SDID, &kinfo->sim_sdid);
1596 if (result != ERROR_OK)
1597 return result;
1598
1599 if ((kinfo->sim_sdid & (~KINETIS_SDID_K_SERIES_MASK)) == 0) {
1600 /* older K-series MCU */
1601 uint32_t mcu_type = kinfo->sim_sdid & KINETIS_K_SDID_TYPE_MASK;
1602
1603 switch (mcu_type) {
1604 case KINETIS_K_SDID_K10_M50:
1605 case KINETIS_K_SDID_K20_M50:
1606 /* 1kB sectors */
1607 pflash_sector_size_bytes = 1<<10;
1608 nvm_sector_size_bytes = 1<<10;
1609 num_blocks = 2;
1610 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1611 break;
1612 case KINETIS_K_SDID_K10_M72:
1613 case KINETIS_K_SDID_K20_M72:
1614 case KINETIS_K_SDID_K30_M72:
1615 case KINETIS_K_SDID_K30_M100:
1616 case KINETIS_K_SDID_K40_M72:
1617 case KINETIS_K_SDID_K40_M100:
1618 case KINETIS_K_SDID_K50_M72:
1619 /* 2kB sectors, 1kB FlexNVM sectors */
1620 pflash_sector_size_bytes = 2<<10;
1621 nvm_sector_size_bytes = 1<<10;
1622 num_blocks = 2;
1623 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1624 kinfo->max_flash_prog_size = 1<<10;
1625 break;
1626 case KINETIS_K_SDID_K10_M100:
1627 case KINETIS_K_SDID_K20_M100:
1628 case KINETIS_K_SDID_K11:
1629 case KINETIS_K_SDID_K12:
1630 case KINETIS_K_SDID_K21_M50:
1631 case KINETIS_K_SDID_K22_M50:
1632 case KINETIS_K_SDID_K51_M72:
1633 case KINETIS_K_SDID_K53:
1634 case KINETIS_K_SDID_K60_M100:
1635 /* 2kB sectors */
1636 pflash_sector_size_bytes = 2<<10;
1637 nvm_sector_size_bytes = 2<<10;
1638 num_blocks = 2;
1639 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1640 break;
1641 case KINETIS_K_SDID_K21_M120:
1642 case KINETIS_K_SDID_K22_M120:
1643 /* 4kB sectors (MK21FN1M0, MK21FX512, MK22FN1M0, MK22FX512) */
1644 pflash_sector_size_bytes = 4<<10;
1645 kinfo->max_flash_prog_size = 1<<10;
1646 nvm_sector_size_bytes = 4<<10;
1647 num_blocks = 2;
1648 kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1649 break;
1650 case KINETIS_K_SDID_K10_M120:
1651 case KINETIS_K_SDID_K20_M120:
1652 case KINETIS_K_SDID_K60_M150:
1653 case KINETIS_K_SDID_K70_M150:
1654 /* 4kB sectors */
1655 pflash_sector_size_bytes = 4<<10;
1656 nvm_sector_size_bytes = 4<<10;
1657 num_blocks = 4;
1658 kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1659 break;
1660 default:
1661 LOG_ERROR("Unsupported K-family FAMID");
1662 }
1663 } else {
1664 /* Newer K-series or KL series MCU */
1665 switch (kinfo->sim_sdid & KINETIS_SDID_SERIESID_MASK) {
1666 case KINETIS_SDID_SERIESID_K:
1667 switch (kinfo->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
1668 case KINETIS_SDID_FAMILYID_K0X | KINETIS_SDID_SUBFAMID_KX2:
1669 /* K02FN64, K02FN128: FTFA, 2kB sectors */
1670 pflash_sector_size_bytes = 2<<10;
1671 num_blocks = 1;
1672 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_INVALIDATE_CACHE;
1673 break;
1674
1675 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX2: {
1676 /* MK24FN1M reports as K22, this should detect it (according to errata note 1N83J) */
1677 uint32_t sopt1;
1678 result = target_read_u32(target, SIM_SOPT1, &sopt1);
1679 if (result != ERROR_OK)
1680 return result;
1681
1682 if (((kinfo->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K24FN1M) &&
1683 ((sopt1 & KINETIS_SOPT1_RAMSIZE_MASK) == KINETIS_SOPT1_RAMSIZE_K24FN1M)) {
1684 /* MK24FN1M */
1685 pflash_sector_size_bytes = 4<<10;
1686 num_blocks = 2;
1687 kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1688 kinfo->max_flash_prog_size = 1<<10;
1689 break;
1690 }
1691 if ((kinfo->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN128
1692 || (kinfo->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN256
1693 || (kinfo->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN512) {
1694 /* K22 with new-style SDID - smaller pflash with FTFA, 2kB sectors */
1695 pflash_sector_size_bytes = 2<<10;
1696 /* autodetect 1 or 2 blocks */
1697 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_INVALIDATE_CACHE;
1698 break;
1699 }
1700 LOG_ERROR("Unsupported Kinetis K22 DIEID");
1701 break;
1702 }
1703 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX4:
1704 pflash_sector_size_bytes = 4<<10;
1705 if ((kinfo->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K24FN256) {
1706 /* K24FN256 - smaller pflash with FTFA */
1707 num_blocks = 1;
1708 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_INVALIDATE_CACHE;
1709 break;
1710 }
1711 /* K24FN1M without errata 7534 */
1712 num_blocks = 2;
1713 kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1714 kinfo->max_flash_prog_size = 1<<10;
1715 break;
1716
1717 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX3:
1718 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX1: /* errata 7534 - should be K63 */
1719 /* K63FN1M0 */
1720 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX4:
1721 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX2: /* errata 7534 - should be K64 */
1722 /* K64FN1M0, K64FX512 */
1723 pflash_sector_size_bytes = 4<<10;
1724 nvm_sector_size_bytes = 4<<10;
1725 kinfo->max_flash_prog_size = 1<<10;
1726 num_blocks = 2;
1727 kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1728 break;
1729
1730 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX6:
1731 /* K26FN2M0 */
1732 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX6:
1733 /* K66FN2M0, K66FX1M0 */
1734 pflash_sector_size_bytes = 4<<10;
1735 nvm_sector_size_bytes = 4<<10;
1736 kinfo->max_flash_prog_size = 1<<10;
1737 num_blocks = 4;
1738 kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1739 break;
1740 default:
1741 LOG_ERROR("Unsupported Kinetis FAMILYID SUBFAMID");
1742 }
1743 break;
1744
1745 case KINETIS_SDID_SERIESID_KL:
1746 /* KL-series */
1747 pflash_sector_size_bytes = 1<<10;
1748 nvm_sector_size_bytes = 1<<10;
1749 /* autodetect 1 or 2 blocks */
1750 kinfo->flash_support = FS_PROGRAM_LONGWORD;
1751 break;
1752
1753 case KINETIS_SDID_SERIESID_KV:
1754 /* KV-series */
1755 switch (kinfo->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
1756 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX0:
1757 /* KV10: FTFA, 1kB sectors */
1758 pflash_sector_size_bytes = 1<<10;
1759 num_blocks = 1;
1760 kinfo->flash_support = FS_PROGRAM_LONGWORD;
1761 break;
1762
1763 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX1:
1764 /* KV11: FTFA, 2kB sectors */
1765 pflash_sector_size_bytes = 2<<10;
1766 num_blocks = 1;
1767 kinfo->flash_support = FS_PROGRAM_LONGWORD;
1768 break;
1769
1770 case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX0:
1771 /* KV30: FTFA, 2kB sectors, 1 block */
1772 case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX1:
1773 /* KV31: FTFA, 2kB sectors, 2 blocks */
1774 pflash_sector_size_bytes = 2<<10;
1775 /* autodetect 1 or 2 blocks */
1776 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_INVALIDATE_CACHE;
1777 break;
1778
1779 case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX2:
1780 case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX4:
1781 case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX6:
1782 /* KV4x: FTFA, 4kB sectors */
1783 pflash_sector_size_bytes = 4<<10;
1784 num_blocks = 1;
1785 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_INVALIDATE_CACHE;
1786 break;
1787
1788 default:
1789 LOG_ERROR("Unsupported KV FAMILYID SUBFAMID");
1790 }
1791 break;
1792
1793 default:
1794 LOG_ERROR("Unsupported K-series");
1795 }
1796 }
1797
1798 if (pflash_sector_size_bytes == 0) {
1799 LOG_ERROR("MCU is unsupported, SDID 0x%08" PRIx32, kinfo->sim_sdid);
1800 return ERROR_FLASH_OPER_UNSUPPORTED;
1801 }
1802
1803 result = target_read_u32(target, SIM_FCFG1, &kinfo->sim_fcfg1);
1804 if (result != ERROR_OK)
1805 return result;
1806
1807 result = target_read_u32(target, SIM_FCFG2, &kinfo->sim_fcfg2);
1808 if (result != ERROR_OK)
1809 return result;
1810
1811 LOG_DEBUG("SDID: 0x%08" PRIX32 " FCFG1: 0x%08" PRIX32 " FCFG2: 0x%08" PRIX32, kinfo->sim_sdid,
1812 kinfo->sim_fcfg1, kinfo->sim_fcfg2);
1813
1814 fcfg1_nvmsize = (uint8_t)((kinfo->sim_fcfg1 >> 28) & 0x0f);
1815 fcfg1_pfsize = (uint8_t)((kinfo->sim_fcfg1 >> 24) & 0x0f);
1816 fcfg1_eesize = (uint8_t)((kinfo->sim_fcfg1 >> 16) & 0x0f);
1817 fcfg1_depart = (uint8_t)((kinfo->sim_fcfg1 >> 8) & 0x0f);
1818
1819 fcfg2_pflsh = (uint8_t)((kinfo->sim_fcfg2 >> 23) & 0x01);
1820 fcfg2_maxaddr0 = (uint8_t)((kinfo->sim_fcfg2 >> 24) & 0x7f);
1821 fcfg2_maxaddr1 = (uint8_t)((kinfo->sim_fcfg2 >> 16) & 0x7f);
1822
1823 if (num_blocks == 0)
1824 num_blocks = fcfg2_maxaddr1 ? 2 : 1;
1825 else if (fcfg2_maxaddr1 == 0 && num_blocks >= 2) {
1826 num_blocks = 1;
1827 LOG_WARNING("MAXADDR1 is zero, number of flash banks adjusted to 1");
1828 } else if (fcfg2_maxaddr1 != 0 && num_blocks == 1) {
1829 num_blocks = 2;
1830 LOG_WARNING("MAXADDR1 is non zero, number of flash banks adjusted to 2");
1831 }
1832
1833 /* when the PFLSH bit is set, there is no FlexNVM/FlexRAM */
1834 if (!fcfg2_pflsh) {
1835 switch (fcfg1_nvmsize) {
1836 case 0x03:
1837 case 0x05:
1838 case 0x07:
1839 case 0x09:
1840 case 0x0b:
1841 nvm_size = 1 << (14 + (fcfg1_nvmsize >> 1));
1842 break;
1843 case 0x0f:
1844 if (pflash_sector_size_bytes >= 4<<10)
1845 nvm_size = 512<<10;
1846 else
1847 /* K20_100 */
1848 nvm_size = 256<<10;
1849 break;
1850 default:
1851 nvm_size = 0;
1852 break;
1853 }
1854
1855 switch (fcfg1_eesize) {
1856 case 0x00:
1857 case 0x01:
1858 case 0x02:
1859 case 0x03:
1860 case 0x04:
1861 case 0x05:
1862 case 0x06:
1863 case 0x07:
1864 case 0x08:
1865 case 0x09:
1866 ee_size = (16 << (10 - fcfg1_eesize));
1867 break;
1868 default:
1869 ee_size = 0;
1870 break;
1871 }
1872
1873 switch (fcfg1_depart) {
1874 case 0x01:
1875 case 0x02:
1876 case 0x03:
1877 case 0x04:
1878 case 0x05:
1879 case 0x06:
1880 df_size = nvm_size - (4096 << fcfg1_depart);
1881 break;
1882 case 0x08:
1883 df_size = 0;
1884 break;
1885 case 0x09:
1886 case 0x0a:
1887 case 0x0b:
1888 case 0x0c:
1889 case 0x0d:
1890 df_size = 4096 << (fcfg1_depart & 0x7);
1891 break;
1892 default:
1893 df_size = nvm_size;
1894 break;
1895 }
1896 }
1897
1898 switch (fcfg1_pfsize) {
1899 case 0x03:
1900 case 0x05:
1901 case 0x07:
1902 case 0x09:
1903 case 0x0b:
1904 case 0x0d:
1905 pf_size = 1 << (14 + (fcfg1_pfsize >> 1));
1906 break;
1907 case 0x0f:
1908 /* a peculiar case: Freescale states different sizes for 0xf
1909 * K02P64M100SFARM 128 KB ... duplicate of code 0x7
1910 * K22P121M120SF8RM 256 KB ... duplicate of code 0x9
1911 * K22P121M120SF7RM 512 KB ... duplicate of code 0xb
1912 * K22P100M120SF5RM 1024 KB ... duplicate of code 0xd
1913 * K26P169M180SF5RM 2048 KB ... the only unique value
1914 * fcfg2_maxaddr0 seems to be the only clue to pf_size
1915 * Checking fcfg2_maxaddr0 later in this routine is pointless then
1916 */
1917 if (fcfg2_pflsh)
1918 pf_size = ((uint32_t)fcfg2_maxaddr0 << 13) * num_blocks;
1919 else
1920 pf_size = ((uint32_t)fcfg2_maxaddr0 << 13) * num_blocks / 2;
1921 if (pf_size != 2048<<10)
1922 LOG_WARNING("SIM_FCFG1 PFSIZE = 0xf: please check if pflash is %u KB", pf_size>>10);
1923
1924 break;
1925 default:
1926 pf_size = 0;
1927 break;
1928 }
1929
1930 LOG_DEBUG("FlexNVM: %" PRIu32 " PFlash: %" PRIu32 " FlexRAM: %" PRIu32 " PFLSH: %d",
1931 nvm_size, pf_size, ee_size, fcfg2_pflsh);
1932
1933 num_pflash_blocks = num_blocks / (2 - fcfg2_pflsh);
1934 first_nvm_bank = num_pflash_blocks;
1935 num_nvm_blocks = num_blocks - num_pflash_blocks;
1936
1937 LOG_DEBUG("%d blocks total: %d PFlash, %d FlexNVM",
1938 num_blocks, num_pflash_blocks, num_nvm_blocks);
1939
1940 LOG_INFO("Probing flash info for bank %d", bank->bank_number);
1941
1942 if ((unsigned)bank->bank_number < num_pflash_blocks) {
1943 /* pflash, banks start at address zero */
1944 kinfo->flash_class = FC_PFLASH;
1945 bank->size = (pf_size / num_pflash_blocks);
1946 bank->base = 0x00000000 + bank->size * bank->bank_number;
1947 kinfo->prog_base = bank->base;
1948 kinfo->sector_size = pflash_sector_size_bytes;
1949 /* pflash is divided into 32 protection areas for
1950 * parts with more than 32K of PFlash. For parts with
1951 * less the protection unit is set to 1024 bytes */
1952 kinfo->protection_size = MAX(pf_size / 32, 1024);
1953 bank->num_prot_blocks = 32 / num_pflash_blocks;
1954 kinfo->protection_block = bank->num_prot_blocks * bank->bank_number;
1955
1956 } else if ((unsigned)bank->bank_number < num_blocks) {
1957 /* nvm, banks start at address 0x10000000 */
1958 unsigned nvm_ord = bank->bank_number - first_nvm_bank;
1959 uint32_t limit;
1960
1961 kinfo->flash_class = FC_FLEX_NVM;
1962 bank->size = (nvm_size / num_nvm_blocks);
1963 bank->base = 0x10000000 + bank->size * nvm_ord;
1964 kinfo->prog_base = 0x00800000 + bank->size * nvm_ord;
1965 kinfo->sector_size = nvm_sector_size_bytes;
1966 if (df_size == 0) {
1967 kinfo->protection_size = 0;
1968 } else {
1969 for (i = df_size; ~i & 1; i >>= 1)
1970 ;
1971 if (i == 1)
1972 kinfo->protection_size = df_size / 8; /* data flash size = 2^^n */
1973 else
1974 kinfo->protection_size = nvm_size / 8; /* TODO: verify on SF1, not documented in RM */
1975 }
1976 bank->num_prot_blocks = 8 / num_nvm_blocks;
1977 kinfo->protection_block = bank->num_prot_blocks * nvm_ord;
1978
1979 /* EEPROM backup part of FlexNVM is not accessible, use df_size as a limit */
1980 if (df_size > bank->size * nvm_ord)
1981 limit = df_size - bank->size * nvm_ord;
1982 else
1983 limit = 0;
1984
1985 if (bank->size > limit) {
1986 bank->size = limit;
1987 LOG_DEBUG("FlexNVM bank %d limited to 0x%08" PRIx32 " due to active EEPROM backup",
1988 bank->bank_number, limit);
1989 }
1990
1991 } else if ((unsigned)bank->bank_number == num_blocks) {
1992 LOG_ERROR("FlexRAM support not yet implemented");
1993 return ERROR_FLASH_OPER_UNSUPPORTED;
1994 } else {
1995 LOG_ERROR("Cannot determine parameters for bank %d, only %d banks on device",
1996 bank->bank_number, num_blocks);
1997 return ERROR_FLASH_BANK_INVALID;
1998 }
1999
2000 if (bank->bank_number == 0 && ((uint32_t)fcfg2_maxaddr0 << 13) != bank->size)
2001 LOG_WARNING("MAXADDR0 0x%02" PRIx8 " check failed,"
2002 " please report to OpenOCD mailing list", fcfg2_maxaddr0);
2003 if (fcfg2_pflsh) {
2004 if (bank->bank_number == 1 && ((uint32_t)fcfg2_maxaddr1 << 13) != bank->size)
2005 LOG_WARNING("MAXADDR1 0x%02" PRIx8 " check failed,"
2006 " please report to OpenOCD mailing list", fcfg2_maxaddr1);
2007 } else {
2008 if ((unsigned)bank->bank_number == first_nvm_bank
2009 && ((uint32_t)fcfg2_maxaddr1 << 13) != df_size)
2010 LOG_WARNING("FlexNVM MAXADDR1 0x%02" PRIx8 " check failed,"
2011 " please report to OpenOCD mailing list", fcfg2_maxaddr1);
2012 }
2013
2014 if (bank->sectors) {
2015 free(bank->sectors);
2016 bank->sectors = NULL;
2017 }
2018 if (bank->prot_blocks) {
2019 free(bank->prot_blocks);
2020 bank->prot_blocks = NULL;
2021 }
2022
2023 if (kinfo->sector_size == 0) {
2024 LOG_ERROR("Unknown sector size for bank %d", bank->bank_number);
2025 return ERROR_FLASH_BANK_INVALID;
2026 }
2027
2028 if (kinfo->flash_support & FS_PROGRAM_SECTOR
2029 && kinfo->max_flash_prog_size == 0) {
2030 kinfo->max_flash_prog_size = kinfo->sector_size;
2031 /* Program section size is equal to sector size by default */
2032 }
2033
2034 bank->num_sectors = bank->size / kinfo->sector_size;
2035
2036 if (bank->num_sectors > 0) {
2037 /* FlexNVM bank can be used for EEPROM backup therefore zero sized */
2038 bank->sectors = alloc_block_array(0, kinfo->sector_size, bank->num_sectors);
2039 if (!bank->sectors)
2040 return ERROR_FAIL;
2041
2042 bank->prot_blocks = alloc_block_array(0, kinfo->protection_size, bank->num_prot_blocks);
2043 if (!bank->prot_blocks)
2044 return ERROR_FAIL;
2045
2046 } else {
2047 bank->num_prot_blocks = 0;
2048 }
2049
2050 kinfo->probed = true;
2051
2052 return ERROR_OK;
2053 }
2054
2055 static int kinetis_auto_probe(struct flash_bank *bank)
2056 {
2057 struct kinetis_flash_bank *kinfo = bank->driver_priv;
2058
2059 if (kinfo && kinfo->probed)
2060 return ERROR_OK;
2061
2062 return kinetis_probe(bank);
2063 }
2064
2065 static int kinetis_info(struct flash_bank *bank, char *buf, int buf_size)
2066 {
2067 const char *bank_class_names[] = {
2068 "(ANY)", "PFlash", "FlexNVM", "FlexRAM"
2069 };
2070
2071 struct kinetis_flash_bank *kinfo = bank->driver_priv;
2072
2073 (void) snprintf(buf, buf_size,
2074 "%s driver for %s flash bank %s at 0x%8.8" PRIx32 "",
2075 bank->driver->name, bank_class_names[kinfo->flash_class],
2076 bank->name, bank->base);
2077
2078 return ERROR_OK;
2079 }
2080
2081 static int kinetis_blank_check(struct flash_bank *bank)
2082 {
2083 struct kinetis_flash_bank *kinfo = bank->driver_priv;
2084 int result;
2085
2086 /* suprisingly blank check does not work in VLPR and HSRUN modes */
2087 result = kinetis_check_run_mode(bank->target);
2088 if (result != ERROR_OK)
2089 return result;
2090
2091 /* reset error flags */
2092 result = kinetis_ftfx_prepare(bank->target);
2093 if (result != ERROR_OK)
2094 return result;
2095
2096 if (kinfo->flash_class == FC_PFLASH || kinfo->flash_class == FC_FLEX_NVM) {
2097 bool block_dirty = false;
2098 uint8_t ftfx_fstat;
2099
2100 if (kinfo->flash_class == FC_FLEX_NVM) {
2101 uint8_t fcfg1_depart = (uint8_t)((kinfo->sim_fcfg1 >> 8) & 0x0f);
2102 /* block operation cannot be used on FlexNVM when EEPROM backup partition is set */
2103 if (fcfg1_depart != 0xf && fcfg1_depart != 0)
2104 block_dirty = true;
2105 }
2106
2107 if (!block_dirty) {
2108 /* check if whole bank is blank */
2109 result = kinetis_ftfx_command(bank->target, FTFx_CMD_BLOCKSTAT, kinfo->prog_base,
2110 0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
2111
2112 if (result != ERROR_OK || (ftfx_fstat & 0x01))
2113 block_dirty = true;
2114 }
2115
2116 if (block_dirty) {
2117 /* the whole bank is not erased, check sector-by-sector */
2118 int i;
2119 for (i = 0; i < bank->num_sectors; i++) {
2120 /* normal margin */
2121 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTSTAT,
2122 kinfo->prog_base + bank->sectors[i].offset,
2123 1, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
2124
2125 if (result == ERROR_OK) {
2126 bank->sectors[i].is_erased = !(ftfx_fstat & 0x01);
2127 } else {
2128 LOG_DEBUG("Ignoring errored PFlash sector blank-check");
2129 bank->sectors[i].is_erased = -1;
2130 }
2131 }
2132 } else {
2133 /* the whole bank is erased, update all sectors */
2134 int i;
2135 for (i = 0; i < bank->num_sectors; i++)
2136 bank->sectors[i].is_erased = 1;
2137 }
2138 } else {
2139 LOG_WARNING("kinetis_blank_check not supported yet for FlexRAM");
2140 return ERROR_FLASH_OPERATION_FAILED;
2141 }
2142
2143 return ERROR_OK;
2144 }
2145
2146
2147 COMMAND_HANDLER(kinetis_nvm_partition)
2148 {
2149 int result, i;
2150 unsigned long par, log2 = 0, ee1 = 0, ee2 = 0;
2151 enum { SHOW_INFO, DF_SIZE, EEBKP_SIZE } sz_type = SHOW_INFO;
2152 bool enable;
2153 uint8_t load_flex_ram = 1;
2154 uint8_t ee_size_code = 0x3f;
2155 uint8_t flex_nvm_partition_code = 0;
2156 uint8_t ee_split = 3;
2157 struct target *target = get_current_target(CMD_CTX);
2158 struct flash_bank *bank;
2159 struct kinetis_flash_bank *kinfo;
2160 uint32_t sim_fcfg1;
2161
2162 if (CMD_ARGC >= 2) {
2163 if (strcmp(CMD_ARGV[0], "dataflash") == 0)
2164 sz_type = DF_SIZE;
2165 else if (strcmp(CMD_ARGV[0], "eebkp") == 0)
2166 sz_type = EEBKP_SIZE;
2167
2168 par = strtoul(CMD_ARGV[1], NULL, 10);
2169 while (par >> (log2 + 3))
2170 log2++;
2171 }
2172 switch (sz_type) {
2173 case SHOW_INFO:
2174 result = target_read_u32(target, SIM_FCFG1, &sim_fcfg1);
2175 if (result != ERROR_OK)
2176 return result;
2177
2178 flex_nvm_partition_code = (uint8_t)((sim_fcfg1 >> 8) & 0x0f);
2179 switch (flex_nvm_partition_code) {
2180 case 0:
2181 command_print(CMD_CTX, "No EEPROM backup, data flash only");
2182 break;
2183 case 1:
2184 case 2:
2185 case 3:
2186 case 4:
2187 case 5:
2188 case 6:
2189 command_print(CMD_CTX, "EEPROM backup %d KB", 4 << flex_nvm_partition_code);
2190 break;
2191 case 8:
2192 command_print(CMD_CTX, "No data flash, EEPROM backup only");
2193 break;
2194 case 0x9:
2195 case 0xA:
2196 case 0xB:
2197 case 0xC:
2198 case 0xD:
2199 case 0xE:
2200 command_print(CMD_CTX, "data flash %d KB", 4 << (flex_nvm_partition_code & 7));
2201 break;
2202 case 0xf:
2203 command_print(CMD_CTX, "No EEPROM backup, data flash only (DEPART not set)");
2204 break;
2205 default:
2206 command_print(CMD_CTX, "Unsupported EEPROM backup size code 0x%02" PRIx8, flex_nvm_partition_code);
2207 }
2208 return ERROR_OK;
2209
2210 case DF_SIZE:
2211 flex_nvm_partition_code = 0x8 | log2;
2212 break;
2213
2214 case EEBKP_SIZE:
2215 flex_nvm_partition_code = log2;
2216 break;
2217 }
2218
2219 if (CMD_ARGC == 3)
2220 ee1 = ee2 = strtoul(CMD_ARGV[2], NULL, 10) / 2;
2221 else if (CMD_ARGC >= 4) {
2222 ee1 = strtoul(CMD_ARGV[2], NULL, 10);
2223 ee2 = strtoul(CMD_ARGV[3], NULL, 10);
2224 }
2225
2226 enable = ee1 + ee2 > 0;
2227 if (enable) {
2228 for (log2 = 2; ; log2++) {
2229 if (ee1 + ee2 == (16u << 10) >> log2)
2230 break;
2231 if (ee1 + ee2 > (16u << 10) >> log2 || log2 >= 9) {
2232 LOG_ERROR("Unsupported EEPROM size");
2233 return ERROR_FLASH_OPERATION_FAILED;
2234 }
2235 }
2236
2237 if (ee1 * 3 == ee2)
2238 ee_split = 1;
2239 else if (ee1 * 7 == ee2)
2240 ee_split = 0;
2241 else if (ee1 != ee2) {
2242 LOG_ERROR("Unsupported EEPROM sizes ratio");
2243 return ERROR_FLASH_OPERATION_FAILED;
2244 }
2245
2246 ee_size_code = log2 | ee_split << 4;
2247 }
2248
2249 if (CMD_ARGC >= 5)
2250 COMMAND_PARSE_ON_OFF(CMD_ARGV[4], enable);
2251 if (enable)
2252 load_flex_ram = 0;
2253
2254 LOG_INFO("DEPART 0x%" PRIx8 ", EEPROM size code 0x%" PRIx8,
2255 flex_nvm_partition_code, ee_size_code);
2256
2257 result = kinetis_check_run_mode(target);
2258 if (result != ERROR_OK)
2259 return result;
2260
2261 /* reset error flags */
2262 result = kinetis_ftfx_prepare(target);
2263 if (result != ERROR_OK)
2264 return result;
2265
2266 result = kinetis_ftfx_command(target, FTFx_CMD_PGMPART, load_flex_ram,
2267 ee_size_code, flex_nvm_partition_code, 0, 0,
2268 0, 0, 0, 0, NULL);
2269 if (result != ERROR_OK)
2270 return result;
2271
2272 command_print(CMD_CTX, "FlexNVM partition set. Please reset MCU.");
2273
2274 for (i = 1; i < 4; i++) {
2275 bank = get_flash_bank_by_num_noprobe(i);
2276 if (bank == NULL)
2277 break;
2278
2279 kinfo = bank->driver_priv;
2280 if (kinfo && kinfo->flash_class == FC_FLEX_NVM)
2281 kinfo->probed = false; /* re-probe before next use */
2282 }
2283
2284 command_print(CMD_CTX, "FlexNVM banks will be re-probed to set new data flash size.");
2285 return ERROR_OK;
2286 }
2287
2288 COMMAND_HANDLER(kinetis_fcf_source_handler)
2289 {
2290 if (CMD_ARGC > 1)
2291 return ERROR_COMMAND_SYNTAX_ERROR;
2292
2293 if (CMD_ARGC == 1) {
2294 if (strcmp(CMD_ARGV[0], "write") == 0)
2295 allow_fcf_writes = true;
2296 else if (strcmp(CMD_ARGV[0], "protection") == 0)
2297 allow_fcf_writes = false;
2298 else
2299 return ERROR_COMMAND_SYNTAX_ERROR;
2300 }
2301
2302 if (allow_fcf_writes) {
2303 command_print(CMD_CTX, "Arbitrary Flash Configuration Field writes enabled.");
2304 command_print(CMD_CTX, "Protection info writes to FCF disabled.");
2305 LOG_WARNING("BEWARE: incorrect flash configuration may permanently lock the device.");
2306 } else {
2307 command_print(CMD_CTX, "Protection info writes to Flash Configuration Field enabled.");
2308 command_print(CMD_CTX, "Arbitrary FCF writes disabled. Mode safe from unwanted locking of the device.");
2309 }
2310
2311 return ERROR_OK;
2312 }
2313
2314 COMMAND_HANDLER(kinetis_fopt_handler)
2315 {
2316 if (CMD_ARGC > 1)
2317 return ERROR_COMMAND_SYNTAX_ERROR;
2318
2319 if (CMD_ARGC == 1)
2320 fcf_fopt = (uint8_t)strtoul(CMD_ARGV[0], NULL, 0);
2321 else
2322 command_print(CMD_CTX, "FCF_FOPT 0x%02" PRIx8, fcf_fopt);
2323
2324 return ERROR_OK;
2325 }
2326
2327
2328 static const struct command_registration kinetis_security_command_handlers[] = {
2329 {
2330 .name = "check_security",
2331 .mode = COMMAND_EXEC,
2332 .help = "Check status of device security lock",
2333 .usage = "",
2334 .handler = kinetis_check_flash_security_status,
2335 },
2336 {
2337 .name = "halt",
2338 .mode = COMMAND_EXEC,
2339 .help = "Issue a halt via the MDM-AP",
2340 .usage = "",
2341 .handler = kinetis_mdm_halt,
2342 },
2343 {
2344 .name = "mass_erase",
2345 .mode = COMMAND_EXEC,
2346 .help = "Issue a complete flash erase via the MDM-AP",
2347 .usage = "",
2348 .handler = kinetis_mdm_mass_erase,
2349 },
2350 { .name = "reset",
2351 .mode = COMMAND_EXEC,
2352 .help = "Issue a reset via the MDM-AP",
2353 .usage = "",
2354 .handler = kinetis_mdm_reset,
2355 },
2356 COMMAND_REGISTRATION_DONE
2357 };
2358
2359 static const struct command_registration kinetis_exec_command_handlers[] = {
2360 {
2361 .name = "mdm",
2362 .mode = COMMAND_ANY,
2363 .help = "MDM-AP command group",
2364 .usage = "",
2365 .chain = kinetis_security_command_handlers,
2366 },
2367 {
2368 .name = "disable_wdog",
2369 .mode = COMMAND_EXEC,
2370 .help = "Disable the watchdog timer",
2371 .usage = "",
2372 .handler = kinetis_disable_wdog_handler,
2373 },
2374 {
2375 .name = "nvm_partition",
2376 .mode = COMMAND_EXEC,
2377 .help = "Show/set data flash or EEPROM backup size in kilobytes,"
2378 " set two EEPROM sizes in bytes and FlexRAM loading during reset",
2379 .usage = "('info'|'dataflash' size|'eebkp' size) [eesize1 eesize2] ['on'|'off']",
2380 .handler = kinetis_nvm_partition,
2381 },
2382 {
2383 .name = "fcf_source",
2384 .mode = COMMAND_EXEC,
2385 .help = "Use protection as a source for Flash Configuration Field or allow writing arbitrary values to the FCF"
2386 " Mode 'protection' is safe from unwanted locking of the device.",
2387 .usage = "['protection'|'write']",
2388 .handler = kinetis_fcf_source_handler,
2389 },
2390 {
2391 .name = "fopt",
2392 .mode = COMMAND_EXEC,
2393 .help = "FCF_FOPT value source in 'kinetis fcf_source protection' mode",
2394 .usage = "[num]",
2395 .handler = kinetis_fopt_handler,
2396 },
2397 COMMAND_REGISTRATION_DONE
2398 };
2399
2400 static const struct command_registration kinetis_command_handler[] = {
2401 {
2402 .name = "kinetis",
2403 .mode = COMMAND_ANY,
2404 .help = "Kinetis flash controller commands",
2405 .usage = "",
2406 .chain = kinetis_exec_command_handlers,
2407 },
2408 COMMAND_REGISTRATION_DONE
2409 };
2410
2411
2412
2413 struct flash_driver kinetis_flash = {
2414 .name = "kinetis",
2415 .commands = kinetis_command_handler,
2416 .flash_bank_command = kinetis_flash_bank_command,
2417 .erase = kinetis_erase,
2418 .protect = kinetis_protect,
2419 .write = kinetis_write,
2420 .read = default_flash_read,
2421 .probe = kinetis_probe,
2422 .auto_probe = kinetis_auto_probe,
2423 .erase_check = kinetis_blank_check,
2424 .protect_check = kinetis_protect_check,
2425 .info = kinetis_info,
2426 };
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