1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
11 * Copyright (C) 2013 by Roman Dmitrienko *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
35 #include <helper/binarybuffer.h>
36 #include <target/algorithm.h>
37 #include <target/armv7m.h>
38 #include <target/cortex_m.h>
40 /* keep family IDs in decimal */
41 #define EFM_FAMILY_ID_GECKO 71
42 #define EFM_FAMILY_ID_GIANT_GECKO 72
43 #define EFM_FAMILY_ID_TINY_GECKO 73
44 #define EFM_FAMILY_ID_LEOPARD_GECKO 74
46 #define EFM32_FLASH_ERASE_TMO 100
47 #define EFM32_FLASH_WDATAREADY_TMO 100
48 #define EFM32_FLASH_WRITE_TMO 100
50 /* size in bytes, not words; must fit all Gecko devices */
51 #define LOCKBITS_PAGE_SZ 512
53 #define EFM32_MSC_INFO_BASE 0x0fe00000
55 #define EFM32_MSC_USER_DATA EFM32_MSC_INFO_BASE
56 #define EFM32_MSC_LOCK_BITS (EFM32_MSC_INFO_BASE+0x4000)
57 #define EFM32_MSC_DEV_INFO (EFM32_MSC_INFO_BASE+0x8000)
59 /* PAGE_SIZE is only present in Leopard and Giant Gecko MCUs */
60 #define EFM32_MSC_DI_PAGE_SIZE (EFM32_MSC_DEV_INFO+0x1e7)
61 #define EFM32_MSC_DI_FLASH_SZ (EFM32_MSC_DEV_INFO+0x1f8)
62 #define EFM32_MSC_DI_RAM_SZ (EFM32_MSC_DEV_INFO+0x1fa)
63 #define EFM32_MSC_DI_PART_NUM (EFM32_MSC_DEV_INFO+0x1fc)
64 #define EFM32_MSC_DI_PART_FAMILY (EFM32_MSC_DEV_INFO+0x1fe)
65 #define EFM32_MSC_DI_PROD_REV (EFM32_MSC_DEV_INFO+0x1ff)
67 #define EFM32_MSC_REGBASE 0x400c0000
68 #define EFM32_MSC_WRITECTRL (EFM32_MSC_REGBASE+0x008)
69 #define EFM32_MSC_WRITECTRL_WREN_MASK 0x1
70 #define EFM32_MSC_WRITECMD (EFM32_MSC_REGBASE+0x00c)
71 #define EFM32_MSC_WRITECMD_LADDRIM_MASK 0x1
72 #define EFM32_MSC_WRITECMD_ERASEPAGE_MASK 0x2
73 #define EFM32_MSC_WRITECMD_WRITEONCE_MASK 0x8
74 #define EFM32_MSC_ADDRB (EFM32_MSC_REGBASE+0x010)
75 #define EFM32_MSC_WDATA (EFM32_MSC_REGBASE+0x018)
76 #define EFM32_MSC_STATUS (EFM32_MSC_REGBASE+0x01c)
77 #define EFM32_MSC_STATUS_BUSY_MASK 0x1
78 #define EFM32_MSC_STATUS_LOCKED_MASK 0x2
79 #define EFM32_MSC_STATUS_INVADDR_MASK 0x4
80 #define EFM32_MSC_STATUS_WDATAREADY_MASK 0x8
81 #define EFM32_MSC_STATUS_WORDTIMEOUT_MASK 0x10
82 #define EFM32_MSC_STATUS_ERASEABORTED_MASK 0x20
83 #define EFM32_MSC_LOCK (EFM32_MSC_REGBASE+0x03c)
84 #define EFM32_MSC_LOCK_LOCKKEY 0x1b71
86 struct efm32x_flash_bank
{
88 uint8_t lb_page
[LOCKBITS_PAGE_SZ
];
92 uint16_t flash_sz_kib
;
100 static int efm32x_write(struct flash_bank
*bank
, uint8_t *buffer
,
101 uint32_t offset
, uint32_t count
);
103 static int efm32x_get_flash_size(struct flash_bank
*bank
, uint16_t *flash_sz
)
105 return target_read_u16(bank
->target
, EFM32_MSC_DI_FLASH_SZ
, flash_sz
);
108 static int efm32x_get_ram_size(struct flash_bank
*bank
, uint16_t *ram_sz
)
110 return target_read_u16(bank
->target
, EFM32_MSC_DI_RAM_SZ
, ram_sz
);
113 static int efm32x_get_part_num(struct flash_bank
*bank
, uint16_t *pnum
)
115 return target_read_u16(bank
->target
, EFM32_MSC_DI_PART_NUM
, pnum
);
118 static int efm32x_get_part_family(struct flash_bank
*bank
, uint8_t *pfamily
)
120 return target_read_u8(bank
->target
, EFM32_MSC_DI_PART_FAMILY
, pfamily
);
123 static int efm32x_get_prod_rev(struct flash_bank
*bank
, uint8_t *prev
)
125 return target_read_u8(bank
->target
, EFM32_MSC_DI_PROD_REV
, prev
);
128 static int efm32x_read_info(struct flash_bank
*bank
,
129 struct efm32_info
*efm32_info
)
134 memset(efm32_info
, 0, sizeof(struct efm32_info
));
136 ret
= target_read_u32(bank
->target
, CPUID
, &cpuid
);
140 if (((cpuid
>> 4) & 0xfff) == 0xc23) {
141 /* Cortex M3 device */
143 LOG_ERROR("Target is not CortexM3");
147 ret
= efm32x_get_flash_size(bank
, &(efm32_info
->flash_sz_kib
));
151 ret
= efm32x_get_ram_size(bank
, &(efm32_info
->ram_sz_kib
));
155 ret
= efm32x_get_part_num(bank
, &(efm32_info
->part_num
));
159 ret
= efm32x_get_part_family(bank
, &(efm32_info
->part_family
));
163 ret
= efm32x_get_prod_rev(bank
, &(efm32_info
->prod_rev
));
167 if (EFM_FAMILY_ID_GECKO
== efm32_info
->part_family
||
168 EFM_FAMILY_ID_TINY_GECKO
== efm32_info
->part_family
)
169 efm32_info
->page_size
= 512;
170 else if (EFM_FAMILY_ID_GIANT_GECKO
== efm32_info
->part_family
||
171 EFM_FAMILY_ID_LEOPARD_GECKO
== efm32_info
->part_family
) {
174 ret
= target_read_u8(bank
->target
, EFM32_MSC_DI_PAGE_SIZE
,
179 efm32_info
->page_size
= (1 << ((pg_size
+10) & 0xff));
181 if ((2048 != efm32_info
->page_size
) &&
182 (4096 != efm32_info
->page_size
)) {
183 LOG_ERROR("Invalid page size %u", efm32_info
->page_size
);
187 LOG_ERROR("Unknown MCU family %d", efm32_info
->part_family
);
194 /* flash bank efm32 <base> <size> 0 0 <target#>
196 FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command
)
198 struct efm32x_flash_bank
*efm32x_info
;
201 return ERROR_COMMAND_SYNTAX_ERROR
;
203 efm32x_info
= malloc(sizeof(struct efm32x_flash_bank
));
205 bank
->driver_priv
= efm32x_info
;
206 efm32x_info
->probed
= 0;
207 memset(efm32x_info
->lb_page
, 0xff, LOCKBITS_PAGE_SZ
);
212 /* set or reset given bits in a register */
213 static int efm32x_set_reg_bits(struct flash_bank
*bank
, uint32_t reg
,
214 uint32_t bitmask
, int set
)
217 uint32_t reg_val
= 0;
219 ret
= target_read_u32(bank
->target
, reg
, ®_val
);
228 return target_write_u32(bank
->target
, reg
, reg_val
);
231 static int efm32x_set_wren(struct flash_bank
*bank
, int write_enable
)
233 return efm32x_set_reg_bits(bank
, EFM32_MSC_WRITECTRL
,
234 EFM32_MSC_WRITECTRL_WREN_MASK
, write_enable
);
237 static int efm32x_msc_lock(struct flash_bank
*bank
, int lock
)
239 return target_write_u32(bank
->target
, EFM32_MSC_LOCK
,
240 (lock
? 0 : EFM32_MSC_LOCK_LOCKKEY
));
243 static int efm32x_wait_status(struct flash_bank
*bank
, int timeout
,
244 uint32_t wait_mask
, int wait_for_set
)
250 ret
= target_read_u32(bank
->target
, EFM32_MSC_STATUS
, &status
);
254 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
256 if (((status
& wait_mask
) == 0) && (0 == wait_for_set
))
258 else if (((status
& wait_mask
) != 0) && wait_for_set
)
261 if (timeout
-- <= 0) {
262 LOG_ERROR("timed out waiting for MSC status");
269 if (status
& EFM32_MSC_STATUS_ERASEABORTED_MASK
)
270 LOG_WARNING("page erase was aborted");
275 static int efm32x_erase_page(struct flash_bank
*bank
, uint32_t addr
)
277 /* this function DOES NOT set WREN; must be set already */
278 /* 1. write address to ADDRB
280 3. check status (INVADDR, LOCKED)
282 5. wait until !STATUS_BUSY
287 LOG_DEBUG("erasing flash page at 0x%08x", addr
);
289 ret
= target_write_u32(bank
->target
, EFM32_MSC_ADDRB
, addr
);
293 ret
= efm32x_set_reg_bits(bank
, EFM32_MSC_WRITECMD
,
294 EFM32_MSC_WRITECMD_LADDRIM_MASK
, 1);
298 ret
= target_read_u32(bank
->target
, EFM32_MSC_STATUS
, &status
);
302 LOG_DEBUG("status 0x%x", status
);
304 if (status
& EFM32_MSC_STATUS_LOCKED_MASK
) {
305 LOG_ERROR("Page is locked");
307 } else if (status
& EFM32_MSC_STATUS_INVADDR_MASK
) {
308 LOG_ERROR("Invalid address 0x%x", addr
);
312 ret
= efm32x_set_reg_bits(bank
, EFM32_MSC_WRITECMD
,
313 EFM32_MSC_WRITECMD_ERASEPAGE_MASK
, 1);
317 return efm32x_wait_status(bank
, EFM32_FLASH_ERASE_TMO
,
318 EFM32_MSC_STATUS_BUSY_MASK
, 0);
321 static int efm32x_erase(struct flash_bank
*bank
, int first
, int last
)
323 struct target
*target
= bank
->target
;
327 if (TARGET_HALTED
!= target
->state
) {
328 LOG_ERROR("Target not halted");
329 return ERROR_TARGET_NOT_HALTED
;
332 efm32x_msc_lock(bank
, 0);
333 ret
= efm32x_set_wren(bank
, 1);
334 if (ERROR_OK
!= ret
) {
335 LOG_ERROR("Failed to enable MSC write");
339 for (i
= first
; i
<= last
; i
++) {
340 ret
= efm32x_erase_page(bank
, bank
->sectors
[i
].offset
);
342 LOG_ERROR("Failed to erase page %d", i
);
345 ret
= efm32x_set_wren(bank
, 0);
346 efm32x_msc_lock(bank
, 1);
351 static int efm32x_read_lock_data(struct flash_bank
*bank
)
353 struct efm32x_flash_bank
*efm32x_info
= bank
->driver_priv
;
354 struct target
*target
= bank
->target
;
357 uint32_t *ptr
= NULL
;
360 assert(!(bank
->num_sectors
& 0x1f));
362 data_size
= bank
->num_sectors
/ 8; /* number of data bytes */
363 data_size
/= 4; /* ...and data dwords */
365 ptr
= (uint32_t *)efm32x_info
->lb_page
;
367 for (i
= 0; i
< data_size
; i
++, ptr
++) {
368 ret
= target_read_u32(target
, EFM32_MSC_LOCK_BITS
+i
*4, ptr
);
369 if (ERROR_OK
!= ret
) {
370 LOG_ERROR("Failed to read PLW %d", i
);
375 /* also, read ULW, DLW and MLW */
378 ptr
= ((uint32_t *)efm32x_info
->lb_page
) + 126;
379 ret
= target_read_u32(target
, EFM32_MSC_LOCK_BITS
+126*4, ptr
);
380 if (ERROR_OK
!= ret
) {
381 LOG_ERROR("Failed to read ULW");
386 ptr
= ((uint32_t *)efm32x_info
->lb_page
) + 127;
387 ret
= target_read_u32(target
, EFM32_MSC_LOCK_BITS
+127*4, ptr
);
388 if (ERROR_OK
!= ret
) {
389 LOG_ERROR("Failed to read DLW");
393 /* MLW, word 125, present in GG and LG */
394 ptr
= ((uint32_t *)efm32x_info
->lb_page
) + 125;
395 ret
= target_read_u32(target
, EFM32_MSC_LOCK_BITS
+125*4, ptr
);
396 if (ERROR_OK
!= ret
) {
397 LOG_ERROR("Failed to read MLW");
404 static int efm32x_write_lock_data(struct flash_bank
*bank
)
406 struct efm32x_flash_bank
*efm32x_info
= bank
->driver_priv
;
409 ret
= efm32x_erase_page(bank
, EFM32_MSC_LOCK_BITS
);
410 if (ERROR_OK
!= ret
) {
411 LOG_ERROR("Failed to erase LB page");
415 return efm32x_write(bank
, efm32x_info
->lb_page
, EFM32_MSC_LOCK_BITS
,
419 static int efm32x_get_page_lock(struct flash_bank
*bank
, size_t page
)
421 struct efm32x_flash_bank
*efm32x_info
= bank
->driver_priv
;
422 uint32_t dw
= ((uint32_t *)efm32x_info
->lb_page
)[page
>> 5];
425 mask
= 1 << (page
& 0x1f);
427 return (dw
& mask
) ? 0 : 1;
430 static int efm32x_set_page_lock(struct flash_bank
*bank
, size_t page
, int set
)
432 struct efm32x_flash_bank
*efm32x_info
= bank
->driver_priv
;
433 uint32_t *dw
= &((uint32_t *)efm32x_info
->lb_page
)[page
>> 5];
436 mask
= 1 << (page
& 0x1f);
446 static int efm32x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
448 struct target
*target
= bank
->target
;
453 LOG_ERROR("Erase device data to reset page locks");
457 if (target
->state
!= TARGET_HALTED
) {
458 LOG_ERROR("Target not halted");
459 return ERROR_TARGET_NOT_HALTED
;
462 for (i
= first
; i
<= last
; i
++) {
463 ret
= efm32x_set_page_lock(bank
, i
, set
);
464 if (ERROR_OK
!= ret
) {
465 LOG_ERROR("Failed to set lock on page %d", i
);
470 ret
= efm32x_write_lock_data(bank
);
471 if (ERROR_OK
!= ret
) {
472 LOG_ERROR("Failed to write LB page");
479 static int efm32x_write_block(struct flash_bank
*bank
, uint8_t *buf
,
480 uint32_t offset
, uint32_t count
)
482 struct target
*target
= bank
->target
;
483 uint32_t buffer_size
= 16384;
484 struct working_area
*write_algorithm
;
485 struct working_area
*source
;
486 uint32_t address
= bank
->base
+ offset
;
487 struct reg_param reg_params
[5];
488 struct armv7m_algorithm armv7m_info
;
491 /* see contrib/loaders/flash/efm32.S for src */
492 static const uint8_t efm32x_flash_write_code
[] = {
493 /* #define EFM32_MSC_WRITECTRL_OFFSET 0x008 */
494 /* #define EFM32_MSC_WRITECMD_OFFSET 0x00c */
495 /* #define EFM32_MSC_ADDRB_OFFSET 0x010 */
496 /* #define EFM32_MSC_WDATA_OFFSET 0x018 */
497 /* #define EFM32_MSC_STATUS_OFFSET 0x01c */
498 /* #define EFM32_MSC_LOCK_OFFSET 0x03c */
500 0x15, 0x4e, /* ldr r6, =#0x1b71 */
501 0xc6, 0x63, /* str r6, [r0, #EFM32_MSC_LOCK_OFFSET] */
502 0x01, 0x26, /* movs r6, #1 */
503 0x86, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET] */
506 0x16, 0x68, /* ldr r6, [r2, #0] */
507 0x00, 0x2e, /* cmp r6, #0 */
508 0x22, 0xd0, /* beq exit */
509 0x55, 0x68, /* ldr r5, [r2, #4] */
510 0xb5, 0x42, /* cmp r5, r6 */
511 0xf9, 0xd0, /* beq wait_fifo */
513 0x04, 0x61, /* str r4, [r0, #EFM32_MSC_ADDRB_OFFSET] */
514 0x01, 0x26, /* movs r6, #1 */
515 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
516 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
517 0x06, 0x27, /* movs r7, #6 */
518 0x3e, 0x42, /* tst r6, r7 */
519 0x16, 0xd1, /* bne error */
521 /* wait_wdataready: */
522 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
523 0x08, 0x27, /* movs r7, #8 */
524 0x3e, 0x42, /* tst r6, r7 */
525 0xfb, 0xd0, /* beq wait_wdataready */
527 0x2e, 0x68, /* ldr r6, [r5] */
528 0x86, 0x61, /* str r6, [r0, #EFM32_MSC_WDATA_OFFSET] */
529 0x08, 0x26, /* movs r6, #8 */
530 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
532 0x04, 0x35, /* adds r5, #4 */
533 0x04, 0x34, /* adds r4, #4 */
536 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
537 0x01, 0x27, /* movs r7, #1 */
538 0x3e, 0x42, /* tst r6, r7 */
539 0xfb, 0xd1, /* bne busy */
541 0x9d, 0x42, /* cmp r5, r3 */
542 0x01, 0xd3, /* bcc no_wrap */
543 0x15, 0x46, /* mov r5, r2 */
544 0x08, 0x35, /* adds r5, #8 */
547 0x55, 0x60, /* str r5, [r2, #4] */
548 0x01, 0x39, /* subs r1, r1, #1 */
549 0x00, 0x29, /* cmp r1, #0 */
550 0x02, 0xd0, /* beq exit */
551 0xdb, 0xe7, /* b wait_fifo */
554 0x00, 0x20, /* movs r0, #0 */
555 0x50, 0x60, /* str r0, [r2, #4] */
558 0x30, 0x46, /* mov r0, r6 */
559 0x00, 0xbe, /* bkpt #0 */
562 0x71, 0x1b, 0x00, 0x00
565 /* flash write code */
566 if (target_alloc_working_area(target
, sizeof(efm32x_flash_write_code
),
567 &write_algorithm
) != ERROR_OK
) {
568 LOG_WARNING("no working area available, can't do block memory writes");
569 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
572 ret
= target_write_buffer(target
, write_algorithm
->address
,
573 sizeof(efm32x_flash_write_code
),
574 (uint8_t *)efm32x_flash_write_code
);
579 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
581 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
582 if (buffer_size
<= 256) {
583 /* we already allocated the writing code, but failed to get a
584 * buffer, free the algorithm */
585 target_free_working_area(target
, write_algorithm
);
587 LOG_WARNING("no large enough working area available, can't do block memory writes");
588 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
592 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* flash base (in), status (out) */
593 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* count (word-32bit) */
594 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer start */
595 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* buffer end */
596 init_reg_param(®_params
[4], "r4", 32, PARAM_IN_OUT
); /* target address */
598 buf_set_u32(reg_params
[0].value
, 0, 32, EFM32_MSC_REGBASE
);
599 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
600 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
);
601 buf_set_u32(reg_params
[3].value
, 0, 32, source
->address
+ source
->size
);
602 buf_set_u32(reg_params
[4].value
, 0, 32, address
);
604 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
605 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
607 ret
= target_run_flash_async_algorithm(target
, buf
, count
, 4,
610 source
->address
, source
->size
,
611 write_algorithm
->address
, 0,
614 if (ret
== ERROR_FLASH_OPERATION_FAILED
) {
615 LOG_ERROR("flash write failed at address 0x%"PRIx32
,
616 buf_get_u32(reg_params
[4].value
, 0, 32));
618 if (buf_get_u32(reg_params
[0].value
, 0, 32) &
619 EFM32_MSC_STATUS_LOCKED_MASK
) {
620 LOG_ERROR("flash memory write protected");
623 if (buf_get_u32(reg_params
[0].value
, 0, 32) &
624 EFM32_MSC_STATUS_INVADDR_MASK
) {
625 LOG_ERROR("invalid flash memory write address");
629 target_free_working_area(target
, source
);
630 target_free_working_area(target
, write_algorithm
);
632 destroy_reg_param(®_params
[0]);
633 destroy_reg_param(®_params
[1]);
634 destroy_reg_param(®_params
[2]);
635 destroy_reg_param(®_params
[3]);
636 destroy_reg_param(®_params
[4]);
641 static int efm32x_write_word(struct flash_bank
*bank
, uint32_t addr
,
644 /* this function DOES NOT set WREN; must be set already */
645 /* 1. write address to ADDRB
647 3. check status (INVADDR, LOCKED)
648 4. wait for WDATAREADY
649 5. write data to WDATA
650 6. write WRITECMD_WRITEONCE to WRITECMD
651 7. wait until !STATUS_BUSY
654 /* FIXME: EFM32G ref states (7.3.2) that writes should be
655 * performed twice per dword */
660 /* if not called, GDB errors will be reported during large writes */
663 ret
= target_write_u32(bank
->target
, EFM32_MSC_ADDRB
, addr
);
667 ret
= efm32x_set_reg_bits(bank
, EFM32_MSC_WRITECMD
,
668 EFM32_MSC_WRITECMD_LADDRIM_MASK
, 1);
672 ret
= target_read_u32(bank
->target
, EFM32_MSC_STATUS
, &status
);
676 LOG_DEBUG("status 0x%x", status
);
678 if (status
& EFM32_MSC_STATUS_LOCKED_MASK
) {
679 LOG_ERROR("Page is locked");
681 } else if (status
& EFM32_MSC_STATUS_INVADDR_MASK
) {
682 LOG_ERROR("Invalid address 0x%x", addr
);
686 ret
= efm32x_wait_status(bank
, EFM32_FLASH_WDATAREADY_TMO
,
687 EFM32_MSC_STATUS_WDATAREADY_MASK
, 1);
688 if (ERROR_OK
!= ret
) {
689 LOG_ERROR("Wait for WDATAREADY failed");
693 ret
= target_write_u32(bank
->target
, EFM32_MSC_WDATA
, val
);
694 if (ERROR_OK
!= ret
) {
695 LOG_ERROR("WDATA write failed");
699 ret
= target_write_u32(bank
->target
, EFM32_MSC_WRITECMD
,
700 EFM32_MSC_WRITECMD_WRITEONCE_MASK
);
701 if (ERROR_OK
!= ret
) {
702 LOG_ERROR("WRITECMD write failed");
706 ret
= efm32x_wait_status(bank
, EFM32_FLASH_WRITE_TMO
,
707 EFM32_MSC_STATUS_BUSY_MASK
, 0);
708 if (ERROR_OK
!= ret
) {
709 LOG_ERROR("Wait for BUSY failed");
716 static int efm32x_write(struct flash_bank
*bank
, uint8_t *buffer
,
717 uint32_t offset
, uint32_t count
)
719 struct target
*target
= bank
->target
;
720 uint8_t *new_buffer
= NULL
;
722 if (target
->state
!= TARGET_HALTED
) {
723 LOG_ERROR("Target not halted");
724 return ERROR_TARGET_NOT_HALTED
;
728 LOG_ERROR("offset 0x%" PRIx32
" breaks required 4-byte "
729 "alignment", offset
);
730 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
734 uint32_t old_count
= count
;
735 count
= (old_count
| 3) + 1;
736 new_buffer
= malloc(count
);
737 if (new_buffer
== NULL
) {
738 LOG_ERROR("odd number of bytes to write and no memory "
739 "for padding buffer");
742 LOG_INFO("odd number of bytes to write (%d), extending to %d "
743 "and padding with 0xff", old_count
, count
);
744 memset(buffer
, 0xff, count
);
745 buffer
= memcpy(new_buffer
, buffer
, old_count
);
748 uint32_t words_remaining
= count
/ 4;
751 /* unlock flash registers */
752 efm32x_msc_lock(bank
, 0);
753 retval
= efm32x_set_wren(bank
, 1);
754 if (retval
!= ERROR_OK
)
757 /* try using a block write */
758 retval
= efm32x_write_block(bank
, buffer
, offset
, words_remaining
);
760 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
761 /* if block write failed (no sufficient working area),
762 * we use normal (slow) single word accesses */
763 LOG_WARNING("couldn't use block writes, falling back to single "
766 while (words_remaining
> 0) {
768 memcpy(&value
, buffer
, sizeof(uint32_t));
770 retval
= efm32x_write_word(bank
, offset
, value
);
771 if (retval
!= ERROR_OK
)
772 goto reset_pg_and_lock
;
781 retval2
= efm32x_set_wren(bank
, 0);
782 efm32x_msc_lock(bank
, 1);
783 if (retval
== ERROR_OK
)
793 static int efm32x_probe(struct flash_bank
*bank
)
795 struct efm32x_flash_bank
*efm32x_info
= bank
->driver_priv
;
796 struct efm32_info efm32_mcu_info
;
799 uint32_t base_address
= 0x00000000;
801 efm32x_info
->probed
= 0;
802 memset(efm32x_info
->lb_page
, 0xff, LOCKBITS_PAGE_SZ
);
804 ret
= efm32x_read_info(bank
, &efm32_mcu_info
);
808 switch (efm32_mcu_info
.part_family
) {
809 case EFM_FAMILY_ID_GECKO
:
810 LOG_INFO("Gecko MCU detected");
812 case EFM_FAMILY_ID_GIANT_GECKO
:
813 LOG_INFO("Giant Gecko MCU detected");
815 case EFM_FAMILY_ID_TINY_GECKO
:
816 LOG_INFO("Tiny Gecko MCU detected");
818 case EFM_FAMILY_ID_LEOPARD_GECKO
:
819 LOG_INFO("Leopard Gecko MCU detected");
822 LOG_ERROR("Unsupported MCU family %d",
823 efm32_mcu_info
.part_family
);
827 LOG_INFO("flash size = %dkbytes", efm32_mcu_info
.flash_sz_kib
);
828 LOG_INFO("flash page size = %dbytes", efm32_mcu_info
.page_size
);
830 assert(0 != efm32_mcu_info
.page_size
);
832 int num_pages
= efm32_mcu_info
.flash_sz_kib
* 1024 /
833 efm32_mcu_info
.page_size
;
835 assert(num_pages
> 0);
839 bank
->sectors
= NULL
;
842 bank
->base
= base_address
;
843 bank
->size
= (num_pages
* efm32_mcu_info
.page_size
);
844 bank
->num_sectors
= num_pages
;
846 ret
= efm32x_read_lock_data(bank
);
847 if (ERROR_OK
!= ret
) {
848 LOG_ERROR("Failed to read LB data");
852 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_pages
);
854 for (i
= 0; i
< num_pages
; i
++) {
855 bank
->sectors
[i
].offset
= i
* efm32_mcu_info
.page_size
;
856 bank
->sectors
[i
].size
= efm32_mcu_info
.page_size
;
857 bank
->sectors
[i
].is_erased
= -1;
858 bank
->sectors
[i
].is_protected
= 1;
861 efm32x_info
->probed
= 1;
866 static int efm32x_auto_probe(struct flash_bank
*bank
)
868 struct efm32x_flash_bank
*efm32x_info
= bank
->driver_priv
;
869 if (efm32x_info
->probed
)
871 return efm32x_probe(bank
);
874 static int efm32x_protect_check(struct flash_bank
*bank
)
876 struct target
*target
= bank
->target
;
880 if (target
->state
!= TARGET_HALTED
) {
881 LOG_ERROR("Target not halted");
882 return ERROR_TARGET_NOT_HALTED
;
885 ret
= efm32x_read_lock_data(bank
);
886 if (ERROR_OK
!= ret
) {
887 LOG_ERROR("Failed to read LB data");
891 assert(NULL
!= bank
->sectors
);
893 for (i
= 0; i
< bank
->num_sectors
; i
++)
894 bank
->sectors
[i
].is_protected
= efm32x_get_page_lock(bank
, i
);
899 static int get_efm32x_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
901 struct efm32_info info
;
905 ret
= efm32x_read_info(bank
, &info
);
906 if (ERROR_OK
!= ret
) {
907 LOG_ERROR("Failed to read EFM32 info");
911 printed
= snprintf(buf
, buf_size
, "EFM32 ");
916 return ERROR_BUF_TOO_SMALL
;
918 switch (info
.part_family
) {
919 case EFM_FAMILY_ID_GECKO
:
920 printed
= snprintf(buf
, buf_size
, "Gecko");
922 case EFM_FAMILY_ID_GIANT_GECKO
:
923 printed
= snprintf(buf
, buf_size
, "Giant Gecko");
925 case EFM_FAMILY_ID_TINY_GECKO
:
926 printed
= snprintf(buf
, buf_size
, "Tiny Gecko");
928 case EFM_FAMILY_ID_LEOPARD_GECKO
:
929 printed
= snprintf(buf
, buf_size
, "Leopard Gecko");
937 return ERROR_BUF_TOO_SMALL
;
939 printed
= snprintf(buf
, buf_size
, " - Rev: %d", info
.prod_rev
);
944 return ERROR_BUF_TOO_SMALL
;
949 static const struct command_registration efm32x_exec_command_handlers
[] = {
950 COMMAND_REGISTRATION_DONE
953 static const struct command_registration efm32x_command_handlers
[] = {
957 .help
= "efm32 flash command group",
959 .chain
= efm32x_exec_command_handlers
,
961 COMMAND_REGISTRATION_DONE
964 struct flash_driver efm32_flash
= {
966 .commands
= efm32x_command_handlers
,
967 .flash_bank_command
= efm32x_flash_bank_command
,
968 .erase
= efm32x_erase
,
969 .protect
= efm32x_protect
,
970 .write
= efm32x_write
,
971 .read
= default_flash_read
,
972 .probe
= efm32x_probe
,
973 .auto_probe
= efm32x_auto_probe
,
974 .erase_check
= default_flash_blank_check
,
975 .protect_check
= efm32x_protect_check
,
976 .info
= get_efm32x_info
,
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