Code Review / openocd.git / blob
? search:


9cdc325735f0c63349ebb3fe33dba72341ea09d8
[openocd.git] / src / flash / nor / efm32.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 * *
11 * Copyright (C) 2013 by Roman Dmitrienko *
12 * me@iamroman.org *
13 * *
14 * Copyright (C) 2014 Nemui Trinomius *
15 * nemuisan_kawausogasuki@live.jp *
16 * *
17 * This program is free software; you can redistribute it and/or modify *
18 * it under the terms of the GNU General Public License as published by *
19 * the Free Software Foundation; either version 2 of the License, or *
20 * (at your option) any later version. *
21 * *
22 * This program is distributed in the hope that it will be useful, *
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
25 * GNU General Public License for more details. *
26 * *
27 * You should have received a copy of the GNU General Public License *
28 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
29 ***************************************************************************/
30
31 #ifdef HAVE_CONFIG_H
32 #include "config.h"
33 #endif
34
35 #include "imp.h"
36 #include <helper/binarybuffer.h>
37 #include <target/algorithm.h>
38 #include <target/armv7m.h>
39 #include <target/cortex_m.h>
40
41 #define EFM_FAMILY_ID_GIANT_GECKO 72
42 #define EFM_FAMILY_ID_LEOPARD_GECKO 74
43
44 #define EFM32_FLASH_ERASE_TMO 100
45 #define EFM32_FLASH_WDATAREADY_TMO 100
46 #define EFM32_FLASH_WRITE_TMO 100
47
48 /* size in bytes, not words; must fit all Gecko devices */
49 #define LOCKBITS_PAGE_SZ 512
50
51 #define EFM32_MSC_INFO_BASE 0x0fe00000
52
53 #define EFM32_MSC_USER_DATA EFM32_MSC_INFO_BASE
54 #define EFM32_MSC_LOCK_BITS (EFM32_MSC_INFO_BASE+0x4000)
55 #define EFM32_MSC_DEV_INFO (EFM32_MSC_INFO_BASE+0x8000)
56
57 /* PAGE_SIZE is not present in Zero, Happy and the original Gecko MCU */
58 #define EFM32_MSC_DI_PAGE_SIZE (EFM32_MSC_DEV_INFO+0x1e7)
59 #define EFM32_MSC_DI_FLASH_SZ (EFM32_MSC_DEV_INFO+0x1f8)
60 #define EFM32_MSC_DI_RAM_SZ (EFM32_MSC_DEV_INFO+0x1fa)
61 #define EFM32_MSC_DI_PART_NUM (EFM32_MSC_DEV_INFO+0x1fc)
62 #define EFM32_MSC_DI_PART_FAMILY (EFM32_MSC_DEV_INFO+0x1fe)
63 #define EFM32_MSC_DI_PROD_REV (EFM32_MSC_DEV_INFO+0x1ff)
64
65 #define EFM32_MSC_REGBASE 0x400c0000
66 #define EFM32_MSC_REGBASE_SERIES1 0x400e0000
67 #define EFM32_MSC_REG_WRITECTRL 0x008
68 #define EFM32_MSC_WRITECTRL_WREN_MASK 0x1
69 #define EFM32_MSC_REG_WRITECMD 0x00c
70 #define EFM32_MSC_WRITECMD_LADDRIM_MASK 0x1
71 #define EFM32_MSC_WRITECMD_ERASEPAGE_MASK 0x2
72 #define EFM32_MSC_WRITECMD_WRITEONCE_MASK 0x8
73 #define EFM32_MSC_REG_ADDRB 0x010
74 #define EFM32_MSC_REG_WDATA 0x018
75 #define EFM32_MSC_REG_STATUS 0x01c
76 #define EFM32_MSC_STATUS_BUSY_MASK 0x1
77 #define EFM32_MSC_STATUS_LOCKED_MASK 0x2
78 #define EFM32_MSC_STATUS_INVADDR_MASK 0x4
79 #define EFM32_MSC_STATUS_WDATAREADY_MASK 0x8
80 #define EFM32_MSC_STATUS_WORDTIMEOUT_MASK 0x10
81 #define EFM32_MSC_STATUS_ERASEABORTED_MASK 0x20
82 #define EFM32_MSC_REG_LOCK 0x03c
83 #define EFM32_MSC_REG_LOCK_SERIES1 0x040
84 #define EFM32_MSC_LOCK_LOCKKEY 0x1b71
85
86 struct efm32_family_data {
87 int family_id;
88 const char *name;
89
90 /* EFM32 series (EFM32LG995F is the "old" series 0, while EFR32MG12P132
91 is the "new" series 1). Determines location of MSC registers. */
92 int series;
93
94 /* Page size in bytes, or 0 to read from EFM32_MSC_DI_PAGE_SIZE */
95 int page_size;
96
97 /* MSC register base address, or 0 to use default */
98 uint32_t msc_regbase;
99 };
100
101 struct efm32x_flash_bank {
102 int probed;
103 uint32_t lb_page[LOCKBITS_PAGE_SZ/4];
104 uint32_t reg_base;
105 uint32_t reg_lock;
106 };
107
108 struct efm32_info {
109 const struct efm32_family_data *family_data;
110 uint16_t flash_sz_kib;
111 uint16_t ram_sz_kib;
112 uint16_t part_num;
113 uint8_t part_family;
114 uint8_t prod_rev;
115 uint16_t page_size;
116 };
117
118 static const struct efm32_family_data efm32_families[] = {
119 { 16, "EFR32MG1P Mighty", .series = 1 },
120 { 17, "EFR32MG1B Mighty", .series = 1 },
121 { 18, "EFR32MG1V Mighty", .series = 1 },
122 { 19, "EFR32MG1P Blue", .series = 1 },
123 { 20, "EFR32MG1B Blue", .series = 1 },
124 { 21, "EFR32MG1V Blue", .series = 1 },
125 { 25, "EFR32FG1P Flex", .series = 1 },
126 { 26, "EFR32FG1B Flex", .series = 1 },
127 { 27, "EFR32FG1V Flex", .series = 1 },
128 { 28, "EFR32MG2P Mighty", .series = 1 },
129 { 29, "EFR32MG2B Mighty", .series = 1 },
130 { 30, "EFR32MG2V Mighty", .series = 1 },
131 { 31, "EFR32BG12P Blue", .series = 1 },
132 { 32, "EFR32BG12B Blue", .series = 1 },
133 { 33, "EFR32BG12V Blue", .series = 1 },
134 { 37, "EFR32FG12P Flex", .series = 1 },
135 { 38, "EFR32FG12B Flex", .series = 1 },
136 { 39, "EFR32FG12V Flex", .series = 1 },
137 { 40, "EFR32MG13P Mighty", .series = 1 },
138 { 41, "EFR32MG13B Mighty", .series = 1 },
139 { 42, "EFR32MG13V Mighty", .series = 1 },
140 { 43, "EFR32BG13P Blue", .series = 1 },
141 { 44, "EFR32BG13B Blue", .series = 1 },
142 { 45, "EFR32BG13V Blue", .series = 1 },
143 { 46, "EFR32ZG13P Zen", .series = 1 },
144 { 49, "EFR32FG13P Flex", .series = 1 },
145 { 50, "EFR32FG13B Flex", .series = 1 },
146 { 51, "EFR32FG13V Flex", .series = 1 },
147 { 52, "EFR32MG14P Mighty", .series = 1 },
148 { 53, "EFR32MG14B Mighty", .series = 1 },
149 { 54, "EFR32MG14V Mighty", .series = 1 },
150 { 55, "EFR32BG14P Blue", .series = 1 },
151 { 56, "EFR32BG14B Blue", .series = 1 },
152 { 57, "EFR32BG14V Blue", .series = 1 },
153 { 58, "EFR32ZG14P Zen", .series = 1 },
154 { 61, "EFR32FG14P Flex", .series = 1 },
155 { 62, "EFR32FG14B Flex", .series = 1 },
156 { 63, "EFR32FG14V Flex", .series = 1 },
157 { 71, "EFM32G", .series = 0, .page_size = 512 },
158 { 72, "EFM32GG Giant", .series = 0 },
159 { 73, "EFM32TG Tiny", .series = 0, .page_size = 512 },
160 { 74, "EFM32LG Leopard", .series = 0 },
161 { 75, "EFM32WG Wonder", .series = 0 },
162 { 76, "EFM32ZG Zero", .series = 0, .page_size = 1024 },
163 { 77, "EFM32HG Happy", .series = 0, .page_size = 1024 },
164 { 81, "EFM32PG1B Pearl", .series = 1 },
165 { 83, "EFM32JG1B Jade", .series = 1 },
166 { 85, "EFM32PG12B Pearl", .series = 1 },
167 { 87, "EFM32JG12B Jade", .series = 1 },
168 { 89, "EFM32PG13B Pearl", .series = 1 },
169 { 91, "EFM32JG13B Jade", .series = 1 },
170 { 100, "EFM32GG11B Giant", .series = 1, .msc_regbase = 0x40000000 },
171 { 103, "EFM32TG11B Tiny", .series = 1, .msc_regbase = 0x40000000 },
172 { 106, "EFM32GG12B Giant", .series = 1, .msc_regbase = 0x40000000 },
173 { 120, "EZR32WG Wonder", .series = 0 },
174 { 121, "EZR32LG Leopard", .series = 0 },
175 { 122, "EZR32HG Happy", .series = 0, .page_size = 1024 },
176 };
177
178
179 static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
180 uint32_t offset, uint32_t count);
181
182 static int efm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_sz)
183 {
184 return target_read_u16(bank->target, EFM32_MSC_DI_FLASH_SZ, flash_sz);
185 }
186
187 static int efm32x_get_ram_size(struct flash_bank *bank, uint16_t *ram_sz)
188 {
189 return target_read_u16(bank->target, EFM32_MSC_DI_RAM_SZ, ram_sz);
190 }
191
192 static int efm32x_get_part_num(struct flash_bank *bank, uint16_t *pnum)
193 {
194 return target_read_u16(bank->target, EFM32_MSC_DI_PART_NUM, pnum);
195 }
196
197 static int efm32x_get_part_family(struct flash_bank *bank, uint8_t *pfamily)
198 {
199 return target_read_u8(bank->target, EFM32_MSC_DI_PART_FAMILY, pfamily);
200 }
201
202 static int efm32x_get_prod_rev(struct flash_bank *bank, uint8_t *prev)
203 {
204 return target_read_u8(bank->target, EFM32_MSC_DI_PROD_REV, prev);
205 }
206
207 static int efm32x_read_reg_u32(struct flash_bank *bank, target_addr_t offset,
208 uint32_t *value)
209 {
210 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
211 uint32_t base = efm32x_info->reg_base;
212
213 return target_read_u32(bank->target, base + offset, value);
214 }
215
216 static int efm32x_write_reg_u32(struct flash_bank *bank, target_addr_t offset,
217 uint32_t value)
218 {
219 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
220 uint32_t base = efm32x_info->reg_base;
221
222 return target_write_u32(bank->target, base + offset, value);
223 }
224
225 static int efm32x_read_info(struct flash_bank *bank,
226 struct efm32_info *efm32_info)
227 {
228 int ret;
229 uint32_t cpuid = 0;
230 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
231
232 memset(efm32_info, 0, sizeof(struct efm32_info));
233
234 ret = target_read_u32(bank->target, CPUID, &cpuid);
235 if (ERROR_OK != ret)
236 return ret;
237
238 if (((cpuid >> 4) & 0xfff) == 0xc23) {
239 /* Cortex-M3 device */
240 } else if (((cpuid >> 4) & 0xfff) == 0xc24) {
241 /* Cortex-M4 device (WONDER GECKO) */
242 } else if (((cpuid >> 4) & 0xfff) == 0xc60) {
243 /* Cortex-M0+ device */
244 } else {
245 LOG_ERROR("Target is not Cortex-Mx Device");
246 return ERROR_FAIL;
247 }
248
249 ret = efm32x_get_flash_size(bank, &(efm32_info->flash_sz_kib));
250 if (ERROR_OK != ret)
251 return ret;
252
253 ret = efm32x_get_ram_size(bank, &(efm32_info->ram_sz_kib));
254 if (ERROR_OK != ret)
255 return ret;
256
257 ret = efm32x_get_part_num(bank, &(efm32_info->part_num));
258 if (ERROR_OK != ret)
259 return ret;
260
261 ret = efm32x_get_part_family(bank, &(efm32_info->part_family));
262 if (ERROR_OK != ret)
263 return ret;
264
265 ret = efm32x_get_prod_rev(bank, &(efm32_info->prod_rev));
266 if (ERROR_OK != ret)
267 return ret;
268
269 for (size_t i = 0; i < ARRAY_SIZE(efm32_families); i++) {
270 if (efm32_families[i].family_id == efm32_info->part_family)
271 efm32_info->family_data = &efm32_families[i];
272 }
273
274 if (efm32_info->family_data == NULL) {
275 LOG_ERROR("Unknown MCU family %d", efm32_info->part_family);
276 return ERROR_FAIL;
277 }
278
279 switch (efm32_info->family_data->series) {
280 case 0:
281 efm32x_info->reg_base = EFM32_MSC_REGBASE;
282 efm32x_info->reg_lock = EFM32_MSC_REG_LOCK;
283 break;
284 case 1:
285 efm32x_info->reg_base = EFM32_MSC_REGBASE_SERIES1;
286 efm32x_info->reg_lock = EFM32_MSC_REG_LOCK_SERIES1;
287 break;
288 }
289
290 if (efm32_info->family_data->msc_regbase != 0)
291 efm32x_info->reg_base = efm32_info->family_data->msc_regbase;
292
293 if (efm32_info->family_data->page_size != 0) {
294 efm32_info->page_size = efm32_info->family_data->page_size;
295 } else {
296 uint8_t pg_size = 0;
297 ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
298 &pg_size);
299 if (ERROR_OK != ret)
300 return ret;
301
302 efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
303
304 if (efm32_info->part_family == EFM_FAMILY_ID_GIANT_GECKO ||
305 efm32_info->part_family == EFM_FAMILY_ID_LEOPARD_GECKO) {
306 /* Giant or Leopard Gecko */
307 if (efm32_info->prod_rev < 18) {
308 /* EFM32 GG/LG errata: MEM_INFO_PAGE_SIZE is invalid
309 for MCUs with PROD_REV < 18 */
310 if (efm32_info->flash_sz_kib < 512)
311 efm32_info->page_size = 2048;
312 else
313 efm32_info->page_size = 4096;
314 }
315 }
316
317 if ((efm32_info->page_size != 2048) &&
318 (efm32_info->page_size != 4096)) {
319 LOG_ERROR("Invalid page size %u", efm32_info->page_size);
320 return ERROR_FAIL;
321 }
322 }
323
324 return ERROR_OK;
325 }
326
327 /*
328 * Helper to create a human friendly string describing a part
329 */
330 static int efm32x_decode_info(struct efm32_info *info, char *buf, int buf_size)
331 {
332 int printed = 0;
333 printed = snprintf(buf, buf_size, "%s Gecko, rev %d",
334 info->family_data->name, info->prod_rev);
335
336 if (printed >= buf_size)
337 return ERROR_BUF_TOO_SMALL;
338
339 return ERROR_OK;
340 }
341
342 /* flash bank efm32 <base> <size> 0 0 <target#>
343 */
344 FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
345 {
346 struct efm32x_flash_bank *efm32x_info;
347
348 if (CMD_ARGC < 6)
349 return ERROR_COMMAND_SYNTAX_ERROR;
350
351 efm32x_info = malloc(sizeof(struct efm32x_flash_bank));
352
353 bank->driver_priv = efm32x_info;
354 efm32x_info->probed = 0;
355 memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
356
357 return ERROR_OK;
358 }
359
360 /* set or reset given bits in a register */
361 static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
362 uint32_t bitmask, int set)
363 {
364 int ret = 0;
365 uint32_t reg_val = 0;
366
367 ret = efm32x_read_reg_u32(bank, reg, &reg_val);
368 if (ERROR_OK != ret)
369 return ret;
370
371 if (set)
372 reg_val |= bitmask;
373 else
374 reg_val &= ~bitmask;
375
376 return efm32x_write_reg_u32(bank, reg, reg_val);
377 }
378
379 static int efm32x_set_wren(struct flash_bank *bank, int write_enable)
380 {
381 return efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECTRL,
382 EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
383 }
384
385 static int efm32x_msc_lock(struct flash_bank *bank, int lock)
386 {
387 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
388 return efm32x_write_reg_u32(bank, efm32x_info->reg_lock,
389 (lock ? 0 : EFM32_MSC_LOCK_LOCKKEY));
390 }
391
392 static int efm32x_wait_status(struct flash_bank *bank, int timeout,
393 uint32_t wait_mask, int wait_for_set)
394 {
395 int ret = 0;
396 uint32_t status = 0;
397
398 while (1) {
399 ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
400 if (ERROR_OK != ret)
401 break;
402
403 LOG_DEBUG("status: 0x%" PRIx32 "", status);
404
405 if (((status & wait_mask) == 0) && (0 == wait_for_set))
406 break;
407 else if (((status & wait_mask) != 0) && wait_for_set)
408 break;
409
410 if (timeout-- <= 0) {
411 LOG_ERROR("timed out waiting for MSC status");
412 return ERROR_FAIL;
413 }
414
415 alive_sleep(1);
416 }
417
418 if (status & EFM32_MSC_STATUS_ERASEABORTED_MASK)
419 LOG_WARNING("page erase was aborted");
420
421 return ret;
422 }
423
424 static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
425 {
426 /* this function DOES NOT set WREN; must be set already */
427 /* 1. write address to ADDRB
428 2. write LADDRIM
429 3. check status (INVADDR, LOCKED)
430 4. write ERASEPAGE
431 5. wait until !STATUS_BUSY
432 */
433 int ret = 0;
434 uint32_t status = 0;
435 addr += bank->base;
436 LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
437
438 ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
439 if (ERROR_OK != ret)
440 return ret;
441
442 ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
443 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
444 if (ERROR_OK != ret)
445 return ret;
446
447 ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
448 if (ERROR_OK != ret)
449 return ret;
450
451 LOG_DEBUG("status 0x%" PRIx32, status);
452
453 if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
454 LOG_ERROR("Page is locked");
455 return ERROR_FAIL;
456 } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
457 LOG_ERROR("Invalid address 0x%" PRIx32, addr);
458 return ERROR_FAIL;
459 }
460
461 ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
462 EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
463 if (ERROR_OK != ret)
464 return ret;
465
466 return efm32x_wait_status(bank, EFM32_FLASH_ERASE_TMO,
467 EFM32_MSC_STATUS_BUSY_MASK, 0);
468 }
469
470 static int efm32x_erase(struct flash_bank *bank, int first, int last)
471 {
472 struct target *target = bank->target;
473 int i = 0;
474 int ret = 0;
475
476 if (TARGET_HALTED != target->state) {
477 LOG_ERROR("Target not halted");
478 return ERROR_TARGET_NOT_HALTED;
479 }
480
481 efm32x_msc_lock(bank, 0);
482 ret = efm32x_set_wren(bank, 1);
483 if (ERROR_OK != ret) {
484 LOG_ERROR("Failed to enable MSC write");
485 return ret;
486 }
487
488 for (i = first; i <= last; i++) {
489 ret = efm32x_erase_page(bank, bank->sectors[i].offset);
490 if (ERROR_OK != ret)
491 LOG_ERROR("Failed to erase page %d", i);
492 }
493
494 ret = efm32x_set_wren(bank, 0);
495 efm32x_msc_lock(bank, 1);
496
497 return ret;
498 }
499
500 static int efm32x_read_lock_data(struct flash_bank *bank)
501 {
502 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
503 struct target *target = bank->target;
504 int i = 0;
505 int data_size = 0;
506 uint32_t *ptr = NULL;
507 int ret = 0;
508
509 assert(bank->num_sectors > 0);
510
511 /* calculate the number of 32-bit words to read (one lock bit per sector) */
512 data_size = (bank->num_sectors + 31) / 32;
513
514 ptr = efm32x_info->lb_page;
515
516 for (i = 0; i < data_size; i++, ptr++) {
517 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+i*4, ptr);
518 if (ERROR_OK != ret) {
519 LOG_ERROR("Failed to read PLW %d", i);
520 return ret;
521 }
522 }
523
524 /* also, read ULW, DLW, MLW, ALW and CLW words */
525
526 /* ULW, word 126 */
527 ptr = efm32x_info->lb_page + 126;
528 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+126*4, ptr);
529 if (ERROR_OK != ret) {
530 LOG_ERROR("Failed to read ULW");
531 return ret;
532 }
533
534 /* DLW, word 127 */
535 ptr = efm32x_info->lb_page + 127;
536 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+127*4, ptr);
537 if (ERROR_OK != ret) {
538 LOG_ERROR("Failed to read DLW");
539 return ret;
540 }
541
542 /* MLW, word 125, present in GG, LG, PG, JG, EFR32 */
543 ptr = efm32x_info->lb_page + 125;
544 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+125*4, ptr);
545 if (ERROR_OK != ret) {
546 LOG_ERROR("Failed to read MLW");
547 return ret;
548 }
549
550 /* ALW, word 124, present in GG, LG, PG, JG, EFR32 */
551 ptr = efm32x_info->lb_page + 124;
552 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+124*4, ptr);
553 if (ERROR_OK != ret) {
554 LOG_ERROR("Failed to read ALW");
555 return ret;
556 }
557
558 /* CLW1, word 123, present in EFR32 */
559 ptr = efm32x_info->lb_page + 123;
560 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+123*4, ptr);
561 if (ERROR_OK != ret) {
562 LOG_ERROR("Failed to read CLW1");
563 return ret;
564 }
565
566 /* CLW0, word 122, present in GG, LG, PG, JG, EFR32 */
567 ptr = efm32x_info->lb_page + 122;
568 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+122*4, ptr);
569 if (ERROR_OK != ret) {
570 LOG_ERROR("Failed to read CLW0");
571 return ret;
572 }
573
574 return ERROR_OK;
575 }
576
577 static int efm32x_write_lock_data(struct flash_bank *bank)
578 {
579 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
580 int ret = 0;
581
582 ret = efm32x_erase_page(bank, EFM32_MSC_LOCK_BITS);
583 if (ERROR_OK != ret) {
584 LOG_ERROR("Failed to erase LB page");
585 return ret;
586 }
587
588 return efm32x_write(bank, (uint8_t *)efm32x_info->lb_page, EFM32_MSC_LOCK_BITS,
589 LOCKBITS_PAGE_SZ);
590 }
591
592 static int efm32x_get_page_lock(struct flash_bank *bank, size_t page)
593 {
594 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
595 uint32_t dw = efm32x_info->lb_page[page >> 5];
596 uint32_t mask = 0;
597
598 mask = 1 << (page & 0x1f);
599
600 return (dw & mask) ? 0 : 1;
601 }
602
603 static int efm32x_set_page_lock(struct flash_bank *bank, size_t page, int set)
604 {
605 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
606 uint32_t *dw = &efm32x_info->lb_page[page >> 5];
607 uint32_t mask = 0;
608
609 mask = 1 << (page & 0x1f);
610
611 if (!set)
612 *dw |= mask;
613 else
614 *dw &= ~mask;
615
616 return ERROR_OK;
617 }
618
619 static int efm32x_protect(struct flash_bank *bank, int set, int first, int last)
620 {
621 struct target *target = bank->target;
622 int i = 0;
623 int ret = 0;
624
625 if (!set) {
626 LOG_ERROR("Erase device data to reset page locks");
627 return ERROR_FAIL;
628 }
629
630 if (target->state != TARGET_HALTED) {
631 LOG_ERROR("Target not halted");
632 return ERROR_TARGET_NOT_HALTED;
633 }
634
635 for (i = first; i <= last; i++) {
636 ret = efm32x_set_page_lock(bank, i, set);
637 if (ERROR_OK != ret) {
638 LOG_ERROR("Failed to set lock on page %d", i);
639 return ret;
640 }
641 }
642
643 ret = efm32x_write_lock_data(bank);
644 if (ERROR_OK != ret) {
645 LOG_ERROR("Failed to write LB page");
646 return ret;
647 }
648
649 return ERROR_OK;
650 }
651
652 static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
653 uint32_t offset, uint32_t count)
654 {
655 struct target *target = bank->target;
656 uint32_t buffer_size = 16384;
657 struct working_area *write_algorithm;
658 struct working_area *source;
659 uint32_t address = bank->base + offset;
660 struct reg_param reg_params[5];
661 struct armv7m_algorithm armv7m_info;
662 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
663 int ret = ERROR_OK;
664
665 /* see contrib/loaders/flash/efm32.S for src */
666 static const uint8_t efm32x_flash_write_code[] = {
667 /* #define EFM32_MSC_WRITECTRL_OFFSET 0x008 */
668 /* #define EFM32_MSC_WRITECMD_OFFSET 0x00c */
669 /* #define EFM32_MSC_ADDRB_OFFSET 0x010 */
670 /* #define EFM32_MSC_WDATA_OFFSET 0x018 */
671 /* #define EFM32_MSC_STATUS_OFFSET 0x01c */
672
673 0x01, 0x26, /* movs r6, #1 */
674 0x86, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET] */
675
676 /* wait_fifo: */
677 0x16, 0x68, /* ldr r6, [r2, #0] */
678 0x00, 0x2e, /* cmp r6, #0 */
679 0x22, 0xd0, /* beq exit */
680 0x55, 0x68, /* ldr r5, [r2, #4] */
681 0xb5, 0x42, /* cmp r5, r6 */
682 0xf9, 0xd0, /* beq wait_fifo */
683
684 0x04, 0x61, /* str r4, [r0, #EFM32_MSC_ADDRB_OFFSET] */
685 0x01, 0x26, /* movs r6, #1 */
686 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
687 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
688 0x06, 0x27, /* movs r7, #6 */
689 0x3e, 0x42, /* tst r6, r7 */
690 0x16, 0xd1, /* bne error */
691
692 /* wait_wdataready: */
693 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
694 0x08, 0x27, /* movs r7, #8 */
695 0x3e, 0x42, /* tst r6, r7 */
696 0xfb, 0xd0, /* beq wait_wdataready */
697
698 0x2e, 0x68, /* ldr r6, [r5] */
699 0x86, 0x61, /* str r6, [r0, #EFM32_MSC_WDATA_OFFSET] */
700 0x08, 0x26, /* movs r6, #8 */
701 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
702
703 0x04, 0x35, /* adds r5, #4 */
704 0x04, 0x34, /* adds r4, #4 */
705
706 /* busy: */
707 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
708 0x01, 0x27, /* movs r7, #1 */
709 0x3e, 0x42, /* tst r6, r7 */
710 0xfb, 0xd1, /* bne busy */
711
712 0x9d, 0x42, /* cmp r5, r3 */
713 0x01, 0xd3, /* bcc no_wrap */
714 0x15, 0x46, /* mov r5, r2 */
715 0x08, 0x35, /* adds r5, #8 */
716
717 /* no_wrap: */
718 0x55, 0x60, /* str r5, [r2, #4] */
719 0x01, 0x39, /* subs r1, r1, #1 */
720 0x00, 0x29, /* cmp r1, #0 */
721 0x02, 0xd0, /* beq exit */
722 0xdb, 0xe7, /* b wait_fifo */
723
724 /* error: */
725 0x00, 0x20, /* movs r0, #0 */
726 0x50, 0x60, /* str r0, [r2, #4] */
727
728 /* exit: */
729 0x30, 0x46, /* mov r0, r6 */
730 0x00, 0xbe, /* bkpt #0 */
731 };
732
733
734 /* flash write code */
735 if (target_alloc_working_area(target, sizeof(efm32x_flash_write_code),
736 &write_algorithm) != ERROR_OK) {
737 LOG_WARNING("no working area available, can't do block memory writes");
738 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
739 }
740
741 ret = target_write_buffer(target, write_algorithm->address,
742 sizeof(efm32x_flash_write_code), efm32x_flash_write_code);
743 if (ret != ERROR_OK)
744 return ret;
745
746 /* memory buffer */
747 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
748 buffer_size /= 2;
749 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
750 if (buffer_size <= 256) {
751 /* we already allocated the writing code, but failed to get a
752 * buffer, free the algorithm */
753 target_free_working_area(target, write_algorithm);
754
755 LOG_WARNING("no large enough working area available, can't do block memory writes");
756 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
757 }
758 }
759
760 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
761 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (word-32bit) */
762 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
763 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
764 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
765
766 buf_set_u32(reg_params[0].value, 0, 32, efm32x_info->reg_base);
767 buf_set_u32(reg_params[1].value, 0, 32, count);
768 buf_set_u32(reg_params[2].value, 0, 32, source->address);
769 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
770 buf_set_u32(reg_params[4].value, 0, 32, address);
771
772 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
773 armv7m_info.core_mode = ARM_MODE_THREAD;
774
775 ret = target_run_flash_async_algorithm(target, buf, count, 4,
776 0, NULL,
777 5, reg_params,
778 source->address, source->size,
779 write_algorithm->address, 0,
780 &armv7m_info);
781
782 if (ret == ERROR_FLASH_OPERATION_FAILED) {
783 LOG_ERROR("flash write failed at address 0x%"PRIx32,
784 buf_get_u32(reg_params[4].value, 0, 32));
785
786 if (buf_get_u32(reg_params[0].value, 0, 32) &
787 EFM32_MSC_STATUS_LOCKED_MASK) {
788 LOG_ERROR("flash memory write protected");
789 }
790
791 if (buf_get_u32(reg_params[0].value, 0, 32) &
792 EFM32_MSC_STATUS_INVADDR_MASK) {
793 LOG_ERROR("invalid flash memory write address");
794 }
795 }
796
797 target_free_working_area(target, source);
798 target_free_working_area(target, write_algorithm);
799
800 destroy_reg_param(&reg_params[0]);
801 destroy_reg_param(&reg_params[1]);
802 destroy_reg_param(&reg_params[2]);
803 destroy_reg_param(&reg_params[3]);
804 destroy_reg_param(&reg_params[4]);
805
806 return ret;
807 }
808
809 static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
810 uint32_t val)
811 {
812 /* this function DOES NOT set WREN; must be set already */
813 /* 1. write address to ADDRB
814 2. write LADDRIM
815 3. check status (INVADDR, LOCKED)
816 4. wait for WDATAREADY
817 5. write data to WDATA
818 6. write WRITECMD_WRITEONCE to WRITECMD
819 7. wait until !STATUS_BUSY
820 */
821
822 /* FIXME: EFM32G ref states (7.3.2) that writes should be
823 * performed twice per dword */
824
825 int ret = 0;
826 uint32_t status = 0;
827
828 /* if not called, GDB errors will be reported during large writes */
829 keep_alive();
830
831 ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
832 if (ERROR_OK != ret)
833 return ret;
834
835 ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
836 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
837 if (ERROR_OK != ret)
838 return ret;
839
840 ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
841 if (ERROR_OK != ret)
842 return ret;
843
844 LOG_DEBUG("status 0x%" PRIx32, status);
845
846 if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
847 LOG_ERROR("Page is locked");
848 return ERROR_FAIL;
849 } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
850 LOG_ERROR("Invalid address 0x%" PRIx32, addr);
851 return ERROR_FAIL;
852 }
853
854 ret = efm32x_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
855 EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
856 if (ERROR_OK != ret) {
857 LOG_ERROR("Wait for WDATAREADY failed");
858 return ret;
859 }
860
861 ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WDATA, val);
862 if (ERROR_OK != ret) {
863 LOG_ERROR("WDATA write failed");
864 return ret;
865 }
866
867 ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WRITECMD,
868 EFM32_MSC_WRITECMD_WRITEONCE_MASK);
869 if (ERROR_OK != ret) {
870 LOG_ERROR("WRITECMD write failed");
871 return ret;
872 }
873
874 ret = efm32x_wait_status(bank, EFM32_FLASH_WRITE_TMO,
875 EFM32_MSC_STATUS_BUSY_MASK, 0);
876 if (ERROR_OK != ret) {
877 LOG_ERROR("Wait for BUSY failed");
878 return ret;
879 }
880
881 return ERROR_OK;
882 }
883
884 static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
885 uint32_t offset, uint32_t count)
886 {
887 struct target *target = bank->target;
888 uint8_t *new_buffer = NULL;
889
890 if (target->state != TARGET_HALTED) {
891 LOG_ERROR("Target not halted");
892 return ERROR_TARGET_NOT_HALTED;
893 }
894
895 if (offset & 0x3) {
896 LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte "
897 "alignment", offset);
898 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
899 }
900
901 if (count & 0x3) {
902 uint32_t old_count = count;
903 count = (old_count | 3) + 1;
904 new_buffer = malloc(count);
905 if (new_buffer == NULL) {
906 LOG_ERROR("odd number of bytes to write and no memory "
907 "for padding buffer");
908 return ERROR_FAIL;
909 }
910 LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
911 "and padding with 0xff", old_count, count);
912 memset(new_buffer, 0xff, count);
913 buffer = memcpy(new_buffer, buffer, old_count);
914 }
915
916 uint32_t words_remaining = count / 4;
917 int retval, retval2;
918
919 /* unlock flash registers */
920 efm32x_msc_lock(bank, 0);
921 retval = efm32x_set_wren(bank, 1);
922 if (retval != ERROR_OK)
923 goto cleanup;
924
925 /* try using a block write */
926 retval = efm32x_write_block(bank, buffer, offset, words_remaining);
927
928 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
929 /* if block write failed (no sufficient working area),
930 * we use normal (slow) single word accesses */
931 LOG_WARNING("couldn't use block writes, falling back to single "
932 "memory accesses");
933
934 while (words_remaining > 0) {
935 uint32_t value;
936 memcpy(&value, buffer, sizeof(uint32_t));
937
938 retval = efm32x_write_word(bank, offset, value);
939 if (retval != ERROR_OK)
940 goto reset_pg_and_lock;
941
942 words_remaining--;
943 buffer += 4;
944 offset += 4;
945 }
946 }
947
948 reset_pg_and_lock:
949 retval2 = efm32x_set_wren(bank, 0);
950 efm32x_msc_lock(bank, 1);
951 if (retval == ERROR_OK)
952 retval = retval2;
953
954 cleanup:
955 if (new_buffer)
956 free(new_buffer);
957
958 return retval;
959 }
960
961 static int efm32x_probe(struct flash_bank *bank)
962 {
963 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
964 struct efm32_info efm32_mcu_info;
965 int ret;
966 int i;
967 uint32_t base_address = 0x00000000;
968 char buf[256];
969
970 efm32x_info->probed = 0;
971 memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
972
973 ret = efm32x_read_info(bank, &efm32_mcu_info);
974 if (ERROR_OK != ret)
975 return ret;
976
977 ret = efm32x_decode_info(&efm32_mcu_info, buf, sizeof(buf));
978 if (ERROR_OK != ret)
979 return ret;
980
981 LOG_INFO("detected part: %s", buf);
982 LOG_INFO("flash size = %dkbytes", efm32_mcu_info.flash_sz_kib);
983 LOG_INFO("flash page size = %dbytes", efm32_mcu_info.page_size);
984
985 assert(0 != efm32_mcu_info.page_size);
986
987 int num_pages = efm32_mcu_info.flash_sz_kib * 1024 /
988 efm32_mcu_info.page_size;
989
990 assert(num_pages > 0);
991
992 if (bank->sectors) {
993 free(bank->sectors);
994 bank->sectors = NULL;
995 }
996
997 bank->base = base_address;
998 bank->size = (num_pages * efm32_mcu_info.page_size);
999 bank->num_sectors = num_pages;
1000
1001 ret = efm32x_read_lock_data(bank);
1002 if (ERROR_OK != ret) {
1003 LOG_ERROR("Failed to read LB data");
1004 return ret;
1005 }
1006
1007 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
1008
1009 for (i = 0; i < num_pages; i++) {
1010 bank->sectors[i].offset = i * efm32_mcu_info.page_size;
1011 bank->sectors[i].size = efm32_mcu_info.page_size;
1012 bank->sectors[i].is_erased = -1;
1013 bank->sectors[i].is_protected = 1;
1014 }
1015
1016 efm32x_info->probed = 1;
1017
1018 return ERROR_OK;
1019 }
1020
1021 static int efm32x_auto_probe(struct flash_bank *bank)
1022 {
1023 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
1024 if (efm32x_info->probed)
1025 return ERROR_OK;
1026 return efm32x_probe(bank);
1027 }
1028
1029 static int efm32x_protect_check(struct flash_bank *bank)
1030 {
1031 struct target *target = bank->target;
1032 int ret = 0;
1033 int i = 0;
1034
1035 if (target->state != TARGET_HALTED) {
1036 LOG_ERROR("Target not halted");
1037 return ERROR_TARGET_NOT_HALTED;
1038 }
1039
1040 ret = efm32x_read_lock_data(bank);
1041 if (ERROR_OK != ret) {
1042 LOG_ERROR("Failed to read LB data");
1043 return ret;
1044 }
1045
1046 assert(NULL != bank->sectors);
1047
1048 for (i = 0; i < bank->num_sectors; i++)
1049 bank->sectors[i].is_protected = efm32x_get_page_lock(bank, i);
1050
1051 return ERROR_OK;
1052 }
1053
1054 static int get_efm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1055 {
1056 struct efm32_info info;
1057 int ret = 0;
1058
1059 ret = efm32x_read_info(bank, &info);
1060 if (ERROR_OK != ret) {
1061 LOG_ERROR("Failed to read EFM32 info");
1062 return ret;
1063 }
1064
1065 return efm32x_decode_info(&info, buf, buf_size);
1066 }
1067
1068 COMMAND_HANDLER(efm32x_handle_debuglock_command)
1069 {
1070 struct target *target = NULL;
1071
1072 if (CMD_ARGC < 1)
1073 return ERROR_COMMAND_SYNTAX_ERROR;
1074
1075 struct flash_bank *bank;
1076 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1077 if (ERROR_OK != retval)
1078 return retval;
1079
1080 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
1081
1082 target = bank->target;
1083
1084 if (target->state != TARGET_HALTED) {
1085 LOG_ERROR("Target not halted");
1086 return ERROR_TARGET_NOT_HALTED;
1087 }
1088
1089 uint32_t *ptr;
1090 ptr = efm32x_info->lb_page + 127;
1091 *ptr = 0;
1092
1093 retval = efm32x_write_lock_data(bank);
1094 if (ERROR_OK != retval) {
1095 LOG_ERROR("Failed to write LB page");
1096 return retval;
1097 }
1098
1099 command_print(CMD, "efm32x debug interface locked, reset the device to apply");
1100
1101 return ERROR_OK;
1102 }
1103
1104 static const struct command_registration efm32x_exec_command_handlers[] = {
1105 {
1106 .name = "debuglock",
1107 .handler = efm32x_handle_debuglock_command,
1108 .mode = COMMAND_EXEC,
1109 .usage = "bank_id",
1110 .help = "Lock the debug interface of the device.",
1111 },
1112 COMMAND_REGISTRATION_DONE
1113 };
1114
1115 static const struct command_registration efm32x_command_handlers[] = {
1116 {
1117 .name = "efm32",
1118 .mode = COMMAND_ANY,
1119 .help = "efm32 flash command group",
1120 .usage = "",
1121 .chain = efm32x_exec_command_handlers,
1122 },
1123 COMMAND_REGISTRATION_DONE
1124 };
1125
1126 const struct flash_driver efm32_flash = {
1127 .name = "efm32",
1128 .commands = efm32x_command_handlers,
1129 .flash_bank_command = efm32x_flash_bank_command,
1130 .erase = efm32x_erase,
1131 .protect = efm32x_protect,
1132 .write = efm32x_write,
1133 .read = default_flash_read,
1134 .probe = efm32x_probe,
1135 .auto_probe = efm32x_auto_probe,
1136 .erase_check = default_flash_blank_check,
1137 .protect_check = efm32x_protect_check,
1138 .info = get_efm32x_info,
1139 .free_driver_priv = default_flash_free_driver_priv,
1140 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)