1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
6 * Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com> *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
30 #include <target/arm.h>
31 #include <helper/binarybuffer.h>
32 #include <target/algorithm.h>
35 #define CFI_MAX_BUS_WIDTH 4
36 #define CFI_MAX_CHIP_WIDTH 4
38 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
39 #define CFI_MAX_INTEL_CODESIZE 256
41 static struct cfi_unlock_addresses cfi_unlock_addresses
[] =
43 [CFI_UNLOCK_555_2AA
] = { .unlock1
= 0x555, .unlock2
= 0x2aa },
44 [CFI_UNLOCK_5555_2AAA
] = { .unlock1
= 0x5555, .unlock2
= 0x2aaa },
47 /* CFI fixups foward declarations */
48 static void cfi_fixup_0002_erase_regions(struct flash_bank
*flash
, void *param
);
49 static void cfi_fixup_0002_unlock_addresses(struct flash_bank
*flash
, void *param
);
50 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank
*flash
, void *param
);
52 /* fixup after reading cmdset 0002 primary query table */
53 static const struct cfi_fixup cfi_0002_fixups
[] = {
54 {CFI_MFR_SST
, 0x00D4, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
55 {CFI_MFR_SST
, 0x00D5, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
56 {CFI_MFR_SST
, 0x00D6, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
57 {CFI_MFR_SST
, 0x00D7, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
58 {CFI_MFR_SST
, 0x2780, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
59 {CFI_MFR_ATMEL
, 0x00C8, cfi_fixup_atmel_reversed_erase_regions
, NULL
},
60 {CFI_MFR_FUJITSU
, 0x22ea, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
61 {CFI_MFR_FUJITSU
, 0x226b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
62 {CFI_MFR_AMIC
, 0xb31a, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
63 {CFI_MFR_MX
, 0x225b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
64 {CFI_MFR_AMD
, 0x225b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
65 {CFI_MFR_ANY
, CFI_ID_ANY
, cfi_fixup_0002_erase_regions
, NULL
},
69 /* fixup after reading cmdset 0001 primary query table */
70 static const struct cfi_fixup cfi_0001_fixups
[] = {
74 static void cfi_fixup(struct flash_bank
*bank
, const struct cfi_fixup
*fixups
)
76 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
77 const struct cfi_fixup
*f
;
79 for (f
= fixups
; f
->fixup
; f
++)
81 if (((f
->mfr
== CFI_MFR_ANY
) || (f
->mfr
== cfi_info
->manufacturer
)) &&
82 ((f
->id
== CFI_ID_ANY
) || (f
->id
== cfi_info
->device_id
)))
84 f
->fixup(bank
, f
->param
);
89 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
90 static __inline__
uint32_t flash_address(struct flash_bank
*bank
, int sector
, uint32_t offset
)
92 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
94 if (cfi_info
->x16_as_x8
) offset
*= 2;
96 /* while the sector list isn't built, only accesses to sector 0 work */
98 return bank
->base
+ offset
* bank
->bus_width
;
103 LOG_ERROR("BUG: sector list not yet built");
106 return bank
->base
+ bank
->sectors
[sector
].offset
+ offset
* bank
->bus_width
;
110 static void cfi_command(struct flash_bank
*bank
, uint8_t cmd
, uint8_t *cmd_buf
)
114 /* clear whole buffer, to ensure bits that exceed the bus_width
117 for (i
= 0; i
< CFI_MAX_BUS_WIDTH
; i
++)
120 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
122 for (i
= bank
->bus_width
; i
> 0; i
--)
124 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
129 for (i
= 1; i
<= bank
->bus_width
; i
++)
131 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
136 static int cfi_send_command(struct flash_bank
*bank
, uint8_t cmd
, uint32_t address
)
138 uint8_t command
[CFI_MAX_BUS_WIDTH
];
140 cfi_command(bank
, cmd
, command
);
141 return target_write_memory(bank
->target
, address
, bank
->bus_width
, 1, command
);
144 /* read unsigned 8-bit value from the bank
145 * flash banks are expected to be made of similar chips
146 * the query result should be the same for all
148 static uint8_t cfi_query_u8(struct flash_bank
*bank
, int sector
, uint32_t offset
)
150 struct target
*target
= bank
->target
;
151 uint8_t data
[CFI_MAX_BUS_WIDTH
];
153 target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
155 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
158 return data
[bank
->bus_width
- 1];
161 /* read unsigned 8-bit value from the bank
162 * in case of a bank made of multiple chips,
163 * the individual values are ORed
165 static uint8_t cfi_get_u8(struct flash_bank
*bank
, int sector
, uint32_t offset
)
167 struct target
*target
= bank
->target
;
168 uint8_t data
[CFI_MAX_BUS_WIDTH
];
171 target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
173 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
175 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
183 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
184 value
|= data
[bank
->bus_width
- 1 - i
];
190 static uint16_t cfi_query_u16(struct flash_bank
*bank
, int sector
, uint32_t offset
)
192 struct target
*target
= bank
->target
;
193 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
194 uint8_t data
[CFI_MAX_BUS_WIDTH
* 2];
196 if (cfi_info
->x16_as_x8
)
199 for (i
= 0;i
< 2;i
++)
200 target_read_memory(target
, flash_address(bank
, sector
, offset
+ i
), bank
->bus_width
, 1,
201 &data
[i
*bank
->bus_width
]);
204 target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 2, data
);
206 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
207 return data
[0] | data
[bank
->bus_width
] << 8;
209 return data
[bank
->bus_width
- 1] | data
[(2 * bank
->bus_width
) - 1] << 8;
212 static uint32_t cfi_query_u32(struct flash_bank
*bank
, int sector
, uint32_t offset
)
214 struct target
*target
= bank
->target
;
215 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
216 uint8_t data
[CFI_MAX_BUS_WIDTH
* 4];
218 if (cfi_info
->x16_as_x8
)
221 for (i
= 0;i
< 4;i
++)
222 target_read_memory(target
, flash_address(bank
, sector
, offset
+ i
), bank
->bus_width
, 1,
223 &data
[i
*bank
->bus_width
]);
226 target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 4, data
);
228 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
229 return data
[0] | data
[bank
->bus_width
] << 8 | data
[bank
->bus_width
* 2] << 16 | data
[bank
->bus_width
* 3] << 24;
231 return data
[bank
->bus_width
- 1] | data
[(2* bank
->bus_width
) - 1] << 8 |
232 data
[(3 * bank
->bus_width
) - 1] << 16 | data
[(4 * bank
->bus_width
) - 1] << 24;
235 static int cfi_reset(struct flash_bank
*bank
)
237 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
238 int retval
= ERROR_OK
;
240 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
245 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
250 if (cfi_info
->manufacturer
== 0x20 &&
251 (cfi_info
->device_id
== 0x227E || cfi_info
->device_id
== 0x7E))
253 /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
254 * so we send an extra 0xF0 reset to fix the bug */
255 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x00))) != ERROR_OK
)
264 static void cfi_intel_clear_status_register(struct flash_bank
*bank
)
266 struct target
*target
= bank
->target
;
268 if (target
->state
!= TARGET_HALTED
)
270 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
274 cfi_send_command(bank
, 0x50, flash_address(bank
, 0, 0x0));
277 static uint8_t cfi_intel_wait_status_busy(struct flash_bank
*bank
, int timeout
)
281 while ((!((status
= cfi_get_u8(bank
, 0, 0x0)) & 0x80)) && (timeout
-- > 0))
283 LOG_DEBUG("status: 0x%x", status
);
287 /* mask out bit 0 (reserved) */
288 status
= status
& 0xfe;
290 LOG_DEBUG("status: 0x%x", status
);
292 if ((status
& 0x80) != 0x80)
294 LOG_ERROR("timeout while waiting for WSM to become ready");
296 else if (status
!= 0x80)
298 LOG_ERROR("status register: 0x%x", status
);
300 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
302 LOG_ERROR("Program suspended");
304 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
306 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
308 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
310 LOG_ERROR("Block Erase Suspended");
312 cfi_intel_clear_status_register(bank
);
318 static int cfi_spansion_wait_status_busy(struct flash_bank
*bank
, int timeout
)
320 uint8_t status
, oldstatus
;
321 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
323 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
326 status
= cfi_get_u8(bank
, 0, 0x0);
327 if ((status
^ oldstatus
) & 0x40) {
328 if (status
& cfi_info
->status_poll_mask
& 0x20) {
329 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
330 status
= cfi_get_u8(bank
, 0, 0x0);
331 if ((status
^ oldstatus
) & 0x40) {
332 LOG_ERROR("dq5 timeout, status: 0x%x", status
);
333 return(ERROR_FLASH_OPERATION_FAILED
);
335 LOG_DEBUG("status: 0x%x", status
);
339 } else { /* no toggle: finished, OK */
340 LOG_DEBUG("status: 0x%x", status
);
346 } while (timeout
-- > 0);
348 LOG_ERROR("timeout, status: 0x%x", status
);
350 return(ERROR_FLASH_BUSY
);
353 static int cfi_read_intel_pri_ext(struct flash_bank
*bank
)
356 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
357 struct cfi_intel_pri_ext
*pri_ext
= malloc(sizeof(struct cfi_intel_pri_ext
));
359 cfi_info
->pri_ext
= pri_ext
;
361 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
362 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
363 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
365 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
367 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
371 LOG_ERROR("Could not read bank flash bank information");
372 return ERROR_FLASH_BANK_INVALID
;
375 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
376 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
378 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
380 pri_ext
->feature_support
= cfi_query_u32(bank
, 0, cfi_info
->pri_addr
+ 5);
381 pri_ext
->suspend_cmd_support
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
382 pri_ext
->blk_status_reg_mask
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xa);
384 LOG_DEBUG("feature_support: 0x%" PRIx32
", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
385 pri_ext
->feature_support
,
386 pri_ext
->suspend_cmd_support
,
387 pri_ext
->blk_status_reg_mask
);
389 pri_ext
->vcc_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xc);
390 pri_ext
->vpp_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xd);
392 LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
393 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
394 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
396 pri_ext
->num_protection_fields
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xe);
397 if (pri_ext
->num_protection_fields
!= 1)
399 LOG_WARNING("expected one protection register field, but found %i", pri_ext
->num_protection_fields
);
402 pri_ext
->prot_reg_addr
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xf);
403 pri_ext
->fact_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x11);
404 pri_ext
->user_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x12);
406 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
411 static int cfi_read_spansion_pri_ext(struct flash_bank
*bank
)
414 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
415 struct cfi_spansion_pri_ext
*pri_ext
= malloc(sizeof(struct cfi_spansion_pri_ext
));
417 cfi_info
->pri_ext
= pri_ext
;
419 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
420 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
421 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
423 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
425 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
429 LOG_ERROR("Could not read spansion bank information");
430 return ERROR_FLASH_BANK_INVALID
;
433 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
434 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
436 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
438 pri_ext
->SiliconRevision
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
439 pri_ext
->EraseSuspend
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
440 pri_ext
->BlkProt
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
441 pri_ext
->TmpBlkUnprotect
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
442 pri_ext
->BlkProtUnprot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
443 pri_ext
->SimultaneousOps
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 10);
444 pri_ext
->BurstMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 11);
445 pri_ext
->PageMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 12);
446 pri_ext
->VppMin
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 13);
447 pri_ext
->VppMax
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 14);
448 pri_ext
->TopBottom
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 15);
450 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext
->SiliconRevision
,
451 pri_ext
->EraseSuspend
, pri_ext
->BlkProt
);
453 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext
->TmpBlkUnprotect
,
454 pri_ext
->BlkProtUnprot
, pri_ext
->SimultaneousOps
);
456 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext
->BurstMode
, pri_ext
->PageMode
);
459 LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
460 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
461 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
463 LOG_DEBUG("WP# protection 0x%x", pri_ext
->TopBottom
);
465 /* default values for implementation specific workarounds */
466 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
467 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
468 pri_ext
->_reversed_geometry
= 0;
473 static int cfi_read_atmel_pri_ext(struct flash_bank
*bank
)
476 struct cfi_atmel_pri_ext atmel_pri_ext
;
477 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
478 struct cfi_spansion_pri_ext
*pri_ext
= malloc(sizeof(struct cfi_spansion_pri_ext
));
480 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
481 * but a different primary extended query table.
482 * We read the atmel table, and prepare a valid AMD/Spansion query table.
485 memset(pri_ext
, 0, sizeof(struct cfi_spansion_pri_ext
));
487 cfi_info
->pri_ext
= pri_ext
;
489 atmel_pri_ext
.pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
490 atmel_pri_ext
.pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
491 atmel_pri_ext
.pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
493 if ((atmel_pri_ext
.pri
[0] != 'P') || (atmel_pri_ext
.pri
[1] != 'R') || (atmel_pri_ext
.pri
[2] != 'I'))
495 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
499 LOG_ERROR("Could not read atmel bank information");
500 return ERROR_FLASH_BANK_INVALID
;
503 pri_ext
->pri
[0] = atmel_pri_ext
.pri
[0];
504 pri_ext
->pri
[1] = atmel_pri_ext
.pri
[1];
505 pri_ext
->pri
[2] = atmel_pri_ext
.pri
[2];
507 atmel_pri_ext
.major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
508 atmel_pri_ext
.minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
510 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext
.pri
[0], atmel_pri_ext
.pri
[1], atmel_pri_ext
.pri
[2], atmel_pri_ext
.major_version
, atmel_pri_ext
.minor_version
);
512 pri_ext
->major_version
= atmel_pri_ext
.major_version
;
513 pri_ext
->minor_version
= atmel_pri_ext
.minor_version
;
515 atmel_pri_ext
.features
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
516 atmel_pri_ext
.bottom_boot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
517 atmel_pri_ext
.burst_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
518 atmel_pri_ext
.page_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
520 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
521 atmel_pri_ext
.features
, atmel_pri_ext
.bottom_boot
, atmel_pri_ext
.burst_mode
, atmel_pri_ext
.page_mode
);
523 if (atmel_pri_ext
.features
& 0x02)
524 pri_ext
->EraseSuspend
= 2;
526 if (atmel_pri_ext
.bottom_boot
)
527 pri_ext
->TopBottom
= 2;
529 pri_ext
->TopBottom
= 3;
531 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
532 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
537 static int cfi_read_0002_pri_ext(struct flash_bank
*bank
)
539 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
541 if (cfi_info
->manufacturer
== CFI_MFR_ATMEL
)
543 return cfi_read_atmel_pri_ext(bank
);
547 return cfi_read_spansion_pri_ext(bank
);
551 static int cfi_spansion_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
554 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
555 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
557 printed
= snprintf(buf
, buf_size
, "\nSpansion primary algorithm extend information:\n");
561 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0],
562 pri_ext
->pri
[1], pri_ext
->pri
[2],
563 pri_ext
->major_version
, pri_ext
->minor_version
);
567 printed
= snprintf(buf
, buf_size
, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
568 (pri_ext
->SiliconRevision
) >> 2,
569 (pri_ext
->SiliconRevision
) & 0x03);
573 printed
= snprintf(buf
, buf_size
, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
574 pri_ext
->EraseSuspend
,
579 printed
= snprintf(buf
, buf_size
, "VppMin: %u.%x, VppMax: %u.%x\n",
580 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
581 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
586 static int cfi_intel_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
589 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
590 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
592 printed
= snprintf(buf
, buf_size
, "\nintel primary algorithm extend information:\n");
596 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
600 printed
= snprintf(buf
, buf_size
, "feature_support: 0x%" PRIx32
", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
604 printed
= snprintf(buf
, buf_size
, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
605 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
606 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
610 printed
= snprintf(buf
, buf_size
, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
615 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
617 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command
)
619 struct cfi_flash_bank
*cfi_info
;
623 LOG_WARNING("incomplete flash_bank cfi configuration");
624 return ERROR_FLASH_BANK_INVALID
;
628 * - not exceed max value;
630 * - be equal to a power of 2.
631 * bus must be wide enought to hold one chip */
632 if ((bank
->chip_width
> CFI_MAX_CHIP_WIDTH
)
633 || (bank
->bus_width
> CFI_MAX_BUS_WIDTH
)
634 || (bank
->chip_width
== 0)
635 || (bank
->bus_width
== 0)
636 || (bank
->chip_width
& (bank
->chip_width
- 1))
637 || (bank
->bus_width
& (bank
->bus_width
- 1))
638 || (bank
->chip_width
> bank
->bus_width
))
640 LOG_ERROR("chip and bus width have to specified in bytes");
641 return ERROR_FLASH_BANK_INVALID
;
644 cfi_info
= malloc(sizeof(struct cfi_flash_bank
));
645 cfi_info
->probed
= 0;
646 bank
->driver_priv
= cfi_info
;
648 cfi_info
->write_algorithm
= NULL
;
650 cfi_info
->x16_as_x8
= 0;
651 cfi_info
->jedec_probe
= 0;
652 cfi_info
->not_cfi
= 0;
654 for (unsigned i
= 6; i
< CMD_ARGC
; i
++)
656 if (strcmp(CMD_ARGV
[i
], "x16_as_x8") == 0)
658 cfi_info
->x16_as_x8
= 1;
660 else if (strcmp(CMD_ARGV
[i
], "jedec_probe") == 0)
662 cfi_info
->jedec_probe
= 1;
666 cfi_info
->write_algorithm
= NULL
;
668 /* bank wasn't probed yet */
669 cfi_info
->qry
[0] = -1;
674 static int cfi_intel_erase(struct flash_bank
*bank
, int first
, int last
)
677 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
680 cfi_intel_clear_status_register(bank
);
682 for (i
= first
; i
<= last
; i
++)
684 if ((retval
= cfi_send_command(bank
, 0x20, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
689 if ((retval
= cfi_send_command(bank
, 0xd0, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
694 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == 0x80)
695 bank
->sectors
[i
].is_erased
= 1;
698 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
703 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32
, i
, bank
->base
);
704 return ERROR_FLASH_OPERATION_FAILED
;
708 return cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0));
711 static int cfi_spansion_erase(struct flash_bank
*bank
, int first
, int last
)
714 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
715 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
718 for (i
= first
; i
<= last
; i
++)
720 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
725 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
730 if ((retval
= cfi_send_command(bank
, 0x80, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
735 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
740 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
745 if ((retval
= cfi_send_command(bank
, 0x30, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
750 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == ERROR_OK
)
751 bank
->sectors
[i
].is_erased
= 1;
754 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
759 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32
, i
, bank
->base
);
760 return ERROR_FLASH_OPERATION_FAILED
;
764 return cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0));
767 static int cfi_erase(struct flash_bank
*bank
, int first
, int last
)
769 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
771 if (bank
->target
->state
!= TARGET_HALTED
)
773 LOG_ERROR("Target not halted");
774 return ERROR_TARGET_NOT_HALTED
;
777 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
779 return ERROR_FLASH_SECTOR_INVALID
;
782 if (cfi_info
->qry
[0] != 'Q')
783 return ERROR_FLASH_BANK_NOT_PROBED
;
785 switch (cfi_info
->pri_id
)
789 return cfi_intel_erase(bank
, first
, last
);
792 return cfi_spansion_erase(bank
, first
, last
);
795 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
802 static int cfi_intel_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
805 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
806 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
807 struct target
*target
= bank
->target
; /* FIXME: to be removed */
808 uint8_t command
[CFI_MAX_BUS_WIDTH
]; /* FIXME: to be removed */
812 /* if the device supports neither legacy lock/unlock (bit 3) nor
813 * instant individual block locking (bit 5).
815 if (!(pri_ext
->feature_support
& 0x28))
816 return ERROR_FLASH_OPERATION_FAILED
;
818 cfi_intel_clear_status_register(bank
);
820 for (i
= first
; i
<= last
; i
++)
822 cfi_command(bank
, 0x60, command
); /* FIXME: to be removed */
823 LOG_DEBUG("address: 0x%4.4" PRIx32
", command: 0x%4.4" PRIx32
, flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
824 if ((retval
= cfi_send_command(bank
, 0x60, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
830 cfi_command(bank
, 0x01, command
); /* FIXME: to be removed */
831 LOG_DEBUG("address: 0x%4.4" PRIx32
", command: 0x%4.4" PRIx32
, flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
832 if ((retval
= cfi_send_command(bank
, 0x01, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
836 bank
->sectors
[i
].is_protected
= 1;
840 cfi_command(bank
, 0xd0, command
); /* FIXME: to be removed */
841 LOG_DEBUG("address: 0x%4.4" PRIx32
", command: 0x%4.4" PRIx32
, flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
842 if ((retval
= cfi_send_command(bank
, 0xd0, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
846 bank
->sectors
[i
].is_protected
= 0;
849 /* instant individual block locking doesn't require reading of the status register */
850 if (!(pri_ext
->feature_support
& 0x20))
852 /* Clear lock bits operation may take up to 1.4s */
853 cfi_intel_wait_status_busy(bank
, 1400);
857 uint8_t block_status
;
858 /* read block lock bit, to verify status */
859 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, 0x55))) != ERROR_OK
)
863 block_status
= cfi_get_u8(bank
, i
, 0x2);
865 if ((block_status
& 0x1) != set
)
867 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set
, block_status
);
868 if ((retval
= cfi_send_command(bank
, 0x70, flash_address(bank
, 0, 0x55))) != ERROR_OK
)
872 cfi_intel_wait_status_busy(bank
, 10);
875 return ERROR_FLASH_OPERATION_FAILED
;
885 /* if the device doesn't support individual block lock bits set/clear,
886 * all blocks have been unlocked in parallel, so we set those that should be protected
888 if ((!set
) && (!(pri_ext
->feature_support
& 0x20)))
890 /* FIX!!! this code path is broken!!!
892 * The correct approach is:
894 * 1. read out current protection status
896 * 2. override read out protection status w/unprotected.
898 * 3. re-protect what should be protected.
901 for (i
= 0; i
< bank
->num_sectors
; i
++)
903 if (bank
->sectors
[i
].is_protected
== 1)
905 cfi_intel_clear_status_register(bank
);
907 if ((retval
= cfi_send_command(bank
, 0x60, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
912 if ((retval
= cfi_send_command(bank
, 0x01, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
917 cfi_intel_wait_status_busy(bank
, 100);
922 return cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0));
925 static int cfi_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
927 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
929 if (bank
->target
->state
!= TARGET_HALTED
)
931 LOG_ERROR("Target not halted");
932 return ERROR_TARGET_NOT_HALTED
;
935 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
937 LOG_ERROR("Invalid sector range");
938 return ERROR_FLASH_SECTOR_INVALID
;
941 if (cfi_info
->qry
[0] != 'Q')
942 return ERROR_FLASH_BANK_NOT_PROBED
;
944 switch (cfi_info
->pri_id
)
948 return cfi_intel_protect(bank
, set
, first
, last
);
951 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info
->pri_id
);
956 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
957 static void cfi_add_byte(struct flash_bank
*bank
, uint8_t *word
, uint8_t byte
)
959 /* struct target *target = bank->target; */
964 * The data to flash must not be changed in endian! We write a bytestrem in
965 * target byte order already. Only the control and status byte lane of the flash
966 * WSM is interpreted by the CPU in different ways, when read a uint16_t or uint32_t
967 * word (data seems to be in the upper or lower byte lane for uint16_t accesses).
971 if (target
->endianness
== TARGET_LITTLE_ENDIAN
)
975 for (i
= 0; i
< bank
->bus_width
- 1; i
++)
976 word
[i
] = word
[i
+ 1];
977 word
[bank
->bus_width
- 1] = byte
;
983 for (i
= bank
->bus_width
- 1; i
> 0; i
--)
984 word
[i
] = word
[i
- 1];
990 /* Convert code image to target endian */
991 /* FIXME create general block conversion fcts in target.c?) */
992 static void cfi_fix_code_endian(struct target
*target
, uint8_t *dest
, const uint32_t *src
, uint32_t count
)
995 for (i
= 0; i
< count
; i
++)
997 target_buffer_set_u32(target
, dest
, *src
);
1003 static uint32_t cfi_command_val(struct flash_bank
*bank
, uint8_t cmd
)
1005 struct target
*target
= bank
->target
;
1007 uint8_t buf
[CFI_MAX_BUS_WIDTH
];
1008 cfi_command(bank
, cmd
, buf
);
1009 switch (bank
->bus_width
)
1015 return target_buffer_get_u16(target
, buf
);
1018 return target_buffer_get_u32(target
, buf
);
1021 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1026 static int cfi_intel_write_block(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t address
, uint32_t count
)
1028 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1029 struct target
*target
= bank
->target
;
1030 struct reg_param reg_params
[7];
1031 struct arm_algorithm armv4_5_info
;
1032 struct working_area
*source
;
1033 uint32_t buffer_size
= 32768;
1034 uint32_t write_command_val
, busy_pattern_val
, error_pattern_val
;
1036 /* algorithm register usage:
1037 * r0: source address (in RAM)
1038 * r1: target address (in Flash)
1040 * r3: flash write command
1041 * r4: status byte (returned to host)
1042 * r5: busy test pattern
1043 * r6: error test pattern
1046 static const uint32_t word_32_code
[] = {
1047 0xe4904004, /* loop: ldr r4, [r0], #4 */
1048 0xe5813000, /* str r3, [r1] */
1049 0xe5814000, /* str r4, [r1] */
1050 0xe5914000, /* busy: ldr r4, [r1] */
1051 0xe0047005, /* and r7, r4, r5 */
1052 0xe1570005, /* cmp r7, r5 */
1053 0x1afffffb, /* bne busy */
1054 0xe1140006, /* tst r4, r6 */
1055 0x1a000003, /* bne done */
1056 0xe2522001, /* subs r2, r2, #1 */
1057 0x0a000001, /* beq done */
1058 0xe2811004, /* add r1, r1 #4 */
1059 0xeafffff2, /* b loop */
1060 0xeafffffe /* done: b -2 */
1063 static const uint32_t word_16_code
[] = {
1064 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1065 0xe1c130b0, /* strh r3, [r1] */
1066 0xe1c140b0, /* strh r4, [r1] */
1067 0xe1d140b0, /* busy ldrh r4, [r1] */
1068 0xe0047005, /* and r7, r4, r5 */
1069 0xe1570005, /* cmp r7, r5 */
1070 0x1afffffb, /* bne busy */
1071 0xe1140006, /* tst r4, r6 */
1072 0x1a000003, /* bne done */
1073 0xe2522001, /* subs r2, r2, #1 */
1074 0x0a000001, /* beq done */
1075 0xe2811002, /* add r1, r1 #2 */
1076 0xeafffff2, /* b loop */
1077 0xeafffffe /* done: b -2 */
1080 static const uint32_t word_8_code
[] = {
1081 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1082 0xe5c13000, /* strb r3, [r1] */
1083 0xe5c14000, /* strb r4, [r1] */
1084 0xe5d14000, /* busy ldrb r4, [r1] */
1085 0xe0047005, /* and r7, r4, r5 */
1086 0xe1570005, /* cmp r7, r5 */
1087 0x1afffffb, /* bne busy */
1088 0xe1140006, /* tst r4, r6 */
1089 0x1a000003, /* bne done */
1090 0xe2522001, /* subs r2, r2, #1 */
1091 0x0a000001, /* beq done */
1092 0xe2811001, /* add r1, r1 #1 */
1093 0xeafffff2, /* b loop */
1094 0xeafffffe /* done: b -2 */
1096 uint8_t target_code
[4*CFI_MAX_INTEL_CODESIZE
];
1097 const uint32_t *target_code_src
;
1098 uint32_t target_code_size
;
1099 int retval
= ERROR_OK
;
1102 cfi_intel_clear_status_register(bank
);
1104 armv4_5_info
.common_magic
= ARM_COMMON_MAGIC
;
1105 armv4_5_info
.core_mode
= ARM_MODE_SVC
;
1106 armv4_5_info
.core_state
= ARM_STATE_ARM
;
1108 /* If we are setting up the write_algorith, we need target_code_src */
1109 /* if not we only need target_code_size. */
1111 /* However, we don't want to create multiple code paths, so we */
1112 /* do the unecessary evaluation of target_code_src, which the */
1113 /* compiler will probably nicely optimize away if not needed */
1115 /* prepare algorithm code for target endian */
1116 switch (bank
->bus_width
)
1119 target_code_src
= word_8_code
;
1120 target_code_size
= sizeof(word_8_code
);
1123 target_code_src
= word_16_code
;
1124 target_code_size
= sizeof(word_16_code
);
1127 target_code_src
= word_32_code
;
1128 target_code_size
= sizeof(word_32_code
);
1131 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1132 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1135 /* flash write code */
1136 if (!cfi_info
->write_algorithm
)
1138 if (target_code_size
> sizeof(target_code
))
1140 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1141 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1143 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
/ 4);
1145 /* Get memory for block write handler */
1146 retval
= target_alloc_working_area(target
, target_code_size
, &cfi_info
->write_algorithm
);
1147 if (retval
!= ERROR_OK
)
1149 LOG_WARNING("No working area available, can't do block memory writes");
1150 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1153 /* write algorithm code to working area */
1154 retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
, target_code_size
, target_code
);
1155 if (retval
!= ERROR_OK
)
1157 LOG_ERROR("Unable to write block write code to target");
1162 /* Get a workspace buffer for the data to flash starting with 32k size.
1163 Half size until buffer would be smaller 256 Bytem then fail back */
1164 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1165 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
)
1168 if (buffer_size
<= 256)
1170 LOG_WARNING("no large enough working area available, can't do block memory writes");
1171 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1176 /* setup algo registers */
1177 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1178 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1179 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1180 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1181 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
1182 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
1183 init_reg_param(®_params
[6], "r6", 32, PARAM_OUT
);
1185 /* prepare command and status register patterns */
1186 write_command_val
= cfi_command_val(bank
, 0x40);
1187 busy_pattern_val
= cfi_command_val(bank
, 0x80);
1188 error_pattern_val
= cfi_command_val(bank
, 0x7e);
1190 LOG_DEBUG("Using target buffer at 0x%08" PRIx32
" and of size 0x%04" PRIx32
, source
->address
, buffer_size
);
1192 /* Programming main loop */
1195 uint32_t thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1198 if ((retval
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
)) != ERROR_OK
)
1203 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1204 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1205 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1207 buf_set_u32(reg_params
[3].value
, 0, 32, write_command_val
);
1208 buf_set_u32(reg_params
[5].value
, 0, 32, busy_pattern_val
);
1209 buf_set_u32(reg_params
[6].value
, 0, 32, error_pattern_val
);
1211 LOG_DEBUG("Write 0x%04" PRIx32
" bytes to flash at 0x%08" PRIx32
, thisrun_count
, address
);
1213 /* Execute algorithm, assume breakpoint for last instruction */
1214 retval
= target_run_algorithm(target
, 0, NULL
, 7, reg_params
,
1215 cfi_info
->write_algorithm
->address
,
1216 cfi_info
->write_algorithm
->address
+ target_code_size
- sizeof(uint32_t),
1217 10000, /* 10s should be enough for max. 32k of data */
1220 /* On failure try a fall back to direct word writes */
1221 if (retval
!= ERROR_OK
)
1223 cfi_intel_clear_status_register(bank
);
1224 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1225 retval
= ERROR_FLASH_OPERATION_FAILED
;
1226 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1227 /* FIXME To allow fall back or recovery, we must save the actual status
1228 somewhere, so that a higher level code can start recovery. */
1232 /* Check return value from algo code */
1233 wsm_error
= buf_get_u32(reg_params
[4].value
, 0, 32) & error_pattern_val
;
1236 /* read status register (outputs debug inforation) */
1237 cfi_intel_wait_status_busy(bank
, 100);
1238 cfi_intel_clear_status_register(bank
);
1239 retval
= ERROR_FLASH_OPERATION_FAILED
;
1243 buffer
+= thisrun_count
;
1244 address
+= thisrun_count
;
1245 count
-= thisrun_count
;
1248 /* free up resources */
1251 target_free_working_area(target
, source
);
1253 if (cfi_info
->write_algorithm
)
1255 target_free_working_area(target
, cfi_info
->write_algorithm
);
1256 cfi_info
->write_algorithm
= NULL
;
1259 destroy_reg_param(®_params
[0]);
1260 destroy_reg_param(®_params
[1]);
1261 destroy_reg_param(®_params
[2]);
1262 destroy_reg_param(®_params
[3]);
1263 destroy_reg_param(®_params
[4]);
1264 destroy_reg_param(®_params
[5]);
1265 destroy_reg_param(®_params
[6]);
1270 static int cfi_spansion_write_block(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t address
, uint32_t count
)
1272 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1273 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1274 struct target
*target
= bank
->target
;
1275 struct reg_param reg_params
[10];
1276 struct arm_algorithm armv4_5_info
;
1277 struct working_area
*source
;
1278 uint32_t buffer_size
= 32768;
1280 int retval
, retvaltemp
;
1281 int exit_code
= ERROR_OK
;
1283 /* input parameters - */
1284 /* R0 = source address */
1285 /* R1 = destination address */
1286 /* R2 = number of writes */
1287 /* R3 = flash write command */
1288 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1289 /* output parameters - */
1290 /* R5 = 0x80 ok 0x00 bad */
1291 /* temp registers - */
1292 /* R6 = value read from flash to test status */
1293 /* R7 = holding register */
1294 /* unlock registers - */
1295 /* R8 = unlock1_addr */
1296 /* R9 = unlock1_cmd */
1297 /* R10 = unlock2_addr */
1298 /* R11 = unlock2_cmd */
1300 static const uint32_t word_32_code
[] = {
1301 /* 00008100 <sp_32_code>: */
1302 0xe4905004, /* ldr r5, [r0], #4 */
1303 0xe5889000, /* str r9, [r8] */
1304 0xe58ab000, /* str r11, [r10] */
1305 0xe5883000, /* str r3, [r8] */
1306 0xe5815000, /* str r5, [r1] */
1307 0xe1a00000, /* nop */
1309 /* 00008110 <sp_32_busy>: */
1310 0xe5916000, /* ldr r6, [r1] */
1311 0xe0257006, /* eor r7, r5, r6 */
1312 0xe0147007, /* ands r7, r4, r7 */
1313 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1314 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1315 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1316 0xe5916000, /* ldr r6, [r1] */
1317 0xe0257006, /* eor r7, r5, r6 */
1318 0xe0147007, /* ands r7, r4, r7 */
1319 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1320 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1321 0x1a000004, /* bne 8154 <sp_32_done> */
1323 /* 00008140 <sp_32_cont>: */
1324 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1325 0x03a05080, /* moveq r5, #128 ; 0x80 */
1326 0x0a000001, /* beq 8154 <sp_32_done> */
1327 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1328 0xeaffffe8, /* b 8100 <sp_32_code> */
1330 /* 00008154 <sp_32_done>: */
1331 0xeafffffe /* b 8154 <sp_32_done> */
1334 static const uint32_t word_16_code
[] = {
1335 /* 00008158 <sp_16_code>: */
1336 0xe0d050b2, /* ldrh r5, [r0], #2 */
1337 0xe1c890b0, /* strh r9, [r8] */
1338 0xe1cab0b0, /* strh r11, [r10] */
1339 0xe1c830b0, /* strh r3, [r8] */
1340 0xe1c150b0, /* strh r5, [r1] */
1341 0xe1a00000, /* nop (mov r0,r0) */
1343 /* 00008168 <sp_16_busy>: */
1344 0xe1d160b0, /* ldrh r6, [r1] */
1345 0xe0257006, /* eor r7, r5, r6 */
1346 0xe0147007, /* ands r7, r4, r7 */
1347 0x0a000007, /* beq 8198 <sp_16_cont> */
1348 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1349 0x0afffff9, /* beq 8168 <sp_16_busy> */
1350 0xe1d160b0, /* ldrh r6, [r1] */
1351 0xe0257006, /* eor r7, r5, r6 */
1352 0xe0147007, /* ands r7, r4, r7 */
1353 0x0a000001, /* beq 8198 <sp_16_cont> */
1354 0xe3a05000, /* mov r5, #0 ; 0x0 */
1355 0x1a000004, /* bne 81ac <sp_16_done> */
1357 /* 00008198 <sp_16_cont>: */
1358 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1359 0x03a05080, /* moveq r5, #128 ; 0x80 */
1360 0x0a000001, /* beq 81ac <sp_16_done> */
1361 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1362 0xeaffffe8, /* b 8158 <sp_16_code> */
1364 /* 000081ac <sp_16_done>: */
1365 0xeafffffe /* b 81ac <sp_16_done> */
1368 static const uint32_t word_16_code_dq7only
[] = {
1370 0xe0d050b2, /* ldrh r5, [r0], #2 */
1371 0xe1c890b0, /* strh r9, [r8] */
1372 0xe1cab0b0, /* strh r11, [r10] */
1373 0xe1c830b0, /* strh r3, [r8] */
1374 0xe1c150b0, /* strh r5, [r1] */
1375 0xe1a00000, /* nop (mov r0,r0) */
1378 0xe1d160b0, /* ldrh r6, [r1] */
1379 0xe0257006, /* eor r7, r5, r6 */
1380 0xe2177080, /* ands r7, #0x80 */
1381 0x1afffffb, /* bne 8168 <sp_16_busy> */
1383 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1384 0x03a05080, /* moveq r5, #128 ; 0x80 */
1385 0x0a000001, /* beq 81ac <sp_16_done> */
1386 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1387 0xeafffff0, /* b 8158 <sp_16_code> */
1389 /* 000081ac <sp_16_done>: */
1390 0xeafffffe /* b 81ac <sp_16_done> */
1393 static const uint32_t word_8_code
[] = {
1394 /* 000081b0 <sp_16_code_end>: */
1395 0xe4d05001, /* ldrb r5, [r0], #1 */
1396 0xe5c89000, /* strb r9, [r8] */
1397 0xe5cab000, /* strb r11, [r10] */
1398 0xe5c83000, /* strb r3, [r8] */
1399 0xe5c15000, /* strb r5, [r1] */
1400 0xe1a00000, /* nop (mov r0,r0) */
1402 /* 000081c0 <sp_8_busy>: */
1403 0xe5d16000, /* ldrb r6, [r1] */
1404 0xe0257006, /* eor r7, r5, r6 */
1405 0xe0147007, /* ands r7, r4, r7 */
1406 0x0a000007, /* beq 81f0 <sp_8_cont> */
1407 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1408 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1409 0xe5d16000, /* ldrb r6, [r1] */
1410 0xe0257006, /* eor r7, r5, r6 */
1411 0xe0147007, /* ands r7, r4, r7 */
1412 0x0a000001, /* beq 81f0 <sp_8_cont> */
1413 0xe3a05000, /* mov r5, #0 ; 0x0 */
1414 0x1a000004, /* bne 8204 <sp_8_done> */
1416 /* 000081f0 <sp_8_cont>: */
1417 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1418 0x03a05080, /* moveq r5, #128 ; 0x80 */
1419 0x0a000001, /* beq 8204 <sp_8_done> */
1420 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1421 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1423 /* 00008204 <sp_8_done>: */
1424 0xeafffffe /* b 8204 <sp_8_done> */
1427 armv4_5_info
.common_magic
= ARM_COMMON_MAGIC
;
1428 armv4_5_info
.core_mode
= ARM_MODE_SVC
;
1429 armv4_5_info
.core_state
= ARM_STATE_ARM
;
1431 int target_code_size
;
1432 const uint32_t *target_code_src
;
1434 switch (bank
->bus_width
)
1437 target_code_src
= word_8_code
;
1438 target_code_size
= sizeof(word_8_code
);
1441 /* Check for DQ5 support */
1442 if( cfi_info
->status_poll_mask
& (1 << 5) )
1444 target_code_src
= word_16_code
;
1445 target_code_size
= sizeof(word_16_code
);
1449 /* No DQ5 support. Use DQ7 DATA# polling only. */
1450 target_code_src
= word_16_code_dq7only
;
1451 target_code_size
= sizeof(word_16_code_dq7only
);
1455 target_code_src
= word_32_code
;
1456 target_code_size
= sizeof(word_32_code
);
1459 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1460 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1463 /* flash write code */
1464 if (!cfi_info
->write_algorithm
)
1466 uint8_t *target_code
;
1468 /* convert bus-width dependent algorithm code to correct endiannes */
1469 target_code
= malloc(target_code_size
);
1470 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
/ 4);
1472 /* allocate working area */
1473 retval
= target_alloc_working_area(target
, target_code_size
,
1474 &cfi_info
->write_algorithm
);
1475 if (retval
!= ERROR_OK
)
1481 /* write algorithm code to working area */
1482 if ((retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
,
1483 target_code_size
, target_code
)) != ERROR_OK
)
1491 /* the following code still assumes target code is fixed 24*4 bytes */
1493 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
)
1496 if (buffer_size
<= 256)
1498 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1499 if (cfi_info
->write_algorithm
)
1500 target_free_working_area(target
, cfi_info
->write_algorithm
);
1502 LOG_WARNING("not enough working area available, can't do block memory writes");
1503 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1507 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1508 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1509 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1510 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1511 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
1512 init_reg_param(®_params
[5], "r5", 32, PARAM_IN
);
1513 init_reg_param(®_params
[6], "r8", 32, PARAM_OUT
);
1514 init_reg_param(®_params
[7], "r9", 32, PARAM_OUT
);
1515 init_reg_param(®_params
[8], "r10", 32, PARAM_OUT
);
1516 init_reg_param(®_params
[9], "r11", 32, PARAM_OUT
);
1520 uint32_t thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1522 retvaltemp
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1524 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1525 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1526 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1527 buf_set_u32(reg_params
[3].value
, 0, 32, cfi_command_val(bank
, 0xA0));
1528 buf_set_u32(reg_params
[4].value
, 0, 32, cfi_command_val(bank
, 0x80));
1529 buf_set_u32(reg_params
[6].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock1
));
1530 buf_set_u32(reg_params
[7].value
, 0, 32, 0xaaaaaaaa);
1531 buf_set_u32(reg_params
[8].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock2
));
1532 buf_set_u32(reg_params
[9].value
, 0, 32, 0x55555555);
1534 retval
= target_run_algorithm(target
, 0, NULL
, 10, reg_params
,
1535 cfi_info
->write_algorithm
->address
,
1536 cfi_info
->write_algorithm
->address
+ ((target_code_size
) - 4),
1537 10000, &armv4_5_info
);
1539 status
= buf_get_u32(reg_params
[5].value
, 0, 32);
1541 if ((retval
!= ERROR_OK
) || (retvaltemp
!= ERROR_OK
) || status
!= 0x80)
1543 LOG_DEBUG("status: 0x%" PRIx32
, status
);
1544 exit_code
= ERROR_FLASH_OPERATION_FAILED
;
1548 buffer
+= thisrun_count
;
1549 address
+= thisrun_count
;
1550 count
-= thisrun_count
;
1553 target_free_all_working_areas(target
);
1555 destroy_reg_param(®_params
[0]);
1556 destroy_reg_param(®_params
[1]);
1557 destroy_reg_param(®_params
[2]);
1558 destroy_reg_param(®_params
[3]);
1559 destroy_reg_param(®_params
[4]);
1560 destroy_reg_param(®_params
[5]);
1561 destroy_reg_param(®_params
[6]);
1562 destroy_reg_param(®_params
[7]);
1563 destroy_reg_param(®_params
[8]);
1564 destroy_reg_param(®_params
[9]);
1569 static int cfi_intel_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
1572 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1573 struct target
*target
= bank
->target
;
1575 cfi_intel_clear_status_register(bank
);
1576 if ((retval
= cfi_send_command(bank
, 0x40, address
)) != ERROR_OK
)
1581 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, word
)) != ERROR_OK
)
1586 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != 0x80)
1588 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1593 LOG_ERROR("couldn't write word at base 0x%" PRIx32
", address %" PRIx32
, bank
->base
, address
);
1594 return ERROR_FLASH_OPERATION_FAILED
;
1600 static int cfi_intel_write_words(struct flash_bank
*bank
, uint8_t *word
, uint32_t wordcount
, uint32_t address
)
1603 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1604 struct target
*target
= bank
->target
;
1606 /* Calculate buffer size and boundary mask */
1607 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1608 uint32_t buffermask
= buffersize
-1;
1609 uint32_t bufferwsize
;
1611 /* Check for valid range */
1612 if (address
& buffermask
)
1614 LOG_ERROR("Write address at base 0x%" PRIx32
", address %" PRIx32
" not aligned to 2^%d boundary",
1615 bank
->base
, address
, cfi_info
->max_buf_write_size
);
1616 return ERROR_FLASH_OPERATION_FAILED
;
1618 switch (bank
->chip_width
)
1620 case 4 : bufferwsize
= buffersize
/ 4; break;
1621 case 2 : bufferwsize
= buffersize
/ 2; break;
1622 case 1 : bufferwsize
= buffersize
; break;
1624 LOG_ERROR("Unsupported chip width %d", bank
->chip_width
);
1625 return ERROR_FLASH_OPERATION_FAILED
;
1628 bufferwsize
/=(bank
->bus_width
/ bank
->chip_width
);
1631 /* Check for valid size */
1632 if (wordcount
> bufferwsize
)
1634 LOG_ERROR("Number of data words %" PRId32
" exceeds available buffersize %" PRId32
, wordcount
, buffersize
);
1635 return ERROR_FLASH_OPERATION_FAILED
;
1638 /* Write to flash buffer */
1639 cfi_intel_clear_status_register(bank
);
1641 /* Initiate buffer operation _*/
1642 if ((retval
= cfi_send_command(bank
, 0xe8, address
)) != ERROR_OK
)
1646 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1648 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1653 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32
", address %" PRIx32
, bank
->base
, address
);
1654 return ERROR_FLASH_OPERATION_FAILED
;
1657 /* Write buffer wordcount-1 and data words */
1658 if ((retval
= cfi_send_command(bank
, bufferwsize
-1, address
)) != ERROR_OK
)
1663 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
)) != ERROR_OK
)
1668 /* Commit write operation */
1669 if ((retval
= cfi_send_command(bank
, 0xd0, address
)) != ERROR_OK
)
1673 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1675 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1680 LOG_ERROR("Buffer write at base 0x%" PRIx32
", address %" PRIx32
" failed.", bank
->base
, address
);
1681 return ERROR_FLASH_OPERATION_FAILED
;
1687 static int cfi_spansion_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
1690 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1691 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1692 struct target
*target
= bank
->target
;
1694 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
1699 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
1704 if ((retval
= cfi_send_command(bank
, 0xa0, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
1709 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, word
)) != ERROR_OK
)
1714 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1716 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1721 LOG_ERROR("couldn't write word at base 0x%" PRIx32
", address %" PRIx32
, bank
->base
, address
);
1722 return ERROR_FLASH_OPERATION_FAILED
;
1728 static int cfi_spansion_write_words(struct flash_bank
*bank
, uint8_t *word
, uint32_t wordcount
, uint32_t address
)
1731 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1732 struct target
*target
= bank
->target
;
1733 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1735 /* Calculate buffer size and boundary mask */
1736 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1737 uint32_t buffermask
= buffersize
-1;
1738 uint32_t bufferwsize
;
1740 /* Check for valid range */
1741 if (address
& buffermask
)
1743 LOG_ERROR("Write address at base 0x%" PRIx32
", address %" PRIx32
" not aligned to 2^%d boundary", bank
->base
, address
, cfi_info
->max_buf_write_size
);
1744 return ERROR_FLASH_OPERATION_FAILED
;
1746 switch (bank
->chip_width
)
1748 case 4 : bufferwsize
= buffersize
/ 4; break;
1749 case 2 : bufferwsize
= buffersize
/ 2; break;
1750 case 1 : bufferwsize
= buffersize
; break;
1752 LOG_ERROR("Unsupported chip width %d", bank
->chip_width
);
1753 return ERROR_FLASH_OPERATION_FAILED
;
1756 bufferwsize
/=(bank
->bus_width
/ bank
->chip_width
);
1758 /* Check for valid size */
1759 if (wordcount
> bufferwsize
)
1761 LOG_ERROR("Number of data words %" PRId32
" exceeds available buffersize %" PRId32
, wordcount
, buffersize
);
1762 return ERROR_FLASH_OPERATION_FAILED
;
1766 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
1771 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
1776 // Buffer load command
1777 if ((retval
= cfi_send_command(bank
, 0x25, address
)) != ERROR_OK
)
1782 /* Write buffer wordcount-1 and data words */
1783 if ((retval
= cfi_send_command(bank
, bufferwsize
-1, address
)) != ERROR_OK
)
1788 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
)) != ERROR_OK
)
1793 /* Commit write operation */
1794 if ((retval
= cfi_send_command(bank
, 0x29, address
)) != ERROR_OK
)
1799 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1801 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1806 LOG_ERROR("couldn't write block at base 0x%" PRIx32
", address %" PRIx32
", size %" PRIx32
, bank
->base
, address
, bufferwsize
);
1807 return ERROR_FLASH_OPERATION_FAILED
;
1813 static int cfi_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
1815 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1817 switch (cfi_info
->pri_id
)
1821 return cfi_intel_write_word(bank
, word
, address
);
1824 return cfi_spansion_write_word(bank
, word
, address
);
1827 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1831 return ERROR_FLASH_OPERATION_FAILED
;
1834 static int cfi_write_words(struct flash_bank
*bank
, uint8_t *word
, uint32_t wordcount
, uint32_t address
)
1836 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1838 switch (cfi_info
->pri_id
)
1842 return cfi_intel_write_words(bank
, word
, wordcount
, address
);
1845 return cfi_spansion_write_words(bank
, word
, wordcount
, address
);
1848 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1852 return ERROR_FLASH_OPERATION_FAILED
;
1855 static int cfi_write(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
)
1857 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1858 struct target
*target
= bank
->target
;
1859 uint32_t address
= bank
->base
+ offset
; /* address of first byte to be programmed */
1860 uint32_t write_p
, copy_p
;
1861 int align
; /* number of unaligned bytes */
1862 int blk_count
; /* number of bus_width bytes for block copy */
1863 uint8_t current_word
[CFI_MAX_BUS_WIDTH
* 4]; /* word (bus_width size) currently being programmed */
1867 if (bank
->target
->state
!= TARGET_HALTED
)
1869 LOG_ERROR("Target not halted");
1870 return ERROR_TARGET_NOT_HALTED
;
1873 if (offset
+ count
> bank
->size
)
1874 return ERROR_FLASH_DST_OUT_OF_BANK
;
1876 if (cfi_info
->qry
[0] != 'Q')
1877 return ERROR_FLASH_BANK_NOT_PROBED
;
1879 /* start at the first byte of the first word (bus_width size) */
1880 write_p
= address
& ~(bank
->bus_width
- 1);
1881 if ((align
= address
- write_p
) != 0)
1883 LOG_INFO("Fixup %d unaligned head bytes", align
);
1885 for (i
= 0; i
< bank
->bus_width
; i
++)
1886 current_word
[i
] = 0;
1889 /* copy bytes before the first write address */
1890 for (i
= 0; i
< align
; ++i
, ++copy_p
)
1893 if ((retval
= target_read_memory(target
, copy_p
, 1, 1, &byte
)) != ERROR_OK
)
1897 cfi_add_byte(bank
, current_word
, byte
);
1900 /* add bytes from the buffer */
1901 for (; (i
< bank
->bus_width
) && (count
> 0); i
++)
1903 cfi_add_byte(bank
, current_word
, *buffer
++);
1908 /* if the buffer is already finished, copy bytes after the last write address */
1909 for (; (count
== 0) && (i
< bank
->bus_width
); ++i
, ++copy_p
)
1912 if ((retval
= target_read_memory(target
, copy_p
, 1, 1, &byte
)) != ERROR_OK
)
1916 cfi_add_byte(bank
, current_word
, byte
);
1919 retval
= cfi_write_word(bank
, current_word
, write_p
);
1920 if (retval
!= ERROR_OK
)
1925 /* handle blocks of bus_size aligned bytes */
1926 blk_count
= count
& ~(bank
->bus_width
- 1); /* round down, leave tail bytes */
1927 switch (cfi_info
->pri_id
)
1929 /* try block writes (fails without working area) */
1932 retval
= cfi_intel_write_block(bank
, buffer
, write_p
, blk_count
);
1935 retval
= cfi_spansion_write_block(bank
, buffer
, write_p
, blk_count
);
1938 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1939 retval
= ERROR_FLASH_OPERATION_FAILED
;
1942 if (retval
== ERROR_OK
)
1944 /* Increment pointers and decrease count on succesful block write */
1945 buffer
+= blk_count
;
1946 write_p
+= blk_count
;
1951 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
1953 //adjust buffersize for chip width
1954 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1955 uint32_t buffermask
= buffersize
-1;
1956 uint32_t bufferwsize
;
1958 switch (bank
->chip_width
)
1960 case 4 : bufferwsize
= buffersize
/ 4; break;
1961 case 2 : bufferwsize
= buffersize
/ 2; break;
1962 case 1 : bufferwsize
= buffersize
; break;
1964 LOG_ERROR("Unsupported chip width %d", bank
->chip_width
);
1965 return ERROR_FLASH_OPERATION_FAILED
;
1968 bufferwsize
/=(bank
->bus_width
/ bank
->chip_width
);
1970 /* fall back to memory writes */
1971 while (count
>= (uint32_t)bank
->bus_width
)
1974 if ((write_p
& 0xff) == 0)
1976 LOG_INFO("Programming at %08" PRIx32
", count %08" PRIx32
" bytes remaining", write_p
, count
);
1979 if ((bufferwsize
> 0) && (count
>= buffersize
) && !(write_p
& buffermask
))
1981 retval
= cfi_write_words(bank
, buffer
, bufferwsize
, write_p
);
1982 if (retval
== ERROR_OK
)
1984 buffer
+= buffersize
;
1985 write_p
+= buffersize
;
1986 count
-= buffersize
;
1990 /* try the slow way? */
1993 for (i
= 0; i
< bank
->bus_width
; i
++)
1994 current_word
[i
] = 0;
1996 for (i
= 0; i
< bank
->bus_width
; i
++)
1998 cfi_add_byte(bank
, current_word
, *buffer
++);
2001 retval
= cfi_write_word(bank
, current_word
, write_p
);
2002 if (retval
!= ERROR_OK
)
2005 write_p
+= bank
->bus_width
;
2006 count
-= bank
->bus_width
;
2014 /* return to read array mode, so we can read from flash again for padding */
2015 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
2020 /* handle unaligned tail bytes */
2023 LOG_INFO("Fixup %" PRId32
" unaligned tail bytes", count
);
2026 for (i
= 0; i
< bank
->bus_width
; i
++)
2027 current_word
[i
] = 0;
2029 for (i
= 0; (i
< bank
->bus_width
) && (count
> 0); ++i
, ++copy_p
)
2031 cfi_add_byte(bank
, current_word
, *buffer
++);
2034 for (; i
< bank
->bus_width
; ++i
, ++copy_p
)
2037 if ((retval
= target_read_memory(target
, copy_p
, 1, 1, &byte
)) != ERROR_OK
)
2041 cfi_add_byte(bank
, current_word
, byte
);
2043 retval
= cfi_write_word(bank
, current_word
, write_p
);
2044 if (retval
!= ERROR_OK
)
2048 /* return to read array mode */
2049 return cfi_reset(bank
);
2052 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank
*bank
, void *param
)
2055 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2056 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2058 pri_ext
->_reversed_geometry
= 1;
2061 static void cfi_fixup_0002_erase_regions(struct flash_bank
*bank
, void *param
)
2064 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2065 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2068 if ((pri_ext
->_reversed_geometry
) || (pri_ext
->TopBottom
== 3))
2070 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2072 for (i
= 0; i
< cfi_info
->num_erase_regions
/ 2; i
++)
2074 int j
= (cfi_info
->num_erase_regions
- 1) - i
;
2077 swap
= cfi_info
->erase_region_info
[i
];
2078 cfi_info
->erase_region_info
[i
] = cfi_info
->erase_region_info
[j
];
2079 cfi_info
->erase_region_info
[j
] = swap
;
2084 static void cfi_fixup_0002_unlock_addresses(struct flash_bank
*bank
, void *param
)
2086 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2087 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2088 struct cfi_unlock_addresses
*unlock_addresses
= param
;
2090 pri_ext
->_unlock1
= unlock_addresses
->unlock1
;
2091 pri_ext
->_unlock2
= unlock_addresses
->unlock2
;
2095 static int cfi_query_string(struct flash_bank
*bank
, int address
)
2097 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2100 if ((retval
= cfi_send_command(bank
, 0x98, flash_address(bank
, 0, address
))) != ERROR_OK
)
2105 cfi_info
->qry
[0] = cfi_query_u8(bank
, 0, 0x10);
2106 cfi_info
->qry
[1] = cfi_query_u8(bank
, 0, 0x11);
2107 cfi_info
->qry
[2] = cfi_query_u8(bank
, 0, 0x12);
2109 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2]);
2111 if ((cfi_info
->qry
[0] != 'Q') || (cfi_info
->qry
[1] != 'R') || (cfi_info
->qry
[2] != 'Y'))
2113 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
2117 LOG_ERROR("Could not probe bank: no QRY");
2118 return ERROR_FLASH_BANK_INVALID
;
2124 static int cfi_probe(struct flash_bank
*bank
)
2126 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2127 struct target
*target
= bank
->target
;
2128 int num_sectors
= 0;
2131 uint32_t unlock1
= 0x555;
2132 uint32_t unlock2
= 0x2aa;
2135 if (bank
->target
->state
!= TARGET_HALTED
)
2137 LOG_ERROR("Target not halted");
2138 return ERROR_TARGET_NOT_HALTED
;
2141 cfi_info
->probed
= 0;
2143 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2144 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2146 if (cfi_info
->jedec_probe
)
2152 /* switch to read identifier codes mode ("AUTOSELECT") */
2153 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, unlock1
))) != ERROR_OK
)
2157 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, unlock2
))) != ERROR_OK
)
2161 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, unlock1
))) != ERROR_OK
)
2166 if (bank
->chip_width
== 1)
2168 uint8_t manufacturer
, device_id
;
2169 if ((retval
= target_read_u8(target
, flash_address(bank
, 0, 0x00), &manufacturer
)) != ERROR_OK
)
2173 if ((retval
= target_read_u8(target
, flash_address(bank
, 0, 0x01), &device_id
)) != ERROR_OK
)
2177 cfi_info
->manufacturer
= manufacturer
;
2178 cfi_info
->device_id
= device_id
;
2180 else if (bank
->chip_width
== 2)
2182 if ((retval
= target_read_u16(target
, flash_address(bank
, 0, 0x00), &cfi_info
->manufacturer
)) != ERROR_OK
)
2186 if ((retval
= target_read_u16(target
, flash_address(bank
, 0, 0x01), &cfi_info
->device_id
)) != ERROR_OK
)
2192 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info
->manufacturer
, cfi_info
->device_id
);
2193 /* switch back to read array mode */
2194 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
2199 /* check device/manufacturer ID for known non-CFI flashes. */
2200 cfi_fixup_non_cfi(bank
);
2202 /* query only if this is a CFI compatible flash,
2203 * otherwise the relevant info has already been filled in
2205 if (cfi_info
->not_cfi
== 0)
2209 /* enter CFI query mode
2210 * according to JEDEC Standard No. 68.01,
2211 * a single bus sequence with address = 0x55, data = 0x98 should put
2212 * the device into CFI query mode.
2214 * SST flashes clearly violate this, and we will consider them incompatbile for now
2217 retval
= cfi_query_string(bank
, 0x55);
2218 if (retval
!= ERROR_OK
)
2221 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2222 * be harmless enough:
2224 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2226 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2227 retval
= cfi_query_string(bank
, 0x555);
2229 if (retval
!= ERROR_OK
)
2232 cfi_info
->pri_id
= cfi_query_u16(bank
, 0, 0x13);
2233 cfi_info
->pri_addr
= cfi_query_u16(bank
, 0, 0x15);
2234 cfi_info
->alt_id
= cfi_query_u16(bank
, 0, 0x17);
2235 cfi_info
->alt_addr
= cfi_query_u16(bank
, 0, 0x19);
2237 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2239 cfi_info
->vcc_min
= cfi_query_u8(bank
, 0, 0x1b);
2240 cfi_info
->vcc_max
= cfi_query_u8(bank
, 0, 0x1c);
2241 cfi_info
->vpp_min
= cfi_query_u8(bank
, 0, 0x1d);
2242 cfi_info
->vpp_max
= cfi_query_u8(bank
, 0, 0x1e);
2243 cfi_info
->word_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x1f);
2244 cfi_info
->buf_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x20);
2245 cfi_info
->block_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x21);
2246 cfi_info
->chip_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x22);
2247 cfi_info
->word_write_timeout_max
= cfi_query_u8(bank
, 0, 0x23);
2248 cfi_info
->buf_write_timeout_max
= cfi_query_u8(bank
, 0, 0x24);
2249 cfi_info
->block_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x25);
2250 cfi_info
->chip_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x26);
2252 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2253 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2254 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2255 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2256 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2257 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
2258 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
2259 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2260 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2261 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2262 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2264 cfi_info
->dev_size
= 1 << cfi_query_u8(bank
, 0, 0x27);
2265 cfi_info
->interface_desc
= cfi_query_u16(bank
, 0, 0x28);
2266 cfi_info
->max_buf_write_size
= cfi_query_u16(bank
, 0, 0x2a);
2267 cfi_info
->num_erase_regions
= cfi_query_u8(bank
, 0, 0x2c);
2269 LOG_DEBUG("size: 0x%" PRIx32
", interface desc: %i, max buffer write size: %x", cfi_info
->dev_size
, cfi_info
->interface_desc
, (1 << cfi_info
->max_buf_write_size
));
2271 if (cfi_info
->num_erase_regions
)
2273 cfi_info
->erase_region_info
= malloc(4 * cfi_info
->num_erase_regions
);
2274 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2276 cfi_info
->erase_region_info
[i
] = cfi_query_u32(bank
, 0, 0x2d + (4 * i
));
2277 LOG_DEBUG("erase region[%i]: %" PRIu32
" blocks of size 0x%" PRIx32
"",
2279 (cfi_info
->erase_region_info
[i
] & 0xffff) + 1,
2280 (cfi_info
->erase_region_info
[i
] >> 16) * 256);
2285 cfi_info
->erase_region_info
= NULL
;
2288 /* We need to read the primary algorithm extended query table before calculating
2289 * the sector layout to be able to apply fixups
2291 switch (cfi_info
->pri_id
)
2293 /* Intel command set (standard and extended) */
2296 cfi_read_intel_pri_ext(bank
);
2298 /* AMD/Spansion, Atmel, ... command set */
2300 cfi_info
->status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
; /* default for all CFI flashs */
2301 cfi_read_0002_pri_ext(bank
);
2304 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2308 /* return to read array mode
2309 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2311 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
2315 } /* end CFI case */
2317 /* apply fixups depending on the primary command set */
2318 switch (cfi_info
->pri_id
)
2320 /* Intel command set (standard and extended) */
2323 cfi_fixup(bank
, cfi_0001_fixups
);
2325 /* AMD/Spansion, Atmel, ... command set */
2327 cfi_fixup(bank
, cfi_0002_fixups
);
2330 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2334 if ((cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
) != bank
->size
)
2336 LOG_WARNING("configuration specifies 0x%" PRIx32
" size, but a 0x%" PRIx32
" size flash was found", bank
->size
, cfi_info
->dev_size
);
2339 if (cfi_info
->num_erase_regions
== 0)
2341 /* a device might have only one erase block, spanning the whole device */
2342 bank
->num_sectors
= 1;
2343 bank
->sectors
= malloc(sizeof(struct flash_sector
));
2345 bank
->sectors
[sector
].offset
= 0x0;
2346 bank
->sectors
[sector
].size
= bank
->size
;
2347 bank
->sectors
[sector
].is_erased
= -1;
2348 bank
->sectors
[sector
].is_protected
= -1;
2352 uint32_t offset
= 0;
2354 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2356 num_sectors
+= (cfi_info
->erase_region_info
[i
] & 0xffff) + 1;
2359 bank
->num_sectors
= num_sectors
;
2360 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
2362 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2365 for (j
= 0; j
< (cfi_info
->erase_region_info
[i
] & 0xffff) + 1; j
++)
2367 bank
->sectors
[sector
].offset
= offset
;
2368 bank
->sectors
[sector
].size
= ((cfi_info
->erase_region_info
[i
] >> 16) * 256) * bank
->bus_width
/ bank
->chip_width
;
2369 offset
+= bank
->sectors
[sector
].size
;
2370 bank
->sectors
[sector
].is_erased
= -1;
2371 bank
->sectors
[sector
].is_protected
= -1;
2375 if (offset
!= (cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
))
2377 LOG_WARNING("CFI size is 0x%" PRIx32
", but total sector size is 0x%" PRIx32
"", \
2378 (cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
), offset
);
2382 cfi_info
->probed
= 1;
2387 static int cfi_auto_probe(struct flash_bank
*bank
)
2389 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2390 if (cfi_info
->probed
)
2392 return cfi_probe(bank
);
2395 static int cfi_intel_protect_check(struct flash_bank
*bank
)
2398 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2399 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2402 /* check if block lock bits are supported on this device */
2403 if (!(pri_ext
->blk_status_reg_mask
& 0x1))
2404 return ERROR_FLASH_OPERATION_FAILED
;
2406 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, 0x55))) != ERROR_OK
)
2411 for (i
= 0; i
< bank
->num_sectors
; i
++)
2413 uint8_t block_status
= cfi_get_u8(bank
, i
, 0x2);
2415 if (block_status
& 1)
2416 bank
->sectors
[i
].is_protected
= 1;
2418 bank
->sectors
[i
].is_protected
= 0;
2421 return cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0));
2424 static int cfi_spansion_protect_check(struct flash_bank
*bank
)
2427 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2428 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2431 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
2436 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
2441 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
2446 for (i
= 0; i
< bank
->num_sectors
; i
++)
2448 uint8_t block_status
= cfi_get_u8(bank
, i
, 0x2);
2450 if (block_status
& 1)
2451 bank
->sectors
[i
].is_protected
= 1;
2453 bank
->sectors
[i
].is_protected
= 0;
2456 return cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0));
2459 static int cfi_protect_check(struct flash_bank
*bank
)
2461 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2463 if (bank
->target
->state
!= TARGET_HALTED
)
2465 LOG_ERROR("Target not halted");
2466 return ERROR_TARGET_NOT_HALTED
;
2469 if (cfi_info
->qry
[0] != 'Q')
2470 return ERROR_FLASH_BANK_NOT_PROBED
;
2472 switch (cfi_info
->pri_id
)
2476 return cfi_intel_protect_check(bank
);
2479 return cfi_spansion_protect_check(bank
);
2482 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2489 static int cfi_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
2492 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2494 if (cfi_info
->qry
[0] == (char)-1)
2496 printed
= snprintf(buf
, buf_size
, "\ncfi flash bank not probed yet\n");
2500 if (cfi_info
->not_cfi
== 0)
2501 printed
= snprintf(buf
, buf_size
, "\ncfi information:\n");
2503 printed
= snprintf(buf
, buf_size
, "\nnon-cfi flash:\n");
2505 buf_size
-= printed
;
2507 printed
= snprintf(buf
, buf_size
, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2508 cfi_info
->manufacturer
, cfi_info
->device_id
);
2510 buf_size
-= printed
;
2512 if (cfi_info
->not_cfi
== 0)
2514 printed
= snprintf(buf
, buf_size
, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2516 buf_size
-= printed
;
2518 printed
= snprintf(buf
, buf_size
, "Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x\n",
2519 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2520 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2521 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2522 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2524 buf_size
-= printed
;
2526 printed
= snprintf(buf
, buf_size
, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2527 1 << cfi_info
->word_write_timeout_typ
,
2528 1 << cfi_info
->buf_write_timeout_typ
,
2529 1 << cfi_info
->block_erase_timeout_typ
,
2530 1 << cfi_info
->chip_erase_timeout_typ
);
2532 buf_size
-= printed
;
2534 printed
= snprintf(buf
, buf_size
, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2535 (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2536 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2537 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2538 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2540 buf_size
-= printed
;
2542 printed
= snprintf(buf
, buf_size
, "size: 0x%" PRIx32
", interface desc: %i, max buffer write size: %x\n",
2544 cfi_info
->interface_desc
,
2545 1 << cfi_info
->max_buf_write_size
);
2547 buf_size
-= printed
;
2549 switch (cfi_info
->pri_id
)
2553 cfi_intel_info(bank
, buf
, buf_size
);
2556 cfi_spansion_info(bank
, buf
, buf_size
);
2559 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2567 struct flash_driver cfi_flash
= {
2569 .flash_bank_command
= cfi_flash_bank_command
,
2571 .protect
= cfi_protect
,
2574 .auto_probe
= cfi_auto_probe
,
2575 .erase_check
= default_flash_blank_check
,
2576 .protect_check
= cfi_protect_check
,
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