1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
6 * Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com> *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
30 #include <target/arm.h>
31 #include <helper/binarybuffer.h>
32 #include <target/algorithm.h>
35 #define CFI_MAX_BUS_WIDTH 4
36 #define CFI_MAX_CHIP_WIDTH 4
38 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
39 #define CFI_MAX_INTEL_CODESIZE 256
41 static struct cfi_unlock_addresses cfi_unlock_addresses
[] =
43 [CFI_UNLOCK_555_2AA
] = { .unlock1
= 0x555, .unlock2
= 0x2aa },
44 [CFI_UNLOCK_5555_2AAA
] = { .unlock1
= 0x5555, .unlock2
= 0x2aaa },
47 /* CFI fixups foward declarations */
48 static void cfi_fixup_0002_erase_regions(struct flash_bank
*flash
, void *param
);
49 static void cfi_fixup_0002_unlock_addresses(struct flash_bank
*flash
, void *param
);
50 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank
*flash
, void *param
);
52 /* fixup after reading cmdset 0002 primary query table */
53 static const struct cfi_fixup cfi_0002_fixups
[] = {
54 {CFI_MFR_SST
, 0x00D4, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
55 {CFI_MFR_SST
, 0x00D5, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
56 {CFI_MFR_SST
, 0x00D6, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
57 {CFI_MFR_SST
, 0x00D7, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
58 {CFI_MFR_SST
, 0x2780, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
59 {CFI_MFR_ATMEL
, 0x00C8, cfi_fixup_atmel_reversed_erase_regions
, NULL
},
60 {CFI_MFR_FUJITSU
, 0x226b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
61 {CFI_MFR_AMIC
, 0xb31a, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
62 {CFI_MFR_MX
, 0x225b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
63 {CFI_MFR_AMD
, 0x225b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
64 {CFI_MFR_ANY
, CFI_ID_ANY
, cfi_fixup_0002_erase_regions
, NULL
},
68 /* fixup after reading cmdset 0001 primary query table */
69 static const struct cfi_fixup cfi_0001_fixups
[] = {
73 static void cfi_fixup(struct flash_bank
*bank
, const struct cfi_fixup
*fixups
)
75 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
76 const struct cfi_fixup
*f
;
78 for (f
= fixups
; f
->fixup
; f
++)
80 if (((f
->mfr
== CFI_MFR_ANY
) || (f
->mfr
== cfi_info
->manufacturer
)) &&
81 ((f
->id
== CFI_ID_ANY
) || (f
->id
== cfi_info
->device_id
)))
83 f
->fixup(bank
, f
->param
);
88 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
89 static __inline__
uint32_t flash_address(struct flash_bank
*bank
, int sector
, uint32_t offset
)
91 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
93 if (cfi_info
->x16_as_x8
) offset
*= 2;
95 /* while the sector list isn't built, only accesses to sector 0 work */
97 return bank
->base
+ offset
* bank
->bus_width
;
102 LOG_ERROR("BUG: sector list not yet built");
105 return bank
->base
+ bank
->sectors
[sector
].offset
+ offset
* bank
->bus_width
;
110 static void cfi_command(struct flash_bank
*bank
, uint8_t cmd
, uint8_t *cmd_buf
)
114 /* clear whole buffer, to ensure bits that exceed the bus_width
117 for (i
= 0; i
< CFI_MAX_BUS_WIDTH
; i
++)
120 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
122 for (i
= bank
->bus_width
; i
> 0; i
--)
124 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
129 for (i
= 1; i
<= bank
->bus_width
; i
++)
131 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
136 static int cfi_send_command(struct flash_bank
*bank
, uint8_t cmd
, uint32_t address
)
138 uint8_t command
[CFI_MAX_BUS_WIDTH
];
140 cfi_command(bank
, cmd
, command
);
141 return target_write_memory(bank
->target
, address
, bank
->bus_width
, 1, command
);
144 /* read unsigned 8-bit value from the bank
145 * flash banks are expected to be made of similar chips
146 * the query result should be the same for all
148 static uint8_t cfi_query_u8(struct flash_bank
*bank
, int sector
, uint32_t offset
)
150 struct target
*target
= bank
->target
;
151 uint8_t data
[CFI_MAX_BUS_WIDTH
];
153 target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
155 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
158 return data
[bank
->bus_width
- 1];
161 /* read unsigned 8-bit value from the bank
162 * in case of a bank made of multiple chips,
163 * the individual values are ORed
165 static uint8_t cfi_get_u8(struct flash_bank
*bank
, int sector
, uint32_t offset
)
167 struct target
*target
= bank
->target
;
168 uint8_t data
[CFI_MAX_BUS_WIDTH
];
171 target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
173 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
175 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
183 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
184 value
|= data
[bank
->bus_width
- 1 - i
];
190 static uint16_t cfi_query_u16(struct flash_bank
*bank
, int sector
, uint32_t offset
)
192 struct target
*target
= bank
->target
;
193 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
194 uint8_t data
[CFI_MAX_BUS_WIDTH
* 2];
196 if (cfi_info
->x16_as_x8
)
199 for (i
= 0;i
< 2;i
++)
200 target_read_memory(target
, flash_address(bank
, sector
, offset
+ i
), bank
->bus_width
, 1,
201 &data
[i
*bank
->bus_width
]);
204 target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 2, data
);
206 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
207 return data
[0] | data
[bank
->bus_width
] << 8;
209 return data
[bank
->bus_width
- 1] | data
[(2 * bank
->bus_width
) - 1] << 8;
212 static uint32_t cfi_query_u32(struct flash_bank
*bank
, int sector
, uint32_t offset
)
214 struct target
*target
= bank
->target
;
215 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
216 uint8_t data
[CFI_MAX_BUS_WIDTH
* 4];
218 if (cfi_info
->x16_as_x8
)
221 for (i
= 0;i
< 4;i
++)
222 target_read_memory(target
, flash_address(bank
, sector
, offset
+ i
), bank
->bus_width
, 1,
223 &data
[i
*bank
->bus_width
]);
226 target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 4, data
);
228 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
229 return data
[0] | data
[bank
->bus_width
] << 8 | data
[bank
->bus_width
* 2] << 16 | data
[bank
->bus_width
* 3] << 24;
231 return data
[bank
->bus_width
- 1] | data
[(2* bank
->bus_width
) - 1] << 8 |
232 data
[(3 * bank
->bus_width
) - 1] << 16 | data
[(4 * bank
->bus_width
) - 1] << 24;
235 static void cfi_intel_clear_status_register(struct flash_bank
*bank
)
237 struct target
*target
= bank
->target
;
239 if (target
->state
!= TARGET_HALTED
)
241 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
245 cfi_send_command(bank
, 0x50, flash_address(bank
, 0, 0x0));
248 static uint8_t cfi_intel_wait_status_busy(struct flash_bank
*bank
, int timeout
)
252 while ((!((status
= cfi_get_u8(bank
, 0, 0x0)) & 0x80)) && (timeout
-- > 0))
254 LOG_DEBUG("status: 0x%x", status
);
258 /* mask out bit 0 (reserved) */
259 status
= status
& 0xfe;
261 LOG_DEBUG("status: 0x%x", status
);
263 if ((status
& 0x80) != 0x80)
265 LOG_ERROR("timeout while waiting for WSM to become ready");
267 else if (status
!= 0x80)
269 LOG_ERROR("status register: 0x%x", status
);
271 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
273 LOG_ERROR("Program suspended");
275 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
277 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
279 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
281 LOG_ERROR("Block Erase Suspended");
283 cfi_intel_clear_status_register(bank
);
289 static int cfi_spansion_wait_status_busy(struct flash_bank
*bank
, int timeout
)
291 uint8_t status
, oldstatus
;
292 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
294 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
297 status
= cfi_get_u8(bank
, 0, 0x0);
298 if ((status
^ oldstatus
) & 0x40) {
299 if (status
& cfi_info
->status_poll_mask
& 0x20) {
300 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
301 status
= cfi_get_u8(bank
, 0, 0x0);
302 if ((status
^ oldstatus
) & 0x40) {
303 LOG_ERROR("dq5 timeout, status: 0x%x", status
);
304 return(ERROR_FLASH_OPERATION_FAILED
);
306 LOG_DEBUG("status: 0x%x", status
);
310 } else { /* no toggle: finished, OK */
311 LOG_DEBUG("status: 0x%x", status
);
317 } while (timeout
-- > 0);
319 LOG_ERROR("timeout, status: 0x%x", status
);
321 return(ERROR_FLASH_BUSY
);
324 static int cfi_read_intel_pri_ext(struct flash_bank
*bank
)
327 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
328 struct cfi_intel_pri_ext
*pri_ext
= malloc(sizeof(struct cfi_intel_pri_ext
));
330 cfi_info
->pri_ext
= pri_ext
;
332 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
333 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
334 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
336 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
338 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
342 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
346 LOG_ERROR("Could not read bank flash bank information");
347 return ERROR_FLASH_BANK_INVALID
;
350 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
351 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
353 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
355 pri_ext
->feature_support
= cfi_query_u32(bank
, 0, cfi_info
->pri_addr
+ 5);
356 pri_ext
->suspend_cmd_support
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
357 pri_ext
->blk_status_reg_mask
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xa);
359 LOG_DEBUG("feature_support: 0x%" PRIx32
", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
360 pri_ext
->feature_support
,
361 pri_ext
->suspend_cmd_support
,
362 pri_ext
->blk_status_reg_mask
);
364 pri_ext
->vcc_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xc);
365 pri_ext
->vpp_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xd);
367 LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
368 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
369 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
371 pri_ext
->num_protection_fields
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xe);
372 if (pri_ext
->num_protection_fields
!= 1)
374 LOG_WARNING("expected one protection register field, but found %i", pri_ext
->num_protection_fields
);
377 pri_ext
->prot_reg_addr
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xf);
378 pri_ext
->fact_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x11);
379 pri_ext
->user_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x12);
381 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
386 static int cfi_read_spansion_pri_ext(struct flash_bank
*bank
)
389 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
390 struct cfi_spansion_pri_ext
*pri_ext
= malloc(sizeof(struct cfi_spansion_pri_ext
));
392 cfi_info
->pri_ext
= pri_ext
;
394 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
395 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
396 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
398 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
400 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
404 LOG_ERROR("Could not read spansion bank information");
405 return ERROR_FLASH_BANK_INVALID
;
408 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
409 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
411 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
413 pri_ext
->SiliconRevision
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
414 pri_ext
->EraseSuspend
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
415 pri_ext
->BlkProt
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
416 pri_ext
->TmpBlkUnprotect
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
417 pri_ext
->BlkProtUnprot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
418 pri_ext
->SimultaneousOps
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 10);
419 pri_ext
->BurstMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 11);
420 pri_ext
->PageMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 12);
421 pri_ext
->VppMin
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 13);
422 pri_ext
->VppMax
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 14);
423 pri_ext
->TopBottom
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 15);
425 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext
->SiliconRevision
,
426 pri_ext
->EraseSuspend
, pri_ext
->BlkProt
);
428 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext
->TmpBlkUnprotect
,
429 pri_ext
->BlkProtUnprot
, pri_ext
->SimultaneousOps
);
431 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext
->BurstMode
, pri_ext
->PageMode
);
434 LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
435 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
436 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
438 LOG_DEBUG("WP# protection 0x%x", pri_ext
->TopBottom
);
440 /* default values for implementation specific workarounds */
441 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
442 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
443 pri_ext
->_reversed_geometry
= 0;
448 static int cfi_read_atmel_pri_ext(struct flash_bank
*bank
)
451 struct cfi_atmel_pri_ext atmel_pri_ext
;
452 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
453 struct cfi_spansion_pri_ext
*pri_ext
= malloc(sizeof(struct cfi_spansion_pri_ext
));
455 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
456 * but a different primary extended query table.
457 * We read the atmel table, and prepare a valid AMD/Spansion query table.
460 memset(pri_ext
, 0, sizeof(struct cfi_spansion_pri_ext
));
462 cfi_info
->pri_ext
= pri_ext
;
464 atmel_pri_ext
.pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
465 atmel_pri_ext
.pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
466 atmel_pri_ext
.pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
468 if ((atmel_pri_ext
.pri
[0] != 'P') || (atmel_pri_ext
.pri
[1] != 'R') || (atmel_pri_ext
.pri
[2] != 'I'))
470 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
474 LOG_ERROR("Could not read atmel bank information");
475 return ERROR_FLASH_BANK_INVALID
;
478 pri_ext
->pri
[0] = atmel_pri_ext
.pri
[0];
479 pri_ext
->pri
[1] = atmel_pri_ext
.pri
[1];
480 pri_ext
->pri
[2] = atmel_pri_ext
.pri
[2];
482 atmel_pri_ext
.major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
483 atmel_pri_ext
.minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
485 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext
.pri
[0], atmel_pri_ext
.pri
[1], atmel_pri_ext
.pri
[2], atmel_pri_ext
.major_version
, atmel_pri_ext
.minor_version
);
487 pri_ext
->major_version
= atmel_pri_ext
.major_version
;
488 pri_ext
->minor_version
= atmel_pri_ext
.minor_version
;
490 atmel_pri_ext
.features
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
491 atmel_pri_ext
.bottom_boot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
492 atmel_pri_ext
.burst_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
493 atmel_pri_ext
.page_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
495 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
496 atmel_pri_ext
.features
, atmel_pri_ext
.bottom_boot
, atmel_pri_ext
.burst_mode
, atmel_pri_ext
.page_mode
);
498 if (atmel_pri_ext
.features
& 0x02)
499 pri_ext
->EraseSuspend
= 2;
501 if (atmel_pri_ext
.bottom_boot
)
502 pri_ext
->TopBottom
= 2;
504 pri_ext
->TopBottom
= 3;
506 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
507 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
512 static int cfi_read_0002_pri_ext(struct flash_bank
*bank
)
514 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
516 if (cfi_info
->manufacturer
== CFI_MFR_ATMEL
)
518 return cfi_read_atmel_pri_ext(bank
);
522 return cfi_read_spansion_pri_ext(bank
);
526 static int cfi_spansion_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
529 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
530 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
532 printed
= snprintf(buf
, buf_size
, "\nSpansion primary algorithm extend information:\n");
536 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0],
537 pri_ext
->pri
[1], pri_ext
->pri
[2],
538 pri_ext
->major_version
, pri_ext
->minor_version
);
542 printed
= snprintf(buf
, buf_size
, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
543 (pri_ext
->SiliconRevision
) >> 2,
544 (pri_ext
->SiliconRevision
) & 0x03);
548 printed
= snprintf(buf
, buf_size
, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
549 pri_ext
->EraseSuspend
,
554 printed
= snprintf(buf
, buf_size
, "VppMin: %u.%x, VppMax: %u.%x\n",
555 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
556 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
561 static int cfi_intel_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
564 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
565 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
567 printed
= snprintf(buf
, buf_size
, "\nintel primary algorithm extend information:\n");
571 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
575 printed
= snprintf(buf
, buf_size
, "feature_support: 0x%" PRIx32
", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
579 printed
= snprintf(buf
, buf_size
, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
580 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
581 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
585 printed
= snprintf(buf
, buf_size
, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
590 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
592 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command
)
594 struct cfi_flash_bank
*cfi_info
;
598 LOG_WARNING("incomplete flash_bank cfi configuration");
599 return ERROR_FLASH_BANK_INVALID
;
602 if ((bank
->chip_width
> CFI_MAX_CHIP_WIDTH
)
603 || (bank
->bus_width
> CFI_MAX_BUS_WIDTH
))
605 LOG_ERROR("chip and bus width have to specified in bytes");
606 return ERROR_FLASH_BANK_INVALID
;
609 cfi_info
= malloc(sizeof(struct cfi_flash_bank
));
610 cfi_info
->probed
= 0;
611 bank
->driver_priv
= cfi_info
;
613 cfi_info
->write_algorithm
= NULL
;
615 cfi_info
->x16_as_x8
= 0;
616 cfi_info
->jedec_probe
= 0;
617 cfi_info
->not_cfi
= 0;
619 for (unsigned i
= 6; i
< CMD_ARGC
; i
++)
621 if (strcmp(CMD_ARGV
[i
], "x16_as_x8") == 0)
623 cfi_info
->x16_as_x8
= 1;
625 else if (strcmp(CMD_ARGV
[i
], "jedec_probe") == 0)
627 cfi_info
->jedec_probe
= 1;
631 cfi_info
->write_algorithm
= NULL
;
633 /* bank wasn't probed yet */
634 cfi_info
->qry
[0] = -1;
639 static int cfi_intel_erase(struct flash_bank
*bank
, int first
, int last
)
642 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
645 cfi_intel_clear_status_register(bank
);
647 for (i
= first
; i
<= last
; i
++)
649 if ((retval
= cfi_send_command(bank
, 0x20, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
654 if ((retval
= cfi_send_command(bank
, 0xd0, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
659 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == 0x80)
660 bank
->sectors
[i
].is_erased
= 1;
663 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
668 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32
, i
, bank
->base
);
669 return ERROR_FLASH_OPERATION_FAILED
;
673 return cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0));
676 static int cfi_spansion_erase(struct flash_bank
*bank
, int first
, int last
)
679 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
680 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
683 for (i
= first
; i
<= last
; i
++)
685 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
690 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
695 if ((retval
= cfi_send_command(bank
, 0x80, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
700 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
705 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
710 if ((retval
= cfi_send_command(bank
, 0x30, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
715 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == ERROR_OK
)
716 bank
->sectors
[i
].is_erased
= 1;
719 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
724 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32
, i
, bank
->base
);
725 return ERROR_FLASH_OPERATION_FAILED
;
729 return cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0));
732 static int cfi_erase(struct flash_bank
*bank
, int first
, int last
)
734 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
736 if (bank
->target
->state
!= TARGET_HALTED
)
738 LOG_ERROR("Target not halted");
739 return ERROR_TARGET_NOT_HALTED
;
742 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
744 return ERROR_FLASH_SECTOR_INVALID
;
747 if (cfi_info
->qry
[0] != 'Q')
748 return ERROR_FLASH_BANK_NOT_PROBED
;
750 switch (cfi_info
->pri_id
)
754 return cfi_intel_erase(bank
, first
, last
);
757 return cfi_spansion_erase(bank
, first
, last
);
760 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
767 static int cfi_intel_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
770 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
771 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
772 struct target
*target
= bank
->target
; /* FIXME: to be removed */
773 uint8_t command
[CFI_MAX_BUS_WIDTH
]; /* FIXME: to be removed */
777 /* if the device supports neither legacy lock/unlock (bit 3) nor
778 * instant individual block locking (bit 5).
780 if (!(pri_ext
->feature_support
& 0x28))
781 return ERROR_FLASH_OPERATION_FAILED
;
783 cfi_intel_clear_status_register(bank
);
785 for (i
= first
; i
<= last
; i
++)
787 cfi_command(bank
, 0x60, command
); /* FIXME: to be removed */
788 LOG_DEBUG("address: 0x%4.4" PRIx32
", command: 0x%4.4" PRIx32
, flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
789 if ((retval
= cfi_send_command(bank
, 0x60, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
795 cfi_command(bank
, 0x01, command
); /* FIXME: to be removed */
796 LOG_DEBUG("address: 0x%4.4" PRIx32
", command: 0x%4.4" PRIx32
, flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
797 if ((retval
= cfi_send_command(bank
, 0x01, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
801 bank
->sectors
[i
].is_protected
= 1;
805 cfi_command(bank
, 0xd0, command
); /* FIXME: to be removed */
806 LOG_DEBUG("address: 0x%4.4" PRIx32
", command: 0x%4.4" PRIx32
, flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
807 if ((retval
= cfi_send_command(bank
, 0xd0, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
811 bank
->sectors
[i
].is_protected
= 0;
814 /* instant individual block locking doesn't require reading of the status register */
815 if (!(pri_ext
->feature_support
& 0x20))
817 /* Clear lock bits operation may take up to 1.4s */
818 cfi_intel_wait_status_busy(bank
, 1400);
822 uint8_t block_status
;
823 /* read block lock bit, to verify status */
824 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, 0x55))) != ERROR_OK
)
828 block_status
= cfi_get_u8(bank
, i
, 0x2);
830 if ((block_status
& 0x1) != set
)
832 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set
, block_status
);
833 if ((retval
= cfi_send_command(bank
, 0x70, flash_address(bank
, 0, 0x55))) != ERROR_OK
)
837 cfi_intel_wait_status_busy(bank
, 10);
840 return ERROR_FLASH_OPERATION_FAILED
;
850 /* if the device doesn't support individual block lock bits set/clear,
851 * all blocks have been unlocked in parallel, so we set those that should be protected
853 if ((!set
) && (!(pri_ext
->feature_support
& 0x20)))
855 for (i
= 0; i
< bank
->num_sectors
; i
++)
857 if (bank
->sectors
[i
].is_protected
== 1)
859 cfi_intel_clear_status_register(bank
);
861 if ((retval
= cfi_send_command(bank
, 0x60, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
866 if ((retval
= cfi_send_command(bank
, 0x01, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
871 cfi_intel_wait_status_busy(bank
, 100);
876 return cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0));
879 static int cfi_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
881 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
883 if (bank
->target
->state
!= TARGET_HALTED
)
885 LOG_ERROR("Target not halted");
886 return ERROR_TARGET_NOT_HALTED
;
889 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
891 LOG_ERROR("Invalid sector range");
892 return ERROR_FLASH_SECTOR_INVALID
;
895 if (cfi_info
->qry
[0] != 'Q')
896 return ERROR_FLASH_BANK_NOT_PROBED
;
898 switch (cfi_info
->pri_id
)
902 return cfi_intel_protect(bank
, set
, first
, last
);
905 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info
->pri_id
);
910 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
911 static void cfi_add_byte(struct flash_bank
*bank
, uint8_t *word
, uint8_t byte
)
913 /* struct target *target = bank->target; */
918 * The data to flash must not be changed in endian! We write a bytestrem in
919 * target byte order already. Only the control and status byte lane of the flash
920 * WSM is interpreted by the CPU in different ways, when read a uint16_t or uint32_t
921 * word (data seems to be in the upper or lower byte lane for uint16_t accesses).
925 if (target
->endianness
== TARGET_LITTLE_ENDIAN
)
929 for (i
= 0; i
< bank
->bus_width
- 1; i
++)
930 word
[i
] = word
[i
+ 1];
931 word
[bank
->bus_width
- 1] = byte
;
937 for (i
= bank
->bus_width
- 1; i
> 0; i
--)
938 word
[i
] = word
[i
- 1];
944 /* Convert code image to target endian */
945 /* FIXME create general block conversion fcts in target.c?) */
946 static void cfi_fix_code_endian(struct target
*target
, uint8_t *dest
, const uint32_t *src
, uint32_t count
)
949 for (i
= 0; i
< count
; i
++)
951 target_buffer_set_u32(target
, dest
, *src
);
957 static uint32_t cfi_command_val(struct flash_bank
*bank
, uint8_t cmd
)
959 struct target
*target
= bank
->target
;
961 uint8_t buf
[CFI_MAX_BUS_WIDTH
];
962 cfi_command(bank
, cmd
, buf
);
963 switch (bank
->bus_width
)
969 return target_buffer_get_u16(target
, buf
);
972 return target_buffer_get_u32(target
, buf
);
975 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
980 static int cfi_intel_write_block(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t address
, uint32_t count
)
982 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
983 struct target
*target
= bank
->target
;
984 struct reg_param reg_params
[7];
985 struct arm_algorithm armv4_5_info
;
986 struct working_area
*source
;
987 uint32_t buffer_size
= 32768;
988 uint32_t write_command_val
, busy_pattern_val
, error_pattern_val
;
990 /* algorithm register usage:
991 * r0: source address (in RAM)
992 * r1: target address (in Flash)
994 * r3: flash write command
995 * r4: status byte (returned to host)
996 * r5: busy test pattern
997 * r6: error test pattern
1000 static const uint32_t word_32_code
[] = {
1001 0xe4904004, /* loop: ldr r4, [r0], #4 */
1002 0xe5813000, /* str r3, [r1] */
1003 0xe5814000, /* str r4, [r1] */
1004 0xe5914000, /* busy: ldr r4, [r1] */
1005 0xe0047005, /* and r7, r4, r5 */
1006 0xe1570005, /* cmp r7, r5 */
1007 0x1afffffb, /* bne busy */
1008 0xe1140006, /* tst r4, r6 */
1009 0x1a000003, /* bne done */
1010 0xe2522001, /* subs r2, r2, #1 */
1011 0x0a000001, /* beq done */
1012 0xe2811004, /* add r1, r1 #4 */
1013 0xeafffff2, /* b loop */
1014 0xeafffffe /* done: b -2 */
1017 static const uint32_t word_16_code
[] = {
1018 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1019 0xe1c130b0, /* strh r3, [r1] */
1020 0xe1c140b0, /* strh r4, [r1] */
1021 0xe1d140b0, /* busy ldrh r4, [r1] */
1022 0xe0047005, /* and r7, r4, r5 */
1023 0xe1570005, /* cmp r7, r5 */
1024 0x1afffffb, /* bne busy */
1025 0xe1140006, /* tst r4, r6 */
1026 0x1a000003, /* bne done */
1027 0xe2522001, /* subs r2, r2, #1 */
1028 0x0a000001, /* beq done */
1029 0xe2811002, /* add r1, r1 #2 */
1030 0xeafffff2, /* b loop */
1031 0xeafffffe /* done: b -2 */
1034 static const uint32_t word_8_code
[] = {
1035 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1036 0xe5c13000, /* strb r3, [r1] */
1037 0xe5c14000, /* strb r4, [r1] */
1038 0xe5d14000, /* busy ldrb r4, [r1] */
1039 0xe0047005, /* and r7, r4, r5 */
1040 0xe1570005, /* cmp r7, r5 */
1041 0x1afffffb, /* bne busy */
1042 0xe1140006, /* tst r4, r6 */
1043 0x1a000003, /* bne done */
1044 0xe2522001, /* subs r2, r2, #1 */
1045 0x0a000001, /* beq done */
1046 0xe2811001, /* add r1, r1 #1 */
1047 0xeafffff2, /* b loop */
1048 0xeafffffe /* done: b -2 */
1050 uint8_t target_code
[4*CFI_MAX_INTEL_CODESIZE
];
1051 const uint32_t *target_code_src
;
1052 uint32_t target_code_size
;
1053 int retval
= ERROR_OK
;
1056 cfi_intel_clear_status_register(bank
);
1058 armv4_5_info
.common_magic
= ARM_COMMON_MAGIC
;
1059 armv4_5_info
.core_mode
= ARM_MODE_SVC
;
1060 armv4_5_info
.core_state
= ARM_STATE_ARM
;
1062 /* If we are setting up the write_algorith, we need target_code_src */
1063 /* if not we only need target_code_size. */
1065 /* However, we don't want to create multiple code paths, so we */
1066 /* do the unecessary evaluation of target_code_src, which the */
1067 /* compiler will probably nicely optimize away if not needed */
1069 /* prepare algorithm code for target endian */
1070 switch (bank
->bus_width
)
1073 target_code_src
= word_8_code
;
1074 target_code_size
= sizeof(word_8_code
);
1077 target_code_src
= word_16_code
;
1078 target_code_size
= sizeof(word_16_code
);
1081 target_code_src
= word_32_code
;
1082 target_code_size
= sizeof(word_32_code
);
1085 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1086 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1089 /* flash write code */
1090 if (!cfi_info
->write_algorithm
)
1092 if (target_code_size
> sizeof(target_code
))
1094 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1095 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1097 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
/ 4);
1099 /* Get memory for block write handler */
1100 retval
= target_alloc_working_area(target
, target_code_size
, &cfi_info
->write_algorithm
);
1101 if (retval
!= ERROR_OK
)
1103 LOG_WARNING("No working area available, can't do block memory writes");
1104 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1107 /* write algorithm code to working area */
1108 retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
, target_code_size
, target_code
);
1109 if (retval
!= ERROR_OK
)
1111 LOG_ERROR("Unable to write block write code to target");
1116 /* Get a workspace buffer for the data to flash starting with 32k size.
1117 Half size until buffer would be smaller 256 Bytem then fail back */
1118 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1119 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
)
1122 if (buffer_size
<= 256)
1124 LOG_WARNING("no large enough working area available, can't do block memory writes");
1125 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1130 /* setup algo registers */
1131 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1132 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1133 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1134 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1135 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
1136 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
1137 init_reg_param(®_params
[6], "r6", 32, PARAM_OUT
);
1139 /* prepare command and status register patterns */
1140 write_command_val
= cfi_command_val(bank
, 0x40);
1141 busy_pattern_val
= cfi_command_val(bank
, 0x80);
1142 error_pattern_val
= cfi_command_val(bank
, 0x7e);
1144 LOG_DEBUG("Using target buffer at 0x%08" PRIx32
" and of size 0x%04" PRIx32
, source
->address
, buffer_size
);
1146 /* Programming main loop */
1149 uint32_t thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1152 if ((retval
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
)) != ERROR_OK
)
1157 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1158 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1159 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1161 buf_set_u32(reg_params
[3].value
, 0, 32, write_command_val
);
1162 buf_set_u32(reg_params
[5].value
, 0, 32, busy_pattern_val
);
1163 buf_set_u32(reg_params
[6].value
, 0, 32, error_pattern_val
);
1165 LOG_DEBUG("Write 0x%04" PRIx32
" bytes to flash at 0x%08" PRIx32
, thisrun_count
, address
);
1167 /* Execute algorithm, assume breakpoint for last instruction */
1168 retval
= target_run_algorithm(target
, 0, NULL
, 7, reg_params
,
1169 cfi_info
->write_algorithm
->address
,
1170 cfi_info
->write_algorithm
->address
+ target_code_size
- sizeof(uint32_t),
1171 10000, /* 10s should be enough for max. 32k of data */
1174 /* On failure try a fall back to direct word writes */
1175 if (retval
!= ERROR_OK
)
1177 cfi_intel_clear_status_register(bank
);
1178 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1179 retval
= ERROR_FLASH_OPERATION_FAILED
;
1180 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1181 /* FIXME To allow fall back or recovery, we must save the actual status
1182 somewhere, so that a higher level code can start recovery. */
1186 /* Check return value from algo code */
1187 wsm_error
= buf_get_u32(reg_params
[4].value
, 0, 32) & error_pattern_val
;
1190 /* read status register (outputs debug inforation) */
1191 cfi_intel_wait_status_busy(bank
, 100);
1192 cfi_intel_clear_status_register(bank
);
1193 retval
= ERROR_FLASH_OPERATION_FAILED
;
1197 buffer
+= thisrun_count
;
1198 address
+= thisrun_count
;
1199 count
-= thisrun_count
;
1202 /* free up resources */
1205 target_free_working_area(target
, source
);
1207 if (cfi_info
->write_algorithm
)
1209 target_free_working_area(target
, cfi_info
->write_algorithm
);
1210 cfi_info
->write_algorithm
= NULL
;
1213 destroy_reg_param(®_params
[0]);
1214 destroy_reg_param(®_params
[1]);
1215 destroy_reg_param(®_params
[2]);
1216 destroy_reg_param(®_params
[3]);
1217 destroy_reg_param(®_params
[4]);
1218 destroy_reg_param(®_params
[5]);
1219 destroy_reg_param(®_params
[6]);
1224 static int cfi_spansion_write_block(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t address
, uint32_t count
)
1226 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1227 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1228 struct target
*target
= bank
->target
;
1229 struct reg_param reg_params
[10];
1230 struct arm_algorithm armv4_5_info
;
1231 struct working_area
*source
;
1232 uint32_t buffer_size
= 32768;
1234 int retval
, retvaltemp
;
1235 int exit_code
= ERROR_OK
;
1237 /* input parameters - */
1238 /* R0 = source address */
1239 /* R1 = destination address */
1240 /* R2 = number of writes */
1241 /* R3 = flash write command */
1242 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1243 /* output parameters - */
1244 /* R5 = 0x80 ok 0x00 bad */
1245 /* temp registers - */
1246 /* R6 = value read from flash to test status */
1247 /* R7 = holding register */
1248 /* unlock registers - */
1249 /* R8 = unlock1_addr */
1250 /* R9 = unlock1_cmd */
1251 /* R10 = unlock2_addr */
1252 /* R11 = unlock2_cmd */
1254 static const uint32_t word_32_code
[] = {
1255 /* 00008100 <sp_32_code>: */
1256 0xe4905004, /* ldr r5, [r0], #4 */
1257 0xe5889000, /* str r9, [r8] */
1258 0xe58ab000, /* str r11, [r10] */
1259 0xe5883000, /* str r3, [r8] */
1260 0xe5815000, /* str r5, [r1] */
1261 0xe1a00000, /* nop */
1263 /* 00008110 <sp_32_busy>: */
1264 0xe5916000, /* ldr r6, [r1] */
1265 0xe0257006, /* eor r7, r5, r6 */
1266 0xe0147007, /* ands r7, r4, r7 */
1267 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1268 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1269 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1270 0xe5916000, /* ldr r6, [r1] */
1271 0xe0257006, /* eor r7, r5, r6 */
1272 0xe0147007, /* ands r7, r4, r7 */
1273 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1274 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1275 0x1a000004, /* bne 8154 <sp_32_done> */
1277 /* 00008140 <sp_32_cont>: */
1278 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1279 0x03a05080, /* moveq r5, #128 ; 0x80 */
1280 0x0a000001, /* beq 8154 <sp_32_done> */
1281 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1282 0xeaffffe8, /* b 8100 <sp_32_code> */
1284 /* 00008154 <sp_32_done>: */
1285 0xeafffffe /* b 8154 <sp_32_done> */
1288 static const uint32_t word_16_code
[] = {
1289 /* 00008158 <sp_16_code>: */
1290 0xe0d050b2, /* ldrh r5, [r0], #2 */
1291 0xe1c890b0, /* strh r9, [r8] */
1292 0xe1cab0b0, /* strh r11, [r10] */
1293 0xe1c830b0, /* strh r3, [r8] */
1294 0xe1c150b0, /* strh r5, [r1] */
1295 0xe1a00000, /* nop (mov r0,r0) */
1297 /* 00008168 <sp_16_busy>: */
1298 0xe1d160b0, /* ldrh r6, [r1] */
1299 0xe0257006, /* eor r7, r5, r6 */
1300 0xe0147007, /* ands r7, r4, r7 */
1301 0x0a000007, /* beq 8198 <sp_16_cont> */
1302 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1303 0x0afffff9, /* beq 8168 <sp_16_busy> */
1304 0xe1d160b0, /* ldrh r6, [r1] */
1305 0xe0257006, /* eor r7, r5, r6 */
1306 0xe0147007, /* ands r7, r4, r7 */
1307 0x0a000001, /* beq 8198 <sp_16_cont> */
1308 0xe3a05000, /* mov r5, #0 ; 0x0 */
1309 0x1a000004, /* bne 81ac <sp_16_done> */
1311 /* 00008198 <sp_16_cont>: */
1312 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1313 0x03a05080, /* moveq r5, #128 ; 0x80 */
1314 0x0a000001, /* beq 81ac <sp_16_done> */
1315 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1316 0xeaffffe8, /* b 8158 <sp_16_code> */
1318 /* 000081ac <sp_16_done>: */
1319 0xeafffffe /* b 81ac <sp_16_done> */
1322 static const uint32_t word_16_code_dq7only
[] = {
1324 0xe0d050b2, /* ldrh r5, [r0], #2 */
1325 0xe1c890b0, /* strh r9, [r8] */
1326 0xe1cab0b0, /* strh r11, [r10] */
1327 0xe1c830b0, /* strh r3, [r8] */
1328 0xe1c150b0, /* strh r5, [r1] */
1329 0xe1a00000, /* nop (mov r0,r0) */
1332 0xe1d160b0, /* ldrh r6, [r1] */
1333 0xe0257006, /* eor r7, r5, r6 */
1334 0xe2177080, /* ands r7, #0x80 */
1335 0x1afffffb, /* bne 8168 <sp_16_busy> */
1337 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1338 0x03a05080, /* moveq r5, #128 ; 0x80 */
1339 0x0a000001, /* beq 81ac <sp_16_done> */
1340 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1341 0xeafffff0, /* b 8158 <sp_16_code> */
1343 /* 000081ac <sp_16_done>: */
1344 0xeafffffe /* b 81ac <sp_16_done> */
1347 static const uint32_t word_8_code
[] = {
1348 /* 000081b0 <sp_16_code_end>: */
1349 0xe4d05001, /* ldrb r5, [r0], #1 */
1350 0xe5c89000, /* strb r9, [r8] */
1351 0xe5cab000, /* strb r11, [r10] */
1352 0xe5c83000, /* strb r3, [r8] */
1353 0xe5c15000, /* strb r5, [r1] */
1354 0xe1a00000, /* nop (mov r0,r0) */
1356 /* 000081c0 <sp_8_busy>: */
1357 0xe5d16000, /* ldrb r6, [r1] */
1358 0xe0257006, /* eor r7, r5, r6 */
1359 0xe0147007, /* ands r7, r4, r7 */
1360 0x0a000007, /* beq 81f0 <sp_8_cont> */
1361 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1362 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1363 0xe5d16000, /* ldrb r6, [r1] */
1364 0xe0257006, /* eor r7, r5, r6 */
1365 0xe0147007, /* ands r7, r4, r7 */
1366 0x0a000001, /* beq 81f0 <sp_8_cont> */
1367 0xe3a05000, /* mov r5, #0 ; 0x0 */
1368 0x1a000004, /* bne 8204 <sp_8_done> */
1370 /* 000081f0 <sp_8_cont>: */
1371 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1372 0x03a05080, /* moveq r5, #128 ; 0x80 */
1373 0x0a000001, /* beq 8204 <sp_8_done> */
1374 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1375 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1377 /* 00008204 <sp_8_done>: */
1378 0xeafffffe /* b 8204 <sp_8_done> */
1381 armv4_5_info
.common_magic
= ARM_COMMON_MAGIC
;
1382 armv4_5_info
.core_mode
= ARM_MODE_SVC
;
1383 armv4_5_info
.core_state
= ARM_STATE_ARM
;
1385 int target_code_size
;
1386 const uint32_t *target_code_src
;
1388 switch (bank
->bus_width
)
1391 target_code_src
= word_8_code
;
1392 target_code_size
= sizeof(word_8_code
);
1395 /* Check for DQ5 support */
1396 if( cfi_info
->status_poll_mask
& (1 << 5) )
1398 target_code_src
= word_16_code
;
1399 target_code_size
= sizeof(word_16_code
);
1403 /* No DQ5 support. Use DQ7 DATA# polling only. */
1404 target_code_src
= word_16_code_dq7only
;
1405 target_code_size
= sizeof(word_16_code_dq7only
);
1409 target_code_src
= word_32_code
;
1410 target_code_size
= sizeof(word_32_code
);
1413 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1414 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1417 /* flash write code */
1418 if (!cfi_info
->write_algorithm
)
1420 uint8_t *target_code
;
1422 /* convert bus-width dependent algorithm code to correct endiannes */
1423 target_code
= malloc(target_code_size
);
1424 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
/ 4);
1426 /* allocate working area */
1427 retval
= target_alloc_working_area(target
, target_code_size
,
1428 &cfi_info
->write_algorithm
);
1429 if (retval
!= ERROR_OK
)
1435 /* write algorithm code to working area */
1436 if ((retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
,
1437 target_code_size
, target_code
)) != ERROR_OK
)
1445 /* the following code still assumes target code is fixed 24*4 bytes */
1447 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
)
1450 if (buffer_size
<= 256)
1452 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1453 if (cfi_info
->write_algorithm
)
1454 target_free_working_area(target
, cfi_info
->write_algorithm
);
1456 LOG_WARNING("not enough working area available, can't do block memory writes");
1457 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1461 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1462 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1463 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1464 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1465 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
1466 init_reg_param(®_params
[5], "r5", 32, PARAM_IN
);
1467 init_reg_param(®_params
[6], "r8", 32, PARAM_OUT
);
1468 init_reg_param(®_params
[7], "r9", 32, PARAM_OUT
);
1469 init_reg_param(®_params
[8], "r10", 32, PARAM_OUT
);
1470 init_reg_param(®_params
[9], "r11", 32, PARAM_OUT
);
1474 uint32_t thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1476 retvaltemp
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1478 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1479 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1480 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1481 buf_set_u32(reg_params
[3].value
, 0, 32, cfi_command_val(bank
, 0xA0));
1482 buf_set_u32(reg_params
[4].value
, 0, 32, cfi_command_val(bank
, 0x80));
1483 buf_set_u32(reg_params
[6].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock1
));
1484 buf_set_u32(reg_params
[7].value
, 0, 32, 0xaaaaaaaa);
1485 buf_set_u32(reg_params
[8].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock2
));
1486 buf_set_u32(reg_params
[9].value
, 0, 32, 0x55555555);
1488 retval
= target_run_algorithm(target
, 0, NULL
, 10, reg_params
,
1489 cfi_info
->write_algorithm
->address
,
1490 cfi_info
->write_algorithm
->address
+ ((target_code_size
) - 4),
1491 10000, &armv4_5_info
);
1493 status
= buf_get_u32(reg_params
[5].value
, 0, 32);
1495 if ((retval
!= ERROR_OK
) || (retvaltemp
!= ERROR_OK
) || status
!= 0x80)
1497 LOG_DEBUG("status: 0x%" PRIx32
, status
);
1498 exit_code
= ERROR_FLASH_OPERATION_FAILED
;
1502 buffer
+= thisrun_count
;
1503 address
+= thisrun_count
;
1504 count
-= thisrun_count
;
1507 target_free_all_working_areas(target
);
1509 destroy_reg_param(®_params
[0]);
1510 destroy_reg_param(®_params
[1]);
1511 destroy_reg_param(®_params
[2]);
1512 destroy_reg_param(®_params
[3]);
1513 destroy_reg_param(®_params
[4]);
1514 destroy_reg_param(®_params
[5]);
1515 destroy_reg_param(®_params
[6]);
1516 destroy_reg_param(®_params
[7]);
1517 destroy_reg_param(®_params
[8]);
1518 destroy_reg_param(®_params
[9]);
1523 static int cfi_intel_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
1526 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1527 struct target
*target
= bank
->target
;
1529 cfi_intel_clear_status_register(bank
);
1530 if ((retval
= cfi_send_command(bank
, 0x40, address
)) != ERROR_OK
)
1535 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, word
)) != ERROR_OK
)
1540 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != 0x80)
1542 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1547 LOG_ERROR("couldn't write word at base 0x%" PRIx32
", address %" PRIx32
, bank
->base
, address
);
1548 return ERROR_FLASH_OPERATION_FAILED
;
1554 static int cfi_intel_write_words(struct flash_bank
*bank
, uint8_t *word
, uint32_t wordcount
, uint32_t address
)
1557 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1558 struct target
*target
= bank
->target
;
1560 /* Calculate buffer size and boundary mask */
1561 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1562 uint32_t buffermask
= buffersize
-1;
1563 uint32_t bufferwsize
;
1565 /* Check for valid range */
1566 if (address
& buffermask
)
1568 LOG_ERROR("Write address at base 0x%" PRIx32
", address %" PRIx32
" not aligned to 2^%d boundary",
1569 bank
->base
, address
, cfi_info
->max_buf_write_size
);
1570 return ERROR_FLASH_OPERATION_FAILED
;
1572 switch (bank
->chip_width
)
1574 case 4 : bufferwsize
= buffersize
/ 4; break;
1575 case 2 : bufferwsize
= buffersize
/ 2; break;
1576 case 1 : bufferwsize
= buffersize
; break;
1578 LOG_ERROR("Unsupported chip width %d", bank
->chip_width
);
1579 return ERROR_FLASH_OPERATION_FAILED
;
1582 bufferwsize
/=(bank
->bus_width
/ bank
->chip_width
);
1585 /* Check for valid size */
1586 if (wordcount
> bufferwsize
)
1588 LOG_ERROR("Number of data words %" PRId32
" exceeds available buffersize %" PRId32
, wordcount
, buffersize
);
1589 return ERROR_FLASH_OPERATION_FAILED
;
1592 /* Write to flash buffer */
1593 cfi_intel_clear_status_register(bank
);
1595 /* Initiate buffer operation _*/
1596 if ((retval
= cfi_send_command(bank
, 0xe8, address
)) != ERROR_OK
)
1600 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1602 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1607 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32
", address %" PRIx32
, bank
->base
, address
);
1608 return ERROR_FLASH_OPERATION_FAILED
;
1611 /* Write buffer wordcount-1 and data words */
1612 if ((retval
= cfi_send_command(bank
, bufferwsize
-1, address
)) != ERROR_OK
)
1617 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
)) != ERROR_OK
)
1622 /* Commit write operation */
1623 if ((retval
= cfi_send_command(bank
, 0xd0, address
)) != ERROR_OK
)
1627 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1629 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1634 LOG_ERROR("Buffer write at base 0x%" PRIx32
", address %" PRIx32
" failed.", bank
->base
, address
);
1635 return ERROR_FLASH_OPERATION_FAILED
;
1641 static int cfi_spansion_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
1644 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1645 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1646 struct target
*target
= bank
->target
;
1648 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
1653 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
1658 if ((retval
= cfi_send_command(bank
, 0xa0, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
1663 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, word
)) != ERROR_OK
)
1668 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1670 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1675 LOG_ERROR("couldn't write word at base 0x%" PRIx32
", address %" PRIx32
, bank
->base
, address
);
1676 return ERROR_FLASH_OPERATION_FAILED
;
1682 static int cfi_spansion_write_words(struct flash_bank
*bank
, uint8_t *word
, uint32_t wordcount
, uint32_t address
)
1685 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1686 struct target
*target
= bank
->target
;
1687 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1689 /* Calculate buffer size and boundary mask */
1690 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1691 uint32_t buffermask
= buffersize
-1;
1692 uint32_t bufferwsize
;
1694 /* Check for valid range */
1695 if (address
& buffermask
)
1697 LOG_ERROR("Write address at base 0x%" PRIx32
", address %" PRIx32
" not aligned to 2^%d boundary", bank
->base
, address
, cfi_info
->max_buf_write_size
);
1698 return ERROR_FLASH_OPERATION_FAILED
;
1700 switch (bank
->chip_width
)
1702 case 4 : bufferwsize
= buffersize
/ 4; break;
1703 case 2 : bufferwsize
= buffersize
/ 2; break;
1704 case 1 : bufferwsize
= buffersize
; break;
1706 LOG_ERROR("Unsupported chip width %d", bank
->chip_width
);
1707 return ERROR_FLASH_OPERATION_FAILED
;
1710 bufferwsize
/=(bank
->bus_width
/ bank
->chip_width
);
1712 /* Check for valid size */
1713 if (wordcount
> bufferwsize
)
1715 LOG_ERROR("Number of data words %" PRId32
" exceeds available buffersize %" PRId32
, wordcount
, buffersize
);
1716 return ERROR_FLASH_OPERATION_FAILED
;
1720 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
1725 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
1730 // Buffer load command
1731 if ((retval
= cfi_send_command(bank
, 0x25, address
)) != ERROR_OK
)
1736 /* Write buffer wordcount-1 and data words */
1737 if ((retval
= cfi_send_command(bank
, bufferwsize
-1, address
)) != ERROR_OK
)
1742 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
)) != ERROR_OK
)
1747 /* Commit write operation */
1748 if ((retval
= cfi_send_command(bank
, 0x29, address
)) != ERROR_OK
)
1753 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1755 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1760 LOG_ERROR("couldn't write block at base 0x%" PRIx32
", address %" PRIx32
", size %" PRIx32
, bank
->base
, address
, bufferwsize
);
1761 return ERROR_FLASH_OPERATION_FAILED
;
1767 static int cfi_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
1769 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1771 switch (cfi_info
->pri_id
)
1775 return cfi_intel_write_word(bank
, word
, address
);
1778 return cfi_spansion_write_word(bank
, word
, address
);
1781 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1785 return ERROR_FLASH_OPERATION_FAILED
;
1788 static int cfi_write_words(struct flash_bank
*bank
, uint8_t *word
, uint32_t wordcount
, uint32_t address
)
1790 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1792 switch (cfi_info
->pri_id
)
1796 return cfi_intel_write_words(bank
, word
, wordcount
, address
);
1799 return cfi_spansion_write_words(bank
, word
, wordcount
, address
);
1802 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1806 return ERROR_FLASH_OPERATION_FAILED
;
1809 static int cfi_write(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
)
1811 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1812 struct target
*target
= bank
->target
;
1813 uint32_t address
= bank
->base
+ offset
; /* address of first byte to be programmed */
1814 uint32_t write_p
, copy_p
;
1815 int align
; /* number of unaligned bytes */
1816 int blk_count
; /* number of bus_width bytes for block copy */
1817 uint8_t current_word
[CFI_MAX_BUS_WIDTH
* 4]; /* word (bus_width size) currently being programmed */
1821 if (bank
->target
->state
!= TARGET_HALTED
)
1823 LOG_ERROR("Target not halted");
1824 return ERROR_TARGET_NOT_HALTED
;
1827 if (offset
+ count
> bank
->size
)
1828 return ERROR_FLASH_DST_OUT_OF_BANK
;
1830 if (cfi_info
->qry
[0] != 'Q')
1831 return ERROR_FLASH_BANK_NOT_PROBED
;
1833 /* start at the first byte of the first word (bus_width size) */
1834 write_p
= address
& ~(bank
->bus_width
- 1);
1835 if ((align
= address
- write_p
) != 0)
1837 LOG_INFO("Fixup %d unaligned head bytes", align
);
1839 for (i
= 0; i
< bank
->bus_width
; i
++)
1840 current_word
[i
] = 0;
1843 /* copy bytes before the first write address */
1844 for (i
= 0; i
< align
; ++i
, ++copy_p
)
1847 if ((retval
= target_read_memory(target
, copy_p
, 1, 1, &byte
)) != ERROR_OK
)
1851 cfi_add_byte(bank
, current_word
, byte
);
1854 /* add bytes from the buffer */
1855 for (; (i
< bank
->bus_width
) && (count
> 0); i
++)
1857 cfi_add_byte(bank
, current_word
, *buffer
++);
1862 /* if the buffer is already finished, copy bytes after the last write address */
1863 for (; (count
== 0) && (i
< bank
->bus_width
); ++i
, ++copy_p
)
1866 if ((retval
= target_read_memory(target
, copy_p
, 1, 1, &byte
)) != ERROR_OK
)
1870 cfi_add_byte(bank
, current_word
, byte
);
1873 retval
= cfi_write_word(bank
, current_word
, write_p
);
1874 if (retval
!= ERROR_OK
)
1879 /* handle blocks of bus_size aligned bytes */
1880 blk_count
= count
& ~(bank
->bus_width
- 1); /* round down, leave tail bytes */
1881 switch (cfi_info
->pri_id
)
1883 /* try block writes (fails without working area) */
1886 retval
= cfi_intel_write_block(bank
, buffer
, write_p
, blk_count
);
1889 retval
= cfi_spansion_write_block(bank
, buffer
, write_p
, blk_count
);
1892 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1893 retval
= ERROR_FLASH_OPERATION_FAILED
;
1896 if (retval
== ERROR_OK
)
1898 /* Increment pointers and decrease count on succesful block write */
1899 buffer
+= blk_count
;
1900 write_p
+= blk_count
;
1905 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
1907 //adjust buffersize for chip width
1908 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1909 uint32_t buffermask
= buffersize
-1;
1910 uint32_t bufferwsize
;
1912 switch (bank
->chip_width
)
1914 case 4 : bufferwsize
= buffersize
/ 4; break;
1915 case 2 : bufferwsize
= buffersize
/ 2; break;
1916 case 1 : bufferwsize
= buffersize
; break;
1918 LOG_ERROR("Unsupported chip width %d", bank
->chip_width
);
1919 return ERROR_FLASH_OPERATION_FAILED
;
1922 bufferwsize
/=(bank
->bus_width
/ bank
->chip_width
);
1924 /* fall back to memory writes */
1925 while (count
>= (uint32_t)bank
->bus_width
)
1928 if ((write_p
& 0xff) == 0)
1930 LOG_INFO("Programming at %08" PRIx32
", count %08" PRIx32
" bytes remaining", write_p
, count
);
1933 if ((bufferwsize
> 0) && (count
>= buffersize
) && !(write_p
& buffermask
))
1935 retval
= cfi_write_words(bank
, buffer
, bufferwsize
, write_p
);
1936 if (retval
== ERROR_OK
)
1938 buffer
+= buffersize
;
1939 write_p
+= buffersize
;
1940 count
-= buffersize
;
1944 /* try the slow way? */
1947 for (i
= 0; i
< bank
->bus_width
; i
++)
1948 current_word
[i
] = 0;
1950 for (i
= 0; i
< bank
->bus_width
; i
++)
1952 cfi_add_byte(bank
, current_word
, *buffer
++);
1955 retval
= cfi_write_word(bank
, current_word
, write_p
);
1956 if (retval
!= ERROR_OK
)
1959 write_p
+= bank
->bus_width
;
1960 count
-= bank
->bus_width
;
1968 /* return to read array mode, so we can read from flash again for padding */
1969 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1973 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1978 /* handle unaligned tail bytes */
1981 LOG_INFO("Fixup %" PRId32
" unaligned tail bytes", count
);
1984 for (i
= 0; i
< bank
->bus_width
; i
++)
1985 current_word
[i
] = 0;
1987 for (i
= 0; (i
< bank
->bus_width
) && (count
> 0); ++i
, ++copy_p
)
1989 cfi_add_byte(bank
, current_word
, *buffer
++);
1992 for (; i
< bank
->bus_width
; ++i
, ++copy_p
)
1995 if ((retval
= target_read_memory(target
, copy_p
, 1, 1, &byte
)) != ERROR_OK
)
1999 cfi_add_byte(bank
, current_word
, byte
);
2001 retval
= cfi_write_word(bank
, current_word
, write_p
);
2002 if (retval
!= ERROR_OK
)
2006 /* return to read array mode */
2007 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
2011 return cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0));
2014 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank
*bank
, void *param
)
2017 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2018 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2020 pri_ext
->_reversed_geometry
= 1;
2023 static void cfi_fixup_0002_erase_regions(struct flash_bank
*bank
, void *param
)
2026 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2027 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2030 if ((pri_ext
->_reversed_geometry
) || (pri_ext
->TopBottom
== 3))
2032 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2034 for (i
= 0; i
< cfi_info
->num_erase_regions
/ 2; i
++)
2036 int j
= (cfi_info
->num_erase_regions
- 1) - i
;
2039 swap
= cfi_info
->erase_region_info
[i
];
2040 cfi_info
->erase_region_info
[i
] = cfi_info
->erase_region_info
[j
];
2041 cfi_info
->erase_region_info
[j
] = swap
;
2046 static void cfi_fixup_0002_unlock_addresses(struct flash_bank
*bank
, void *param
)
2048 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2049 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2050 struct cfi_unlock_addresses
*unlock_addresses
= param
;
2052 pri_ext
->_unlock1
= unlock_addresses
->unlock1
;
2053 pri_ext
->_unlock2
= unlock_addresses
->unlock2
;
2057 static int cfi_query_string(struct flash_bank
*bank
, int address
)
2059 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2062 if ((retval
= cfi_send_command(bank
, 0x98, flash_address(bank
, 0, address
))) != ERROR_OK
)
2067 cfi_info
->qry
[0] = cfi_query_u8(bank
, 0, 0x10);
2068 cfi_info
->qry
[1] = cfi_query_u8(bank
, 0, 0x11);
2069 cfi_info
->qry
[2] = cfi_query_u8(bank
, 0, 0x12);
2071 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2]);
2073 if ((cfi_info
->qry
[0] != 'Q') || (cfi_info
->qry
[1] != 'R') || (cfi_info
->qry
[2] != 'Y'))
2075 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
2079 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
2083 LOG_ERROR("Could not probe bank: no QRY");
2084 return ERROR_FLASH_BANK_INVALID
;
2090 static int cfi_probe(struct flash_bank
*bank
)
2092 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2093 struct target
*target
= bank
->target
;
2094 int num_sectors
= 0;
2097 uint32_t unlock1
= 0x555;
2098 uint32_t unlock2
= 0x2aa;
2101 if (bank
->target
->state
!= TARGET_HALTED
)
2103 LOG_ERROR("Target not halted");
2104 return ERROR_TARGET_NOT_HALTED
;
2107 cfi_info
->probed
= 0;
2109 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2110 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2112 if (cfi_info
->jedec_probe
)
2118 /* switch to read identifier codes mode ("AUTOSELECT") */
2119 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, unlock1
))) != ERROR_OK
)
2123 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, unlock2
))) != ERROR_OK
)
2127 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, unlock1
))) != ERROR_OK
)
2132 if (bank
->chip_width
== 1)
2134 uint8_t manufacturer
, device_id
;
2135 if ((retval
= target_read_u8(target
, flash_address(bank
, 0, 0x00), &manufacturer
)) != ERROR_OK
)
2139 if ((retval
= target_read_u8(target
, flash_address(bank
, 0, 0x01), &device_id
)) != ERROR_OK
)
2143 cfi_info
->manufacturer
= manufacturer
;
2144 cfi_info
->device_id
= device_id
;
2146 else if (bank
->chip_width
== 2)
2148 if ((retval
= target_read_u16(target
, flash_address(bank
, 0, 0x00), &cfi_info
->manufacturer
)) != ERROR_OK
)
2152 if ((retval
= target_read_u16(target
, flash_address(bank
, 0, 0x01), &cfi_info
->device_id
)) != ERROR_OK
)
2158 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info
->manufacturer
, cfi_info
->device_id
);
2159 /* switch back to read array mode */
2160 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x00))) != ERROR_OK
)
2164 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x00))) != ERROR_OK
)
2169 /* check device/manufacturer ID for known non-CFI flashes. */
2170 cfi_fixup_non_cfi(bank
);
2172 /* query only if this is a CFI compatible flash,
2173 * otherwise the relevant info has already been filled in
2175 if (cfi_info
->not_cfi
== 0)
2179 /* enter CFI query mode
2180 * according to JEDEC Standard No. 68.01,
2181 * a single bus sequence with address = 0x55, data = 0x98 should put
2182 * the device into CFI query mode.
2184 * SST flashes clearly violate this, and we will consider them incompatbile for now
2187 retval
= cfi_query_string(bank
, 0x55);
2188 if (retval
!= ERROR_OK
)
2191 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2192 * be harmless enough:
2194 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2196 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2197 retval
= cfi_query_string(bank
, 0x555);
2199 if (retval
!= ERROR_OK
)
2202 cfi_info
->pri_id
= cfi_query_u16(bank
, 0, 0x13);
2203 cfi_info
->pri_addr
= cfi_query_u16(bank
, 0, 0x15);
2204 cfi_info
->alt_id
= cfi_query_u16(bank
, 0, 0x17);
2205 cfi_info
->alt_addr
= cfi_query_u16(bank
, 0, 0x19);
2207 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2209 cfi_info
->vcc_min
= cfi_query_u8(bank
, 0, 0x1b);
2210 cfi_info
->vcc_max
= cfi_query_u8(bank
, 0, 0x1c);
2211 cfi_info
->vpp_min
= cfi_query_u8(bank
, 0, 0x1d);
2212 cfi_info
->vpp_max
= cfi_query_u8(bank
, 0, 0x1e);
2213 cfi_info
->word_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x1f);
2214 cfi_info
->buf_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x20);
2215 cfi_info
->block_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x21);
2216 cfi_info
->chip_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x22);
2217 cfi_info
->word_write_timeout_max
= cfi_query_u8(bank
, 0, 0x23);
2218 cfi_info
->buf_write_timeout_max
= cfi_query_u8(bank
, 0, 0x24);
2219 cfi_info
->block_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x25);
2220 cfi_info
->chip_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x26);
2222 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2223 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2224 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2225 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2226 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2227 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
2228 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
2229 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2230 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2231 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2232 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2234 cfi_info
->dev_size
= 1 << cfi_query_u8(bank
, 0, 0x27);
2235 cfi_info
->interface_desc
= cfi_query_u16(bank
, 0, 0x28);
2236 cfi_info
->max_buf_write_size
= cfi_query_u16(bank
, 0, 0x2a);
2237 cfi_info
->num_erase_regions
= cfi_query_u8(bank
, 0, 0x2c);
2239 LOG_DEBUG("size: 0x%" PRIx32
", interface desc: %i, max buffer write size: %x", cfi_info
->dev_size
, cfi_info
->interface_desc
, (1 << cfi_info
->max_buf_write_size
));
2241 if (cfi_info
->num_erase_regions
)
2243 cfi_info
->erase_region_info
= malloc(4 * cfi_info
->num_erase_regions
);
2244 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2246 cfi_info
->erase_region_info
[i
] = cfi_query_u32(bank
, 0, 0x2d + (4 * i
));
2247 LOG_DEBUG("erase region[%i]: %" PRIu32
" blocks of size 0x%" PRIx32
"",
2249 (cfi_info
->erase_region_info
[i
] & 0xffff) + 1,
2250 (cfi_info
->erase_region_info
[i
] >> 16) * 256);
2255 cfi_info
->erase_region_info
= NULL
;
2258 /* We need to read the primary algorithm extended query table before calculating
2259 * the sector layout to be able to apply fixups
2261 switch (cfi_info
->pri_id
)
2263 /* Intel command set (standard and extended) */
2266 cfi_read_intel_pri_ext(bank
);
2268 /* AMD/Spansion, Atmel, ... command set */
2270 cfi_info
->status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
; /* default for all CFI flashs */
2271 cfi_read_0002_pri_ext(bank
);
2274 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2278 /* return to read array mode
2279 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2281 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
2285 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
2289 } /* end CFI case */
2291 /* apply fixups depending on the primary command set */
2292 switch (cfi_info
->pri_id
)
2294 /* Intel command set (standard and extended) */
2297 cfi_fixup(bank
, cfi_0001_fixups
);
2299 /* AMD/Spansion, Atmel, ... command set */
2301 cfi_fixup(bank
, cfi_0002_fixups
);
2304 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2308 if ((cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
) != bank
->size
)
2310 LOG_WARNING("configuration specifies 0x%" PRIx32
" size, but a 0x%" PRIx32
" size flash was found", bank
->size
, cfi_info
->dev_size
);
2313 if (cfi_info
->num_erase_regions
== 0)
2315 /* a device might have only one erase block, spanning the whole device */
2316 bank
->num_sectors
= 1;
2317 bank
->sectors
= malloc(sizeof(struct flash_sector
));
2319 bank
->sectors
[sector
].offset
= 0x0;
2320 bank
->sectors
[sector
].size
= bank
->size
;
2321 bank
->sectors
[sector
].is_erased
= -1;
2322 bank
->sectors
[sector
].is_protected
= -1;
2326 uint32_t offset
= 0;
2328 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2330 num_sectors
+= (cfi_info
->erase_region_info
[i
] & 0xffff) + 1;
2333 bank
->num_sectors
= num_sectors
;
2334 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
2336 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2339 for (j
= 0; j
< (cfi_info
->erase_region_info
[i
] & 0xffff) + 1; j
++)
2341 bank
->sectors
[sector
].offset
= offset
;
2342 bank
->sectors
[sector
].size
= ((cfi_info
->erase_region_info
[i
] >> 16) * 256) * bank
->bus_width
/ bank
->chip_width
;
2343 offset
+= bank
->sectors
[sector
].size
;
2344 bank
->sectors
[sector
].is_erased
= -1;
2345 bank
->sectors
[sector
].is_protected
= -1;
2349 if (offset
!= (cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
))
2351 LOG_WARNING("CFI size is 0x%" PRIx32
", but total sector size is 0x%" PRIx32
"", \
2352 (cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
), offset
);
2356 cfi_info
->probed
= 1;
2361 static int cfi_auto_probe(struct flash_bank
*bank
)
2363 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2364 if (cfi_info
->probed
)
2366 return cfi_probe(bank
);
2370 static int cfi_intel_protect_check(struct flash_bank
*bank
)
2373 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2374 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2377 /* check if block lock bits are supported on this device */
2378 if (!(pri_ext
->blk_status_reg_mask
& 0x1))
2379 return ERROR_FLASH_OPERATION_FAILED
;
2381 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, 0x55))) != ERROR_OK
)
2386 for (i
= 0; i
< bank
->num_sectors
; i
++)
2388 uint8_t block_status
= cfi_get_u8(bank
, i
, 0x2);
2390 if (block_status
& 1)
2391 bank
->sectors
[i
].is_protected
= 1;
2393 bank
->sectors
[i
].is_protected
= 0;
2396 return cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0));
2399 static int cfi_spansion_protect_check(struct flash_bank
*bank
)
2402 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2403 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2406 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
2411 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
2416 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
2421 for (i
= 0; i
< bank
->num_sectors
; i
++)
2423 uint8_t block_status
= cfi_get_u8(bank
, i
, 0x2);
2425 if (block_status
& 1)
2426 bank
->sectors
[i
].is_protected
= 1;
2428 bank
->sectors
[i
].is_protected
= 0;
2431 return cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0));
2434 static int cfi_protect_check(struct flash_bank
*bank
)
2436 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2438 if (bank
->target
->state
!= TARGET_HALTED
)
2440 LOG_ERROR("Target not halted");
2441 return ERROR_TARGET_NOT_HALTED
;
2444 if (cfi_info
->qry
[0] != 'Q')
2445 return ERROR_FLASH_BANK_NOT_PROBED
;
2447 switch (cfi_info
->pri_id
)
2451 return cfi_intel_protect_check(bank
);
2454 return cfi_spansion_protect_check(bank
);
2457 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2464 static int cfi_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
2467 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2469 if (cfi_info
->qry
[0] == (char)-1)
2471 printed
= snprintf(buf
, buf_size
, "\ncfi flash bank not probed yet\n");
2475 if (cfi_info
->not_cfi
== 0)
2476 printed
= snprintf(buf
, buf_size
, "\ncfi information:\n");
2478 printed
= snprintf(buf
, buf_size
, "\nnon-cfi flash:\n");
2480 buf_size
-= printed
;
2482 printed
= snprintf(buf
, buf_size
, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2483 cfi_info
->manufacturer
, cfi_info
->device_id
);
2485 buf_size
-= printed
;
2487 if (cfi_info
->not_cfi
== 0)
2489 printed
= snprintf(buf
, buf_size
, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2491 buf_size
-= printed
;
2493 printed
= snprintf(buf
, buf_size
, "Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x\n",
2494 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2495 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2496 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2497 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2499 buf_size
-= printed
;
2501 printed
= snprintf(buf
, buf_size
, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2502 1 << cfi_info
->word_write_timeout_typ
,
2503 1 << cfi_info
->buf_write_timeout_typ
,
2504 1 << cfi_info
->block_erase_timeout_typ
,
2505 1 << cfi_info
->chip_erase_timeout_typ
);
2507 buf_size
-= printed
;
2509 printed
= snprintf(buf
, buf_size
, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2510 (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2511 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2512 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2513 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2515 buf_size
-= printed
;
2517 printed
= snprintf(buf
, buf_size
, "size: 0x%" PRIx32
", interface desc: %i, max buffer write size: %x\n",
2519 cfi_info
->interface_desc
,
2520 1 << cfi_info
->max_buf_write_size
);
2522 buf_size
-= printed
;
2524 switch (cfi_info
->pri_id
)
2528 cfi_intel_info(bank
, buf
, buf_size
);
2531 cfi_spansion_info(bank
, buf
, buf_size
);
2534 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2542 struct flash_driver cfi_flash
= {
2544 .flash_bank_command
= cfi_flash_bank_command
,
2546 .protect
= cfi_protect
,
2549 .auto_probe
= cfi_auto_probe
,
2550 .erase_check
= default_flash_blank_check
,
2551 .protect_check
= cfi_protect_check
,
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