Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
flash/nor: Factor out cfi_spansion_unlock_seq()
[openocd.git] / src / flash / nor / cfi.c
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
6 * Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com> *
7 * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
21 ***************************************************************************/
22
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "imp.h"
28 #include "cfi.h"
29 #include "non_cfi.h"
30 #include <target/arm.h>
31 #include <target/arm7_9_common.h>
32 #include <target/armv7m.h>
33 #include <target/mips32.h>
34 #include <helper/binarybuffer.h>
35 #include <target/algorithm.h>
36
37 #define CFI_MAX_BUS_WIDTH 4
38 #define CFI_MAX_CHIP_WIDTH 4
39
40 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
41 #define CFI_MAX_INTEL_CODESIZE 256
42
43 /* some id-types with specific handling */
44 #define AT49BV6416 0x00d6
45 #define AT49BV6416T 0x00d2
46
47 static const struct cfi_unlock_addresses cfi_unlock_addresses[] = {
48 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
49 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
50 };
51
52 static const int cfi_status_poll_mask_dq6_dq7 = CFI_STATUS_POLL_MASK_DQ6_DQ7;
53
54 /* CFI fixups forward declarations */
55 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, const void *param);
56 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, const void *param);
57 static void cfi_fixup_reversed_erase_regions(struct flash_bank *bank, const void *param);
58 static void cfi_fixup_0002_write_buffer(struct flash_bank *bank, const void *param);
59 static void cfi_fixup_0002_polling_bits(struct flash_bank *bank, const void *param);
60
61 /* fixup after reading cmdset 0002 primary query table */
62 static const struct cfi_fixup cfi_0002_fixups[] = {
63 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses,
64 &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
65 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses,
66 &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
67 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses,
68 &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
69 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses,
70 &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
71 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses,
72 &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
73 {CFI_MFR_SST, 0x274b, cfi_fixup_0002_unlock_addresses,
74 &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
75 {CFI_MFR_SST, 0x235f, cfi_fixup_0002_polling_bits, /* 39VF3201C */
76 &cfi_status_poll_mask_dq6_dq7},
77 {CFI_MFR_SST, 0x236d, cfi_fixup_0002_unlock_addresses,
78 &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
79 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_reversed_erase_regions, NULL},
80 {CFI_MFR_ST, 0x22C4, cfi_fixup_reversed_erase_regions, NULL}, /* M29W160ET */
81 {CFI_MFR_FUJITSU, 0x22ea, cfi_fixup_0002_unlock_addresses,
82 &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
83 {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses,
84 &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
85 {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses,
86 &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
87 {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses,
88 &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
89 {CFI_MFR_EON, 0x225b, cfi_fixup_0002_unlock_addresses,
90 &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
91 {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses,
92 &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
93 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
94 {CFI_MFR_ST, 0x227E, cfi_fixup_0002_write_buffer, NULL},/* M29W128G */
95 {0, 0, NULL, NULL}
96 };
97
98 /* fixup after reading cmdset 0001 primary query table */
99 static const struct cfi_fixup cfi_0001_fixups[] = {
100 {0, 0, NULL, NULL}
101 };
102
103 static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
104 {
105 struct cfi_flash_bank *cfi_info = bank->driver_priv;
106 const struct cfi_fixup *f;
107
108 for (f = fixups; f->fixup; f++) {
109 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
110 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
111 f->fixup(bank, f->param);
112 }
113 }
114
115 static inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
116 {
117 struct cfi_flash_bank *cfi_info = bank->driver_priv;
118
119 if (cfi_info->x16_as_x8)
120 offset *= 2;
121
122 /* while the sector list isn't built, only accesses to sector 0 work */
123 if (sector == 0)
124 return bank->base + offset * bank->bus_width;
125 else {
126 if (!bank->sectors) {
127 LOG_ERROR("BUG: sector list not yet built");
128 exit(-1);
129 }
130 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
131 }
132 }
133
134 static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
135 {
136 int i;
137 struct cfi_flash_bank *cfi_info = bank->driver_priv;
138
139 /* clear whole buffer, to ensure bits that exceed the bus_width
140 * are set to zero
141 */
142 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
143 cmd_buf[i] = 0;
144
145 if (cfi_info->endianness == TARGET_LITTLE_ENDIAN) {
146 for (i = bank->bus_width; i > 0; i--)
147 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
148 } else {
149 for (i = 1; i <= bank->bus_width; i++)
150 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
151 }
152 }
153
154 static int cfi_send_command(struct flash_bank *bank, uint8_t cmd, uint32_t address)
155 {
156 uint8_t command[CFI_MAX_BUS_WIDTH];
157
158 cfi_command(bank, cmd, command);
159 return target_write_memory(bank->target, address, bank->bus_width, 1, command);
160 }
161
162 /* read unsigned 8-bit value from the bank
163 * flash banks are expected to be made of similar chips
164 * the query result should be the same for all
165 */
166 static int cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
167 {
168 struct target *target = bank->target;
169 struct cfi_flash_bank *cfi_info = bank->driver_priv;
170 uint8_t data[CFI_MAX_BUS_WIDTH];
171
172 int retval;
173 retval = target_read_memory(target, flash_address(bank, sector, offset),
174 bank->bus_width, 1, data);
175 if (retval != ERROR_OK)
176 return retval;
177
178 if (cfi_info->endianness == TARGET_LITTLE_ENDIAN)
179 *val = data[0];
180 else
181 *val = data[bank->bus_width - 1];
182
183 return ERROR_OK;
184 }
185
186 /* read unsigned 8-bit value from the bank
187 * in case of a bank made of multiple chips,
188 * the individual values are ORed
189 */
190 static int cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
191 {
192 struct target *target = bank->target;
193 struct cfi_flash_bank *cfi_info = bank->driver_priv;
194 uint8_t data[CFI_MAX_BUS_WIDTH];
195 int i;
196
197 int retval;
198 retval = target_read_memory(target, flash_address(bank, sector, offset),
199 bank->bus_width, 1, data);
200 if (retval != ERROR_OK)
201 return retval;
202
203 if (cfi_info->endianness == TARGET_LITTLE_ENDIAN) {
204 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
205 data[0] |= data[i];
206
207 *val = data[0];
208 } else {
209 uint8_t value = 0;
210 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
211 value |= data[bank->bus_width - 1 - i];
212
213 *val = value;
214 }
215 return ERROR_OK;
216 }
217
218 static int cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset, uint16_t *val)
219 {
220 struct target *target = bank->target;
221 struct cfi_flash_bank *cfi_info = bank->driver_priv;
222 uint8_t data[CFI_MAX_BUS_WIDTH * 2];
223 int retval;
224
225 if (cfi_info->x16_as_x8) {
226 uint8_t i;
227 for (i = 0; i < 2; i++) {
228 retval = target_read_memory(target, flash_address(bank, sector, offset + i),
229 bank->bus_width, 1, &data[i * bank->bus_width]);
230 if (retval != ERROR_OK)
231 return retval;
232 }
233 } else {
234 retval = target_read_memory(target, flash_address(bank, sector, offset),
235 bank->bus_width, 2, data);
236 if (retval != ERROR_OK)
237 return retval;
238 }
239
240 if (cfi_info->endianness == TARGET_LITTLE_ENDIAN)
241 *val = data[0] | data[bank->bus_width] << 8;
242 else
243 *val = data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
244
245 return ERROR_OK;
246 }
247
248 static int cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset, uint32_t *val)
249 {
250 struct target *target = bank->target;
251 struct cfi_flash_bank *cfi_info = bank->driver_priv;
252 uint8_t data[CFI_MAX_BUS_WIDTH * 4];
253 int retval;
254
255 if (cfi_info->x16_as_x8) {
256 uint8_t i;
257 for (i = 0; i < 4; i++) {
258 retval = target_read_memory(target, flash_address(bank, sector, offset + i),
259 bank->bus_width, 1, &data[i * bank->bus_width]);
260 if (retval != ERROR_OK)
261 return retval;
262 }
263 } else {
264 retval = target_read_memory(target, flash_address(bank, sector, offset),
265 bank->bus_width, 4, data);
266 if (retval != ERROR_OK)
267 return retval;
268 }
269
270 if (cfi_info->endianness == TARGET_LITTLE_ENDIAN)
271 *val = data[0] | data[bank->bus_width] << 8 |
272 data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
273 else
274 *val = data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8 |
275 data[(3 * bank->bus_width) - 1] << 16 |
276 data[(4 * bank->bus_width) - 1] << 24;
277
278 return ERROR_OK;
279 }
280
281 static int cfi_reset(struct flash_bank *bank)
282 {
283 struct cfi_flash_bank *cfi_info = bank->driver_priv;
284 int retval = ERROR_OK;
285
286 retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
287 if (retval != ERROR_OK)
288 return retval;
289
290 retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
291 if (retval != ERROR_OK)
292 return retval;
293
294 if (cfi_info->manufacturer == 0x20 &&
295 (cfi_info->device_id == 0x227E || cfi_info->device_id == 0x7E)) {
296 /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
297 * so we send an extra 0xF0 reset to fix the bug */
298 retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x00));
299 if (retval != ERROR_OK)
300 return retval;
301 }
302
303 return retval;
304 }
305
306 static void cfi_intel_clear_status_register(struct flash_bank *bank)
307 {
308 cfi_send_command(bank, 0x50, flash_address(bank, 0, 0x0));
309 }
310
311 static int cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout, uint8_t *val)
312 {
313 uint8_t status;
314
315 int retval = ERROR_OK;
316
317 for (;; ) {
318 if (timeout-- < 0) {
319 LOG_ERROR("timeout while waiting for WSM to become ready");
320 return ERROR_FAIL;
321 }
322
323 retval = cfi_get_u8(bank, 0, 0x0, &status);
324 if (retval != ERROR_OK)
325 return retval;
326
327 if (status & 0x80)
328 break;
329
330 alive_sleep(1);
331 }
332
333 /* mask out bit 0 (reserved) */
334 status = status & 0xfe;
335
336 LOG_DEBUG("status: 0x%x", status);
337
338 if (status != 0x80) {
339 LOG_ERROR("status register: 0x%x", status);
340 if (status & 0x2)
341 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
342 if (status & 0x4)
343 LOG_ERROR("Program suspended");
344 if (status & 0x8)
345 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
346 if (status & 0x10)
347 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
348 if (status & 0x20)
349 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
350 if (status & 0x40)
351 LOG_ERROR("Block Erase Suspended");
352
353 cfi_intel_clear_status_register(bank);
354
355 retval = ERROR_FAIL;
356 }
357
358 *val = status;
359 return retval;
360 }
361
362 static int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
363 {
364 uint8_t status, oldstatus;
365 struct cfi_flash_bank *cfi_info = bank->driver_priv;
366 int retval;
367
368 retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
369 if (retval != ERROR_OK)
370 return retval;
371
372 do {
373 retval = cfi_get_u8(bank, 0, 0x0, &status);
374
375 if (retval != ERROR_OK)
376 return retval;
377
378 if ((status ^ oldstatus) & 0x40) {
379 if (status & cfi_info->status_poll_mask & 0x20) {
380 retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
381 if (retval != ERROR_OK)
382 return retval;
383 retval = cfi_get_u8(bank, 0, 0x0, &status);
384 if (retval != ERROR_OK)
385 return retval;
386 if ((status ^ oldstatus) & 0x40) {
387 LOG_ERROR("dq5 timeout, status: 0x%x", status);
388 return ERROR_FLASH_OPERATION_FAILED;
389 } else {
390 LOG_DEBUG("status: 0x%x", status);
391 return ERROR_OK;
392 }
393 }
394 } else {/* no toggle: finished, OK */
395 LOG_DEBUG("status: 0x%x", status);
396 return ERROR_OK;
397 }
398
399 oldstatus = status;
400 alive_sleep(1);
401 } while (timeout-- > 0);
402
403 LOG_ERROR("timeout, status: 0x%x", status);
404
405 return ERROR_FLASH_BUSY;
406 }
407
408 static int cfi_read_intel_pri_ext(struct flash_bank *bank)
409 {
410 int retval;
411 struct cfi_flash_bank *cfi_info = bank->driver_priv;
412 struct cfi_intel_pri_ext *pri_ext;
413
414 if (cfi_info->pri_ext)
415 free(cfi_info->pri_ext);
416
417 pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
418 if (pri_ext == NULL) {
419 LOG_ERROR("Out of memory");
420 return ERROR_FAIL;
421 }
422 cfi_info->pri_ext = pri_ext;
423
424 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
425 if (retval != ERROR_OK)
426 return retval;
427 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
428 if (retval != ERROR_OK)
429 return retval;
430 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
431 if (retval != ERROR_OK)
432 return retval;
433
434 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I')) {
435 retval = cfi_reset(bank);
436 if (retval != ERROR_OK)
437 return retval;
438 LOG_ERROR("Could not read bank flash bank information");
439 return ERROR_FLASH_BANK_INVALID;
440 }
441
442 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
443 if (retval != ERROR_OK)
444 return retval;
445 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
446 if (retval != ERROR_OK)
447 return retval;
448
449 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
450 pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
451
452 retval = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5, &pri_ext->feature_support);
453 if (retval != ERROR_OK)
454 return retval;
455 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->suspend_cmd_support);
456 if (retval != ERROR_OK)
457 return retval;
458 retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa, &pri_ext->blk_status_reg_mask);
459 if (retval != ERROR_OK)
460 return retval;
461
462 LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: "
463 "0x%x, blk_status_reg_mask: 0x%x",
464 pri_ext->feature_support,
465 pri_ext->suspend_cmd_support,
466 pri_ext->blk_status_reg_mask);
467
468 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc, &pri_ext->vcc_optimal);
469 if (retval != ERROR_OK)
470 return retval;
471 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd, &pri_ext->vpp_optimal);
472 if (retval != ERROR_OK)
473 return retval;
474
475 LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
476 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
477 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
478
479 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe, &pri_ext->num_protection_fields);
480 if (retval != ERROR_OK)
481 return retval;
482 if (pri_ext->num_protection_fields != 1) {
483 LOG_WARNING("expected one protection register field, but found %i",
484 pri_ext->num_protection_fields);
485 }
486
487 retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf, &pri_ext->prot_reg_addr);
488 if (retval != ERROR_OK)
489 return retval;
490 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11, &pri_ext->fact_prot_reg_size);
491 if (retval != ERROR_OK)
492 return retval;
493 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12, &pri_ext->user_prot_reg_size);
494 if (retval != ERROR_OK)
495 return retval;
496
497 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, "
498 "factory pre-programmed: %i, user programmable: %i",
499 pri_ext->num_protection_fields, pri_ext->prot_reg_addr,
500 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
501
502 return ERROR_OK;
503 }
504
505 static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
506 {
507 int retval;
508 struct cfi_flash_bank *cfi_info = bank->driver_priv;
509 struct cfi_spansion_pri_ext *pri_ext;
510
511 if (cfi_info->pri_ext)
512 free(cfi_info->pri_ext);
513
514 pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
515 if (pri_ext == NULL) {
516 LOG_ERROR("Out of memory");
517 return ERROR_FAIL;
518 }
519 cfi_info->pri_ext = pri_ext;
520
521 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
522 if (retval != ERROR_OK)
523 return retval;
524 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
525 if (retval != ERROR_OK)
526 return retval;
527 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
528 if (retval != ERROR_OK)
529 return retval;
530
531 /* default values for implementation specific workarounds */
532 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
533 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
534 pri_ext->_reversed_geometry = 0;
535
536 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I')) {
537 retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
538 if (retval != ERROR_OK)
539 return retval;
540 LOG_ERROR("Could not read spansion bank information");
541 return ERROR_FLASH_BANK_INVALID;
542 }
543
544 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
545 if (retval != ERROR_OK)
546 return retval;
547 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
548 if (retval != ERROR_OK)
549 return retval;
550
551 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
552 pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
553
554 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &pri_ext->SiliconRevision);
555 if (retval != ERROR_OK)
556 return retval;
557 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &pri_ext->EraseSuspend);
558 if (retval != ERROR_OK)
559 return retval;
560 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &pri_ext->BlkProt);
561 if (retval != ERROR_OK)
562 return retval;
563 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &pri_ext->TmpBlkUnprotect);
564 if (retval != ERROR_OK)
565 return retval;
566 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->BlkProtUnprot);
567 if (retval != ERROR_OK)
568 return retval;
569 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10, &pri_ext->SimultaneousOps);
570 if (retval != ERROR_OK)
571 return retval;
572 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11, &pri_ext->BurstMode);
573 if (retval != ERROR_OK)
574 return retval;
575 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12, &pri_ext->PageMode);
576 if (retval != ERROR_OK)
577 return retval;
578 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13, &pri_ext->VppMin);
579 if (retval != ERROR_OK)
580 return retval;
581 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14, &pri_ext->VppMax);
582 if (retval != ERROR_OK)
583 return retval;
584 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15, &pri_ext->TopBottom);
585 if (retval != ERROR_OK)
586 return retval;
587
588 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x",
589 pri_ext->SiliconRevision, pri_ext->EraseSuspend, pri_ext->BlkProt);
590
591 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, "
592 "Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
593 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
594
595 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
596
597
598 LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
599 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
600 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
601
602 LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
603
604 return ERROR_OK;
605 }
606
607 static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
608 {
609 int retval;
610 struct cfi_atmel_pri_ext atmel_pri_ext;
611 struct cfi_flash_bank *cfi_info = bank->driver_priv;
612 struct cfi_spansion_pri_ext *pri_ext;
613
614 if (cfi_info->pri_ext)
615 free(cfi_info->pri_ext);
616
617 pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
618 if (pri_ext == NULL) {
619 LOG_ERROR("Out of memory");
620 return ERROR_FAIL;
621 }
622
623 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
624 * but a different primary extended query table.
625 * We read the atmel table, and prepare a valid AMD/Spansion query table.
626 */
627
628 memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
629
630 cfi_info->pri_ext = pri_ext;
631
632 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &atmel_pri_ext.pri[0]);
633 if (retval != ERROR_OK)
634 return retval;
635 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &atmel_pri_ext.pri[1]);
636 if (retval != ERROR_OK)
637 return retval;
638 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &atmel_pri_ext.pri[2]);
639 if (retval != ERROR_OK)
640 return retval;
641
642 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R')
643 || (atmel_pri_ext.pri[2] != 'I')) {
644 retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
645 if (retval != ERROR_OK)
646 return retval;
647 LOG_ERROR("Could not read atmel bank information");
648 return ERROR_FLASH_BANK_INVALID;
649 }
650
651 pri_ext->pri[0] = atmel_pri_ext.pri[0];
652 pri_ext->pri[1] = atmel_pri_ext.pri[1];
653 pri_ext->pri[2] = atmel_pri_ext.pri[2];
654
655 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &atmel_pri_ext.major_version);
656 if (retval != ERROR_OK)
657 return retval;
658 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &atmel_pri_ext.minor_version);
659 if (retval != ERROR_OK)
660 return retval;
661
662 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0],
663 atmel_pri_ext.pri[1], atmel_pri_ext.pri[2],
664 atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
665
666 pri_ext->major_version = atmel_pri_ext.major_version;
667 pri_ext->minor_version = atmel_pri_ext.minor_version;
668
669 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &atmel_pri_ext.features);
670 if (retval != ERROR_OK)
671 return retval;
672 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &atmel_pri_ext.bottom_boot);
673 if (retval != ERROR_OK)
674 return retval;
675 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &atmel_pri_ext.burst_mode);
676 if (retval != ERROR_OK)
677 return retval;
678 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &atmel_pri_ext.page_mode);
679 if (retval != ERROR_OK)
680 return retval;
681
682 LOG_DEBUG(
683 "features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
684 atmel_pri_ext.features,
685 atmel_pri_ext.bottom_boot,
686 atmel_pri_ext.burst_mode,
687 atmel_pri_ext.page_mode);
688
689 if (atmel_pri_ext.features & 0x02)
690 pri_ext->EraseSuspend = 2;
691
692 /* some chips got it backwards... */
693 if (cfi_info->device_id == AT49BV6416 ||
694 cfi_info->device_id == AT49BV6416T) {
695 if (atmel_pri_ext.bottom_boot)
696 pri_ext->TopBottom = 3;
697 else
698 pri_ext->TopBottom = 2;
699 } else {
700 if (atmel_pri_ext.bottom_boot)
701 pri_ext->TopBottom = 2;
702 else
703 pri_ext->TopBottom = 3;
704 }
705
706 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
707 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
708
709 return ERROR_OK;
710 }
711
712 static int cfi_read_0002_pri_ext(struct flash_bank *bank)
713 {
714 struct cfi_flash_bank *cfi_info = bank->driver_priv;
715
716 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
717 return cfi_read_atmel_pri_ext(bank);
718 else
719 return cfi_read_spansion_pri_ext(bank);
720 }
721
722 static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
723 {
724 int printed;
725 struct cfi_flash_bank *cfi_info = bank->driver_priv;
726 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
727
728 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
729 buf += printed;
730 buf_size -= printed;
731
732 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
733 pri_ext->pri[1], pri_ext->pri[2],
734 pri_ext->major_version, pri_ext->minor_version);
735 buf += printed;
736 buf_size -= printed;
737
738 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
739 (pri_ext->SiliconRevision) >> 2,
740 (pri_ext->SiliconRevision) & 0x03);
741 buf += printed;
742 buf_size -= printed;
743
744 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
745 pri_ext->EraseSuspend,
746 pri_ext->BlkProt);
747 buf += printed;
748 buf_size -= printed;
749
750 snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
751 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
752 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
753
754 return ERROR_OK;
755 }
756
757 static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
758 {
759 int printed;
760 struct cfi_flash_bank *cfi_info = bank->driver_priv;
761 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
762
763 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
764 buf += printed;
765 buf_size -= printed;
766
767 printed = snprintf(buf,
768 buf_size,
769 "pri: '%c%c%c', version: %c.%c\n",
770 pri_ext->pri[0],
771 pri_ext->pri[1],
772 pri_ext->pri[2],
773 pri_ext->major_version,
774 pri_ext->minor_version);
775 buf += printed;
776 buf_size -= printed;
777
778 printed = snprintf(buf,
779 buf_size,
780 "feature_support: 0x%" PRIx32 ", "
781 "suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n",
782 pri_ext->feature_support,
783 pri_ext->suspend_cmd_support,
784 pri_ext->blk_status_reg_mask);
785 buf += printed;
786 buf_size -= printed;
787
788 printed = snprintf(buf, buf_size, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
789 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
790 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
791 buf += printed;
792 buf_size -= printed;
793
794 snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, "
795 "factory pre-programmed: %i, user programmable: %i\n",
796 pri_ext->num_protection_fields, pri_ext->prot_reg_addr,
797 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
798
799 return ERROR_OK;
800 }
801
802 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
803 */
804 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
805 {
806 struct cfi_flash_bank *cfi_info;
807 int bus_swap = 0;
808
809 if (CMD_ARGC < 6)
810 return ERROR_COMMAND_SYNTAX_ERROR;
811
812 /* both widths must:
813 * - not exceed max value;
814 * - not be null;
815 * - be equal to a power of 2.
816 * bus must be wide enough to hold one chip */
817 if ((bank->chip_width > CFI_MAX_CHIP_WIDTH)
818 || (bank->bus_width > CFI_MAX_BUS_WIDTH)
819 || (bank->chip_width == 0)
820 || (bank->bus_width == 0)
821 || (bank->chip_width & (bank->chip_width - 1))
822 || (bank->bus_width & (bank->bus_width - 1))
823 || (bank->chip_width > bank->bus_width)) {
824 LOG_ERROR("chip and bus width have to specified in bytes");
825 return ERROR_FLASH_BANK_INVALID;
826 }
827
828 cfi_info = malloc(sizeof(struct cfi_flash_bank));
829 cfi_info->probed = 0;
830 cfi_info->erase_region_info = NULL;
831 cfi_info->pri_ext = NULL;
832 bank->driver_priv = cfi_info;
833
834 cfi_info->x16_as_x8 = 0;
835 cfi_info->jedec_probe = 0;
836 cfi_info->not_cfi = 0;
837 cfi_info->data_swap = 0;
838
839 for (unsigned i = 6; i < CMD_ARGC; i++) {
840 if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
841 cfi_info->x16_as_x8 = 1;
842 else if (strcmp(CMD_ARGV[i], "data_swap") == 0)
843 cfi_info->data_swap = 1;
844 else if (strcmp(CMD_ARGV[i], "bus_swap") == 0)
845 bus_swap = 1;
846 else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
847 cfi_info->jedec_probe = 1;
848 }
849
850 if (bus_swap)
851 cfi_info->endianness =
852 bank->target->endianness == TARGET_LITTLE_ENDIAN ?
853 TARGET_BIG_ENDIAN : TARGET_LITTLE_ENDIAN;
854 else
855 cfi_info->endianness = bank->target->endianness;
856
857 /* bank wasn't probed yet */
858 cfi_info->qry[0] = 0xff;
859
860 return ERROR_OK;
861 }
862
863 static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
864 {
865 int retval;
866 struct cfi_flash_bank *cfi_info = bank->driver_priv;
867 int i;
868
869 cfi_intel_clear_status_register(bank);
870
871 for (i = first; i <= last; i++) {
872 retval = cfi_send_command(bank, 0x20, flash_address(bank, i, 0x0));
873 if (retval != ERROR_OK)
874 return retval;
875
876 retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0));
877 if (retval != ERROR_OK)
878 return retval;
879
880 uint8_t status;
881 retval = cfi_intel_wait_status_busy(bank, cfi_info->block_erase_timeout, &status);
882 if (retval != ERROR_OK)
883 return retval;
884
885 if (status == 0x80)
886 bank->sectors[i].is_erased = 1;
887 else {
888 retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
889 if (retval != ERROR_OK)
890 return retval;
891
892 LOG_ERROR("couldn't erase block %i of flash bank at base "
893 TARGET_ADDR_FMT, i, bank->base);
894 return ERROR_FLASH_OPERATION_FAILED;
895 }
896 }
897
898 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
899 }
900
901 static int cfi_spansion_unlock_seq(struct flash_bank *bank)
902 {
903 int retval;
904 struct cfi_flash_bank *cfi_info = bank->driver_priv;
905 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
906
907 retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1));
908 if (retval != ERROR_OK)
909 return retval;
910
911 retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2));
912 if (retval != ERROR_OK)
913 return retval;
914
915 return ERROR_OK;
916 }
917
918 static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
919 {
920 int retval;
921 struct cfi_flash_bank *cfi_info = bank->driver_priv;
922 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
923 int i;
924
925 for (i = first; i <= last; i++) {
926 retval = cfi_spansion_unlock_seq(bank);
927 if (retval != ERROR_OK)
928 return retval;
929
930 retval = cfi_send_command(bank, 0x80, flash_address(bank, 0, pri_ext->_unlock1));
931 if (retval != ERROR_OK)
932 return retval;
933
934 retval = cfi_spansion_unlock_seq(bank);
935 if (retval != ERROR_OK)
936 return retval;
937
938 retval = cfi_send_command(bank, 0x30, flash_address(bank, i, 0x0));
939 if (retval != ERROR_OK)
940 return retval;
941
942 if (cfi_spansion_wait_status_busy(bank, cfi_info->block_erase_timeout) == ERROR_OK)
943 bank->sectors[i].is_erased = 1;
944 else {
945 retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
946 if (retval != ERROR_OK)
947 return retval;
948
949 LOG_ERROR("couldn't erase block %i of flash bank at base "
950 TARGET_ADDR_FMT, i, bank->base);
951 return ERROR_FLASH_OPERATION_FAILED;
952 }
953 }
954
955 return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
956 }
957
958 static int cfi_erase(struct flash_bank *bank, int first, int last)
959 {
960 struct cfi_flash_bank *cfi_info = bank->driver_priv;
961
962 if (bank->target->state != TARGET_HALTED) {
963 LOG_ERROR("Target not halted");
964 return ERROR_TARGET_NOT_HALTED;
965 }
966
967 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
968 return ERROR_FLASH_SECTOR_INVALID;
969
970 if (cfi_info->qry[0] != 'Q')
971 return ERROR_FLASH_BANK_NOT_PROBED;
972
973 switch (cfi_info->pri_id) {
974 case 1:
975 case 3:
976 return cfi_intel_erase(bank, first, last);
977 break;
978 case 2:
979 return cfi_spansion_erase(bank, first, last);
980 break;
981 default:
982 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
983 break;
984 }
985
986 return ERROR_OK;
987 }
988
989 static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
990 {
991 int retval;
992 struct cfi_flash_bank *cfi_info = bank->driver_priv;
993 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
994 int retry = 0;
995 int i;
996
997 /* if the device supports neither legacy lock/unlock (bit 3) nor
998 * instant individual block locking (bit 5).
999 */
1000 if (!(pri_ext->feature_support & 0x28)) {
1001 LOG_ERROR("lock/unlock not supported on flash");
1002 return ERROR_FLASH_OPERATION_FAILED;
1003 }
1004
1005 cfi_intel_clear_status_register(bank);
1006
1007 for (i = first; i <= last; i++) {
1008 retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0));
1009 if (retval != ERROR_OK)
1010 return retval;
1011 if (set) {
1012 retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0));
1013 if (retval != ERROR_OK)
1014 return retval;
1015 bank->sectors[i].is_protected = 1;
1016 } else {
1017 retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0));
1018 if (retval != ERROR_OK)
1019 return retval;
1020 bank->sectors[i].is_protected = 0;
1021 }
1022
1023 /* instant individual block locking doesn't require reading of the status register
1024 **/
1025 if (!(pri_ext->feature_support & 0x20)) {
1026 /* Clear lock bits operation may take up to 1.4s */
1027 uint8_t status;
1028 retval = cfi_intel_wait_status_busy(bank, 1400, &status);
1029 if (retval != ERROR_OK)
1030 return retval;
1031 } else {
1032 uint8_t block_status;
1033 /* read block lock bit, to verify status */
1034 retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55));
1035 if (retval != ERROR_OK)
1036 return retval;
1037 retval = cfi_get_u8(bank, i, 0x2, &block_status);
1038 if (retval != ERROR_OK)
1039 return retval;
1040
1041 if ((block_status & 0x1) != set) {
1042 LOG_ERROR(
1043 "couldn't change block lock status (set = %i, block_status = 0x%2.2x)",
1044 set, block_status);
1045 retval = cfi_send_command(bank, 0x70, flash_address(bank, 0, 0x55));
1046 if (retval != ERROR_OK)
1047 return retval;
1048 uint8_t status;
1049 retval = cfi_intel_wait_status_busy(bank, 10, &status);
1050 if (retval != ERROR_OK)
1051 return retval;
1052
1053 if (retry > 10)
1054 return ERROR_FLASH_OPERATION_FAILED;
1055 else {
1056 i--;
1057 retry++;
1058 }
1059 }
1060 }
1061 }
1062
1063 /* if the device doesn't support individual block lock bits set/clear,
1064 * all blocks have been unlocked in parallel, so we set those that should be protected
1065 */
1066 if ((!set) && (!(pri_ext->feature_support & 0x20))) {
1067 /* FIX!!! this code path is broken!!!
1068 *
1069 * The correct approach is:
1070 *
1071 * 1. read out current protection status
1072 *
1073 * 2. override read out protection status w/unprotected.
1074 *
1075 * 3. re-protect what should be protected.
1076 *
1077 */
1078 for (i = 0; i < bank->num_sectors; i++) {
1079 if (bank->sectors[i].is_protected == 1) {
1080 cfi_intel_clear_status_register(bank);
1081
1082 retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0));
1083 if (retval != ERROR_OK)
1084 return retval;
1085
1086 retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0));
1087 if (retval != ERROR_OK)
1088 return retval;
1089
1090 uint8_t status;
1091 retval = cfi_intel_wait_status_busy(bank, 100, &status);
1092 if (retval != ERROR_OK)
1093 return retval;
1094 }
1095 }
1096 }
1097
1098 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
1099 }
1100
1101 static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
1102 {
1103 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1104
1105 if (bank->target->state != TARGET_HALTED) {
1106 LOG_ERROR("Target not halted");
1107 return ERROR_TARGET_NOT_HALTED;
1108 }
1109
1110 if (cfi_info->qry[0] != 'Q')
1111 return ERROR_FLASH_BANK_NOT_PROBED;
1112
1113 switch (cfi_info->pri_id) {
1114 case 1:
1115 case 3:
1116 return cfi_intel_protect(bank, set, first, last);
1117 break;
1118 default:
1119 LOG_WARNING("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
1120 return ERROR_OK;
1121 }
1122 }
1123
1124 static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
1125 {
1126 struct target *target = bank->target;
1127
1128 uint8_t buf[CFI_MAX_BUS_WIDTH];
1129 cfi_command(bank, cmd, buf);
1130 switch (bank->bus_width) {
1131 case 1:
1132 return buf[0];
1133 break;
1134 case 2:
1135 return target_buffer_get_u16(target, buf);
1136 break;
1137 case 4:
1138 return target_buffer_get_u32(target, buf);
1139 break;
1140 default:
1141 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes",
1142 bank->bus_width);
1143 return 0;
1144 }
1145 }
1146
1147 static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer,
1148 uint32_t address, uint32_t count)
1149 {
1150 struct target *target = bank->target;
1151 struct reg_param reg_params[7];
1152 struct arm_algorithm arm_algo;
1153 struct working_area *write_algorithm;
1154 struct working_area *source = NULL;
1155 uint32_t buffer_size = 32768;
1156 uint32_t write_command_val, busy_pattern_val, error_pattern_val;
1157
1158 /* algorithm register usage:
1159 * r0: source address (in RAM)
1160 * r1: target address (in Flash)
1161 * r2: count
1162 * r3: flash write command
1163 * r4: status byte (returned to host)
1164 * r5: busy test pattern
1165 * r6: error test pattern
1166 */
1167
1168 /* see contib/loaders/flash/armv4_5_cfi_intel_32.s for src */
1169 static const uint32_t word_32_code[] = {
1170 0xe4904004, /* loop: ldr r4, [r0], #4 */
1171 0xe5813000, /* str r3, [r1] */
1172 0xe5814000, /* str r4, [r1] */
1173 0xe5914000, /* busy: ldr r4, [r1] */
1174 0xe0047005, /* and r7, r4, r5 */
1175 0xe1570005, /* cmp r7, r5 */
1176 0x1afffffb, /* bne busy */
1177 0xe1140006, /* tst r4, r6 */
1178 0x1a000003, /* bne done */
1179 0xe2522001, /* subs r2, r2, #1 */
1180 0x0a000001, /* beq done */
1181 0xe2811004, /* add r1, r1 #4 */
1182 0xeafffff2, /* b loop */
1183 0xeafffffe /* done: b -2 */
1184 };
1185
1186 /* see contib/loaders/flash/armv4_5_cfi_intel_16.s for src */
1187 static const uint32_t word_16_code[] = {
1188 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1189 0xe1c130b0, /* strh r3, [r1] */
1190 0xe1c140b0, /* strh r4, [r1] */
1191 0xe1d140b0, /* busy ldrh r4, [r1] */
1192 0xe0047005, /* and r7, r4, r5 */
1193 0xe1570005, /* cmp r7, r5 */
1194 0x1afffffb, /* bne busy */
1195 0xe1140006, /* tst r4, r6 */
1196 0x1a000003, /* bne done */
1197 0xe2522001, /* subs r2, r2, #1 */
1198 0x0a000001, /* beq done */
1199 0xe2811002, /* add r1, r1 #2 */
1200 0xeafffff2, /* b loop */
1201 0xeafffffe /* done: b -2 */
1202 };
1203
1204 /* see contib/loaders/flash/armv4_5_cfi_intel_8.s for src */
1205 static const uint32_t word_8_code[] = {
1206 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1207 0xe5c13000, /* strb r3, [r1] */
1208 0xe5c14000, /* strb r4, [r1] */
1209 0xe5d14000, /* busy ldrb r4, [r1] */
1210 0xe0047005, /* and r7, r4, r5 */
1211 0xe1570005, /* cmp r7, r5 */
1212 0x1afffffb, /* bne busy */
1213 0xe1140006, /* tst r4, r6 */
1214 0x1a000003, /* bne done */
1215 0xe2522001, /* subs r2, r2, #1 */
1216 0x0a000001, /* beq done */
1217 0xe2811001, /* add r1, r1 #1 */
1218 0xeafffff2, /* b loop */
1219 0xeafffffe /* done: b -2 */
1220 };
1221 uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1222 const uint32_t *target_code_src;
1223 uint32_t target_code_size;
1224 int retval = ERROR_OK;
1225
1226 /* check we have a supported arch */
1227 if (is_arm(target_to_arm(target))) {
1228 /* All other ARM CPUs have 32 bit instructions */
1229 arm_algo.common_magic = ARM_COMMON_MAGIC;
1230 arm_algo.core_mode = ARM_MODE_SVC;
1231 arm_algo.core_state = ARM_STATE_ARM;
1232 } else {
1233 LOG_ERROR("Unknown architecture");
1234 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1235 }
1236
1237 cfi_intel_clear_status_register(bank);
1238
1239 /* If we are setting up the write_algorith, we need target_code_src
1240 * if not we only need target_code_size. */
1241
1242 /* However, we don't want to create multiple code paths, so we
1243 * do the unnecessary evaluation of target_code_src, which the
1244 * compiler will probably nicely optimize away if not needed */
1245
1246 /* prepare algorithm code for target endian */
1247 switch (bank->bus_width) {
1248 case 1:
1249 target_code_src = word_8_code;
1250 target_code_size = sizeof(word_8_code);
1251 break;
1252 case 2:
1253 target_code_src = word_16_code;
1254 target_code_size = sizeof(word_16_code);
1255 break;
1256 case 4:
1257 target_code_src = word_32_code;
1258 target_code_size = sizeof(word_32_code);
1259 break;
1260 default:
1261 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes",
1262 bank->bus_width);
1263 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1264 }
1265
1266 /* flash write code */
1267 if (target_code_size > sizeof(target_code)) {
1268 LOG_WARNING("Internal error - target code buffer to small. "
1269 "Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1270 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1271 }
1272
1273 target_buffer_set_u32_array(target, target_code, target_code_size / 4, target_code_src);
1274
1275 /* Get memory for block write handler */
1276 retval = target_alloc_working_area(target,
1277 target_code_size,
1278 &write_algorithm);
1279 if (retval != ERROR_OK) {
1280 LOG_WARNING("No working area available, can't do block memory writes");
1281 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1282 }
1283
1284 /* write algorithm code to working area */
1285 retval = target_write_buffer(target, write_algorithm->address,
1286 target_code_size, target_code);
1287 if (retval != ERROR_OK) {
1288 LOG_ERROR("Unable to write block write code to target");
1289 goto cleanup;
1290 }
1291
1292 /* Get a workspace buffer for the data to flash starting with 32k size.
1293 * Half size until buffer would be smaller 256 Bytes then fail back */
1294 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1295 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
1296 buffer_size /= 2;
1297 if (buffer_size <= 256) {
1298 LOG_WARNING(
1299 "no large enough working area available, can't do block memory writes");
1300 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1301 goto cleanup;
1302 }
1303 }
1304
1305 /* setup algo registers */
1306 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1307 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1308 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1309 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1310 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1311 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1312 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1313
1314 /* prepare command and status register patterns */
1315 write_command_val = cfi_command_val(bank, 0x40);
1316 busy_pattern_val = cfi_command_val(bank, 0x80);
1317 error_pattern_val = cfi_command_val(bank, 0x7e);
1318
1319 LOG_DEBUG("Using target buffer at " TARGET_ADDR_FMT " and of size 0x%04" PRIx32,
1320 source->address, buffer_size);
1321
1322 /* Programming main loop */
1323 while (count > 0) {
1324 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1325 uint32_t wsm_error;
1326
1327 retval = target_write_buffer(target, source->address, thisrun_count, buffer);
1328 if (retval != ERROR_OK)
1329 goto cleanup;
1330
1331 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1332 buf_set_u32(reg_params[1].value, 0, 32, address);
1333 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1334
1335 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1336 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1337 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1338
1339 LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32,
1340 thisrun_count, address);
1341
1342 /* Execute algorithm, assume breakpoint for last instruction */
1343 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1344 write_algorithm->address,
1345 write_algorithm->address + target_code_size -
1346 sizeof(uint32_t),
1347 10000, /* 10s should be enough for max. 32k of data */
1348 &arm_algo);
1349
1350 /* On failure try a fall back to direct word writes */
1351 if (retval != ERROR_OK) {
1352 cfi_intel_clear_status_register(bank);
1353 LOG_ERROR(
1354 "Execution of flash algorythm failed. Can't fall back. Please report.");
1355 retval = ERROR_FLASH_OPERATION_FAILED;
1356 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1357 /* FIXME To allow fall back or recovery, we must save the actual status
1358 * somewhere, so that a higher level code can start recovery. */
1359 goto cleanup;
1360 }
1361
1362 /* Check return value from algo code */
1363 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1364 if (wsm_error) {
1365 /* read status register (outputs debug information) */
1366 uint8_t status;
1367 cfi_intel_wait_status_busy(bank, 100, &status);
1368 cfi_intel_clear_status_register(bank);
1369 retval = ERROR_FLASH_OPERATION_FAILED;
1370 goto cleanup;
1371 }
1372
1373 buffer += thisrun_count;
1374 address += thisrun_count;
1375 count -= thisrun_count;
1376
1377 keep_alive();
1378 }
1379
1380 /* free up resources */
1381 cleanup:
1382 if (source)
1383 target_free_working_area(target, source);
1384
1385 target_free_working_area(target, write_algorithm);
1386
1387 destroy_reg_param(&reg_params[0]);
1388 destroy_reg_param(&reg_params[1]);
1389 destroy_reg_param(&reg_params[2]);
1390 destroy_reg_param(&reg_params[3]);
1391 destroy_reg_param(&reg_params[4]);
1392 destroy_reg_param(&reg_params[5]);
1393 destroy_reg_param(&reg_params[6]);
1394
1395 return retval;
1396 }
1397
1398 static int cfi_spansion_write_block_mips(struct flash_bank *bank, const uint8_t *buffer,
1399 uint32_t address, uint32_t count)
1400 {
1401 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1402 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1403 struct target *target = bank->target;
1404 struct reg_param reg_params[10];
1405 struct mips32_algorithm mips32_info;
1406 struct working_area *write_algorithm;
1407 struct working_area *source;
1408 uint32_t buffer_size = 32768;
1409 uint32_t status;
1410 int retval = ERROR_OK;
1411
1412 /* input parameters -
1413 * 4 A0 = source address
1414 * 5 A1 = destination address
1415 * 6 A2 = number of writes
1416 * 7 A3 = flash write command
1417 * 8 T0 = constant to mask DQ7 bits (also used for Dq5 with shift)
1418 * output parameters -
1419 * 9 T1 = 0x80 ok 0x00 bad
1420 * temp registers -
1421 * 10 T2 = value read from flash to test status
1422 * 11 T3 = holding register
1423 * unlock registers -
1424 * 12 T4 = unlock1_addr
1425 * 13 T5 = unlock1_cmd
1426 * 14 T6 = unlock2_addr
1427 * 15 T7 = unlock2_cmd */
1428
1429 static const uint32_t mips_word_16_code[] = {
1430 /* start: */
1431 MIPS32_LHU(0, 9, 0, 4), /* lhu $t1, ($a0) ; out = &saddr */
1432 MIPS32_ADDI(0, 4, 4, 2), /* addi $a0, $a0, 2 ; saddr += 2 */
1433 MIPS32_SH(0, 13, 0, 12), /* sh $t5, ($t4) ; *fl_unl_addr1 = fl_unl_cmd1 */
1434 MIPS32_SH(0, 15, 0, 14), /* sh $t7, ($t6) ; *fl_unl_addr2 = fl_unl_cmd2 */
1435 MIPS32_SH(0, 7, 0, 12), /* sh $a3, ($t4) ; *fl_unl_addr1 = fl_write_cmd */
1436 MIPS32_SH(0, 9, 0, 5), /* sh $t1, ($a1) ; *daddr = out */
1437 MIPS32_NOP, /* nop */
1438 /* busy: */
1439 MIPS32_LHU(0, 10, 0, 5), /* lhu $t2, ($a1) ; temp1 = *daddr */
1440 MIPS32_XOR(0, 11, 9, 10), /* xor $t3, $a0, $t2 ; temp2 = out ^ temp1; */
1441 MIPS32_AND(0, 11, 8, 11), /* and $t3, $t0, $t3 ; temp2 = temp2 & DQ7mask */
1442 MIPS32_BNE(0, 11, 8, 13), /* bne $t3, $t0, cont ; if (temp2 != DQ7mask) goto cont */
1443 MIPS32_NOP, /* nop */
1444
1445 MIPS32_SRL(0, 10, 8, 2), /* srl $t2,$t0,2 ; temp1 = DQ7mask >> 2 */
1446 MIPS32_AND(0, 11, 10, 11), /* and $t3, $t2, $t3 ; temp2 = temp2 & temp1 */
1447 MIPS32_BNE(0, 11, 10, NEG16(8)), /* bne $t3, $t2, busy ; if (temp2 != temp1) goto busy */
1448 MIPS32_NOP, /* nop */
1449
1450 MIPS32_LHU(0, 10, 0, 5), /* lhu $t2, ($a1) ; temp1 = *daddr */
1451 MIPS32_XOR(0, 11, 9, 10), /* xor $t3, $a0, $t2 ; temp2 = out ^ temp1; */
1452 MIPS32_AND(0, 11, 8, 11), /* and $t3, $t0, $t3 ; temp2 = temp2 & DQ7mask */
1453 MIPS32_BNE(0, 11, 8, 4), /* bne $t3, $t0, cont ; if (temp2 != DQ7mask) goto cont */
1454 MIPS32_NOP, /* nop */
1455
1456 MIPS32_XOR(0, 9, 9, 9), /* xor $t1, $t1, $t1 ; out = 0 */
1457 MIPS32_BEQ(0, 9, 0, 11), /* beq $t1, $zero, done ; if (out == 0) goto done */
1458 MIPS32_NOP, /* nop */
1459 /* cont: */
1460 MIPS32_ADDI(0, 6, 6, NEG16(1)), /* addi, $a2, $a2, -1 ; numwrites-- */
1461 MIPS32_BNE(0, 6, 0, 5), /* bne $a2, $zero, cont2 ; if (numwrite != 0) goto cont2 */
1462 MIPS32_NOP, /* nop */
1463
1464 MIPS32_LUI(0, 9, 0), /* lui $t1, 0 */
1465 MIPS32_ORI(0, 9, 9, 0x80), /* ori $t1, $t1, 0x80 ; out = 0x80 */
1466
1467 MIPS32_B(0, 4), /* b done ; goto done */
1468 MIPS32_NOP, /* nop */
1469 /* cont2: */
1470 MIPS32_ADDI(0, 5, 5, 2), /* addi $a0, $a0, 2 ; daddr += 2 */
1471 MIPS32_B(0, NEG16(33)), /* b start ; goto start */
1472 MIPS32_NOP, /* nop */
1473 /* done: */
1474 MIPS32_SDBBP(0), /* sdbbp ; break(); */
1475 };
1476
1477 mips32_info.common_magic = MIPS32_COMMON_MAGIC;
1478 mips32_info.isa_mode = MIPS32_ISA_MIPS32;
1479
1480 int target_code_size = 0;
1481 const uint32_t *target_code_src = NULL;
1482
1483 switch (bank->bus_width) {
1484 case 2:
1485 /* Check for DQ5 support */
1486 if (cfi_info->status_poll_mask & (1 << 5)) {
1487 target_code_src = mips_word_16_code;
1488 target_code_size = sizeof(mips_word_16_code);
1489 } else {
1490 LOG_ERROR("Need DQ5 support");
1491 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1492 /* target_code_src = mips_word_16_code_dq7only; */
1493 /* target_code_size = sizeof(mips_word_16_code_dq7only); */
1494 }
1495 break;
1496 default:
1497 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes",
1498 bank->bus_width);
1499 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1500 }
1501
1502 /* flash write code */
1503 uint8_t *target_code;
1504
1505 /* convert bus-width dependent algorithm code to correct endianness */
1506 target_code = malloc(target_code_size);
1507 if (target_code == NULL) {
1508 LOG_ERROR("Out of memory");
1509 return ERROR_FAIL;
1510 }
1511
1512 target_buffer_set_u32_array(target, target_code, target_code_size / 4, target_code_src);
1513
1514 /* allocate working area */
1515 retval = target_alloc_working_area(target, target_code_size,
1516 &write_algorithm);
1517 if (retval != ERROR_OK) {
1518 free(target_code);
1519 return retval;
1520 }
1521
1522 /* write algorithm code to working area */
1523 retval = target_write_buffer(target, write_algorithm->address,
1524 target_code_size, target_code);
1525 if (retval != ERROR_OK) {
1526 free(target_code);
1527 return retval;
1528 }
1529
1530 free(target_code);
1531
1532 /* the following code still assumes target code is fixed 24*4 bytes */
1533
1534 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
1535 buffer_size /= 2;
1536 if (buffer_size <= 256) {
1537 /* we already allocated the writing code, but failed to get a
1538 * buffer, free the algorithm */
1539 target_free_working_area(target, write_algorithm);
1540
1541 LOG_WARNING(
1542 "not enough working area available, can't do block memory writes");
1543 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1544 }
1545 }
1546
1547 init_reg_param(&reg_params[0], "r4", 32, PARAM_OUT);
1548 init_reg_param(&reg_params[1], "r5", 32, PARAM_OUT);
1549 init_reg_param(&reg_params[2], "r6", 32, PARAM_OUT);
1550 init_reg_param(&reg_params[3], "r7", 32, PARAM_OUT);
1551 init_reg_param(&reg_params[4], "r8", 32, PARAM_OUT);
1552 init_reg_param(&reg_params[5], "r9", 32, PARAM_IN);
1553 init_reg_param(&reg_params[6], "r12", 32, PARAM_OUT);
1554 init_reg_param(&reg_params[7], "r13", 32, PARAM_OUT);
1555 init_reg_param(&reg_params[8], "r14", 32, PARAM_OUT);
1556 init_reg_param(&reg_params[9], "r15", 32, PARAM_OUT);
1557
1558 while (count > 0) {
1559 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1560
1561 retval = target_write_buffer(target, source->address, thisrun_count, buffer);
1562 if (retval != ERROR_OK)
1563 break;
1564
1565 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1566 buf_set_u32(reg_params[1].value, 0, 32, address);
1567 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1568 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1569 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1570 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1571 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1572 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1573 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1574
1575 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1576 write_algorithm->address,
1577 write_algorithm->address + ((target_code_size) - 4),
1578 10000, &mips32_info);
1579 if (retval != ERROR_OK)
1580 break;
1581
1582 status = buf_get_u32(reg_params[5].value, 0, 32);
1583 if (status != 0x80) {
1584 LOG_ERROR("flash write block failed status: 0x%" PRIx32, status);
1585 retval = ERROR_FLASH_OPERATION_FAILED;
1586 break;
1587 }
1588
1589 buffer += thisrun_count;
1590 address += thisrun_count;
1591 count -= thisrun_count;
1592 }
1593
1594 target_free_all_working_areas(target);
1595
1596 destroy_reg_param(&reg_params[0]);
1597 destroy_reg_param(&reg_params[1]);
1598 destroy_reg_param(&reg_params[2]);
1599 destroy_reg_param(&reg_params[3]);
1600 destroy_reg_param(&reg_params[4]);
1601 destroy_reg_param(&reg_params[5]);
1602 destroy_reg_param(&reg_params[6]);
1603 destroy_reg_param(&reg_params[7]);
1604 destroy_reg_param(&reg_params[8]);
1605 destroy_reg_param(&reg_params[9]);
1606
1607 return retval;
1608 }
1609
1610 static int cfi_spansion_write_block(struct flash_bank *bank, const uint8_t *buffer,
1611 uint32_t address, uint32_t count)
1612 {
1613 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1614 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1615 struct target *target = bank->target;
1616 struct reg_param reg_params[10];
1617 void *arm_algo;
1618 struct arm_algorithm armv4_5_algo;
1619 struct armv7m_algorithm armv7m_algo;
1620 struct working_area *write_algorithm;
1621 struct working_area *source;
1622 uint32_t buffer_size = 32768;
1623 uint32_t status;
1624 int retval = ERROR_OK;
1625
1626 /* input parameters -
1627 * R0 = source address
1628 * R1 = destination address
1629 * R2 = number of writes
1630 * R3 = flash write command
1631 * R4 = constant to mask DQ7 bits (also used for Dq5 with shift)
1632 * output parameters -
1633 * R5 = 0x80 ok 0x00 bad
1634 * temp registers -
1635 * R6 = value read from flash to test status
1636 * R7 = holding register
1637 * unlock registers -
1638 * R8 = unlock1_addr
1639 * R9 = unlock1_cmd
1640 * R10 = unlock2_addr
1641 * R11 = unlock2_cmd */
1642
1643 /* see contib/loaders/flash/armv4_5_cfi_span_32.s for src */
1644 static const uint32_t armv4_5_word_32_code[] = {
1645 /* 00008100 <sp_32_code>: */
1646 0xe4905004, /* ldr r5, [r0], #4 */
1647 0xe5889000, /* str r9, [r8] */
1648 0xe58ab000, /* str r11, [r10] */
1649 0xe5883000, /* str r3, [r8] */
1650 0xe5815000, /* str r5, [r1] */
1651 0xe1a00000, /* nop */
1652 /* 00008110 <sp_32_busy>: */
1653 0xe5916000, /* ldr r6, [r1] */
1654 0xe0257006, /* eor r7, r5, r6 */
1655 0xe0147007, /* ands r7, r4, r7 */
1656 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1657 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1658 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1659 0xe5916000, /* ldr r6, [r1] */
1660 0xe0257006, /* eor r7, r5, r6 */
1661 0xe0147007, /* ands r7, r4, r7 */
1662 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1663 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1664 0x1a000004, /* bne 8154 <sp_32_done> */
1665 /* 00008140 <sp_32_cont>: */
1666 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1667 0x03a05080, /* moveq r5, #128 ; 0x80 */
1668 0x0a000001, /* beq 8154 <sp_32_done> */
1669 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1670 0xeaffffe8, /* b 8100 <sp_32_code> */
1671 /* 00008154 <sp_32_done>: */
1672 0xeafffffe /* b 8154 <sp_32_done> */
1673 };
1674
1675 /* see contib/loaders/flash/armv4_5_cfi_span_16.s for src */
1676 static const uint32_t armv4_5_word_16_code[] = {
1677 /* 00008158 <sp_16_code>: */
1678 0xe0d050b2, /* ldrh r5, [r0], #2 */
1679 0xe1c890b0, /* strh r9, [r8] */
1680 0xe1cab0b0, /* strh r11, [r10] */
1681 0xe1c830b0, /* strh r3, [r8] */
1682 0xe1c150b0, /* strh r5, [r1] */
1683 0xe1a00000, /* nop (mov r0,r0) */
1684 /* 00008168 <sp_16_busy>: */
1685 0xe1d160b0, /* ldrh r6, [r1] */
1686 0xe0257006, /* eor r7, r5, r6 */
1687 0xe0147007, /* ands r7, r4, r7 */
1688 0x0a000007, /* beq 8198 <sp_16_cont> */
1689 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1690 0x0afffff9, /* beq 8168 <sp_16_busy> */
1691 0xe1d160b0, /* ldrh r6, [r1] */
1692 0xe0257006, /* eor r7, r5, r6 */
1693 0xe0147007, /* ands r7, r4, r7 */
1694 0x0a000001, /* beq 8198 <sp_16_cont> */
1695 0xe3a05000, /* mov r5, #0 ; 0x0 */
1696 0x1a000004, /* bne 81ac <sp_16_done> */
1697 /* 00008198 <sp_16_cont>: */
1698 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1699 0x03a05080, /* moveq r5, #128 ; 0x80 */
1700 0x0a000001, /* beq 81ac <sp_16_done> */
1701 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1702 0xeaffffe8, /* b 8158 <sp_16_code> */
1703 /* 000081ac <sp_16_done>: */
1704 0xeafffffe /* b 81ac <sp_16_done> */
1705 };
1706
1707 /* see contrib/loaders/flash/armv7m_cfi_span_16.s for src */
1708 static const uint32_t armv7m_word_16_code[] = {
1709 0x5B02F830,
1710 0x9000F8A8,
1711 0xB000F8AA,
1712 0x3000F8A8,
1713 0xBF00800D,
1714 0xEA85880E,
1715 0x40270706,
1716 0xEA16D00A,
1717 0xD0F70694,
1718 0xEA85880E,
1719 0x40270706,
1720 0xF04FD002,
1721 0xD1070500,
1722 0xD0023A01,
1723 0x0102F101,
1724 0xF04FE7E0,
1725 0xE7FF0580,
1726 0x0000BE00
1727 };
1728
1729 /* see contrib/loaders/flash/armv7m_cfi_span_16_dq7.s for src */
1730 static const uint32_t armv7m_word_16_code_dq7only[] = {
1731 /* 00000000 <code>: */
1732 0x5B02F830, /* ldrh.w r5, [r0], #2 */
1733 0x9000F8A8, /* strh.w r9, [r8] */
1734 0xB000F8AA, /* strh.w fp, [sl] */
1735 0x3000F8A8, /* strh.w r3, [r8] */
1736 0xBF00800D, /* strh r5, [r1, #0] */
1737 /* nop */
1738
1739 /* 00000014 <busy>: */
1740 0xEA85880E, /* ldrh r6, [r1, #0] */
1741 /* eor.w r7, r5, r6 */
1742 0x40270706, /* ands r7, r4 */
1743 0x3A01D1FA, /* bne.n 14 <busy> */
1744 /* subs r2, #1 */
1745 0xF101D002, /* beq.n 28 <success> */
1746 0xE7EB0102, /* add.w r1, r1, #2 */
1747 /* b.n 0 <code> */
1748
1749 /* 00000028 <success>: */
1750 0x0580F04F, /* mov.w r5, #128 */
1751 0xBF00E7FF, /* b.n 30 <done> */
1752 /* nop (for alignment purposes) */
1753
1754 /* 00000030 <done>: */
1755 0x0000BE00 /* bkpt 0x0000 */
1756 };
1757
1758 /* see contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s for src */
1759 static const uint32_t armv4_5_word_16_code_dq7only[] = {
1760 /* <sp_16_code>: */
1761 0xe0d050b2, /* ldrh r5, [r0], #2 */
1762 0xe1c890b0, /* strh r9, [r8] */
1763 0xe1cab0b0, /* strh r11, [r10] */
1764 0xe1c830b0, /* strh r3, [r8] */
1765 0xe1c150b0, /* strh r5, [r1] */
1766 0xe1a00000, /* nop (mov r0,r0) */
1767 /* <sp_16_busy>: */
1768 0xe1d160b0, /* ldrh r6, [r1] */
1769 0xe0257006, /* eor r7, r5, r6 */
1770 0xe2177080, /* ands r7, #0x80 */
1771 0x1afffffb, /* bne 8168 <sp_16_busy> */
1772 /* */
1773 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1774 0x03a05080, /* moveq r5, #128 ; 0x80 */
1775 0x0a000001, /* beq 81ac <sp_16_done> */
1776 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1777 0xeafffff0, /* b 8158 <sp_16_code> */
1778 /* 000081ac <sp_16_done>: */
1779 0xeafffffe /* b 81ac <sp_16_done> */
1780 };
1781
1782 /* see contrib/loaders/flash/armv4_5_cfi_span_8.s for src */
1783 static const uint32_t armv4_5_word_8_code[] = {
1784 /* 000081b0 <sp_16_code_end>: */
1785 0xe4d05001, /* ldrb r5, [r0], #1 */
1786 0xe5c89000, /* strb r9, [r8] */
1787 0xe5cab000, /* strb r11, [r10] */
1788 0xe5c83000, /* strb r3, [r8] */
1789 0xe5c15000, /* strb r5, [r1] */
1790 0xe1a00000, /* nop (mov r0,r0) */
1791 /* 000081c0 <sp_8_busy>: */
1792 0xe5d16000, /* ldrb r6, [r1] */
1793 0xe0257006, /* eor r7, r5, r6 */
1794 0xe0147007, /* ands r7, r4, r7 */
1795 0x0a000007, /* beq 81f0 <sp_8_cont> */
1796 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1797 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1798 0xe5d16000, /* ldrb r6, [r1] */
1799 0xe0257006, /* eor r7, r5, r6 */
1800 0xe0147007, /* ands r7, r4, r7 */
1801 0x0a000001, /* beq 81f0 <sp_8_cont> */
1802 0xe3a05000, /* mov r5, #0 ; 0x0 */
1803 0x1a000004, /* bne 8204 <sp_8_done> */
1804 /* 000081f0 <sp_8_cont>: */
1805 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1806 0x03a05080, /* moveq r5, #128 ; 0x80 */
1807 0x0a000001, /* beq 8204 <sp_8_done> */
1808 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1809 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1810 /* 00008204 <sp_8_done>: */
1811 0xeafffffe /* b 8204 <sp_8_done> */
1812 };
1813
1814 if (strncmp(target_type_name(target), "mips_m4k", 8) == 0)
1815 return cfi_spansion_write_block_mips(bank, buffer, address, count);
1816
1817 if (is_armv7m(target_to_armv7m(target))) { /* armv7m target */
1818 armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC;
1819 armv7m_algo.core_mode = ARM_MODE_THREAD;
1820 arm_algo = &armv7m_algo;
1821 } else if (is_arm(target_to_arm(target))) {
1822 /* All other ARM CPUs have 32 bit instructions */
1823 armv4_5_algo.common_magic = ARM_COMMON_MAGIC;
1824 armv4_5_algo.core_mode = ARM_MODE_SVC;
1825 armv4_5_algo.core_state = ARM_STATE_ARM;
1826 arm_algo = &armv4_5_algo;
1827 } else {
1828 LOG_ERROR("Unknown architecture");
1829 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1830 }
1831
1832 int target_code_size = 0;
1833 const uint32_t *target_code_src = NULL;
1834
1835 switch (bank->bus_width) {
1836 case 1:
1837 if (is_armv7m(target_to_armv7m(target))) {
1838 LOG_ERROR("Unknown ARM architecture");
1839 return ERROR_FAIL;
1840 }
1841 target_code_src = armv4_5_word_8_code;
1842 target_code_size = sizeof(armv4_5_word_8_code);
1843 break;
1844 case 2:
1845 /* Check for DQ5 support */
1846 if (cfi_info->status_poll_mask & (1 << 5)) {
1847 if (is_armv7m(target_to_armv7m(target))) {
1848 /* armv7m target */
1849 target_code_src = armv7m_word_16_code;
1850 target_code_size = sizeof(armv7m_word_16_code);
1851 } else { /* armv4_5 target */
1852 target_code_src = armv4_5_word_16_code;
1853 target_code_size = sizeof(armv4_5_word_16_code);
1854 }
1855 } else {
1856 /* No DQ5 support. Use DQ7 DATA# polling only. */
1857 if (is_armv7m(target_to_armv7m(target))) {
1858 /* armv7m target */
1859 target_code_src = armv7m_word_16_code_dq7only;
1860 target_code_size = sizeof(armv7m_word_16_code_dq7only);
1861 } else { /* armv4_5 target */
1862 target_code_src = armv4_5_word_16_code_dq7only;
1863 target_code_size = sizeof(armv4_5_word_16_code_dq7only);
1864 }
1865 }
1866 break;
1867 case 4:
1868 if (is_armv7m(target_to_armv7m(target))) {
1869 LOG_ERROR("Unknown ARM architecture");
1870 return ERROR_FAIL;
1871 }
1872 target_code_src = armv4_5_word_32_code;
1873 target_code_size = sizeof(armv4_5_word_32_code);
1874 break;
1875 default:
1876 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes",
1877 bank->bus_width);
1878 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1879 }
1880
1881 /* flash write code */
1882 uint8_t *target_code;
1883
1884 /* convert bus-width dependent algorithm code to correct endianness */
1885 target_code = malloc(target_code_size);
1886 if (target_code == NULL) {
1887 LOG_ERROR("Out of memory");
1888 return ERROR_FAIL;
1889 }
1890
1891 target_buffer_set_u32_array(target, target_code, target_code_size / 4, target_code_src);
1892
1893 /* allocate working area */
1894 retval = target_alloc_working_area(target, target_code_size,
1895 &write_algorithm);
1896 if (retval != ERROR_OK) {
1897 free(target_code);
1898 return retval;
1899 }
1900
1901 /* write algorithm code to working area */
1902 retval = target_write_buffer(target, write_algorithm->address,
1903 target_code_size, target_code);
1904 if (retval != ERROR_OK) {
1905 free(target_code);
1906 return retval;
1907 }
1908
1909 free(target_code);
1910
1911 /* the following code still assumes target code is fixed 24*4 bytes */
1912
1913 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
1914 buffer_size /= 2;
1915 if (buffer_size <= 256) {
1916 /* we already allocated the writing code, but failed to get a
1917 * buffer, free the algorithm */
1918 target_free_working_area(target, write_algorithm);
1919
1920 LOG_WARNING(
1921 "not enough working area available, can't do block memory writes");
1922 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1923 }
1924 }
1925
1926 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1927 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1928 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1929 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1930 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1931 init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1932 init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1933 init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1934 init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1935 init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1936
1937 while (count > 0) {
1938 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1939
1940 retval = target_write_buffer(target, source->address, thisrun_count, buffer);
1941 if (retval != ERROR_OK)
1942 break;
1943
1944 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1945 buf_set_u32(reg_params[1].value, 0, 32, address);
1946 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1947 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1948 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1949 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1950 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1951 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1952 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1953
1954 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1955 write_algorithm->address,
1956 write_algorithm->address + ((target_code_size) - 4),
1957 10000, arm_algo);
1958 if (retval != ERROR_OK)
1959 break;
1960
1961 status = buf_get_u32(reg_params[5].value, 0, 32);
1962 if (status != 0x80) {
1963 LOG_ERROR("flash write block failed status: 0x%" PRIx32, status);
1964 retval = ERROR_FLASH_OPERATION_FAILED;
1965 break;
1966 }
1967
1968 buffer += thisrun_count;
1969 address += thisrun_count;
1970 count -= thisrun_count;
1971 }
1972
1973 target_free_all_working_areas(target);
1974
1975 destroy_reg_param(&reg_params[0]);
1976 destroy_reg_param(&reg_params[1]);
1977 destroy_reg_param(&reg_params[2]);
1978 destroy_reg_param(&reg_params[3]);
1979 destroy_reg_param(&reg_params[4]);
1980 destroy_reg_param(&reg_params[5]);
1981 destroy_reg_param(&reg_params[6]);
1982 destroy_reg_param(&reg_params[7]);
1983 destroy_reg_param(&reg_params[8]);
1984 destroy_reg_param(&reg_params[9]);
1985
1986 return retval;
1987 }
1988
1989 static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1990 {
1991 int retval;
1992 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1993 struct target *target = bank->target;
1994
1995 cfi_intel_clear_status_register(bank);
1996 retval = cfi_send_command(bank, 0x40, address);
1997 if (retval != ERROR_OK)
1998 return retval;
1999
2000 retval = target_write_memory(target, address, bank->bus_width, 1, word);
2001 if (retval != ERROR_OK)
2002 return retval;
2003
2004 uint8_t status;
2005 retval = cfi_intel_wait_status_busy(bank, cfi_info->word_write_timeout, &status);
2006 if (retval != ERROR_OK)
2007 return retval;
2008 if (status != 0x80) {
2009 retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
2010 if (retval != ERROR_OK)
2011 return retval;
2012
2013 LOG_ERROR("couldn't write word at base " TARGET_ADDR_FMT
2014 ", address 0x%" PRIx32,
2015 bank->base, address);
2016 return ERROR_FLASH_OPERATION_FAILED;
2017 }
2018
2019 return ERROR_OK;
2020 }
2021
2022 static int cfi_intel_write_words(struct flash_bank *bank, const uint8_t *word,
2023 uint32_t wordcount, uint32_t address)
2024 {
2025 int retval;
2026 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2027 struct target *target = bank->target;
2028
2029 /* Calculate buffer size and boundary mask
2030 * buffersize is (buffer size per chip) * (number of chips)
2031 * bufferwsize is buffersize in words */
2032 uint32_t buffersize =
2033 (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
2034 uint32_t buffermask = buffersize-1;
2035 uint32_t bufferwsize = buffersize / bank->bus_width;
2036
2037 /* Check for valid range */
2038 if (address & buffermask) {
2039 LOG_ERROR("Write address at base " TARGET_ADDR_FMT ", address 0x%"
2040 PRIx32 " not aligned to 2^%d boundary",
2041 bank->base, address, cfi_info->max_buf_write_size);
2042 return ERROR_FLASH_OPERATION_FAILED;
2043 }
2044
2045 /* Check for valid size */
2046 if (wordcount > bufferwsize) {
2047 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32,
2048 wordcount, buffersize);
2049 return ERROR_FLASH_OPERATION_FAILED;
2050 }
2051
2052 /* Write to flash buffer */
2053 cfi_intel_clear_status_register(bank);
2054
2055 /* Initiate buffer operation _*/
2056 retval = cfi_send_command(bank, 0xe8, address);
2057 if (retval != ERROR_OK)
2058 return retval;
2059 uint8_t status;
2060 retval = cfi_intel_wait_status_busy(bank, cfi_info->buf_write_timeout, &status);
2061 if (retval != ERROR_OK)
2062 return retval;
2063 if (status != 0x80) {
2064 retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
2065 if (retval != ERROR_OK)
2066 return retval;
2067
2068 LOG_ERROR(
2069 "couldn't start buffer write operation at base " TARGET_ADDR_FMT
2070 ", address 0x%" PRIx32,
2071 bank->base,
2072 address);
2073 return ERROR_FLASH_OPERATION_FAILED;
2074 }
2075
2076 /* Write buffer wordcount-1 and data words */
2077 retval = cfi_send_command(bank, bufferwsize-1, address);
2078 if (retval != ERROR_OK)
2079 return retval;
2080
2081 retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word);
2082 if (retval != ERROR_OK)
2083 return retval;
2084
2085 /* Commit write operation */
2086 retval = cfi_send_command(bank, 0xd0, address);
2087 if (retval != ERROR_OK)
2088 return retval;
2089
2090 retval = cfi_intel_wait_status_busy(bank, cfi_info->buf_write_timeout, &status);
2091 if (retval != ERROR_OK)
2092 return retval;
2093
2094 if (status != 0x80) {
2095 retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
2096 if (retval != ERROR_OK)
2097 return retval;
2098
2099 LOG_ERROR("Buffer write at base " TARGET_ADDR_FMT
2100 ", address 0x%" PRIx32 " failed.", bank->base, address);
2101 return ERROR_FLASH_OPERATION_FAILED;
2102 }
2103
2104 return ERROR_OK;
2105 }
2106
2107 static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
2108 {
2109 int retval;
2110 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2111 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2112 struct target *target = bank->target;
2113
2114 retval = cfi_spansion_unlock_seq(bank);
2115 if (retval != ERROR_OK)
2116 return retval;
2117
2118 retval = cfi_send_command(bank, 0xa0, flash_address(bank, 0, pri_ext->_unlock1));
2119 if (retval != ERROR_OK)
2120 return retval;
2121
2122 retval = target_write_memory(target, address, bank->bus_width, 1, word);
2123 if (retval != ERROR_OK)
2124 return retval;
2125
2126 if (cfi_spansion_wait_status_busy(bank, cfi_info->word_write_timeout) != ERROR_OK) {
2127 retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
2128 if (retval != ERROR_OK)
2129 return retval;
2130
2131 LOG_ERROR("couldn't write word at base " TARGET_ADDR_FMT
2132 ", address 0x%" PRIx32, bank->base, address);
2133 return ERROR_FLASH_OPERATION_FAILED;
2134 }
2135
2136 return ERROR_OK;
2137 }
2138
2139 static int cfi_spansion_write_words(struct flash_bank *bank, const uint8_t *word,
2140 uint32_t wordcount, uint32_t address)
2141 {
2142 int retval;
2143 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2144 struct target *target = bank->target;
2145
2146 /* Calculate buffer size and boundary mask
2147 * buffersize is (buffer size per chip) * (number of chips)
2148 * bufferwsize is buffersize in words */
2149 uint32_t buffersize =
2150 (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
2151 uint32_t buffermask = buffersize-1;
2152 uint32_t bufferwsize = buffersize / bank->bus_width;
2153
2154 /* Check for valid range */
2155 if (address & buffermask) {
2156 LOG_ERROR("Write address at base " TARGET_ADDR_FMT
2157 ", address 0x%" PRIx32 " not aligned to 2^%d boundary",
2158 bank->base, address, cfi_info->max_buf_write_size);
2159 return ERROR_FLASH_OPERATION_FAILED;
2160 }
2161
2162 /* Check for valid size */
2163 if (wordcount > bufferwsize) {
2164 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %"
2165 PRId32, wordcount, buffersize);
2166 return ERROR_FLASH_OPERATION_FAILED;
2167 }
2168
2169 /* Unlock */
2170 retval = cfi_spansion_unlock_seq(bank);
2171 if (retval != ERROR_OK)
2172 return retval;
2173
2174 /* Buffer load command */
2175 retval = cfi_send_command(bank, 0x25, address);
2176 if (retval != ERROR_OK)
2177 return retval;
2178
2179 /* Write buffer wordcount-1 and data words */
2180 retval = cfi_send_command(bank, bufferwsize-1, address);
2181 if (retval != ERROR_OK)
2182 return retval;
2183
2184 retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word);
2185 if (retval != ERROR_OK)
2186 return retval;
2187
2188 /* Commit write operation */
2189 retval = cfi_send_command(bank, 0x29, address);
2190 if (retval != ERROR_OK)
2191 return retval;
2192
2193 if (cfi_spansion_wait_status_busy(bank, cfi_info->buf_write_timeout) != ERROR_OK) {
2194 retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
2195 if (retval != ERROR_OK)
2196 return retval;
2197
2198 LOG_ERROR("couldn't write block at base " TARGET_ADDR_FMT
2199 ", address 0x%" PRIx32 ", size 0x%" PRIx32, bank->base, address,
2200 bufferwsize);
2201 return ERROR_FLASH_OPERATION_FAILED;
2202 }
2203
2204 return ERROR_OK;
2205 }
2206
2207 static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
2208 {
2209 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2210
2211 switch (cfi_info->pri_id) {
2212 case 1:
2213 case 3:
2214 return cfi_intel_write_word(bank, word, address);
2215 break;
2216 case 2:
2217 return cfi_spansion_write_word(bank, word, address);
2218 break;
2219 default:
2220 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2221 break;
2222 }
2223
2224 return ERROR_FLASH_OPERATION_FAILED;
2225 }
2226
2227 static int cfi_write_words(struct flash_bank *bank, const uint8_t *word,
2228 uint32_t wordcount, uint32_t address)
2229 {
2230 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2231
2232 if (cfi_info->buf_write_timeout_typ == 0) {
2233 /* buffer writes are not supported */
2234 LOG_DEBUG("Buffer Writes Not Supported");
2235 return ERROR_FLASH_OPER_UNSUPPORTED;
2236 }
2237
2238 switch (cfi_info->pri_id) {
2239 case 1:
2240 case 3:
2241 return cfi_intel_write_words(bank, word, wordcount, address);
2242 break;
2243 case 2:
2244 return cfi_spansion_write_words(bank, word, wordcount, address);
2245 break;
2246 default:
2247 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2248 break;
2249 }
2250
2251 return ERROR_FLASH_OPERATION_FAILED;
2252 }
2253
2254 static int cfi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
2255 {
2256 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2257 struct target *target = bank->target;
2258 uint32_t address = bank->base + offset;
2259 uint32_t read_p;
2260 int align; /* number of unaligned bytes */
2261 uint8_t current_word[CFI_MAX_BUS_WIDTH];
2262 int i;
2263 int retval;
2264
2265 LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
2266 (int)count, (unsigned)offset);
2267
2268 if (bank->target->state != TARGET_HALTED) {
2269 LOG_ERROR("Target not halted");
2270 return ERROR_TARGET_NOT_HALTED;
2271 }
2272
2273 if (offset + count > bank->size)
2274 return ERROR_FLASH_DST_OUT_OF_BANK;
2275
2276 if (cfi_info->qry[0] != 'Q')
2277 return ERROR_FLASH_BANK_NOT_PROBED;
2278
2279 /* start at the first byte of the first word (bus_width size) */
2280 read_p = address & ~(bank->bus_width - 1);
2281 align = address - read_p;
2282 if (align != 0) {
2283 LOG_INFO("Fixup %d unaligned read head bytes", align);
2284
2285 /* read a complete word from flash */
2286 retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word);
2287 if (retval != ERROR_OK)
2288 return retval;
2289
2290 /* take only bytes we need */
2291 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
2292 *buffer++ = current_word[i];
2293
2294 read_p += bank->bus_width;
2295 }
2296
2297 align = count / bank->bus_width;
2298 if (align) {
2299 retval = target_read_memory(target, read_p, bank->bus_width, align, buffer);
2300 if (retval != ERROR_OK)
2301 return retval;
2302
2303 read_p += align * bank->bus_width;
2304 buffer += align * bank->bus_width;
2305 count -= align * bank->bus_width;
2306 }
2307
2308 if (count) {
2309 LOG_INFO("Fixup %" PRIu32 " unaligned read tail bytes", count);
2310
2311 /* read a complete word from flash */
2312 retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word);
2313 if (retval != ERROR_OK)
2314 return retval;
2315
2316 /* take only bytes we need */
2317 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2318 *buffer++ = current_word[i];
2319 }
2320
2321 return ERROR_OK;
2322 }
2323
2324 static int cfi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
2325 {
2326 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2327 struct target *target = bank->target;
2328 uint32_t address = bank->base + offset; /* address of first byte to be programmed */
2329 uint32_t write_p;
2330 int align; /* number of unaligned bytes */
2331 int blk_count; /* number of bus_width bytes for block copy */
2332 uint8_t current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being
2333 *programmed */
2334 uint8_t *swapped_buffer = NULL;
2335 const uint8_t *real_buffer = NULL;
2336 int i;
2337 int retval;
2338
2339 if (bank->target->state != TARGET_HALTED) {
2340 LOG_ERROR("Target not halted");
2341 return ERROR_TARGET_NOT_HALTED;
2342 }
2343
2344 if (offset + count > bank->size)
2345 return ERROR_FLASH_DST_OUT_OF_BANK;
2346
2347 if (cfi_info->qry[0] != 'Q')
2348 return ERROR_FLASH_BANK_NOT_PROBED;
2349
2350 /* start at the first byte of the first word (bus_width size) */
2351 write_p = address & ~(bank->bus_width - 1);
2352 align = address - write_p;
2353 if (align != 0) {
2354 LOG_INFO("Fixup %d unaligned head bytes", align);
2355
2356 /* read a complete word from flash */
2357 retval = target_read_memory(target, write_p, bank->bus_width, 1, current_word);
2358 if (retval != ERROR_OK)
2359 return retval;
2360
2361 /* replace only bytes that must be written */
2362 for (i = align;
2363 (i < bank->bus_width) && (count > 0);
2364 i++, count--)
2365 if (cfi_info->data_swap)
2366 /* data bytes are swapped (reverse endianness) */
2367 current_word[bank->bus_width - i] = *buffer++;
2368 else
2369 current_word[i] = *buffer++;
2370
2371 retval = cfi_write_word(bank, current_word, write_p);
2372 if (retval != ERROR_OK)
2373 return retval;
2374 write_p += bank->bus_width;
2375 }
2376
2377 if (cfi_info->data_swap && count) {
2378 swapped_buffer = malloc(count & ~(bank->bus_width - 1));
2379 switch (bank->bus_width) {
2380 case 2:
2381 buf_bswap16(swapped_buffer, buffer,
2382 count & ~(bank->bus_width - 1));
2383 break;
2384 case 4:
2385 buf_bswap32(swapped_buffer, buffer,
2386 count & ~(bank->bus_width - 1));
2387 break;
2388 }
2389 real_buffer = buffer;
2390 buffer = swapped_buffer;
2391 }
2392
2393 /* handle blocks of bus_size aligned bytes */
2394 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
2395 switch (cfi_info->pri_id) {
2396 /* try block writes (fails without working area) */
2397 case 1:
2398 case 3:
2399 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
2400 break;
2401 case 2:
2402 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
2403 break;
2404 default:
2405 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2406 retval = ERROR_FLASH_OPERATION_FAILED;
2407 break;
2408 }
2409 if (retval == ERROR_OK) {
2410 /* Increment pointers and decrease count on succesful block write */
2411 buffer += blk_count;
2412 write_p += blk_count;
2413 count -= blk_count;
2414 } else {
2415 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
2416 /* Calculate buffer size and boundary mask
2417 * buffersize is (buffer size per chip) * (number of chips)
2418 * bufferwsize is buffersize in words */
2419 uint32_t buffersize =
2420 (1UL <<
2421 cfi_info->max_buf_write_size) *
2422 (bank->bus_width / bank->chip_width);
2423 uint32_t buffermask = buffersize-1;
2424 uint32_t bufferwsize = buffersize / bank->bus_width;
2425
2426 /* fall back to memory writes */
2427 while (count >= (uint32_t)bank->bus_width) {
2428 int fallback;
2429 if ((write_p & 0xff) == 0) {
2430 LOG_INFO("Programming at 0x%08" PRIx32 ", count 0x%08"
2431 PRIx32 " bytes remaining", write_p, count);
2432 }
2433 fallback = 1;
2434 if ((bufferwsize > 0) && (count >= buffersize) &&
2435 !(write_p & buffermask)) {
2436 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
2437 if (retval == ERROR_OK) {
2438 buffer += buffersize;
2439 write_p += buffersize;
2440 count -= buffersize;
2441 fallback = 0;
2442 } else if (retval != ERROR_FLASH_OPER_UNSUPPORTED)
2443 return retval;
2444 }
2445 /* try the slow way? */
2446 if (fallback) {
2447 for (i = 0; i < bank->bus_width; i++)
2448 current_word[i] = *buffer++;
2449
2450 retval = cfi_write_word(bank, current_word, write_p);
2451 if (retval != ERROR_OK)
2452 return retval;
2453
2454 write_p += bank->bus_width;
2455 count -= bank->bus_width;
2456 }
2457 }
2458 } else
2459 return retval;
2460 }
2461
2462 if (swapped_buffer) {
2463 buffer = real_buffer + (buffer - swapped_buffer);
2464 free(swapped_buffer);
2465 }
2466
2467 /* return to read array mode, so we can read from flash again for padding */
2468 retval = cfi_reset(bank);
2469 if (retval != ERROR_OK)
2470 return retval;
2471
2472 /* handle unaligned tail bytes */
2473 if (count > 0) {
2474 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
2475
2476 /* read a complete word from flash */
2477 retval = target_read_memory(target, write_p, bank->bus_width, 1, current_word);
2478 if (retval != ERROR_OK)
2479 return retval;
2480
2481 /* replace only bytes that must be written */
2482 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2483 if (cfi_info->data_swap)
2484 /* data bytes are swapped (reverse endianness) */
2485 current_word[bank->bus_width - i] = *buffer++;
2486 else
2487 current_word[i] = *buffer++;
2488
2489 retval = cfi_write_word(bank, current_word, write_p);
2490 if (retval != ERROR_OK)
2491 return retval;
2492 }
2493
2494 /* return to read array mode */
2495 return cfi_reset(bank);
2496 }
2497
2498 static void cfi_fixup_reversed_erase_regions(struct flash_bank *bank, const void *param)
2499 {
2500 (void) param;
2501 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2502 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2503
2504 pri_ext->_reversed_geometry = 1;
2505 }
2506
2507 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, const void *param)
2508 {
2509 int i;
2510 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2511 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2512 (void) param;
2513
2514 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3)) {
2515 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2516
2517 for (i = 0; i < cfi_info->num_erase_regions / 2; i++) {
2518 int j = (cfi_info->num_erase_regions - 1) - i;
2519 uint32_t swap;
2520
2521 swap = cfi_info->erase_region_info[i];
2522 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2523 cfi_info->erase_region_info[j] = swap;
2524 }
2525 }
2526 }
2527
2528 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, const void *param)
2529 {
2530 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2531 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2532 const struct cfi_unlock_addresses *unlock_addresses = param;
2533
2534 pri_ext->_unlock1 = unlock_addresses->unlock1;
2535 pri_ext->_unlock2 = unlock_addresses->unlock2;
2536 }
2537
2538 static void cfi_fixup_0002_polling_bits(struct flash_bank *bank, const void *param)
2539 {
2540 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2541 const int *status_poll_mask = param;
2542
2543 cfi_info->status_poll_mask = *status_poll_mask;
2544 }
2545
2546
2547 static int cfi_query_string(struct flash_bank *bank, int address)
2548 {
2549 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2550 int retval;
2551
2552 retval = cfi_send_command(bank, 0x98, flash_address(bank, 0, address));
2553 if (retval != ERROR_OK)
2554 return retval;
2555
2556 retval = cfi_query_u8(bank, 0, 0x10, &cfi_info->qry[0]);
2557 if (retval != ERROR_OK)
2558 return retval;
2559 retval = cfi_query_u8(bank, 0, 0x11, &cfi_info->qry[1]);
2560 if (retval != ERROR_OK)
2561 return retval;
2562 retval = cfi_query_u8(bank, 0, 0x12, &cfi_info->qry[2]);
2563 if (retval != ERROR_OK)
2564 return retval;
2565
2566 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x",
2567 cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2568
2569 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y')) {
2570 retval = cfi_reset(bank);
2571 if (retval != ERROR_OK)
2572 return retval;
2573 LOG_ERROR("Could not probe bank: no QRY");
2574 return ERROR_FLASH_BANK_INVALID;
2575 }
2576
2577 return ERROR_OK;
2578 }
2579
2580 static int cfi_probe(struct flash_bank *bank)
2581 {
2582 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2583 struct target *target = bank->target;
2584 int num_sectors = 0;
2585 int i;
2586 int sector = 0;
2587 uint32_t unlock1 = 0x555;
2588 uint32_t unlock2 = 0x2aa;
2589 int retval;
2590 uint8_t value_buf0[CFI_MAX_BUS_WIDTH], value_buf1[CFI_MAX_BUS_WIDTH];
2591
2592 if (bank->target->state != TARGET_HALTED) {
2593 LOG_ERROR("Target not halted");
2594 return ERROR_TARGET_NOT_HALTED;
2595 }
2596
2597 cfi_info->probed = 0;
2598 cfi_info->num_erase_regions = 0;
2599 if (bank->sectors) {
2600 free(bank->sectors);
2601 bank->sectors = NULL;
2602 }
2603 if (cfi_info->erase_region_info) {
2604 free(cfi_info->erase_region_info);
2605 cfi_info->erase_region_info = NULL;
2606 }
2607
2608 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2609 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2610 */
2611 if (cfi_info->jedec_probe) {
2612 unlock1 = 0x5555;
2613 unlock2 = 0x2aaa;
2614 }
2615
2616 /* switch to read identifier codes mode ("AUTOSELECT") */
2617 retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, unlock1));
2618 if (retval != ERROR_OK)
2619 return retval;
2620 retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, unlock2));
2621 if (retval != ERROR_OK)
2622 return retval;
2623 retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, unlock1));
2624 if (retval != ERROR_OK)
2625 return retval;
2626
2627 retval = target_read_memory(target, flash_address(bank, 0, 0x00),
2628 bank->bus_width, 1, value_buf0);
2629 if (retval != ERROR_OK)
2630 return retval;
2631 retval = target_read_memory(target, flash_address(bank, 0, 0x01),
2632 bank->bus_width, 1, value_buf1);
2633 if (retval != ERROR_OK)
2634 return retval;
2635 switch (bank->chip_width) {
2636 case 1:
2637 cfi_info->manufacturer = *value_buf0;
2638 cfi_info->device_id = *value_buf1;
2639 break;
2640 case 2:
2641 cfi_info->manufacturer = target_buffer_get_u16(target, value_buf0);
2642 cfi_info->device_id = target_buffer_get_u16(target, value_buf1);
2643 break;
2644 case 4:
2645 cfi_info->manufacturer = target_buffer_get_u32(target, value_buf0);
2646 cfi_info->device_id = target_buffer_get_u32(target, value_buf1);
2647 break;
2648 default:
2649 LOG_ERROR("Unsupported bank chipwidth %d, can't probe memory",
2650 bank->chip_width);
2651 return ERROR_FLASH_OPERATION_FAILED;
2652 }
2653
2654 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x",
2655 cfi_info->manufacturer, cfi_info->device_id);
2656 /* switch back to read array mode */
2657 retval = cfi_reset(bank);
2658 if (retval != ERROR_OK)
2659 return retval;
2660
2661 /* check device/manufacturer ID for known non-CFI flashes. */
2662 cfi_fixup_non_cfi(bank);
2663
2664 /* query only if this is a CFI compatible flash,
2665 * otherwise the relevant info has already been filled in
2666 */
2667 if (cfi_info->not_cfi == 0) {
2668 /* enter CFI query mode
2669 * according to JEDEC Standard No. 68.01,
2670 * a single bus sequence with address = 0x55, data = 0x98 should put
2671 * the device into CFI query mode.
2672 *
2673 * SST flashes clearly violate this, and we will consider them incompatible for now
2674 */
2675
2676 retval = cfi_query_string(bank, 0x55);
2677 if (retval != ERROR_OK) {
2678 /*
2679 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2680 * be harmless enough:
2681 *
2682 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2683 */
2684 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2685 retval = cfi_query_string(bank, 0x555);
2686 }
2687 if (retval != ERROR_OK)
2688 return retval;
2689
2690 retval = cfi_query_u16(bank, 0, 0x13, &cfi_info->pri_id);
2691 if (retval != ERROR_OK)
2692 return retval;
2693 retval = cfi_query_u16(bank, 0, 0x15, &cfi_info->pri_addr);
2694 if (retval != ERROR_OK)
2695 return retval;
2696 retval = cfi_query_u16(bank, 0, 0x17, &cfi_info->alt_id);
2697 if (retval != ERROR_OK)
2698 return retval;
2699 retval = cfi_query_u16(bank, 0, 0x19, &cfi_info->alt_addr);
2700 if (retval != ERROR_OK)
2701 return retval;
2702
2703 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: "
2704 "0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1],
2705 cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr,
2706 cfi_info->alt_id, cfi_info->alt_addr);
2707
2708 retval = cfi_query_u8(bank, 0, 0x1b, &cfi_info->vcc_min);
2709 if (retval != ERROR_OK)
2710 return retval;
2711 retval = cfi_query_u8(bank, 0, 0x1c, &cfi_info->vcc_max);
2712 if (retval != ERROR_OK)
2713 return retval;
2714 retval = cfi_query_u8(bank, 0, 0x1d, &cfi_info->vpp_min);
2715 if (retval != ERROR_OK)
2716 return retval;
2717 retval = cfi_query_u8(bank, 0, 0x1e, &cfi_info->vpp_max);
2718 if (retval != ERROR_OK)
2719 return retval;
2720
2721 retval = cfi_query_u8(bank, 0, 0x1f, &cfi_info->word_write_timeout_typ);
2722 if (retval != ERROR_OK)
2723 return retval;
2724 retval = cfi_query_u8(bank, 0, 0x20, &cfi_info->buf_write_timeout_typ);
2725 if (retval != ERROR_OK)
2726 return retval;
2727 retval = cfi_query_u8(bank, 0, 0x21, &cfi_info->block_erase_timeout_typ);
2728 if (retval != ERROR_OK)
2729 return retval;
2730 retval = cfi_query_u8(bank, 0, 0x22, &cfi_info->chip_erase_timeout_typ);
2731 if (retval != ERROR_OK)
2732 return retval;
2733 retval = cfi_query_u8(bank, 0, 0x23, &cfi_info->word_write_timeout_max);
2734 if (retval != ERROR_OK)
2735 return retval;
2736 retval = cfi_query_u8(bank, 0, 0x24, &cfi_info->buf_write_timeout_max);
2737 if (retval != ERROR_OK)
2738 return retval;
2739 retval = cfi_query_u8(bank, 0, 0x25, &cfi_info->block_erase_timeout_max);
2740 if (retval != ERROR_OK)
2741 return retval;
2742 retval = cfi_query_u8(bank, 0, 0x26, &cfi_info->chip_erase_timeout_max);
2743 if (retval != ERROR_OK)
2744 return retval;
2745
2746 uint8_t data;
2747 retval = cfi_query_u8(bank, 0, 0x27, &data);
2748 if (retval != ERROR_OK)
2749 return retval;
2750 cfi_info->dev_size = 1 << data;
2751
2752 retval = cfi_query_u16(bank, 0, 0x28, &cfi_info->interface_desc);
2753 if (retval != ERROR_OK)
2754 return retval;
2755 retval = cfi_query_u16(bank, 0, 0x2a, &cfi_info->max_buf_write_size);
2756 if (retval != ERROR_OK)
2757 return retval;
2758 retval = cfi_query_u8(bank, 0, 0x2c, &cfi_info->num_erase_regions);
2759 if (retval != ERROR_OK)
2760 return retval;
2761
2762 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: 0x%x",
2763 cfi_info->dev_size, cfi_info->interface_desc,
2764 (1 << cfi_info->max_buf_write_size));
2765
2766 if (cfi_info->num_erase_regions) {
2767 cfi_info->erase_region_info = malloc(sizeof(*cfi_info->erase_region_info)
2768 * cfi_info->num_erase_regions);
2769 for (i = 0; i < cfi_info->num_erase_regions; i++) {
2770 retval = cfi_query_u32(bank,
2771 0,
2772 0x2d + (4 * i),
2773 &cfi_info->erase_region_info[i]);
2774 if (retval != ERROR_OK)
2775 return retval;
2776 LOG_DEBUG(
2777 "erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
2778 i,
2779 (cfi_info->erase_region_info[i] & 0xffff) + 1,
2780 (cfi_info->erase_region_info[i] >> 16) * 256);
2781 }
2782 } else
2783 cfi_info->erase_region_info = NULL;
2784
2785 /* We need to read the primary algorithm extended query table before calculating
2786 * the sector layout to be able to apply fixups
2787 */
2788 switch (cfi_info->pri_id) {
2789 /* Intel command set (standard and extended) */
2790 case 0x0001:
2791 case 0x0003:
2792 cfi_read_intel_pri_ext(bank);
2793 break;
2794 /* AMD/Spansion, Atmel, ... command set */
2795 case 0x0002:
2796 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /*
2797 *default
2798 *for
2799 *all
2800 *CFI
2801 *flashs
2802 **/
2803 cfi_read_0002_pri_ext(bank);
2804 break;
2805 default:
2806 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2807 break;
2808 }
2809
2810 /* return to read array mode
2811 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2812 */
2813 retval = cfi_reset(bank);
2814 if (retval != ERROR_OK)
2815 return retval;
2816 } /* end CFI case */
2817
2818 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2819 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2820 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2821 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2822 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2823
2824 LOG_DEBUG("typ. word write timeout: %u us, typ. buf write timeout: %u us, "
2825 "typ. block erase timeout: %u ms, typ. chip erase timeout: %u ms",
2826 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2827 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2828
2829 LOG_DEBUG("max. word write timeout: %u us, max. buf write timeout: %u us, "
2830 "max. block erase timeout: %u ms, max. chip erase timeout: %u ms",
2831 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2832 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2833 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2834 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2835
2836 /* convert timeouts to real values in ms */
2837 cfi_info->word_write_timeout = DIV_ROUND_UP((1L << cfi_info->word_write_timeout_typ) *
2838 (1L << cfi_info->word_write_timeout_max), 1000);
2839 cfi_info->buf_write_timeout = DIV_ROUND_UP((1L << cfi_info->buf_write_timeout_typ) *
2840 (1L << cfi_info->buf_write_timeout_max), 1000);
2841 cfi_info->block_erase_timeout = (1L << cfi_info->block_erase_timeout_typ) *
2842 (1L << cfi_info->block_erase_timeout_max);
2843 cfi_info->chip_erase_timeout = (1L << cfi_info->chip_erase_timeout_typ) *
2844 (1L << cfi_info->chip_erase_timeout_max);
2845
2846 LOG_DEBUG("calculated word write timeout: %u ms, buf write timeout: %u ms, "
2847 "block erase timeout: %u ms, chip erase timeout: %u ms",
2848 cfi_info->word_write_timeout, cfi_info->buf_write_timeout,
2849 cfi_info->block_erase_timeout, cfi_info->chip_erase_timeout);
2850
2851 /* apply fixups depending on the primary command set */
2852 switch (cfi_info->pri_id) {
2853 /* Intel command set (standard and extended) */
2854 case 0x0001:
2855 case 0x0003:
2856 cfi_fixup(bank, cfi_0001_fixups);
2857 break;
2858 /* AMD/Spansion, Atmel, ... command set */
2859 case 0x0002:
2860 cfi_fixup(bank, cfi_0002_fixups);
2861 break;
2862 default:
2863 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2864 break;
2865 }
2866
2867 if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size) {
2868 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32
2869 " size flash was found", bank->size, cfi_info->dev_size);
2870 }
2871
2872 if (cfi_info->num_erase_regions == 0) {
2873 /* a device might have only one erase block, spanning the whole device */
2874 bank->num_sectors = 1;
2875 bank->sectors = malloc(sizeof(struct flash_sector));
2876
2877 bank->sectors[sector].offset = 0x0;
2878 bank->sectors[sector].size = bank->size;
2879 bank->sectors[sector].is_erased = -1;
2880 bank->sectors[sector].is_protected = -1;
2881 } else {
2882 uint32_t offset = 0;
2883
2884 for (i = 0; i < cfi_info->num_erase_regions; i++)
2885 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2886
2887 bank->num_sectors = num_sectors;
2888 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
2889
2890 for (i = 0; i < cfi_info->num_erase_regions; i++) {
2891 uint32_t j;
2892 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++) {
2893 bank->sectors[sector].offset = offset;
2894 bank->sectors[sector].size =
2895 ((cfi_info->erase_region_info[i] >> 16) * 256)
2896 * bank->bus_width / bank->chip_width;
2897 offset += bank->sectors[sector].size;
2898 bank->sectors[sector].is_erased = -1;
2899 bank->sectors[sector].is_protected = -1;
2900 sector++;
2901 }
2902 }
2903 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width)) {
2904 LOG_WARNING(
2905 "CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2906 (cfi_info->dev_size * bank->bus_width / bank->chip_width),
2907 offset);
2908 }
2909 }
2910
2911 cfi_info->probed = 1;
2912
2913 return ERROR_OK;
2914 }
2915
2916 static int cfi_auto_probe(struct flash_bank *bank)
2917 {
2918 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2919 if (cfi_info->probed)
2920 return ERROR_OK;
2921 return cfi_probe(bank);
2922 }
2923
2924 static int cfi_intel_protect_check(struct flash_bank *bank)
2925 {
2926 int retval;
2927 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2928 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
2929 int i;
2930
2931 /* check if block lock bits are supported on this device */
2932 if (!(pri_ext->blk_status_reg_mask & 0x1))
2933 return ERROR_FLASH_OPERATION_FAILED;
2934
2935 retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55));
2936 if (retval != ERROR_OK)
2937 return retval;
2938
2939 for (i = 0; i < bank->num_sectors; i++) {
2940 uint8_t block_status;
2941 retval = cfi_get_u8(bank, i, 0x2, &block_status);
2942 if (retval != ERROR_OK)
2943 return retval;
2944
2945 if (block_status & 1)
2946 bank->sectors[i].is_protected = 1;
2947 else
2948 bank->sectors[i].is_protected = 0;
2949 }
2950
2951 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
2952 }
2953
2954 static int cfi_spansion_protect_check(struct flash_bank *bank)
2955 {
2956 int retval;
2957 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2958 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2959 int i;
2960
2961 retval = cfi_spansion_unlock_seq(bank);
2962 if (retval != ERROR_OK)
2963 return retval;
2964
2965 retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, pri_ext->_unlock1));
2966 if (retval != ERROR_OK)
2967 return retval;
2968
2969 for (i = 0; i < bank->num_sectors; i++) {
2970 uint8_t block_status;
2971 retval = cfi_get_u8(bank, i, 0x2, &block_status);
2972 if (retval != ERROR_OK)
2973 return retval;
2974
2975 if (block_status & 1)
2976 bank->sectors[i].is_protected = 1;
2977 else
2978 bank->sectors[i].is_protected = 0;
2979 }
2980
2981 return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
2982 }
2983
2984 static int cfi_protect_check(struct flash_bank *bank)
2985 {
2986 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2987
2988 if (bank->target->state != TARGET_HALTED) {
2989 LOG_ERROR("Target not halted");
2990 return ERROR_TARGET_NOT_HALTED;
2991 }
2992
2993 if (cfi_info->qry[0] != 'Q')
2994 return ERROR_FLASH_BANK_NOT_PROBED;
2995
2996 switch (cfi_info->pri_id) {
2997 case 1:
2998 case 3:
2999 return cfi_intel_protect_check(bank);
3000 break;
3001 case 2:
3002 return cfi_spansion_protect_check(bank);
3003 break;
3004 default:
3005 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
3006 break;
3007 }
3008
3009 return ERROR_OK;
3010 }
3011
3012 static int get_cfi_info(struct flash_bank *bank, char *buf, int buf_size)
3013 {
3014 int printed;
3015 struct cfi_flash_bank *cfi_info = bank->driver_priv;
3016
3017 if (cfi_info->qry[0] == 0xff) {
3018 snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
3019 return ERROR_OK;
3020 }
3021
3022 if (cfi_info->not_cfi == 0)
3023 printed = snprintf(buf, buf_size, "\nCFI flash: ");
3024 else
3025 printed = snprintf(buf, buf_size, "\nnon-CFI flash: ");
3026 buf += printed;
3027 buf_size -= printed;
3028
3029 printed = snprintf(buf, buf_size, "mfr: 0x%4.4x, id:0x%4.4x\n\n",
3030 cfi_info->manufacturer, cfi_info->device_id);
3031 buf += printed;
3032 buf_size -= printed;
3033
3034 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: "
3035 "0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n",
3036 cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2],
3037 cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
3038 buf += printed;
3039 buf_size -= printed;
3040
3041 printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, "
3042 "Vpp min: %u.%x, Vpp max: %u.%x\n",
3043 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
3044 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
3045 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
3046 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
3047 buf += printed;
3048 buf_size -= printed;
3049
3050 printed = snprintf(buf, buf_size, "typ. word write timeout: %u us, "
3051 "typ. buf write timeout: %u us, "
3052 "typ. block erase timeout: %u ms, "
3053 "typ. chip erase timeout: %u ms\n",
3054 1 << cfi_info->word_write_timeout_typ,
3055 1 << cfi_info->buf_write_timeout_typ,
3056 1 << cfi_info->block_erase_timeout_typ,
3057 1 << cfi_info->chip_erase_timeout_typ);
3058 buf += printed;
3059 buf_size -= printed;
3060
3061 printed = snprintf(buf,
3062 buf_size,
3063 "max. word write timeout: %u us, "
3064 "max. buf write timeout: %u us, max. "
3065 "block erase timeout: %u ms, max. chip erase timeout: %u ms\n",
3066 (1 <<
3067 cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
3068 (1 <<
3069 cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
3070 (1 <<
3071 cfi_info->block_erase_timeout_max) *
3072 (1 << cfi_info->block_erase_timeout_typ),
3073 (1 <<
3074 cfi_info->chip_erase_timeout_max) *
3075 (1 << cfi_info->chip_erase_timeout_typ));
3076 buf += printed;
3077 buf_size -= printed;
3078
3079 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, "
3080 "max buffer write size: 0x%x\n",
3081 cfi_info->dev_size,
3082 cfi_info->interface_desc,
3083 1 << cfi_info->max_buf_write_size);
3084 buf += printed;
3085 buf_size -= printed;
3086
3087 switch (cfi_info->pri_id) {
3088 case 1:
3089 case 3:
3090 cfi_intel_info(bank, buf, buf_size);
3091 break;
3092 case 2:
3093 cfi_spansion_info(bank, buf, buf_size);
3094 break;
3095 default:
3096 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
3097 break;
3098 }
3099
3100 return ERROR_OK;
3101 }
3102
3103 static void cfi_fixup_0002_write_buffer(struct flash_bank *bank, const void *param)
3104 {
3105 struct cfi_flash_bank *cfi_info = bank->driver_priv;
3106
3107 /* disable write buffer for M29W128G */
3108 cfi_info->buf_write_timeout_typ = 0;
3109 }
3110
3111 const struct flash_driver cfi_flash = {
3112 .name = "cfi",
3113 .flash_bank_command = cfi_flash_bank_command,
3114 .erase = cfi_erase,
3115 .protect = cfi_protect,
3116 .write = cfi_write,
3117 .read = cfi_read,
3118 .probe = cfi_probe,
3119 .auto_probe = cfi_auto_probe,
3120 /* FIXME: access flash at bus_width size */
3121 .erase_check = default_flash_blank_check,
3122 .protect_check = cfi_protect_check,
3123 .info = get_cfi_info,
3124 .free_driver_priv = default_flash_free_driver_priv,
3125 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)