1 /***************************************************************************
2 * Copyright (C) 2013 by Andrey Yurovsky *
3 * Andrey Yurovsky <yurovsky@gmail.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
26 #include "helper/binarybuffer.h"
28 #include <target/cortex_m.h>
30 #define SAMD_NUM_SECTORS 16
31 #define SAMD_PAGE_SIZE_MAX 1024
33 #define SAMD_FLASH ((uint32_t)0x00000000) /* physical Flash memory */
34 #define SAMD_USER_ROW ((uint32_t)0x00804000) /* User Row of Flash */
35 #define SAMD_PAC1 0x41000000 /* Peripheral Access Control 1 */
36 #define SAMD_DSU 0x41002000 /* Device Service Unit */
37 #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
39 #define SAMD_DSU_STATUSA 1 /* DSU status register */
40 #define SAMD_DSU_DID 0x18 /* Device ID register */
42 #define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
43 #define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
44 #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
45 #define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interupt Flag Status & Clear */
46 #define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
47 #define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
48 #define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
50 #define SAMD_CMDEX_KEY 0xA5UL
51 #define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
53 /* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */
54 #define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
55 #define SAMD_NVM_CMD_WP 0x04 /* Write Page */
56 #define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxilary Row */
57 #define SAMD_NVM_CMD_WAP 0x06 /* Write Auxilary Page */
58 #define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
59 #define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
60 #define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */
61 #define SAMD_NVM_CMD_CPRM 0x43 /* Clear Power Reduction Mode */
62 #define SAMD_NVM_CMD_PBC 0x44 /* Page Buffer Clear */
63 #define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */
64 #define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */
67 #define SAMD_NVM_CTRLB_MANW 0x80
69 /* Known identifiers */
70 #define SAMD_PROCESSOR_M0 0x01
71 #define SAMD_FAMILY_D 0x00
72 #define SAMD_FAMILY_L 0x01
73 #define SAMD_FAMILY_C 0x02
74 #define SAMD_SERIES_20 0x00
75 #define SAMD_SERIES_21 0x01
76 #define SAMD_SERIES_10 0x02
77 #define SAMD_SERIES_11 0x03
79 /* Device ID macros */
80 #define SAMD_GET_PROCESSOR(id) (id >> 28)
81 #define SAMD_GET_FAMILY(id) (((id >> 23) & 0x1F))
82 #define SAMD_GET_SERIES(id) (((id >> 16) & 0x3F))
83 #define SAMD_GET_DEVSEL(id) (id & 0xFF)
92 /* Known SAMD10 parts */
93 static const struct samd_part samd10_parts
[] = {
94 { 0x0, "SAMD10D14AMU", 16, 4 },
95 { 0x1, "SAMD10D13AMU", 8, 4 },
96 { 0x2, "SAMD10D12AMU", 4, 4 },
97 { 0x3, "SAMD10D14ASU", 16, 4 },
98 { 0x4, "SAMD10D13ASU", 8, 4 },
99 { 0x5, "SAMD10D12ASU", 4, 4 },
100 { 0x6, "SAMD10C14A", 16, 4 },
101 { 0x7, "SAMD10C13A", 8, 4 },
102 { 0x8, "SAMD10C12A", 4, 4 },
105 /* Known SAMD11 parts */
106 static const struct samd_part samd11_parts
[] = {
107 { 0x0, "SAMD11D14AMU", 16, 4 },
108 { 0x1, "SAMD11D13AMU", 8, 4 },
109 { 0x2, "SAMD11D12AMU", 4, 4 },
110 { 0x3, "SAMD11D14ASU", 16, 4 },
111 { 0x4, "SAMD11D13ASU", 8, 4 },
112 { 0x5, "SAMD11D12ASU", 4, 4 },
113 { 0x6, "SAMD11C14A", 16, 4 },
114 { 0x7, "SAMD11C13A", 8, 4 },
115 { 0x8, "SAMD11C12A", 4, 4 },
118 /* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */
119 static const struct samd_part samd20_parts
[] = {
120 { 0x0, "SAMD20J18A", 256, 32 },
121 { 0x1, "SAMD20J17A", 128, 16 },
122 { 0x2, "SAMD20J16A", 64, 8 },
123 { 0x3, "SAMD20J15A", 32, 4 },
124 { 0x4, "SAMD20J14A", 16, 2 },
125 { 0x5, "SAMD20G18A", 256, 32 },
126 { 0x6, "SAMD20G17A", 128, 16 },
127 { 0x7, "SAMD20G16A", 64, 8 },
128 { 0x8, "SAMD20G15A", 32, 4 },
129 { 0x9, "SAMD20G14A", 16, 2 },
130 { 0xA, "SAMD20E18A", 256, 32 },
131 { 0xB, "SAMD20E17A", 128, 16 },
132 { 0xC, "SAMD20E16A", 64, 8 },
133 { 0xD, "SAMD20E15A", 32, 4 },
134 { 0xE, "SAMD20E14A", 16, 2 },
137 /* Known SAMD21 parts. */
138 static const struct samd_part samd21_parts
[] = {
139 { 0x0, "SAMD21J18A", 256, 32 },
140 { 0x1, "SAMD21J17A", 128, 16 },
141 { 0x2, "SAMD21J16A", 64, 8 },
142 { 0x3, "SAMD21J15A", 32, 4 },
143 { 0x4, "SAMD21J14A", 16, 2 },
144 { 0x5, "SAMD21G18A", 256, 32 },
145 { 0x6, "SAMD21G17A", 128, 16 },
146 { 0x7, "SAMD21G16A", 64, 8 },
147 { 0x8, "SAMD21G15A", 32, 4 },
148 { 0x9, "SAMD21G14A", 16, 2 },
149 { 0xA, "SAMD21E18A", 256, 32 },
150 { 0xB, "SAMD21E17A", 128, 16 },
151 { 0xC, "SAMD21E16A", 64, 8 },
152 { 0xD, "SAMD21E15A", 32, 4 },
153 { 0xE, "SAMD21E14A", 16, 2 },
154 { 0x26, "SAMD21E16B", 64, 8 },
157 /* Known SAMR21 parts. */
158 static const struct samd_part samr21_parts
[] = {
159 { 0x19, "SAMR21G18A", 256, 32 },
160 { 0x1A, "SAMR21G17A", 128, 32 },
161 { 0x1B, "SAMR21G16A", 64, 32 },
162 { 0x1C, "SAMR21E18A", 256, 32 },
163 { 0x1D, "SAMR21E17A", 128, 32 },
164 { 0x1E, "SAMR21E16A", 64, 32 },
167 /* Known SAML21 parts. */
168 static const struct samd_part saml21_parts
[] = {
169 { 0x00, "SAML21J18A", 256, 32 },
170 { 0x01, "SAML21J17A", 128, 16 },
171 { 0x02, "SAML21J16A", 64, 8 },
172 { 0x05, "SAML21G18A", 256, 32 },
173 { 0x06, "SAML21G17A", 128, 16 },
174 { 0x07, "SAML21G16A", 64, 8 },
175 { 0x0A, "SAML21E18A", 256, 32 },
176 { 0x0B, "SAML21E17A", 128, 16 },
177 { 0x0C, "SAML21E16A", 64, 8 },
178 { 0x0D, "SAML21E15A", 32, 4 },
179 { 0x0F, "SAML21J18B", 256, 32 },
180 { 0x10, "SAML21J17B", 128, 16 },
181 { 0x11, "SAML21J16B", 64, 8 },
182 { 0x14, "SAML21G18B", 256, 32 },
183 { 0x15, "SAML21G17B", 128, 16 },
184 { 0x16, "SAML21G16B", 64, 8 },
185 { 0x19, "SAML21E18B", 256, 32 },
186 { 0x1A, "SAML21E17B", 128, 16 },
187 { 0x1B, "SAML21E16B", 64, 8 },
188 { 0x1C, "SAML21E15B", 32, 4 },
191 /* Known SAMC20 parts. */
192 static const struct samd_part samc20_parts
[] = {
193 { 0x00, "SAMC20J18A", 256, 32 },
194 { 0x01, "SAMC20J17A", 128, 16 },
195 { 0x02, "SAMC20J16A", 64, 8 },
196 { 0x03, "SAMC20J15A", 32, 4 },
197 { 0x05, "SAMC20G18A", 256, 32 },
198 { 0x06, "SAMC20G17A", 128, 16 },
199 { 0x07, "SAMC20G16A", 64, 8 },
200 { 0x08, "SAMC20G15A", 32, 4 },
201 { 0x0A, "SAMC20E18A", 256, 32 },
202 { 0x0B, "SAMC20E17A", 128, 16 },
203 { 0x0C, "SAMC20E16A", 64, 8 },
204 { 0x0D, "SAMC20E15A", 32, 4 },
207 /* Known SAMC21 parts. */
208 static const struct samd_part samc21_parts
[] = {
209 { 0x00, "SAMC21J18A", 256, 32 },
210 { 0x01, "SAMC21J17A", 128, 16 },
211 { 0x02, "SAMC21J16A", 64, 8 },
212 { 0x03, "SAMC21J15A", 32, 4 },
213 { 0x05, "SAMC21G18A", 256, 32 },
214 { 0x06, "SAMC21G17A", 128, 16 },
215 { 0x07, "SAMC21G16A", 64, 8 },
216 { 0x08, "SAMC21G15A", 32, 4 },
217 { 0x0A, "SAMC21E18A", 256, 32 },
218 { 0x0B, "SAMC21E17A", 128, 16 },
219 { 0x0C, "SAMC21E16A", 64, 8 },
220 { 0x0D, "SAMC21E15A", 32, 4 },
223 /* Each family of parts contains a parts table in the DEVSEL field of DID. The
224 * processor ID, family ID, and series ID are used to determine which exact
225 * family this is and then we can use the corresponding table. */
230 const struct samd_part
*parts
;
234 /* Known SAMD families */
235 static const struct samd_family samd_families
[] = {
236 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_20
,
237 samd20_parts
, ARRAY_SIZE(samd20_parts
) },
238 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_21
,
239 samd21_parts
, ARRAY_SIZE(samd21_parts
) },
240 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_21
,
241 samr21_parts
, ARRAY_SIZE(samr21_parts
) },
242 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_10
,
243 samd10_parts
, ARRAY_SIZE(samd10_parts
) },
244 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_11
,
245 samd11_parts
, ARRAY_SIZE(samd11_parts
) },
246 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_L
, SAMD_SERIES_21
,
247 saml21_parts
, ARRAY_SIZE(saml21_parts
) },
248 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_C
, SAMD_SERIES_20
,
249 samc20_parts
, ARRAY_SIZE(samc20_parts
) },
250 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_C
, SAMD_SERIES_21
,
251 samc21_parts
, ARRAY_SIZE(samc21_parts
) },
260 struct target
*target
;
261 struct samd_info
*next
;
264 static struct samd_info
*samd_chips
;
268 static const struct samd_part
*samd_find_part(uint32_t id
)
270 uint8_t processor
= SAMD_GET_PROCESSOR(id
);
271 uint8_t family
= SAMD_GET_FAMILY(id
);
272 uint8_t series
= SAMD_GET_SERIES(id
);
273 uint8_t devsel
= SAMD_GET_DEVSEL(id
);
275 for (unsigned i
= 0; i
< ARRAY_SIZE(samd_families
); i
++) {
276 if (samd_families
[i
].processor
== processor
&&
277 samd_families
[i
].series
== series
&&
278 samd_families
[i
].family
== family
) {
279 for (unsigned j
= 0; j
< samd_families
[i
].num_parts
; j
++) {
280 if (samd_families
[i
].parts
[j
].id
== devsel
)
281 return &samd_families
[i
].parts
[j
];
289 static int samd_protect_check(struct flash_bank
*bank
)
294 res
= target_read_u16(bank
->target
,
295 SAMD_NVMCTRL
+ SAMD_NVMCTRL_LOCK
, &lock
);
299 /* Lock bits are active-low */
300 for (int i
= 0; i
< bank
->num_sectors
; i
++)
301 bank
->sectors
[i
].is_protected
= !(lock
& (1<<i
));
306 static int samd_get_flash_page_info(struct target
*target
,
307 uint32_t *sizep
, int *nump
)
312 res
= target_read_u32(target
, SAMD_NVMCTRL
+ SAMD_NVMCTRL_PARAM
, ¶m
);
313 if (res
== ERROR_OK
) {
314 /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n)
315 * so 0 is 8KB and 7 is 1024KB. */
317 *sizep
= (8 << ((param
>> 16) & 0x7));
318 /* The NVMP field (bits 15:0) indicates the total number of pages */
320 *nump
= param
& 0xFFFF;
322 LOG_ERROR("Couldn't read NVM Parameters register");
328 static int samd_probe(struct flash_bank
*bank
)
332 struct samd_info
*chip
= (struct samd_info
*)bank
->driver_priv
;
333 const struct samd_part
*part
;
338 res
= target_read_u32(bank
->target
, SAMD_DSU
+ SAMD_DSU_DID
, &id
);
339 if (res
!= ERROR_OK
) {
340 LOG_ERROR("Couldn't read Device ID register");
344 part
= samd_find_part(id
);
346 LOG_ERROR("Couldn't find part corresponding to DID %08" PRIx32
, id
);
350 bank
->size
= part
->flash_kb
* 1024;
352 chip
->sector_size
= bank
->size
/ SAMD_NUM_SECTORS
;
354 res
= samd_get_flash_page_info(bank
->target
, &chip
->page_size
,
356 if (res
!= ERROR_OK
) {
357 LOG_ERROR("Couldn't determine Flash page size");
361 /* Sanity check: the total flash size in the DSU should match the page size
362 * multiplied by the number of pages. */
363 if (bank
->size
!= chip
->num_pages
* chip
->page_size
) {
364 LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
365 "Identified %" PRIu32
"KB Flash but NVMCTRL reports %u %" PRIu32
"B pages",
366 part
->flash_kb
, chip
->num_pages
, chip
->page_size
);
369 /* Allocate the sector table */
370 bank
->num_sectors
= SAMD_NUM_SECTORS
;
371 bank
->sectors
= calloc(bank
->num_sectors
, sizeof((bank
->sectors
)[0]));
375 /* Fill out the sector information: all SAMD sectors are the same size and
376 * there is always a fixed number of them. */
377 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
378 bank
->sectors
[i
].size
= chip
->sector_size
;
379 bank
->sectors
[i
].offset
= i
* chip
->sector_size
;
380 /* mark as unknown */
381 bank
->sectors
[i
].is_erased
= -1;
382 bank
->sectors
[i
].is_protected
= -1;
385 samd_protect_check(bank
);
390 LOG_INFO("SAMD MCU: %s (%" PRIu32
"KB Flash, %" PRIu32
"KB RAM)", part
->name
,
391 part
->flash_kb
, part
->ram_kb
);
396 static bool samd_check_error(struct target
*target
)
402 ret
= target_read_u16(target
,
403 SAMD_NVMCTRL
+ SAMD_NVMCTRL_STATUS
, &status
);
404 if (ret
!= ERROR_OK
) {
405 LOG_ERROR("Can't read NVM status");
409 if (status
& 0x001C) {
410 if (status
& (1 << 4)) /* NVME */
411 LOG_ERROR("SAMD: NVM Error");
412 if (status
& (1 << 3)) /* LOCKE */
413 LOG_ERROR("SAMD: NVM lock error");
414 if (status
& (1 << 2)) /* PROGE */
415 LOG_ERROR("SAMD: NVM programming error");
422 /* Clear the error conditions by writing a one to them */
423 ret
= target_write_u16(target
,
424 SAMD_NVMCTRL
+ SAMD_NVMCTRL_STATUS
, status
);
426 LOG_ERROR("Can't clear NVM error conditions");
431 static int samd_issue_nvmctrl_command(struct target
*target
, uint16_t cmd
)
435 if (target
->state
!= TARGET_HALTED
) {
436 LOG_ERROR("Target not halted");
437 return ERROR_TARGET_NOT_HALTED
;
440 /* Issue the NVM command */
441 res
= target_write_u16(target
,
442 SAMD_NVMCTRL
+ SAMD_NVMCTRL_CTRLA
, SAMD_NVM_CMD(cmd
));
446 /* Check to see if the NVM command resulted in an error condition. */
447 if (samd_check_error(target
))
453 static int samd_erase_row(struct target
*target
, uint32_t address
)
457 /* Set an address contained in the row to be erased */
458 res
= target_write_u32(target
,
459 SAMD_NVMCTRL
+ SAMD_NVMCTRL_ADDR
, address
>> 1);
461 /* Issue the Erase Row command to erase that row. */
463 res
= samd_issue_nvmctrl_command(target
,
464 address
== SAMD_USER_ROW
? SAMD_NVM_CMD_EAR
: SAMD_NVM_CMD_ER
);
466 if (res
!= ERROR_OK
) {
467 LOG_ERROR("Failed to erase row containing %08" PRIx32
, address
);
474 static bool is_user_row_reserved_bit(uint8_t bit
)
476 /* See Table 9-3 in the SAMD20 datasheet for more information. */
481 /* Voltage regulator internal configuration with default value of 0x70,
482 * may not be changed. */
484 /* 41 is voltage regulator internal configuration and must not be
485 * changed. 42 through 47 are reserved. */
495 /* Modify the contents of the User Row in Flash. These are described in Table
496 * 9-3 of the SAMD20 datasheet. The User Row itself has a size of one page
497 * and contains a combination of "fuses" and calibration data in bits 24:17.
498 * We therefore try not to erase the row's contents unless we absolutely have
499 * to and we don't permit modifying reserved bits. */
500 static int samd_modify_user_row(struct target
*target
, uint32_t value
,
501 uint8_t startb
, uint8_t endb
)
505 if (is_user_row_reserved_bit(startb
) || is_user_row_reserved_bit(endb
)) {
506 LOG_ERROR("Can't modify bits in the requested range");
510 /* Retrieve the MCU's page size, in bytes. This is also the size of the
511 * entire User Row. */
513 res
= samd_get_flash_page_info(target
, &page_size
, NULL
);
514 if (res
!= ERROR_OK
) {
515 LOG_ERROR("Couldn't determine Flash page size");
519 /* Make sure the size is sane before we allocate. */
520 assert(page_size
> 0 && page_size
<= SAMD_PAGE_SIZE_MAX
);
522 /* Make sure we're within the single page that comprises the User Row. */
523 if (startb
>= (page_size
* 8) || endb
>= (page_size
* 8)) {
524 LOG_ERROR("Can't modify bits outside the User Row page range");
528 uint8_t *buf
= malloc(page_size
);
532 /* Read the user row (comprising one page) by half-words. */
533 res
= target_read_memory(target
, SAMD_USER_ROW
, 2, page_size
/ 2, buf
);
537 /* We will need to erase before writing if the new value needs a '1' in any
538 * position for which the current value had a '0'. Otherwise we can avoid
540 uint32_t cur
= buf_get_u32(buf
, startb
, endb
- startb
+ 1);
541 if ((~cur
) & value
) {
542 res
= samd_erase_row(target
, SAMD_USER_ROW
);
543 if (res
!= ERROR_OK
) {
544 LOG_ERROR("Couldn't erase user row");
550 buf_set_u32(buf
, startb
, endb
- startb
+ 1, value
);
552 /* Write the page buffer back out to the target. A Flash write will be
553 * triggered automatically. */
554 res
= target_write_memory(target
, SAMD_USER_ROW
, 4, page_size
/ 4, buf
);
558 if (samd_check_error(target
)) {
572 static int samd_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
574 struct samd_info
*chip
= (struct samd_info
*)bank
->driver_priv
;
576 /* We can issue lock/unlock region commands with the target running but
577 * the settings won't persist unless we're able to modify the LOCK regions
578 * and that requires the target to be halted. */
579 if (bank
->target
->state
!= TARGET_HALTED
) {
580 LOG_ERROR("Target not halted");
581 return ERROR_TARGET_NOT_HALTED
;
586 for (int s
= first
; s
<= last
; s
++) {
587 if (set
!= bank
->sectors
[s
].is_protected
) {
588 /* Load an address that is within this sector (we use offset 0) */
589 res
= target_write_u32(bank
->target
,
590 SAMD_NVMCTRL
+ SAMD_NVMCTRL_ADDR
,
591 ((s
* chip
->sector_size
) >> 1));
595 /* Tell the controller to lock that sector */
596 res
= samd_issue_nvmctrl_command(bank
->target
,
597 set
? SAMD_NVM_CMD_LR
: SAMD_NVM_CMD_UR
);
603 /* We've now applied our changes, however they will be undone by the next
604 * reset unless we also apply them to the LOCK bits in the User Page. The
605 * LOCK bits start at bit 48, corresponding to Sector 0 and end with bit 63,
606 * corresponding to Sector 15. A '1' means unlocked and a '0' means
607 * locked. See Table 9-3 in the SAMD20 datasheet for more details. */
609 res
= samd_modify_user_row(bank
->target
, set
? 0x0000 : 0xFFFF,
610 48 + first
, 48 + last
);
612 LOG_WARNING("SAMD: protect settings were not made persistent!");
617 samd_protect_check(bank
);
622 static int samd_erase(struct flash_bank
*bank
, int first
, int last
)
626 struct samd_info
*chip
= (struct samd_info
*)bank
->driver_priv
;
628 if (bank
->target
->state
!= TARGET_HALTED
) {
629 LOG_ERROR("Target not halted");
631 return ERROR_TARGET_NOT_HALTED
;
635 if (samd_probe(bank
) != ERROR_OK
)
636 return ERROR_FLASH_BANK_NOT_PROBED
;
639 /* The SAMD NVM has row erase granularity. There are four pages in a row
640 * and the number of rows in a sector depends on the sector size, which in
641 * turn depends on the Flash capacity as there is a fixed number of
643 rows_in_sector
= chip
->sector_size
/ (chip
->page_size
* 4);
645 /* For each sector to be erased */
646 for (int s
= first
; s
<= last
; s
++) {
647 if (bank
->sectors
[s
].is_protected
) {
648 LOG_ERROR("SAMD: failed to erase sector %d. That sector is write-protected", s
);
649 return ERROR_FLASH_OPERATION_FAILED
;
652 /* For each row in that sector */
653 for (int r
= s
* rows_in_sector
; r
< (s
+ 1) * rows_in_sector
; r
++) {
654 res
= samd_erase_row(bank
->target
, r
* chip
->page_size
* 4);
655 if (res
!= ERROR_OK
) {
656 LOG_ERROR("SAMD: failed to erase sector %d", s
);
666 static int samd_write(struct flash_bank
*bank
, const uint8_t *buffer
,
667 uint32_t offset
, uint32_t count
)
675 struct samd_info
*chip
= (struct samd_info
*)bank
->driver_priv
;
679 if (bank
->target
->state
!= TARGET_HALTED
) {
680 LOG_ERROR("Target not halted");
681 return ERROR_TARGET_NOT_HALTED
;
685 if (samd_probe(bank
) != ERROR_OK
)
686 return ERROR_FLASH_BANK_NOT_PROBED
;
689 /* Check if we need to do manual page write commands */
690 res
= target_read_u32(bank
->target
, SAMD_NVMCTRL
+ SAMD_NVMCTRL_CTRLB
, &nvm_ctrlb
);
695 if (nvm_ctrlb
& SAMD_NVM_CTRLB_MANW
)
700 res
= samd_issue_nvmctrl_command(bank
->target
, SAMD_NVM_CMD_PBC
);
701 if (res
!= ERROR_OK
) {
702 LOG_ERROR("%s: %d", __func__
, __LINE__
);
707 nb
= chip
->page_size
- offset
% chip
->page_size
;
711 address
= bank
->base
+ offset
;
712 pg_offset
= offset
% chip
->page_size
;
714 if (offset
% 4 || (offset
+ nb
) % 4) {
715 /* Either start or end of write is not word aligned */
717 pb
= malloc(chip
->page_size
);
722 /* Set temporary page buffer to 0xff and overwrite the relevant part */
723 memset(pb
, 0xff, chip
->page_size
);
724 memcpy(pb
+ pg_offset
, buffer
, nb
);
726 /* Align start address to a word boundary */
727 address
-= offset
% 4;
728 pg_offset
-= offset
% 4;
729 assert(pg_offset
% 4 == 0);
731 /* Extend length to whole words */
732 nw
= (nb
+ offset
% 4 + 3) / 4;
733 assert(pg_offset
+ 4 * nw
<= chip
->page_size
);
735 /* Now we have original data extended by 0xff bytes
736 * to the nearest word boundary on both start and end */
737 res
= target_write_memory(bank
->target
, address
, 4, nw
, pb
+ pg_offset
);
741 assert(pg_offset
+ 4 * nw
<= chip
->page_size
);
743 /* Word aligned data, use direct write from buffer */
744 res
= target_write_memory(bank
->target
, address
, 4, nw
, buffer
);
746 if (res
!= ERROR_OK
) {
747 LOG_ERROR("%s: %d", __func__
, __LINE__
);
751 /* Devices with errata 13134 have automatic page write enabled by default
752 * For other devices issue a write page CMD to the NVM
753 * If the page has not been written up to the last word
754 * then issue CMD_WP always */
755 if (manual_wp
|| pg_offset
+ 4 * nw
< chip
->page_size
) {
756 res
= samd_issue_nvmctrl_command(bank
->target
, SAMD_NVM_CMD_WP
);
757 if (res
!= ERROR_OK
) {
758 LOG_ERROR("%s: %d", __func__
, __LINE__
);
763 /* Access through AHB is stalled while flash is being programmed */
766 if (samd_check_error(bank
->target
)) {
767 LOG_ERROR("%s: write failed at address 0x%08" PRIx32
, __func__
, address
);
772 /* We're done with the page contents */
785 FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command
)
787 struct samd_info
*chip
= samd_chips
;
790 if (chip
->target
== bank
->target
)
796 /* Create a new chip */
797 chip
= calloc(1, sizeof(*chip
));
801 chip
->target
= bank
->target
;
802 chip
->probed
= false;
804 bank
->driver_priv
= chip
;
806 /* Insert it into the chips list (at head) */
807 chip
->next
= samd_chips
;
811 if (bank
->base
!= SAMD_FLASH
) {
812 LOG_ERROR("Address 0x%08" PRIx32
" invalid bank address (try 0x%08" PRIx32
813 "[at91samd series] )",
814 bank
->base
, SAMD_FLASH
);
821 COMMAND_HANDLER(samd_handle_info_command
)
826 COMMAND_HANDLER(samd_handle_chip_erase_command
)
828 struct target
*target
= get_current_target(CMD_CTX
);
831 /* Enable access to the DSU by disabling the write protect bit */
832 target_write_u32(target
, SAMD_PAC1
, (1<<1));
833 /* Tell the DSU to perform a full chip erase. It takes about 240ms to
834 * perform the erase. */
835 target_write_u8(target
, SAMD_DSU
, (1<<4));
837 command_print(CMD_CTX
, "chip erased");
843 COMMAND_HANDLER(samd_handle_set_security_command
)
846 struct target
*target
= get_current_target(CMD_CTX
);
848 if (CMD_ARGC
< 1 || (CMD_ARGC
>= 1 && (strcmp(CMD_ARGV
[0], "enable")))) {
849 command_print(CMD_CTX
, "supply the \"enable\" argument to proceed.");
850 return ERROR_COMMAND_SYNTAX_ERROR
;
854 if (target
->state
!= TARGET_HALTED
) {
855 LOG_ERROR("Target not halted");
856 return ERROR_TARGET_NOT_HALTED
;
859 res
= samd_issue_nvmctrl_command(target
, SAMD_NVM_CMD_SSB
);
861 /* Check (and clear) error conditions */
863 command_print(CMD_CTX
, "chip secured on next power-cycle");
865 command_print(CMD_CTX
, "failed to secure chip");
871 COMMAND_HANDLER(samd_handle_eeprom_command
)
874 struct target
*target
= get_current_target(CMD_CTX
);
877 if (target
->state
!= TARGET_HALTED
) {
878 LOG_ERROR("Target not halted");
879 return ERROR_TARGET_NOT_HALTED
;
883 int val
= atoi(CMD_ARGV
[0]);
889 /* Try to match size in bytes with corresponding size code */
890 for (code
= 0; code
<= 6; code
++) {
891 if (val
== (2 << (13 - code
)))
896 command_print(CMD_CTX
, "Invalid EEPROM size. Please see "
897 "datasheet for a list valid sizes.");
898 return ERROR_COMMAND_SYNTAX_ERROR
;
902 res
= samd_modify_user_row(target
, code
, 4, 6);
905 res
= target_read_u16(target
, SAMD_USER_ROW
, &val
);
906 if (res
== ERROR_OK
) {
907 uint32_t size
= ((val
>> 4) & 0x7); /* grab size code */
910 command_print(CMD_CTX
, "EEPROM is disabled");
912 /* Otherwise, 6 is 256B, 0 is 16KB */
913 command_print(CMD_CTX
, "EEPROM size is %u bytes",
923 COMMAND_HANDLER(samd_handle_bootloader_command
)
926 struct target
*target
= get_current_target(CMD_CTX
);
929 if (target
->state
!= TARGET_HALTED
) {
930 LOG_ERROR("Target not halted");
931 return ERROR_TARGET_NOT_HALTED
;
934 /* Retrieve the MCU's page size, in bytes. */
936 res
= samd_get_flash_page_info(target
, &page_size
, NULL
);
937 if (res
!= ERROR_OK
) {
938 LOG_ERROR("Couldn't determine Flash page size");
943 int val
= atoi(CMD_ARGV
[0]);
949 /* Try to match size in bytes with corresponding size code */
950 for (code
= 0; code
<= 6; code
++) {
951 if ((unsigned int)val
== (2UL << (8UL - code
)) * page_size
)
956 command_print(CMD_CTX
, "Invalid bootloader size. Please "
957 "see datasheet for a list valid sizes.");
958 return ERROR_COMMAND_SYNTAX_ERROR
;
963 res
= samd_modify_user_row(target
, code
, 0, 2);
966 res
= target_read_u16(target
, SAMD_USER_ROW
, &val
);
967 if (res
== ERROR_OK
) {
968 uint32_t size
= (val
& 0x7); /* grab size code */
974 nb
= (2 << (8 - size
)) * page_size
;
976 /* There are 4 pages per row */
977 command_print(CMD_CTX
, "Bootloader size is %" PRIu32
" bytes (%" PRIu32
" rows)",
978 nb
, (uint32_t)(nb
/ (page_size
* 4)));
988 COMMAND_HANDLER(samd_handle_reset_deassert
)
990 struct target
*target
= get_current_target(CMD_CTX
);
991 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
992 int retval
= ERROR_OK
;
993 enum reset_types jtag_reset_config
= jtag_get_reset_config();
995 /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
996 * so we just release reset held by DSU
998 * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
1000 * After vectreset DSU release is not needed however makes no harm
1002 if (target
->reset_halt
&& (jtag_reset_config
& RESET_HAS_SRST
)) {
1003 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DHCSR
, DBGKEY
| C_HALT
| C_DEBUGEN
);
1004 if (retval
== ERROR_OK
)
1005 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
,
1006 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1007 /* do not return on error here, releasing DSU reset is more important */
1010 /* clear CPU Reset Phase Extension bit */
1011 int retval2
= target_write_u8(target
, SAMD_DSU
+ SAMD_DSU_STATUSA
, (1<<1));
1012 if (retval2
!= ERROR_OK
)
1018 static const struct command_registration at91samd_exec_command_handlers
[] = {
1020 .name
= "dsu_reset_deassert",
1021 .handler
= samd_handle_reset_deassert
,
1022 .mode
= COMMAND_EXEC
,
1023 .help
= "deasert internal reset held by DSU"
1027 .handler
= samd_handle_info_command
,
1028 .mode
= COMMAND_EXEC
,
1029 .help
= "Print information about the current at91samd chip"
1030 "and its flash configuration.",
1033 .name
= "chip-erase",
1034 .handler
= samd_handle_chip_erase_command
,
1035 .mode
= COMMAND_EXEC
,
1036 .help
= "Erase the entire Flash by using the Chip"
1037 "Erase feature in the Device Service Unit (DSU).",
1040 .name
= "set-security",
1041 .handler
= samd_handle_set_security_command
,
1042 .mode
= COMMAND_EXEC
,
1043 .help
= "Secure the chip's Flash by setting the Security Bit."
1044 "This makes it impossible to read the Flash contents."
1045 "The only way to undo this is to issue the chip-erase"
1050 .usage
= "[size_in_bytes]",
1051 .handler
= samd_handle_eeprom_command
,
1052 .mode
= COMMAND_EXEC
,
1053 .help
= "Show or set the EEPROM size setting, stored in the User Row."
1054 "Please see Table 20-3 of the SAMD20 datasheet for allowed values."
1055 "Changes are stored immediately but take affect after the MCU is"
1059 .name
= "bootloader",
1060 .usage
= "[size_in_bytes]",
1061 .handler
= samd_handle_bootloader_command
,
1062 .mode
= COMMAND_EXEC
,
1063 .help
= "Show or set the bootloader size, stored in the User Row."
1064 "Please see Table 20-2 of the SAMD20 datasheet for allowed values."
1065 "Changes are stored immediately but take affect after the MCU is"
1068 COMMAND_REGISTRATION_DONE
1071 static const struct command_registration at91samd_command_handlers
[] = {
1074 .mode
= COMMAND_ANY
,
1075 .help
= "at91samd flash command group",
1077 .chain
= at91samd_exec_command_handlers
,
1079 COMMAND_REGISTRATION_DONE
1082 struct flash_driver at91samd_flash
= {
1084 .commands
= at91samd_command_handlers
,
1085 .flash_bank_command
= samd_flash_bank_command
,
1086 .erase
= samd_erase
,
1087 .protect
= samd_protect
,
1088 .write
= samd_write
,
1089 .read
= default_flash_read
,
1090 .probe
= samd_probe
,
1091 .auto_probe
= samd_probe
,
1092 .erase_check
= default_flash_blank_check
,
1093 .protect_check
= samd_protect_check
,
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