at91samd: Add flash programming support for SAMC2?N* parts
[openocd.git] / src / flash / nor / at91samd.c
1 /***************************************************************************
2 * Copyright (C) 2013 by Andrey Yurovsky *
3 * Andrey Yurovsky <yurovsky@gmail.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18
19 #ifdef HAVE_CONFIG_H
20 #include "config.h"
21 #endif
22
23 #include "imp.h"
24 #include "helper/binarybuffer.h"
25
26 #include <target/cortex_m.h>
27
28 #define SAMD_NUM_PROT_BLOCKS 16
29 #define SAMD_PAGE_SIZE_MAX 1024
30
31 #define SAMD_FLASH ((uint32_t)0x00000000) /* physical Flash memory */
32 #define SAMD_USER_ROW ((uint32_t)0x00804000) /* User Row of Flash */
33 #define SAMD_PAC1 0x41000000 /* Peripheral Access Control 1 */
34 #define SAMD_DSU 0x41002000 /* Device Service Unit */
35 #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
36
37 #define SAMD_DSU_STATUSA 1 /* DSU status register */
38 #define SAMD_DSU_DID 0x18 /* Device ID register */
39 #define SAMD_DSU_CTRL_EXT 0x100 /* CTRL register, external access */
40
41 #define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
42 #define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
43 #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
44 #define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interupt Flag Status & Clear */
45 #define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
46 #define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
47 #define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
48
49 #define SAMD_CMDEX_KEY 0xA5UL
50 #define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
51
52 /* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */
53 #define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
54 #define SAMD_NVM_CMD_WP 0x04 /* Write Page */
55 #define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxilary Row */
56 #define SAMD_NVM_CMD_WAP 0x06 /* Write Auxilary Page */
57 #define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
58 #define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
59 #define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */
60 #define SAMD_NVM_CMD_CPRM 0x43 /* Clear Power Reduction Mode */
61 #define SAMD_NVM_CMD_PBC 0x44 /* Page Buffer Clear */
62 #define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */
63 #define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */
64
65 /* NVMCTRL bits */
66 #define SAMD_NVM_CTRLB_MANW 0x80
67
68 /* Known identifiers */
69 #define SAMD_PROCESSOR_M0 0x01
70 #define SAMD_FAMILY_D 0x00
71 #define SAMD_FAMILY_L 0x01
72 #define SAMD_FAMILY_C 0x02
73 #define SAMD_SERIES_20 0x00
74 #define SAMD_SERIES_21 0x01
75 #define SAMD_SERIES_22 0x02
76 #define SAMD_SERIES_10 0x02
77 #define SAMD_SERIES_11 0x03
78 #define SAMD_SERIES_09 0x04
79
80 /* Device ID macros */
81 #define SAMD_GET_PROCESSOR(id) (id >> 28)
82 #define SAMD_GET_FAMILY(id) (((id >> 23) & 0x1F))
83 #define SAMD_GET_SERIES(id) (((id >> 16) & 0x3F))
84 #define SAMD_GET_DEVSEL(id) (id & 0xFF)
85
86 /* Bits to mask out lockbits in user row */
87 #define NVMUSERROW_LOCKBIT_MASK ((uint64_t)0x0000FFFFFFFFFFFF)
88
89 struct samd_part {
90 uint8_t id;
91 const char *name;
92 uint32_t flash_kb;
93 uint32_t ram_kb;
94 };
95
96 /* Known SAMD09 parts. DID reset values missing in RM, see
97 * https://github.com/avrxml/asf/blob/master/sam0/utils/cmsis/samd09/include/ */
98 static const struct samd_part samd09_parts[] = {
99 { 0x0, "SAMD09D14A", 16, 4 },
100 { 0x7, "SAMD09C13A", 8, 4 },
101 };
102
103 /* Known SAMD10 parts */
104 static const struct samd_part samd10_parts[] = {
105 { 0x0, "SAMD10D14AMU", 16, 4 },
106 { 0x1, "SAMD10D13AMU", 8, 4 },
107 { 0x2, "SAMD10D12AMU", 4, 4 },
108 { 0x3, "SAMD10D14ASU", 16, 4 },
109 { 0x4, "SAMD10D13ASU", 8, 4 },
110 { 0x5, "SAMD10D12ASU", 4, 4 },
111 { 0x6, "SAMD10C14A", 16, 4 },
112 { 0x7, "SAMD10C13A", 8, 4 },
113 { 0x8, "SAMD10C12A", 4, 4 },
114 };
115
116 /* Known SAMD11 parts */
117 static const struct samd_part samd11_parts[] = {
118 { 0x0, "SAMD11D14AM", 16, 4 },
119 { 0x1, "SAMD11D13AMU", 8, 4 },
120 { 0x2, "SAMD11D12AMU", 4, 4 },
121 { 0x3, "SAMD11D14ASS", 16, 4 },
122 { 0x4, "SAMD11D13ASU", 8, 4 },
123 { 0x5, "SAMD11D12ASU", 4, 4 },
124 { 0x6, "SAMD11C14A", 16, 4 },
125 { 0x7, "SAMD11C13A", 8, 4 },
126 { 0x8, "SAMD11C12A", 4, 4 },
127 { 0x9, "SAMD11D14AU", 16, 4 },
128 };
129
130 /* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */
131 static const struct samd_part samd20_parts[] = {
132 { 0x0, "SAMD20J18A", 256, 32 },
133 { 0x1, "SAMD20J17A", 128, 16 },
134 { 0x2, "SAMD20J16A", 64, 8 },
135 { 0x3, "SAMD20J15A", 32, 4 },
136 { 0x4, "SAMD20J14A", 16, 2 },
137 { 0x5, "SAMD20G18A", 256, 32 },
138 { 0x6, "SAMD20G17A", 128, 16 },
139 { 0x7, "SAMD20G16A", 64, 8 },
140 { 0x8, "SAMD20G15A", 32, 4 },
141 { 0x9, "SAMD20G14A", 16, 2 },
142 { 0xA, "SAMD20E18A", 256, 32 },
143 { 0xB, "SAMD20E17A", 128, 16 },
144 { 0xC, "SAMD20E16A", 64, 8 },
145 { 0xD, "SAMD20E15A", 32, 4 },
146 { 0xE, "SAMD20E14A", 16, 2 },
147 };
148
149 /* Known SAMD21 parts. */
150 static const struct samd_part samd21_parts[] = {
151 { 0x0, "SAMD21J18A", 256, 32 },
152 { 0x1, "SAMD21J17A", 128, 16 },
153 { 0x2, "SAMD21J16A", 64, 8 },
154 { 0x3, "SAMD21J15A", 32, 4 },
155 { 0x4, "SAMD21J14A", 16, 2 },
156 { 0x5, "SAMD21G18A", 256, 32 },
157 { 0x6, "SAMD21G17A", 128, 16 },
158 { 0x7, "SAMD21G16A", 64, 8 },
159 { 0x8, "SAMD21G15A", 32, 4 },
160 { 0x9, "SAMD21G14A", 16, 2 },
161 { 0xA, "SAMD21E18A", 256, 32 },
162 { 0xB, "SAMD21E17A", 128, 16 },
163 { 0xC, "SAMD21E16A", 64, 8 },
164 { 0xD, "SAMD21E15A", 32, 4 },
165 { 0xE, "SAMD21E14A", 16, 2 },
166
167 /* SAMR21 parts have integrated SAMD21 with a radio */
168 { 0x18, "SAMR21G19A", 256, 32 }, /* with 512k of serial flash */
169 { 0x19, "SAMR21G18A", 256, 32 },
170 { 0x1A, "SAMR21G17A", 128, 32 },
171 { 0x1B, "SAMR21G16A", 64, 16 },
172 { 0x1C, "SAMR21E18A", 256, 32 },
173 { 0x1D, "SAMR21E17A", 128, 32 },
174 { 0x1E, "SAMR21E16A", 64, 16 },
175
176 /* SAMD21 B Variants (Table 3-7 from rev I of datasheet) */
177 { 0x20, "SAMD21J16B", 64, 8 },
178 { 0x21, "SAMD21J15B", 32, 4 },
179 { 0x23, "SAMD21G16B", 64, 8 },
180 { 0x24, "SAMD21G15B", 32, 4 },
181 { 0x26, "SAMD21E16B", 64, 8 },
182 { 0x27, "SAMD21E15B", 32, 4 },
183
184 /* Known SAMDA1 parts.
185 SAMD-A1 series uses the same series identifier like the SAMD21
186 taken from http://ww1.microchip.com/downloads/en/DeviceDoc/40001895A.pdf (pages 14-17) */
187 { 0x29, "SAMDA1J16A", 64, 8 },
188 { 0x2A, "SAMDA1J15A", 32, 4 },
189 { 0x2B, "SAMDA1J14A", 16, 4 },
190 { 0x2C, "SAMDA1G16A", 64, 8 },
191 { 0x2D, "SAMDA1G15A", 32, 4 },
192 { 0x2E, "SAMDA1G14A", 16, 4 },
193 { 0x2F, "SAMDA1E16A", 64, 8 },
194 { 0x30, "SAMDA1E15A", 32, 4 },
195 { 0x31, "SAMDA1E14A", 16, 4 },
196 { 0x64, "SAMDA1J16B", 64, 8 },
197 { 0x65, "SAMDA1J15B", 32, 4 },
198 { 0x66, "SAMDA1J14B", 16, 4 },
199 { 0x67, "SAMDA1G16B", 64, 8 },
200 { 0x68, "SAMDA1G15B", 32, 4 },
201 { 0x69, "SAMDA1G14B", 16, 4 },
202 { 0x6A, "SAMDA1E16B", 64, 8 },
203 { 0x6B, "SAMDA1E15B", 32, 4 },
204 { 0x6C, "SAMDA1E14B", 16, 4 },
205 };
206
207 /* Known SAML21 parts. */
208 static const struct samd_part saml21_parts[] = {
209 { 0x00, "SAML21J18A", 256, 32 },
210 { 0x01, "SAML21J17A", 128, 16 },
211 { 0x02, "SAML21J16A", 64, 8 },
212 { 0x05, "SAML21G18A", 256, 32 },
213 { 0x06, "SAML21G17A", 128, 16 },
214 { 0x07, "SAML21G16A", 64, 8 },
215 { 0x0A, "SAML21E18A", 256, 32 },
216 { 0x0B, "SAML21E17A", 128, 16 },
217 { 0x0C, "SAML21E16A", 64, 8 },
218 { 0x0D, "SAML21E15A", 32, 4 },
219 { 0x0F, "SAML21J18B", 256, 32 },
220 { 0x10, "SAML21J17B", 128, 16 },
221 { 0x11, "SAML21J16B", 64, 8 },
222 { 0x14, "SAML21G18B", 256, 32 },
223 { 0x15, "SAML21G17B", 128, 16 },
224 { 0x16, "SAML21G16B", 64, 8 },
225 { 0x19, "SAML21E18B", 256, 32 },
226 { 0x1A, "SAML21E17B", 128, 16 },
227 { 0x1B, "SAML21E16B", 64, 8 },
228 { 0x1C, "SAML21E15B", 32, 4 },
229
230 /* SAMR30 parts have integrated SAML21 with a radio */
231 { 0x1E, "SAMR30G18A", 256, 32 },
232 { 0x1F, "SAMR30E18A", 256, 32 },
233
234 /* SAMR34/R35 parts have integrated SAML21 with a lora radio */
235 { 0x28, "SAMR34J18", 256, 32 },
236 };
237
238 /* Known SAML22 parts. */
239 static const struct samd_part saml22_parts[] = {
240 { 0x00, "SAML22N18A", 256, 32 },
241 { 0x01, "SAML22N17A", 128, 16 },
242 { 0x02, "SAML22N16A", 64, 8 },
243 { 0x05, "SAML22J18A", 256, 32 },
244 { 0x06, "SAML22J17A", 128, 16 },
245 { 0x07, "SAML22J16A", 64, 8 },
246 { 0x0A, "SAML22G18A", 256, 32 },
247 { 0x0B, "SAML22G17A", 128, 16 },
248 { 0x0C, "SAML22G16A", 64, 8 },
249 };
250
251 /* Known SAMC20 parts. */
252 static const struct samd_part samc20_parts[] = {
253 { 0x00, "SAMC20J18A", 256, 32 },
254 { 0x01, "SAMC20J17A", 128, 16 },
255 { 0x02, "SAMC20J16A", 64, 8 },
256 { 0x03, "SAMC20J15A", 32, 4 },
257 { 0x05, "SAMC20G18A", 256, 32 },
258 { 0x06, "SAMC20G17A", 128, 16 },
259 { 0x07, "SAMC20G16A", 64, 8 },
260 { 0x08, "SAMC20G15A", 32, 4 },
261 { 0x0A, "SAMC20E18A", 256, 32 },
262 { 0x0B, "SAMC20E17A", 128, 16 },
263 { 0x0C, "SAMC20E16A", 64, 8 },
264 { 0x0D, "SAMC20E15A", 32, 4 },
265 { 0x20, "SAMC20N18A", 256, 32 },
266 { 0x21, "SAMC20N17A", 128, 16 },
267 };
268
269 /* Known SAMC21 parts. */
270 static const struct samd_part samc21_parts[] = {
271 { 0x00, "SAMC21J18A", 256, 32 },
272 { 0x01, "SAMC21J17A", 128, 16 },
273 { 0x02, "SAMC21J16A", 64, 8 },
274 { 0x03, "SAMC21J15A", 32, 4 },
275 { 0x05, "SAMC21G18A", 256, 32 },
276 { 0x06, "SAMC21G17A", 128, 16 },
277 { 0x07, "SAMC21G16A", 64, 8 },
278 { 0x08, "SAMC21G15A", 32, 4 },
279 { 0x0A, "SAMC21E18A", 256, 32 },
280 { 0x0B, "SAMC21E17A", 128, 16 },
281 { 0x0C, "SAMC21E16A", 64, 8 },
282 { 0x0D, "SAMC21E15A", 32, 4 },
283 { 0x20, "SAMC21N18A", 256, 32 },
284 { 0x21, "SAMC21N17A", 128, 16 },
285 };
286
287 /* Each family of parts contains a parts table in the DEVSEL field of DID. The
288 * processor ID, family ID, and series ID are used to determine which exact
289 * family this is and then we can use the corresponding table. */
290 struct samd_family {
291 uint8_t processor;
292 uint8_t family;
293 uint8_t series;
294 const struct samd_part *parts;
295 size_t num_parts;
296 uint64_t nvm_userrow_res_mask; /* protect bits which are reserved, 0 -> protect */
297 };
298
299 /* Known SAMD families */
300 static const struct samd_family samd_families[] = {
301 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_20,
302 samd20_parts, ARRAY_SIZE(samd20_parts),
303 (uint64_t)0xFFFF01FFFE01FF77 },
304 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
305 samd21_parts, ARRAY_SIZE(samd21_parts),
306 (uint64_t)0xFFFF01FFFE01FF77 },
307 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_09,
308 samd09_parts, ARRAY_SIZE(samd09_parts),
309 (uint64_t)0xFFFF01FFFE01FF77 },
310 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_10,
311 samd10_parts, ARRAY_SIZE(samd10_parts),
312 (uint64_t)0xFFFF01FFFE01FF77 },
313 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11,
314 samd11_parts, ARRAY_SIZE(samd11_parts),
315 (uint64_t)0xFFFF01FFFE01FF77 },
316 { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_21,
317 saml21_parts, ARRAY_SIZE(saml21_parts),
318 (uint64_t)0xFFFF03FFFC01FF77 },
319 { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_22,
320 saml22_parts, ARRAY_SIZE(saml22_parts),
321 (uint64_t)0xFFFF03FFFC01FF77 },
322 { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_20,
323 samc20_parts, ARRAY_SIZE(samc20_parts),
324 (uint64_t)0xFFFF03FFFC01FF77 },
325 { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_21,
326 samc21_parts, ARRAY_SIZE(samc21_parts),
327 (uint64_t)0xFFFF03FFFC01FF77 },
328 };
329
330 struct samd_info {
331 uint32_t page_size;
332 int num_pages;
333 int sector_size;
334 int prot_block_size;
335
336 bool probed;
337 struct target *target;
338 };
339
340
341 /**
342 * Gives the family structure to specific device id.
343 * @param id The id of the device.
344 * @return On failure NULL, otherwise a pointer to the structure.
345 */
346 static const struct samd_family *samd_find_family(uint32_t id)
347 {
348 uint8_t processor = SAMD_GET_PROCESSOR(id);
349 uint8_t family = SAMD_GET_FAMILY(id);
350 uint8_t series = SAMD_GET_SERIES(id);
351
352 for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) {
353 if (samd_families[i].processor == processor &&
354 samd_families[i].series == series &&
355 samd_families[i].family == family)
356 return &samd_families[i];
357 }
358
359 return NULL;
360 }
361
362 /**
363 * Gives the part structure to specific device id.
364 * @param id The id of the device.
365 * @return On failure NULL, otherwise a pointer to the structure.
366 */
367 static const struct samd_part *samd_find_part(uint32_t id)
368 {
369 uint8_t devsel = SAMD_GET_DEVSEL(id);
370 const struct samd_family *family = samd_find_family(id);
371 if (family == NULL)
372 return NULL;
373
374 for (unsigned i = 0; i < family->num_parts; i++) {
375 if (family->parts[i].id == devsel)
376 return &family->parts[i];
377 }
378
379 return NULL;
380 }
381
382 static int samd_protect_check(struct flash_bank *bank)
383 {
384 int res, prot_block;
385 uint16_t lock;
386
387 res = target_read_u16(bank->target,
388 SAMD_NVMCTRL + SAMD_NVMCTRL_LOCK, &lock);
389 if (res != ERROR_OK)
390 return res;
391
392 /* Lock bits are active-low */
393 for (prot_block = 0; prot_block < bank->num_prot_blocks; prot_block++)
394 bank->prot_blocks[prot_block].is_protected = !(lock & (1u<<prot_block));
395
396 return ERROR_OK;
397 }
398
399 static int samd_get_flash_page_info(struct target *target,
400 uint32_t *sizep, int *nump)
401 {
402 int res;
403 uint32_t param;
404
405 res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, &param);
406 if (res == ERROR_OK) {
407 /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n)
408 * so 0 is 8KB and 7 is 1024KB. */
409 if (sizep)
410 *sizep = (8 << ((param >> 16) & 0x7));
411 /* The NVMP field (bits 15:0) indicates the total number of pages */
412 if (nump)
413 *nump = param & 0xFFFF;
414 } else {
415 LOG_ERROR("Couldn't read NVM Parameters register");
416 }
417
418 return res;
419 }
420
421 static int samd_probe(struct flash_bank *bank)
422 {
423 uint32_t id;
424 int res;
425 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
426 const struct samd_part *part;
427
428 if (chip->probed)
429 return ERROR_OK;
430
431 res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
432 if (res != ERROR_OK) {
433 LOG_ERROR("Couldn't read Device ID register");
434 return res;
435 }
436
437 part = samd_find_part(id);
438 if (part == NULL) {
439 LOG_ERROR("Couldn't find part corresponding to DID %08" PRIx32, id);
440 return ERROR_FAIL;
441 }
442
443 bank->size = part->flash_kb * 1024;
444
445 res = samd_get_flash_page_info(bank->target, &chip->page_size,
446 &chip->num_pages);
447 if (res != ERROR_OK) {
448 LOG_ERROR("Couldn't determine Flash page size");
449 return res;
450 }
451
452 /* Sanity check: the total flash size in the DSU should match the page size
453 * multiplied by the number of pages. */
454 if (bank->size != chip->num_pages * chip->page_size) {
455 LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
456 "Identified %" PRIu32 "KB Flash but NVMCTRL reports %u %" PRIu32 "B pages",
457 part->flash_kb, chip->num_pages, chip->page_size);
458 }
459
460 /* Erase granularity = 1 row = 4 pages */
461 chip->sector_size = chip->page_size * 4;
462
463 /* Allocate the sector table */
464 bank->num_sectors = chip->num_pages / 4;
465 bank->sectors = alloc_block_array(0, chip->sector_size, bank->num_sectors);
466 if (!bank->sectors)
467 return ERROR_FAIL;
468
469 /* 16 protection blocks per device */
470 chip->prot_block_size = bank->size / SAMD_NUM_PROT_BLOCKS;
471
472 /* Allocate the table of protection blocks */
473 bank->num_prot_blocks = SAMD_NUM_PROT_BLOCKS;
474 bank->prot_blocks = alloc_block_array(0, chip->prot_block_size, bank->num_prot_blocks);
475 if (!bank->prot_blocks)
476 return ERROR_FAIL;
477
478 samd_protect_check(bank);
479
480 /* Done */
481 chip->probed = true;
482
483 LOG_INFO("SAMD MCU: %s (%" PRIu32 "KB Flash, %" PRIu32 "KB RAM)", part->name,
484 part->flash_kb, part->ram_kb);
485
486 return ERROR_OK;
487 }
488
489 static int samd_check_error(struct target *target)
490 {
491 int ret, ret2;
492 uint16_t status;
493
494 ret = target_read_u16(target,
495 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status);
496 if (ret != ERROR_OK) {
497 LOG_ERROR("Can't read NVM status");
498 return ret;
499 }
500
501 if ((status & 0x001C) == 0)
502 return ERROR_OK;
503
504 if (status & (1 << 4)) { /* NVME */
505 LOG_ERROR("SAMD: NVM Error");
506 ret = ERROR_FLASH_OPERATION_FAILED;
507 }
508
509 if (status & (1 << 3)) { /* LOCKE */
510 LOG_ERROR("SAMD: NVM lock error");
511 ret = ERROR_FLASH_PROTECTED;
512 }
513
514 if (status & (1 << 2)) { /* PROGE */
515 LOG_ERROR("SAMD: NVM programming error");
516 ret = ERROR_FLASH_OPER_UNSUPPORTED;
517 }
518
519 /* Clear the error conditions by writing a one to them */
520 ret2 = target_write_u16(target,
521 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, status);
522 if (ret2 != ERROR_OK)
523 LOG_ERROR("Can't clear NVM error conditions");
524
525 return ret;
526 }
527
528 static int samd_issue_nvmctrl_command(struct target *target, uint16_t cmd)
529 {
530 int res;
531
532 if (target->state != TARGET_HALTED) {
533 LOG_ERROR("Target not halted");
534 return ERROR_TARGET_NOT_HALTED;
535 }
536
537 /* Issue the NVM command */
538 res = target_write_u16(target,
539 SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, SAMD_NVM_CMD(cmd));
540 if (res != ERROR_OK)
541 return res;
542
543 /* Check to see if the NVM command resulted in an error condition. */
544 return samd_check_error(target);
545 }
546
547 /**
548 * Erases a flash-row at the given address.
549 * @param target Pointer to the target structure.
550 * @param address The address of the row.
551 * @return On success ERROR_OK, on failure an errorcode.
552 */
553 static int samd_erase_row(struct target *target, uint32_t address)
554 {
555 int res;
556
557 /* Set an address contained in the row to be erased */
558 res = target_write_u32(target,
559 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, address >> 1);
560
561 /* Issue the Erase Row command to erase that row. */
562 if (res == ERROR_OK)
563 res = samd_issue_nvmctrl_command(target,
564 address == SAMD_USER_ROW ? SAMD_NVM_CMD_EAR : SAMD_NVM_CMD_ER);
565
566 if (res != ERROR_OK) {
567 LOG_ERROR("Failed to erase row containing %08" PRIx32, address);
568 return ERROR_FAIL;
569 }
570
571 return ERROR_OK;
572 }
573
574 /**
575 * Returns the bitmask of reserved bits in register.
576 * @param target Pointer to the target structure.
577 * @param mask Bitmask, 0 -> value stays untouched.
578 * @return On success ERROR_OK, on failure an errorcode.
579 */
580 static int samd_get_reservedmask(struct target *target, uint64_t *mask)
581 {
582 int res;
583 /* Get the devicetype */
584 uint32_t id;
585 res = target_read_u32(target, SAMD_DSU + SAMD_DSU_DID, &id);
586 if (res != ERROR_OK) {
587 LOG_ERROR("Couldn't read Device ID register");
588 return res;
589 }
590 const struct samd_family *family;
591 family = samd_find_family(id);
592 if (family == NULL) {
593 LOG_ERROR("Couldn't determine device family");
594 return ERROR_FAIL;
595 }
596 *mask = family->nvm_userrow_res_mask;
597 return ERROR_OK;
598 }
599
600 static int read_userrow(struct target *target, uint64_t *userrow)
601 {
602 int res;
603 uint8_t buffer[8];
604
605 res = target_read_memory(target, SAMD_USER_ROW, 4, 2, buffer);
606 if (res != ERROR_OK)
607 return res;
608
609 *userrow = target_buffer_get_u64(target, buffer);
610 return ERROR_OK;
611 }
612
613 /**
614 * Modify the contents of the User Row in Flash. The User Row itself
615 * has a size of one page and contains a combination of "fuses" and
616 * calibration data. Bits which have a value of zero in the mask will
617 * not be changed. Up to now devices only use the first 64 bits.
618 * @param target Pointer to the target structure.
619 * @param value_input The value to write.
620 * @param value_mask Bitmask, 0 -> value stays untouched.
621 * @return On success ERROR_OK, on failure an errorcode.
622 */
623 static int samd_modify_user_row_masked(struct target *target,
624 uint64_t value_input, uint64_t value_mask)
625 {
626 int res;
627 uint32_t nvm_ctrlb;
628 bool manual_wp = true;
629
630 /* Retrieve the MCU's page size, in bytes. This is also the size of the
631 * entire User Row. */
632 uint32_t page_size;
633 res = samd_get_flash_page_info(target, &page_size, NULL);
634 if (res != ERROR_OK) {
635 LOG_ERROR("Couldn't determine Flash page size");
636 return res;
637 }
638
639 /* Make sure the size is sane. */
640 assert(page_size <= SAMD_PAGE_SIZE_MAX &&
641 page_size >= sizeof(value_input));
642
643 uint8_t buf[SAMD_PAGE_SIZE_MAX];
644 /* Read the user row (comprising one page) by words. */
645 res = target_read_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
646 if (res != ERROR_OK)
647 return res;
648
649 uint64_t value_device;
650 res = read_userrow(target, &value_device);
651 if (res != ERROR_OK)
652 return res;
653 uint64_t value_new = (value_input & value_mask) | (value_device & ~value_mask);
654
655 /* We will need to erase before writing if the new value needs a '1' in any
656 * position for which the current value had a '0'. Otherwise we can avoid
657 * erasing. */
658 if ((~value_device) & value_new) {
659 res = samd_erase_row(target, SAMD_USER_ROW);
660 if (res != ERROR_OK) {
661 LOG_ERROR("Couldn't erase user row");
662 return res;
663 }
664 }
665
666 /* Modify */
667 target_buffer_set_u64(target, buf, value_new);
668
669 /* Write the page buffer back out to the target. */
670 res = target_write_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
671 if (res != ERROR_OK)
672 return res;
673
674 /* Check if we need to do manual page write commands */
675 res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
676 if (res == ERROR_OK)
677 manual_wp = (nvm_ctrlb & SAMD_NVM_CTRLB_MANW) != 0;
678 else {
679 LOG_ERROR("Read of NVM register CTRKB failed.");
680 return ERROR_FAIL;
681 }
682 if (manual_wp) {
683 /* Trigger flash write */
684 res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_WAP);
685 } else {
686 res = samd_check_error(target);
687 }
688
689 return res;
690 }
691
692 /**
693 * Modifies the user row register to the given value.
694 * @param target Pointer to the target structure.
695 * @param value The value to write.
696 * @param startb The bit-offset by which the given value is shifted.
697 * @param endb The bit-offset of the last bit in value to write.
698 * @return On success ERROR_OK, on failure an errorcode.
699 */
700 static int samd_modify_user_row(struct target *target, uint64_t value,
701 uint8_t startb, uint8_t endb)
702 {
703 uint64_t mask = 0;
704 int i;
705 for (i = startb ; i <= endb ; i++)
706 mask |= ((uint64_t)1) << i;
707
708 return samd_modify_user_row_masked(target, value << startb, mask);
709 }
710
711 static int samd_protect(struct flash_bank *bank, int set, int first_prot_bl, int last_prot_bl)
712 {
713 int res = ERROR_OK;
714 int prot_block;
715
716 /* We can issue lock/unlock region commands with the target running but
717 * the settings won't persist unless we're able to modify the LOCK regions
718 * and that requires the target to be halted. */
719 if (bank->target->state != TARGET_HALTED) {
720 LOG_ERROR("Target not halted");
721 return ERROR_TARGET_NOT_HALTED;
722 }
723
724 for (prot_block = first_prot_bl; prot_block <= last_prot_bl; prot_block++) {
725 if (set != bank->prot_blocks[prot_block].is_protected) {
726 /* Load an address that is within this protection block (we use offset 0) */
727 res = target_write_u32(bank->target,
728 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR,
729 bank->prot_blocks[prot_block].offset >> 1);
730 if (res != ERROR_OK)
731 goto exit;
732
733 /* Tell the controller to lock that block */
734 res = samd_issue_nvmctrl_command(bank->target,
735 set ? SAMD_NVM_CMD_LR : SAMD_NVM_CMD_UR);
736 if (res != ERROR_OK)
737 goto exit;
738 }
739 }
740
741 /* We've now applied our changes, however they will be undone by the next
742 * reset unless we also apply them to the LOCK bits in the User Page. The
743 * LOCK bits start at bit 48, corresponding to Sector 0 and end with bit 63,
744 * corresponding to Sector 15. A '1' means unlocked and a '0' means
745 * locked. See Table 9-3 in the SAMD20 datasheet for more details. */
746
747 res = samd_modify_user_row(bank->target,
748 set ? (uint64_t)0 : (uint64_t)UINT64_MAX,
749 48 + first_prot_bl, 48 + last_prot_bl);
750 if (res != ERROR_OK)
751 LOG_WARNING("SAMD: protect settings were not made persistent!");
752
753 res = ERROR_OK;
754
755 exit:
756 samd_protect_check(bank);
757
758 return res;
759 }
760
761 static int samd_erase(struct flash_bank *bank, int first_sect, int last_sect)
762 {
763 int res, s;
764 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
765
766 if (bank->target->state != TARGET_HALTED) {
767 LOG_ERROR("Target not halted");
768
769 return ERROR_TARGET_NOT_HALTED;
770 }
771
772 if (!chip->probed) {
773 if (samd_probe(bank) != ERROR_OK)
774 return ERROR_FLASH_BANK_NOT_PROBED;
775 }
776
777 /* For each sector to be erased */
778 for (s = first_sect; s <= last_sect; s++) {
779 res = samd_erase_row(bank->target, bank->sectors[s].offset);
780 if (res != ERROR_OK) {
781 LOG_ERROR("SAMD: failed to erase sector %d at 0x%08" PRIx32, s, bank->sectors[s].offset);
782 return res;
783 }
784 }
785
786 return ERROR_OK;
787 }
788
789
790 static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
791 uint32_t offset, uint32_t count)
792 {
793 int res;
794 uint32_t nvm_ctrlb;
795 uint32_t address;
796 uint32_t pg_offset;
797 uint32_t nb;
798 uint32_t nw;
799 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
800 uint8_t *pb = NULL;
801 bool manual_wp;
802
803 if (bank->target->state != TARGET_HALTED) {
804 LOG_ERROR("Target not halted");
805 return ERROR_TARGET_NOT_HALTED;
806 }
807
808 if (!chip->probed) {
809 if (samd_probe(bank) != ERROR_OK)
810 return ERROR_FLASH_BANK_NOT_PROBED;
811 }
812
813 /* Check if we need to do manual page write commands */
814 res = target_read_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
815
816 if (res != ERROR_OK)
817 return res;
818
819 if (nvm_ctrlb & SAMD_NVM_CTRLB_MANW)
820 manual_wp = true;
821 else
822 manual_wp = false;
823
824 res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_PBC);
825 if (res != ERROR_OK) {
826 LOG_ERROR("%s: %d", __func__, __LINE__);
827 return res;
828 }
829
830 while (count) {
831 nb = chip->page_size - offset % chip->page_size;
832 if (count < nb)
833 nb = count;
834
835 address = bank->base + offset;
836 pg_offset = offset % chip->page_size;
837
838 if (offset % 4 || (offset + nb) % 4) {
839 /* Either start or end of write is not word aligned */
840 if (!pb) {
841 pb = malloc(chip->page_size);
842 if (!pb)
843 return ERROR_FAIL;
844 }
845
846 /* Set temporary page buffer to 0xff and overwrite the relevant part */
847 memset(pb, 0xff, chip->page_size);
848 memcpy(pb + pg_offset, buffer, nb);
849
850 /* Align start address to a word boundary */
851 address -= offset % 4;
852 pg_offset -= offset % 4;
853 assert(pg_offset % 4 == 0);
854
855 /* Extend length to whole words */
856 nw = (nb + offset % 4 + 3) / 4;
857 assert(pg_offset + 4 * nw <= chip->page_size);
858
859 /* Now we have original data extended by 0xff bytes
860 * to the nearest word boundary on both start and end */
861 res = target_write_memory(bank->target, address, 4, nw, pb + pg_offset);
862 } else {
863 assert(nb % 4 == 0);
864 nw = nb / 4;
865 assert(pg_offset + 4 * nw <= chip->page_size);
866
867 /* Word aligned data, use direct write from buffer */
868 res = target_write_memory(bank->target, address, 4, nw, buffer);
869 }
870 if (res != ERROR_OK) {
871 LOG_ERROR("%s: %d", __func__, __LINE__);
872 goto free_pb;
873 }
874
875 /* Devices with errata 13134 have automatic page write enabled by default
876 * For other devices issue a write page CMD to the NVM
877 * If the page has not been written up to the last word
878 * then issue CMD_WP always */
879 if (manual_wp || pg_offset + 4 * nw < chip->page_size) {
880 res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_WP);
881 } else {
882 /* Access through AHB is stalled while flash is being programmed */
883 usleep(200);
884
885 res = samd_check_error(bank->target);
886 }
887
888 if (res != ERROR_OK) {
889 LOG_ERROR("%s: write failed at address 0x%08" PRIx32, __func__, address);
890 goto free_pb;
891 }
892
893 /* We're done with the page contents */
894 count -= nb;
895 offset += nb;
896 buffer += nb;
897 }
898
899 free_pb:
900 if (pb)
901 free(pb);
902
903 return res;
904 }
905
906 FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
907 {
908 if (bank->base != SAMD_FLASH) {
909 LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
910 "[at91samd series] )",
911 bank->base, SAMD_FLASH);
912 return ERROR_FAIL;
913 }
914
915 struct samd_info *chip;
916 chip = calloc(1, sizeof(*chip));
917 if (!chip) {
918 LOG_ERROR("No memory for flash bank chip info");
919 return ERROR_FAIL;
920 }
921
922 chip->target = bank->target;
923 chip->probed = false;
924
925 bank->driver_priv = chip;
926
927 return ERROR_OK;
928 }
929
930 COMMAND_HANDLER(samd_handle_info_command)
931 {
932 return ERROR_OK;
933 }
934
935 COMMAND_HANDLER(samd_handle_chip_erase_command)
936 {
937 struct target *target = get_current_target(CMD_CTX);
938 int res = ERROR_FAIL;
939
940 if (target) {
941 /* Enable access to the DSU by disabling the write protect bit */
942 target_write_u32(target, SAMD_PAC1, (1<<1));
943 /* intentionally without error checking - not accessible on secured chip */
944
945 /* Tell the DSU to perform a full chip erase. It takes about 240ms to
946 * perform the erase. */
947 res = target_write_u8(target, SAMD_DSU + SAMD_DSU_CTRL_EXT, (1<<4));
948 if (res == ERROR_OK)
949 command_print(CMD_CTX, "chip erase started");
950 else
951 command_print(CMD_CTX, "write to DSU CTRL failed");
952 }
953
954 return res;
955 }
956
957 COMMAND_HANDLER(samd_handle_set_security_command)
958 {
959 int res = ERROR_OK;
960 struct target *target = get_current_target(CMD_CTX);
961
962 if (CMD_ARGC < 1 || (CMD_ARGC >= 1 && (strcmp(CMD_ARGV[0], "enable")))) {
963 command_print(CMD_CTX, "supply the \"enable\" argument to proceed.");
964 return ERROR_COMMAND_SYNTAX_ERROR;
965 }
966
967 if (target) {
968 if (target->state != TARGET_HALTED) {
969 LOG_ERROR("Target not halted");
970 return ERROR_TARGET_NOT_HALTED;
971 }
972
973 res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_SSB);
974
975 /* Check (and clear) error conditions */
976 if (res == ERROR_OK)
977 command_print(CMD_CTX, "chip secured on next power-cycle");
978 else
979 command_print(CMD_CTX, "failed to secure chip");
980 }
981
982 return res;
983 }
984
985 COMMAND_HANDLER(samd_handle_eeprom_command)
986 {
987 int res = ERROR_OK;
988 struct target *target = get_current_target(CMD_CTX);
989
990 if (target) {
991 if (target->state != TARGET_HALTED) {
992 LOG_ERROR("Target not halted");
993 return ERROR_TARGET_NOT_HALTED;
994 }
995
996 if (CMD_ARGC >= 1) {
997 int val = atoi(CMD_ARGV[0]);
998 uint32_t code;
999
1000 if (val == 0)
1001 code = 7;
1002 else {
1003 /* Try to match size in bytes with corresponding size code */
1004 for (code = 0; code <= 6; code++) {
1005 if (val == (2 << (13 - code)))
1006 break;
1007 }
1008
1009 if (code > 6) {
1010 command_print(CMD_CTX, "Invalid EEPROM size. Please see "
1011 "datasheet for a list valid sizes.");
1012 return ERROR_COMMAND_SYNTAX_ERROR;
1013 }
1014 }
1015
1016 res = samd_modify_user_row(target, code, 4, 6);
1017 } else {
1018 uint16_t val;
1019 res = target_read_u16(target, SAMD_USER_ROW, &val);
1020 if (res == ERROR_OK) {
1021 uint32_t size = ((val >> 4) & 0x7); /* grab size code */
1022
1023 if (size == 0x7)
1024 command_print(CMD_CTX, "EEPROM is disabled");
1025 else {
1026 /* Otherwise, 6 is 256B, 0 is 16KB */
1027 command_print(CMD_CTX, "EEPROM size is %u bytes",
1028 (2 << (13 - size)));
1029 }
1030 }
1031 }
1032 }
1033
1034 return res;
1035 }
1036
1037 static COMMAND_HELPER(get_u64_from_hexarg, unsigned int num, uint64_t *value)
1038 {
1039 if (num >= CMD_ARGC) {
1040 command_print(CMD_CTX, "Too few Arguments.");
1041 return ERROR_COMMAND_SYNTAX_ERROR;
1042 }
1043
1044 if (strlen(CMD_ARGV[num]) >= 3 &&
1045 CMD_ARGV[num][0] == '0' &&
1046 CMD_ARGV[num][1] == 'x') {
1047 char *check = NULL;
1048 *value = strtoull(&(CMD_ARGV[num][2]), &check, 16);
1049 if ((value == 0 && errno == ERANGE) ||
1050 check == NULL || *check != 0) {
1051 command_print(CMD_CTX, "Invalid 64-bit hex value in argument %d.",
1052 num + 1);
1053 return ERROR_COMMAND_SYNTAX_ERROR;
1054 }
1055 } else {
1056 command_print(CMD_CTX, "Argument %d needs to be a hex value.", num + 1);
1057 return ERROR_COMMAND_SYNTAX_ERROR;
1058 }
1059 return ERROR_OK;
1060 }
1061
1062 COMMAND_HANDLER(samd_handle_nvmuserrow_command)
1063 {
1064 int res = ERROR_OK;
1065 struct target *target = get_current_target(CMD_CTX);
1066
1067 if (target) {
1068 if (CMD_ARGC > 2) {
1069 command_print(CMD_CTX, "Too much Arguments given.");
1070 return ERROR_COMMAND_SYNTAX_ERROR;
1071 }
1072
1073 if (CMD_ARGC > 0) {
1074 if (target->state != TARGET_HALTED) {
1075 LOG_ERROR("Target not halted.");
1076 return ERROR_TARGET_NOT_HALTED;
1077 }
1078
1079 uint64_t mask;
1080 res = samd_get_reservedmask(target, &mask);
1081 if (res != ERROR_OK) {
1082 LOG_ERROR("Couldn't determine the mask for reserved bits.");
1083 return ERROR_FAIL;
1084 }
1085 mask &= NVMUSERROW_LOCKBIT_MASK;
1086
1087 uint64_t value;
1088 res = CALL_COMMAND_HANDLER(get_u64_from_hexarg, 0, &value);
1089 if (res != ERROR_OK)
1090 return res;
1091 if (CMD_ARGC == 2) {
1092 uint64_t mask_temp;
1093 res = CALL_COMMAND_HANDLER(get_u64_from_hexarg, 1, &mask_temp);
1094 if (res != ERROR_OK)
1095 return res;
1096 mask &= mask_temp;
1097 }
1098 res = samd_modify_user_row_masked(target, value, mask);
1099 if (res != ERROR_OK)
1100 return res;
1101 }
1102
1103 /* read register */
1104 uint64_t value;
1105 res = read_userrow(target, &value);
1106 if (res == ERROR_OK)
1107 command_print(CMD_CTX, "NVMUSERROW: 0x%016"PRIX64, value);
1108 else
1109 LOG_ERROR("NVMUSERROW could not be read.");
1110 }
1111 return res;
1112 }
1113
1114 COMMAND_HANDLER(samd_handle_bootloader_command)
1115 {
1116 int res = ERROR_OK;
1117 struct target *target = get_current_target(CMD_CTX);
1118
1119 if (target) {
1120 if (target->state != TARGET_HALTED) {
1121 LOG_ERROR("Target not halted");
1122 return ERROR_TARGET_NOT_HALTED;
1123 }
1124
1125 /* Retrieve the MCU's page size, in bytes. */
1126 uint32_t page_size;
1127 res = samd_get_flash_page_info(target, &page_size, NULL);
1128 if (res != ERROR_OK) {
1129 LOG_ERROR("Couldn't determine Flash page size");
1130 return res;
1131 }
1132
1133 if (CMD_ARGC >= 1) {
1134 int val = atoi(CMD_ARGV[0]);
1135 uint32_t code;
1136
1137 if (val == 0)
1138 code = 7;
1139 else {
1140 /* Try to match size in bytes with corresponding size code */
1141 for (code = 0; code <= 6; code++) {
1142 if ((unsigned int)val == (2UL << (8UL - code)) * page_size)
1143 break;
1144 }
1145
1146 if (code > 6) {
1147 command_print(CMD_CTX, "Invalid bootloader size. Please "
1148 "see datasheet for a list valid sizes.");
1149 return ERROR_COMMAND_SYNTAX_ERROR;
1150 }
1151
1152 }
1153
1154 res = samd_modify_user_row(target, code, 0, 2);
1155 } else {
1156 uint16_t val;
1157 res = target_read_u16(target, SAMD_USER_ROW, &val);
1158 if (res == ERROR_OK) {
1159 uint32_t size = (val & 0x7); /* grab size code */
1160 uint32_t nb;
1161
1162 if (size == 0x7)
1163 nb = 0;
1164 else
1165 nb = (2 << (8 - size)) * page_size;
1166
1167 /* There are 4 pages per row */
1168 command_print(CMD_CTX, "Bootloader size is %" PRIu32 " bytes (%" PRIu32 " rows)",
1169 nb, (uint32_t)(nb / (page_size * 4)));
1170 }
1171 }
1172 }
1173
1174 return res;
1175 }
1176
1177
1178
1179 COMMAND_HANDLER(samd_handle_reset_deassert)
1180 {
1181 struct target *target = get_current_target(CMD_CTX);
1182 int retval = ERROR_OK;
1183 enum reset_types jtag_reset_config = jtag_get_reset_config();
1184
1185 /* If the target has been unresponsive before, try to re-establish
1186 * communication now - CPU is held in reset by DSU, DAP is working */
1187 if (!target_was_examined(target))
1188 target_examine_one(target);
1189 target_poll(target);
1190
1191 /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
1192 * so we just release reset held by DSU
1193 *
1194 * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
1195 *
1196 * After vectreset DSU release is not needed however makes no harm
1197 */
1198 if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
1199 retval = target_write_u32(target, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
1200 if (retval == ERROR_OK)
1201 retval = target_write_u32(target, DCB_DEMCR,
1202 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1203 /* do not return on error here, releasing DSU reset is more important */
1204 }
1205
1206 /* clear CPU Reset Phase Extension bit */
1207 int retval2 = target_write_u8(target, SAMD_DSU + SAMD_DSU_STATUSA, (1<<1));
1208 if (retval2 != ERROR_OK)
1209 return retval2;
1210
1211 return retval;
1212 }
1213
1214 static const struct command_registration at91samd_exec_command_handlers[] = {
1215 {
1216 .name = "dsu_reset_deassert",
1217 .handler = samd_handle_reset_deassert,
1218 .mode = COMMAND_EXEC,
1219 .help = "Deasert internal reset held by DSU."
1220 },
1221 {
1222 .name = "info",
1223 .handler = samd_handle_info_command,
1224 .mode = COMMAND_EXEC,
1225 .help = "Print information about the current at91samd chip "
1226 "and its flash configuration.",
1227 },
1228 {
1229 .name = "chip-erase",
1230 .handler = samd_handle_chip_erase_command,
1231 .mode = COMMAND_EXEC,
1232 .help = "Erase the entire Flash by using the Chip-"
1233 "Erase feature in the Device Service Unit (DSU).",
1234 },
1235 {
1236 .name = "set-security",
1237 .handler = samd_handle_set_security_command,
1238 .mode = COMMAND_EXEC,
1239 .help = "Secure the chip's Flash by setting the Security Bit. "
1240 "This makes it impossible to read the Flash contents. "
1241 "The only way to undo this is to issue the chip-erase "
1242 "command.",
1243 },
1244 {
1245 .name = "eeprom",
1246 .usage = "[size_in_bytes]",
1247 .handler = samd_handle_eeprom_command,
1248 .mode = COMMAND_EXEC,
1249 .help = "Show or set the EEPROM size setting, stored in the User Row. "
1250 "Please see Table 20-3 of the SAMD20 datasheet for allowed values. "
1251 "Changes are stored immediately but take affect after the MCU is "
1252 "reset.",
1253 },
1254 {
1255 .name = "bootloader",
1256 .usage = "[size_in_bytes]",
1257 .handler = samd_handle_bootloader_command,
1258 .mode = COMMAND_EXEC,
1259 .help = "Show or set the bootloader size, stored in the User Row. "
1260 "Please see Table 20-2 of the SAMD20 datasheet for allowed values. "
1261 "Changes are stored immediately but take affect after the MCU is "
1262 "reset.",
1263 },
1264 {
1265 .name = "nvmuserrow",
1266 .usage = "[value] [mask]",
1267 .handler = samd_handle_nvmuserrow_command,
1268 .mode = COMMAND_EXEC,
1269 .help = "Show or set the nvmuserrow register. It is 64 bit wide "
1270 "and located at address 0x804000. Use the optional mask argument "
1271 "to prevent changes at positions where the bitvalue is zero. "
1272 "For security reasons the lock- and reserved-bits are masked out "
1273 "in background and therefore cannot be changed.",
1274 },
1275 COMMAND_REGISTRATION_DONE
1276 };
1277
1278 static const struct command_registration at91samd_command_handlers[] = {
1279 {
1280 .name = "at91samd",
1281 .mode = COMMAND_ANY,
1282 .help = "at91samd flash command group",
1283 .usage = "",
1284 .chain = at91samd_exec_command_handlers,
1285 },
1286 COMMAND_REGISTRATION_DONE
1287 };
1288
1289 struct flash_driver at91samd_flash = {
1290 .name = "at91samd",
1291 .commands = at91samd_command_handlers,
1292 .flash_bank_command = samd_flash_bank_command,
1293 .erase = samd_erase,
1294 .protect = samd_protect,
1295 .write = samd_write,
1296 .read = default_flash_read,
1297 .probe = samd_probe,
1298 .auto_probe = samd_probe,
1299 .erase_check = default_flash_blank_check,
1300 .protect_check = samd_protect_check,
1301 .free_driver_priv = default_flash_free_driver_priv,
1302 };