flash/nor/at91samd: add SAMR21E19A DID
[openocd.git] / src / flash / nor / at91samd.c
1 /***************************************************************************
2 * Copyright (C) 2013 by Andrey Yurovsky *
3 * Andrey Yurovsky <yurovsky@gmail.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18
19 #ifdef HAVE_CONFIG_H
20 #include "config.h"
21 #endif
22
23 #include "imp.h"
24 #include "helper/binarybuffer.h"
25
26 #include <target/cortex_m.h>
27
28 #define SAMD_NUM_PROT_BLOCKS 16
29 #define SAMD_PAGE_SIZE_MAX 1024
30
31 #define SAMD_FLASH ((uint32_t)0x00000000) /* physical Flash memory */
32 #define SAMD_USER_ROW ((uint32_t)0x00804000) /* User Row of Flash */
33 #define SAMD_PAC1 0x41000000 /* Peripheral Access Control 1 */
34 #define SAMD_DSU 0x41002000 /* Device Service Unit */
35 #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
36
37 #define SAMD_DSU_STATUSA 1 /* DSU status register */
38 #define SAMD_DSU_DID 0x18 /* Device ID register */
39 #define SAMD_DSU_CTRL_EXT 0x100 /* CTRL register, external access */
40
41 #define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
42 #define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
43 #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
44 #define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interupt Flag Status & Clear */
45 #define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
46 #define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
47 #define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
48
49 #define SAMD_CMDEX_KEY 0xA5UL
50 #define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
51
52 /* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */
53 #define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
54 #define SAMD_NVM_CMD_WP 0x04 /* Write Page */
55 #define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxilary Row */
56 #define SAMD_NVM_CMD_WAP 0x06 /* Write Auxilary Page */
57 #define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
58 #define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
59 #define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */
60 #define SAMD_NVM_CMD_CPRM 0x43 /* Clear Power Reduction Mode */
61 #define SAMD_NVM_CMD_PBC 0x44 /* Page Buffer Clear */
62 #define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */
63 #define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */
64
65 /* NVMCTRL bits */
66 #define SAMD_NVM_CTRLB_MANW 0x80
67
68 /* Known identifiers */
69 #define SAMD_PROCESSOR_M0 0x01
70 #define SAMD_FAMILY_D 0x00
71 #define SAMD_FAMILY_L 0x01
72 #define SAMD_FAMILY_C 0x02
73 #define SAMD_SERIES_20 0x00
74 #define SAMD_SERIES_21 0x01
75 #define SAMD_SERIES_22 0x02
76 #define SAMD_SERIES_10 0x02
77 #define SAMD_SERIES_11 0x03
78 #define SAMD_SERIES_09 0x04
79
80 /* Device ID macros */
81 #define SAMD_GET_PROCESSOR(id) (id >> 28)
82 #define SAMD_GET_FAMILY(id) (((id >> 23) & 0x1F))
83 #define SAMD_GET_SERIES(id) (((id >> 16) & 0x3F))
84 #define SAMD_GET_DEVSEL(id) (id & 0xFF)
85
86 /* Bits to mask out lockbits in user row */
87 #define NVMUSERROW_LOCKBIT_MASK ((uint64_t)0x0000FFFFFFFFFFFF)
88
89 struct samd_part {
90 uint8_t id;
91 const char *name;
92 uint32_t flash_kb;
93 uint32_t ram_kb;
94 };
95
96 /* Known SAMD09 parts. DID reset values missing in RM, see
97 * https://github.com/avrxml/asf/blob/master/sam0/utils/cmsis/samd09/include/ */
98 static const struct samd_part samd09_parts[] = {
99 { 0x0, "SAMD09D14A", 16, 4 },
100 { 0x7, "SAMD09C13A", 8, 4 },
101 };
102
103 /* Known SAMD10 parts */
104 static const struct samd_part samd10_parts[] = {
105 { 0x0, "SAMD10D14AMU", 16, 4 },
106 { 0x1, "SAMD10D13AMU", 8, 4 },
107 { 0x2, "SAMD10D12AMU", 4, 4 },
108 { 0x3, "SAMD10D14ASU", 16, 4 },
109 { 0x4, "SAMD10D13ASU", 8, 4 },
110 { 0x5, "SAMD10D12ASU", 4, 4 },
111 { 0x6, "SAMD10C14A", 16, 4 },
112 { 0x7, "SAMD10C13A", 8, 4 },
113 { 0x8, "SAMD10C12A", 4, 4 },
114 };
115
116 /* Known SAMD11 parts */
117 static const struct samd_part samd11_parts[] = {
118 { 0x0, "SAMD11D14AM", 16, 4 },
119 { 0x1, "SAMD11D13AMU", 8, 4 },
120 { 0x2, "SAMD11D12AMU", 4, 4 },
121 { 0x3, "SAMD11D14ASS", 16, 4 },
122 { 0x4, "SAMD11D13ASU", 8, 4 },
123 { 0x5, "SAMD11D12ASU", 4, 4 },
124 { 0x6, "SAMD11C14A", 16, 4 },
125 { 0x7, "SAMD11C13A", 8, 4 },
126 { 0x8, "SAMD11C12A", 4, 4 },
127 { 0x9, "SAMD11D14AU", 16, 4 },
128 };
129
130 /* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */
131 static const struct samd_part samd20_parts[] = {
132 { 0x0, "SAMD20J18A", 256, 32 },
133 { 0x1, "SAMD20J17A", 128, 16 },
134 { 0x2, "SAMD20J16A", 64, 8 },
135 { 0x3, "SAMD20J15A", 32, 4 },
136 { 0x4, "SAMD20J14A", 16, 2 },
137 { 0x5, "SAMD20G18A", 256, 32 },
138 { 0x6, "SAMD20G17A", 128, 16 },
139 { 0x7, "SAMD20G16A", 64, 8 },
140 { 0x8, "SAMD20G15A", 32, 4 },
141 { 0x9, "SAMD20G14A", 16, 2 },
142 { 0xA, "SAMD20E18A", 256, 32 },
143 { 0xB, "SAMD20E17A", 128, 16 },
144 { 0xC, "SAMD20E16A", 64, 8 },
145 { 0xD, "SAMD20E15A", 32, 4 },
146 { 0xE, "SAMD20E14A", 16, 2 },
147 };
148
149 /* Known SAMD21 parts. */
150 static const struct samd_part samd21_parts[] = {
151 { 0x0, "SAMD21J18A", 256, 32 },
152 { 0x1, "SAMD21J17A", 128, 16 },
153 { 0x2, "SAMD21J16A", 64, 8 },
154 { 0x3, "SAMD21J15A", 32, 4 },
155 { 0x4, "SAMD21J14A", 16, 2 },
156 { 0x5, "SAMD21G18A", 256, 32 },
157 { 0x6, "SAMD21G17A", 128, 16 },
158 { 0x7, "SAMD21G16A", 64, 8 },
159 { 0x8, "SAMD21G15A", 32, 4 },
160 { 0x9, "SAMD21G14A", 16, 2 },
161 { 0xA, "SAMD21E18A", 256, 32 },
162 { 0xB, "SAMD21E17A", 128, 16 },
163 { 0xC, "SAMD21E16A", 64, 8 },
164 { 0xD, "SAMD21E15A", 32, 4 },
165 { 0xE, "SAMD21E14A", 16, 2 },
166
167 /* SAMR21 parts have integrated SAMD21 with a radio */
168 { 0x18, "SAMR21G19A", 256, 32 }, /* with 512k of serial flash */
169 { 0x19, "SAMR21G18A", 256, 32 },
170 { 0x1A, "SAMR21G17A", 128, 32 },
171 { 0x1B, "SAMR21G16A", 64, 16 },
172 { 0x1C, "SAMR21E18A", 256, 32 },
173 { 0x1D, "SAMR21E17A", 128, 32 },
174 { 0x1E, "SAMR21E16A", 64, 16 },
175
176 /* SAMD21 B Variants (Table 3-7 from rev I of datasheet) */
177 { 0x20, "SAMD21J16B", 64, 8 },
178 { 0x21, "SAMD21J15B", 32, 4 },
179 { 0x23, "SAMD21G16B", 64, 8 },
180 { 0x24, "SAMD21G15B", 32, 4 },
181 { 0x26, "SAMD21E16B", 64, 8 },
182 { 0x27, "SAMD21E15B", 32, 4 },
183 };
184
185 /* Known SAML21 parts. */
186 static const struct samd_part saml21_parts[] = {
187 { 0x00, "SAML21J18A", 256, 32 },
188 { 0x01, "SAML21J17A", 128, 16 },
189 { 0x02, "SAML21J16A", 64, 8 },
190 { 0x05, "SAML21G18A", 256, 32 },
191 { 0x06, "SAML21G17A", 128, 16 },
192 { 0x07, "SAML21G16A", 64, 8 },
193 { 0x0A, "SAML21E18A", 256, 32 },
194 { 0x0B, "SAML21E17A", 128, 16 },
195 { 0x0C, "SAML21E16A", 64, 8 },
196 { 0x0D, "SAML21E15A", 32, 4 },
197 { 0x0F, "SAML21J18B", 256, 32 },
198 { 0x10, "SAML21J17B", 128, 16 },
199 { 0x11, "SAML21J16B", 64, 8 },
200 { 0x14, "SAML21G18B", 256, 32 },
201 { 0x15, "SAML21G17B", 128, 16 },
202 { 0x16, "SAML21G16B", 64, 8 },
203 { 0x19, "SAML21E18B", 256, 32 },
204 { 0x1A, "SAML21E17B", 128, 16 },
205 { 0x1B, "SAML21E16B", 64, 8 },
206 { 0x1C, "SAML21E15B", 32, 4 },
207
208 /* SAMR30 parts have integrated SAML21 with a radio */
209 { 0x1E, "SAMR30G18A", 256, 32 },
210 { 0x1F, "SAMR30E18A", 256, 32 },
211 };
212
213 /* Known SAML22 parts. */
214 static const struct samd_part saml22_parts[] = {
215 { 0x00, "SAML22N18A", 256, 32 },
216 { 0x01, "SAML22N17A", 128, 16 },
217 { 0x02, "SAML22N16A", 64, 8 },
218 { 0x05, "SAML22J18A", 256, 32 },
219 { 0x06, "SAML22J17A", 128, 16 },
220 { 0x07, "SAML22J16A", 64, 8 },
221 { 0x0A, "SAML22G18A", 256, 32 },
222 { 0x0B, "SAML22G17A", 128, 16 },
223 { 0x0C, "SAML22G16A", 64, 8 },
224 };
225
226 /* Known SAMC20 parts. */
227 static const struct samd_part samc20_parts[] = {
228 { 0x00, "SAMC20J18A", 256, 32 },
229 { 0x01, "SAMC20J17A", 128, 16 },
230 { 0x02, "SAMC20J16A", 64, 8 },
231 { 0x03, "SAMC20J15A", 32, 4 },
232 { 0x05, "SAMC20G18A", 256, 32 },
233 { 0x06, "SAMC20G17A", 128, 16 },
234 { 0x07, "SAMC20G16A", 64, 8 },
235 { 0x08, "SAMC20G15A", 32, 4 },
236 { 0x0A, "SAMC20E18A", 256, 32 },
237 { 0x0B, "SAMC20E17A", 128, 16 },
238 { 0x0C, "SAMC20E16A", 64, 8 },
239 { 0x0D, "SAMC20E15A", 32, 4 },
240 };
241
242 /* Known SAMC21 parts. */
243 static const struct samd_part samc21_parts[] = {
244 { 0x00, "SAMC21J18A", 256, 32 },
245 { 0x01, "SAMC21J17A", 128, 16 },
246 { 0x02, "SAMC21J16A", 64, 8 },
247 { 0x03, "SAMC21J15A", 32, 4 },
248 { 0x05, "SAMC21G18A", 256, 32 },
249 { 0x06, "SAMC21G17A", 128, 16 },
250 { 0x07, "SAMC21G16A", 64, 8 },
251 { 0x08, "SAMC21G15A", 32, 4 },
252 { 0x0A, "SAMC21E18A", 256, 32 },
253 { 0x0B, "SAMC21E17A", 128, 16 },
254 { 0x0C, "SAMC21E16A", 64, 8 },
255 { 0x0D, "SAMC21E15A", 32, 4 },
256 };
257
258 /* Each family of parts contains a parts table in the DEVSEL field of DID. The
259 * processor ID, family ID, and series ID are used to determine which exact
260 * family this is and then we can use the corresponding table. */
261 struct samd_family {
262 uint8_t processor;
263 uint8_t family;
264 uint8_t series;
265 const struct samd_part *parts;
266 size_t num_parts;
267 uint64_t nvm_userrow_res_mask; /* protect bits which are reserved, 0 -> protect */
268 };
269
270 /* Known SAMD families */
271 static const struct samd_family samd_families[] = {
272 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_20,
273 samd20_parts, ARRAY_SIZE(samd20_parts),
274 (uint64_t)0xFFFF01FFFE01FF77 },
275 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
276 samd21_parts, ARRAY_SIZE(samd21_parts),
277 (uint64_t)0xFFFF01FFFE01FF77 },
278 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_09,
279 samd09_parts, ARRAY_SIZE(samd09_parts),
280 (uint64_t)0xFFFF01FFFE01FF77 },
281 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_10,
282 samd10_parts, ARRAY_SIZE(samd10_parts),
283 (uint64_t)0xFFFF01FFFE01FF77 },
284 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11,
285 samd11_parts, ARRAY_SIZE(samd11_parts),
286 (uint64_t)0xFFFF01FFFE01FF77 },
287 { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_21,
288 saml21_parts, ARRAY_SIZE(saml21_parts),
289 (uint64_t)0xFFFF03FFFC01FF77 },
290 { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_22,
291 saml22_parts, ARRAY_SIZE(saml22_parts),
292 (uint64_t)0xFFFF03FFFC01FF77 },
293 { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_20,
294 samc20_parts, ARRAY_SIZE(samc20_parts),
295 (uint64_t)0xFFFF03FFFC01FF77 },
296 { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_21,
297 samc21_parts, ARRAY_SIZE(samc21_parts),
298 (uint64_t)0xFFFF03FFFC01FF77 },
299 };
300
301 struct samd_info {
302 uint32_t page_size;
303 int num_pages;
304 int sector_size;
305 int prot_block_size;
306
307 bool probed;
308 struct target *target;
309 };
310
311
312 /**
313 * Gives the family structure to specific device id.
314 * @param id The id of the device.
315 * @return On failure NULL, otherwise a pointer to the structure.
316 */
317 static const struct samd_family *samd_find_family(uint32_t id)
318 {
319 uint8_t processor = SAMD_GET_PROCESSOR(id);
320 uint8_t family = SAMD_GET_FAMILY(id);
321 uint8_t series = SAMD_GET_SERIES(id);
322
323 for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) {
324 if (samd_families[i].processor == processor &&
325 samd_families[i].series == series &&
326 samd_families[i].family == family)
327 return &samd_families[i];
328 }
329
330 return NULL;
331 }
332
333 /**
334 * Gives the part structure to specific device id.
335 * @param id The id of the device.
336 * @return On failure NULL, otherwise a pointer to the structure.
337 */
338 static const struct samd_part *samd_find_part(uint32_t id)
339 {
340 uint8_t devsel = SAMD_GET_DEVSEL(id);
341 const struct samd_family *family = samd_find_family(id);
342 if (family == NULL)
343 return NULL;
344
345 for (unsigned i = 0; i < family->num_parts; i++) {
346 if (family->parts[i].id == devsel)
347 return &family->parts[i];
348 }
349
350 return NULL;
351 }
352
353 static int samd_protect_check(struct flash_bank *bank)
354 {
355 int res, prot_block;
356 uint16_t lock;
357
358 res = target_read_u16(bank->target,
359 SAMD_NVMCTRL + SAMD_NVMCTRL_LOCK, &lock);
360 if (res != ERROR_OK)
361 return res;
362
363 /* Lock bits are active-low */
364 for (prot_block = 0; prot_block < bank->num_prot_blocks; prot_block++)
365 bank->prot_blocks[prot_block].is_protected = !(lock & (1u<<prot_block));
366
367 return ERROR_OK;
368 }
369
370 static int samd_get_flash_page_info(struct target *target,
371 uint32_t *sizep, int *nump)
372 {
373 int res;
374 uint32_t param;
375
376 res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, &param);
377 if (res == ERROR_OK) {
378 /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n)
379 * so 0 is 8KB and 7 is 1024KB. */
380 if (sizep)
381 *sizep = (8 << ((param >> 16) & 0x7));
382 /* The NVMP field (bits 15:0) indicates the total number of pages */
383 if (nump)
384 *nump = param & 0xFFFF;
385 } else {
386 LOG_ERROR("Couldn't read NVM Parameters register");
387 }
388
389 return res;
390 }
391
392 static int samd_probe(struct flash_bank *bank)
393 {
394 uint32_t id;
395 int res;
396 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
397 const struct samd_part *part;
398
399 if (chip->probed)
400 return ERROR_OK;
401
402 res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
403 if (res != ERROR_OK) {
404 LOG_ERROR("Couldn't read Device ID register");
405 return res;
406 }
407
408 part = samd_find_part(id);
409 if (part == NULL) {
410 LOG_ERROR("Couldn't find part corresponding to DID %08" PRIx32, id);
411 return ERROR_FAIL;
412 }
413
414 bank->size = part->flash_kb * 1024;
415
416 res = samd_get_flash_page_info(bank->target, &chip->page_size,
417 &chip->num_pages);
418 if (res != ERROR_OK) {
419 LOG_ERROR("Couldn't determine Flash page size");
420 return res;
421 }
422
423 /* Sanity check: the total flash size in the DSU should match the page size
424 * multiplied by the number of pages. */
425 if (bank->size != chip->num_pages * chip->page_size) {
426 LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
427 "Identified %" PRIu32 "KB Flash but NVMCTRL reports %u %" PRIu32 "B pages",
428 part->flash_kb, chip->num_pages, chip->page_size);
429 }
430
431 /* Erase granularity = 1 row = 4 pages */
432 chip->sector_size = chip->page_size * 4;
433
434 /* Allocate the sector table */
435 bank->num_sectors = chip->num_pages / 4;
436 bank->sectors = alloc_block_array(0, chip->sector_size, bank->num_sectors);
437 if (!bank->sectors)
438 return ERROR_FAIL;
439
440 /* 16 protection blocks per device */
441 chip->prot_block_size = bank->size / SAMD_NUM_PROT_BLOCKS;
442
443 /* Allocate the table of protection blocks */
444 bank->num_prot_blocks = SAMD_NUM_PROT_BLOCKS;
445 bank->prot_blocks = alloc_block_array(0, chip->prot_block_size, bank->num_prot_blocks);
446 if (!bank->prot_blocks)
447 return ERROR_FAIL;
448
449 samd_protect_check(bank);
450
451 /* Done */
452 chip->probed = true;
453
454 LOG_INFO("SAMD MCU: %s (%" PRIu32 "KB Flash, %" PRIu32 "KB RAM)", part->name,
455 part->flash_kb, part->ram_kb);
456
457 return ERROR_OK;
458 }
459
460 static int samd_check_error(struct target *target)
461 {
462 int ret, ret2;
463 uint16_t status;
464
465 ret = target_read_u16(target,
466 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status);
467 if (ret != ERROR_OK) {
468 LOG_ERROR("Can't read NVM status");
469 return ret;
470 }
471
472 if ((status & 0x001C) == 0)
473 return ERROR_OK;
474
475 if (status & (1 << 4)) { /* NVME */
476 LOG_ERROR("SAMD: NVM Error");
477 ret = ERROR_FLASH_OPERATION_FAILED;
478 }
479
480 if (status & (1 << 3)) { /* LOCKE */
481 LOG_ERROR("SAMD: NVM lock error");
482 ret = ERROR_FLASH_PROTECTED;
483 }
484
485 if (status & (1 << 2)) { /* PROGE */
486 LOG_ERROR("SAMD: NVM programming error");
487 ret = ERROR_FLASH_OPER_UNSUPPORTED;
488 }
489
490 /* Clear the error conditions by writing a one to them */
491 ret2 = target_write_u16(target,
492 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, status);
493 if (ret2 != ERROR_OK)
494 LOG_ERROR("Can't clear NVM error conditions");
495
496 return ret;
497 }
498
499 static int samd_issue_nvmctrl_command(struct target *target, uint16_t cmd)
500 {
501 int res;
502
503 if (target->state != TARGET_HALTED) {
504 LOG_ERROR("Target not halted");
505 return ERROR_TARGET_NOT_HALTED;
506 }
507
508 /* Issue the NVM command */
509 res = target_write_u16(target,
510 SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, SAMD_NVM_CMD(cmd));
511 if (res != ERROR_OK)
512 return res;
513
514 /* Check to see if the NVM command resulted in an error condition. */
515 return samd_check_error(target);
516 }
517
518 /**
519 * Erases a flash-row at the given address.
520 * @param target Pointer to the target structure.
521 * @param address The address of the row.
522 * @return On success ERROR_OK, on failure an errorcode.
523 */
524 static int samd_erase_row(struct target *target, uint32_t address)
525 {
526 int res;
527
528 /* Set an address contained in the row to be erased */
529 res = target_write_u32(target,
530 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, address >> 1);
531
532 /* Issue the Erase Row command to erase that row. */
533 if (res == ERROR_OK)
534 res = samd_issue_nvmctrl_command(target,
535 address == SAMD_USER_ROW ? SAMD_NVM_CMD_EAR : SAMD_NVM_CMD_ER);
536
537 if (res != ERROR_OK) {
538 LOG_ERROR("Failed to erase row containing %08" PRIx32, address);
539 return ERROR_FAIL;
540 }
541
542 return ERROR_OK;
543 }
544
545 /**
546 * Returns the bitmask of reserved bits in register.
547 * @param target Pointer to the target structure.
548 * @param mask Bitmask, 0 -> value stays untouched.
549 * @return On success ERROR_OK, on failure an errorcode.
550 */
551 static int samd_get_reservedmask(struct target *target, uint64_t *mask)
552 {
553 int res;
554 /* Get the devicetype */
555 uint32_t id;
556 res = target_read_u32(target, SAMD_DSU + SAMD_DSU_DID, &id);
557 if (res != ERROR_OK) {
558 LOG_ERROR("Couldn't read Device ID register");
559 return res;
560 }
561 const struct samd_family *family;
562 family = samd_find_family(id);
563 if (family == NULL) {
564 LOG_ERROR("Couldn't determine device family");
565 return ERROR_FAIL;
566 }
567 *mask = family->nvm_userrow_res_mask;
568 return ERROR_OK;
569 }
570
571 static int read_userrow(struct target *target, uint64_t *userrow)
572 {
573 int res;
574 uint8_t buffer[8];
575
576 res = target_read_memory(target, SAMD_USER_ROW, 4, 2, buffer);
577 if (res != ERROR_OK)
578 return res;
579
580 *userrow = target_buffer_get_u64(target, buffer);
581 return ERROR_OK;
582 }
583
584 /**
585 * Modify the contents of the User Row in Flash. The User Row itself
586 * has a size of one page and contains a combination of "fuses" and
587 * calibration data. Bits which have a value of zero in the mask will
588 * not be changed. Up to now devices only use the first 64 bits.
589 * @param target Pointer to the target structure.
590 * @param value_input The value to write.
591 * @param value_mask Bitmask, 0 -> value stays untouched.
592 * @return On success ERROR_OK, on failure an errorcode.
593 */
594 static int samd_modify_user_row_masked(struct target *target,
595 uint64_t value_input, uint64_t value_mask)
596 {
597 int res;
598 uint32_t nvm_ctrlb;
599 bool manual_wp = true;
600
601 /* Retrieve the MCU's page size, in bytes. This is also the size of the
602 * entire User Row. */
603 uint32_t page_size;
604 res = samd_get_flash_page_info(target, &page_size, NULL);
605 if (res != ERROR_OK) {
606 LOG_ERROR("Couldn't determine Flash page size");
607 return res;
608 }
609
610 /* Make sure the size is sane. */
611 assert(page_size <= SAMD_PAGE_SIZE_MAX &&
612 page_size >= sizeof(value_input));
613
614 uint8_t buf[SAMD_PAGE_SIZE_MAX];
615 /* Read the user row (comprising one page) by words. */
616 res = target_read_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
617 if (res != ERROR_OK)
618 return res;
619
620 uint64_t value_device;
621 res = read_userrow(target, &value_device);
622 if (res != ERROR_OK)
623 return res;
624 uint64_t value_new = (value_input & value_mask) | (value_device & ~value_mask);
625
626 /* We will need to erase before writing if the new value needs a '1' in any
627 * position for which the current value had a '0'. Otherwise we can avoid
628 * erasing. */
629 if ((~value_device) & value_new) {
630 res = samd_erase_row(target, SAMD_USER_ROW);
631 if (res != ERROR_OK) {
632 LOG_ERROR("Couldn't erase user row");
633 return res;
634 }
635 }
636
637 /* Modify */
638 target_buffer_set_u64(target, buf, value_new);
639
640 /* Write the page buffer back out to the target. */
641 res = target_write_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
642 if (res != ERROR_OK)
643 return res;
644
645 /* Check if we need to do manual page write commands */
646 res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
647 if (res == ERROR_OK)
648 manual_wp = (nvm_ctrlb & SAMD_NVM_CTRLB_MANW) != 0;
649 else {
650 LOG_ERROR("Read of NVM register CTRKB failed.");
651 return ERROR_FAIL;
652 }
653 if (manual_wp) {
654 /* Trigger flash write */
655 res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_WAP);
656 } else {
657 res = samd_check_error(target);
658 }
659
660 return res;
661 }
662
663 /**
664 * Modifies the user row register to the given value.
665 * @param target Pointer to the target structure.
666 * @param value The value to write.
667 * @param startb The bit-offset by which the given value is shifted.
668 * @param endb The bit-offset of the last bit in value to write.
669 * @return On success ERROR_OK, on failure an errorcode.
670 */
671 static int samd_modify_user_row(struct target *target, uint64_t value,
672 uint8_t startb, uint8_t endb)
673 {
674 uint64_t mask = 0;
675 int i;
676 for (i = startb ; i <= endb ; i++)
677 mask |= ((uint64_t)1) << i;
678
679 return samd_modify_user_row_masked(target, value << startb, mask);
680 }
681
682 static int samd_protect(struct flash_bank *bank, int set, int first_prot_bl, int last_prot_bl)
683 {
684 int res = ERROR_OK;
685 int prot_block;
686
687 /* We can issue lock/unlock region commands with the target running but
688 * the settings won't persist unless we're able to modify the LOCK regions
689 * and that requires the target to be halted. */
690 if (bank->target->state != TARGET_HALTED) {
691 LOG_ERROR("Target not halted");
692 return ERROR_TARGET_NOT_HALTED;
693 }
694
695 for (prot_block = first_prot_bl; prot_block <= last_prot_bl; prot_block++) {
696 if (set != bank->prot_blocks[prot_block].is_protected) {
697 /* Load an address that is within this protection block (we use offset 0) */
698 res = target_write_u32(bank->target,
699 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR,
700 bank->prot_blocks[prot_block].offset >> 1);
701 if (res != ERROR_OK)
702 goto exit;
703
704 /* Tell the controller to lock that block */
705 res = samd_issue_nvmctrl_command(bank->target,
706 set ? SAMD_NVM_CMD_LR : SAMD_NVM_CMD_UR);
707 if (res != ERROR_OK)
708 goto exit;
709 }
710 }
711
712 /* We've now applied our changes, however they will be undone by the next
713 * reset unless we also apply them to the LOCK bits in the User Page. The
714 * LOCK bits start at bit 48, corresponding to Sector 0 and end with bit 63,
715 * corresponding to Sector 15. A '1' means unlocked and a '0' means
716 * locked. See Table 9-3 in the SAMD20 datasheet for more details. */
717
718 res = samd_modify_user_row(bank->target,
719 set ? (uint64_t)0 : (uint64_t)UINT64_MAX,
720 48 + first_prot_bl, 48 + last_prot_bl);
721 if (res != ERROR_OK)
722 LOG_WARNING("SAMD: protect settings were not made persistent!");
723
724 res = ERROR_OK;
725
726 exit:
727 samd_protect_check(bank);
728
729 return res;
730 }
731
732 static int samd_erase(struct flash_bank *bank, int first_sect, int last_sect)
733 {
734 int res, s;
735 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
736
737 if (bank->target->state != TARGET_HALTED) {
738 LOG_ERROR("Target not halted");
739
740 return ERROR_TARGET_NOT_HALTED;
741 }
742
743 if (!chip->probed) {
744 if (samd_probe(bank) != ERROR_OK)
745 return ERROR_FLASH_BANK_NOT_PROBED;
746 }
747
748 /* For each sector to be erased */
749 for (s = first_sect; s <= last_sect; s++) {
750 res = samd_erase_row(bank->target, bank->sectors[s].offset);
751 if (res != ERROR_OK) {
752 LOG_ERROR("SAMD: failed to erase sector %d at 0x%08" PRIx32, s, bank->sectors[s].offset);
753 return res;
754 }
755 }
756
757 return ERROR_OK;
758 }
759
760
761 static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
762 uint32_t offset, uint32_t count)
763 {
764 int res;
765 uint32_t nvm_ctrlb;
766 uint32_t address;
767 uint32_t pg_offset;
768 uint32_t nb;
769 uint32_t nw;
770 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
771 uint8_t *pb = NULL;
772 bool manual_wp;
773
774 if (bank->target->state != TARGET_HALTED) {
775 LOG_ERROR("Target not halted");
776 return ERROR_TARGET_NOT_HALTED;
777 }
778
779 if (!chip->probed) {
780 if (samd_probe(bank) != ERROR_OK)
781 return ERROR_FLASH_BANK_NOT_PROBED;
782 }
783
784 /* Check if we need to do manual page write commands */
785 res = target_read_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
786
787 if (res != ERROR_OK)
788 return res;
789
790 if (nvm_ctrlb & SAMD_NVM_CTRLB_MANW)
791 manual_wp = true;
792 else
793 manual_wp = false;
794
795 res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_PBC);
796 if (res != ERROR_OK) {
797 LOG_ERROR("%s: %d", __func__, __LINE__);
798 return res;
799 }
800
801 while (count) {
802 nb = chip->page_size - offset % chip->page_size;
803 if (count < nb)
804 nb = count;
805
806 address = bank->base + offset;
807 pg_offset = offset % chip->page_size;
808
809 if (offset % 4 || (offset + nb) % 4) {
810 /* Either start or end of write is not word aligned */
811 if (!pb) {
812 pb = malloc(chip->page_size);
813 if (!pb)
814 return ERROR_FAIL;
815 }
816
817 /* Set temporary page buffer to 0xff and overwrite the relevant part */
818 memset(pb, 0xff, chip->page_size);
819 memcpy(pb + pg_offset, buffer, nb);
820
821 /* Align start address to a word boundary */
822 address -= offset % 4;
823 pg_offset -= offset % 4;
824 assert(pg_offset % 4 == 0);
825
826 /* Extend length to whole words */
827 nw = (nb + offset % 4 + 3) / 4;
828 assert(pg_offset + 4 * nw <= chip->page_size);
829
830 /* Now we have original data extended by 0xff bytes
831 * to the nearest word boundary on both start and end */
832 res = target_write_memory(bank->target, address, 4, nw, pb + pg_offset);
833 } else {
834 assert(nb % 4 == 0);
835 nw = nb / 4;
836 assert(pg_offset + 4 * nw <= chip->page_size);
837
838 /* Word aligned data, use direct write from buffer */
839 res = target_write_memory(bank->target, address, 4, nw, buffer);
840 }
841 if (res != ERROR_OK) {
842 LOG_ERROR("%s: %d", __func__, __LINE__);
843 goto free_pb;
844 }
845
846 /* Devices with errata 13134 have automatic page write enabled by default
847 * For other devices issue a write page CMD to the NVM
848 * If the page has not been written up to the last word
849 * then issue CMD_WP always */
850 if (manual_wp || pg_offset + 4 * nw < chip->page_size) {
851 res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_WP);
852 } else {
853 /* Access through AHB is stalled while flash is being programmed */
854 usleep(200);
855
856 res = samd_check_error(bank->target);
857 }
858
859 if (res != ERROR_OK) {
860 LOG_ERROR("%s: write failed at address 0x%08" PRIx32, __func__, address);
861 goto free_pb;
862 }
863
864 /* We're done with the page contents */
865 count -= nb;
866 offset += nb;
867 buffer += nb;
868 }
869
870 free_pb:
871 if (pb)
872 free(pb);
873
874 return res;
875 }
876
877 FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
878 {
879 if (bank->base != SAMD_FLASH) {
880 LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
881 "[at91samd series] )",
882 bank->base, SAMD_FLASH);
883 return ERROR_FAIL;
884 }
885
886 struct samd_info *chip;
887 chip = calloc(1, sizeof(*chip));
888 if (!chip) {
889 LOG_ERROR("No memory for flash bank chip info");
890 return ERROR_FAIL;
891 }
892
893 chip->target = bank->target;
894 chip->probed = false;
895
896 bank->driver_priv = chip;
897
898 return ERROR_OK;
899 }
900
901 COMMAND_HANDLER(samd_handle_info_command)
902 {
903 return ERROR_OK;
904 }
905
906 COMMAND_HANDLER(samd_handle_chip_erase_command)
907 {
908 struct target *target = get_current_target(CMD_CTX);
909 int res = ERROR_FAIL;
910
911 if (target) {
912 /* Enable access to the DSU by disabling the write protect bit */
913 target_write_u32(target, SAMD_PAC1, (1<<1));
914 /* intentionally without error checking - not accessible on secured chip */
915
916 /* Tell the DSU to perform a full chip erase. It takes about 240ms to
917 * perform the erase. */
918 res = target_write_u8(target, SAMD_DSU + SAMD_DSU_CTRL_EXT, (1<<4));
919 if (res == ERROR_OK)
920 command_print(CMD_CTX, "chip erase started");
921 else
922 command_print(CMD_CTX, "write to DSU CTRL failed");
923 }
924
925 return res;
926 }
927
928 COMMAND_HANDLER(samd_handle_set_security_command)
929 {
930 int res = ERROR_OK;
931 struct target *target = get_current_target(CMD_CTX);
932
933 if (CMD_ARGC < 1 || (CMD_ARGC >= 1 && (strcmp(CMD_ARGV[0], "enable")))) {
934 command_print(CMD_CTX, "supply the \"enable\" argument to proceed.");
935 return ERROR_COMMAND_SYNTAX_ERROR;
936 }
937
938 if (target) {
939 if (target->state != TARGET_HALTED) {
940 LOG_ERROR("Target not halted");
941 return ERROR_TARGET_NOT_HALTED;
942 }
943
944 res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_SSB);
945
946 /* Check (and clear) error conditions */
947 if (res == ERROR_OK)
948 command_print(CMD_CTX, "chip secured on next power-cycle");
949 else
950 command_print(CMD_CTX, "failed to secure chip");
951 }
952
953 return res;
954 }
955
956 COMMAND_HANDLER(samd_handle_eeprom_command)
957 {
958 int res = ERROR_OK;
959 struct target *target = get_current_target(CMD_CTX);
960
961 if (target) {
962 if (target->state != TARGET_HALTED) {
963 LOG_ERROR("Target not halted");
964 return ERROR_TARGET_NOT_HALTED;
965 }
966
967 if (CMD_ARGC >= 1) {
968 int val = atoi(CMD_ARGV[0]);
969 uint32_t code;
970
971 if (val == 0)
972 code = 7;
973 else {
974 /* Try to match size in bytes with corresponding size code */
975 for (code = 0; code <= 6; code++) {
976 if (val == (2 << (13 - code)))
977 break;
978 }
979
980 if (code > 6) {
981 command_print(CMD_CTX, "Invalid EEPROM size. Please see "
982 "datasheet for a list valid sizes.");
983 return ERROR_COMMAND_SYNTAX_ERROR;
984 }
985 }
986
987 res = samd_modify_user_row(target, code, 4, 6);
988 } else {
989 uint16_t val;
990 res = target_read_u16(target, SAMD_USER_ROW, &val);
991 if (res == ERROR_OK) {
992 uint32_t size = ((val >> 4) & 0x7); /* grab size code */
993
994 if (size == 0x7)
995 command_print(CMD_CTX, "EEPROM is disabled");
996 else {
997 /* Otherwise, 6 is 256B, 0 is 16KB */
998 command_print(CMD_CTX, "EEPROM size is %u bytes",
999 (2 << (13 - size)));
1000 }
1001 }
1002 }
1003 }
1004
1005 return res;
1006 }
1007
1008 static COMMAND_HELPER(get_u64_from_hexarg, unsigned int num, uint64_t *value)
1009 {
1010 if (num >= CMD_ARGC) {
1011 command_print(CMD_CTX, "Too few Arguments.");
1012 return ERROR_COMMAND_SYNTAX_ERROR;
1013 }
1014
1015 if (strlen(CMD_ARGV[num]) >= 3 &&
1016 CMD_ARGV[num][0] == '0' &&
1017 CMD_ARGV[num][1] == 'x') {
1018 char *check = NULL;
1019 *value = strtoull(&(CMD_ARGV[num][2]), &check, 16);
1020 if ((value == 0 && errno == ERANGE) ||
1021 check == NULL || *check != 0) {
1022 command_print(CMD_CTX, "Invalid 64-bit hex value in argument %d.",
1023 num + 1);
1024 return ERROR_COMMAND_SYNTAX_ERROR;
1025 }
1026 } else {
1027 command_print(CMD_CTX, "Argument %d needs to be a hex value.", num + 1);
1028 return ERROR_COMMAND_SYNTAX_ERROR;
1029 }
1030 return ERROR_OK;
1031 }
1032
1033 COMMAND_HANDLER(samd_handle_nvmuserrow_command)
1034 {
1035 int res = ERROR_OK;
1036 struct target *target = get_current_target(CMD_CTX);
1037
1038 if (target) {
1039 if (CMD_ARGC > 2) {
1040 command_print(CMD_CTX, "Too much Arguments given.");
1041 return ERROR_COMMAND_SYNTAX_ERROR;
1042 }
1043
1044 if (CMD_ARGC > 0) {
1045 if (target->state != TARGET_HALTED) {
1046 LOG_ERROR("Target not halted.");
1047 return ERROR_TARGET_NOT_HALTED;
1048 }
1049
1050 uint64_t mask;
1051 res = samd_get_reservedmask(target, &mask);
1052 if (res != ERROR_OK) {
1053 LOG_ERROR("Couldn't determine the mask for reserved bits.");
1054 return ERROR_FAIL;
1055 }
1056 mask &= NVMUSERROW_LOCKBIT_MASK;
1057
1058 uint64_t value;
1059 res = CALL_COMMAND_HANDLER(get_u64_from_hexarg, 0, &value);
1060 if (res != ERROR_OK)
1061 return res;
1062 if (CMD_ARGC == 2) {
1063 uint64_t mask_temp;
1064 res = CALL_COMMAND_HANDLER(get_u64_from_hexarg, 1, &mask_temp);
1065 if (res != ERROR_OK)
1066 return res;
1067 mask &= mask_temp;
1068 }
1069 res = samd_modify_user_row_masked(target, value, mask);
1070 if (res != ERROR_OK)
1071 return res;
1072 }
1073
1074 /* read register */
1075 uint64_t value;
1076 res = read_userrow(target, &value);
1077 if (res == ERROR_OK)
1078 command_print(CMD_CTX, "NVMUSERROW: 0x%016"PRIX64, value);
1079 else
1080 LOG_ERROR("NVMUSERROW could not be read.");
1081 }
1082 return res;
1083 }
1084
1085 COMMAND_HANDLER(samd_handle_bootloader_command)
1086 {
1087 int res = ERROR_OK;
1088 struct target *target = get_current_target(CMD_CTX);
1089
1090 if (target) {
1091 if (target->state != TARGET_HALTED) {
1092 LOG_ERROR("Target not halted");
1093 return ERROR_TARGET_NOT_HALTED;
1094 }
1095
1096 /* Retrieve the MCU's page size, in bytes. */
1097 uint32_t page_size;
1098 res = samd_get_flash_page_info(target, &page_size, NULL);
1099 if (res != ERROR_OK) {
1100 LOG_ERROR("Couldn't determine Flash page size");
1101 return res;
1102 }
1103
1104 if (CMD_ARGC >= 1) {
1105 int val = atoi(CMD_ARGV[0]);
1106 uint32_t code;
1107
1108 if (val == 0)
1109 code = 7;
1110 else {
1111 /* Try to match size in bytes with corresponding size code */
1112 for (code = 0; code <= 6; code++) {
1113 if ((unsigned int)val == (2UL << (8UL - code)) * page_size)
1114 break;
1115 }
1116
1117 if (code > 6) {
1118 command_print(CMD_CTX, "Invalid bootloader size. Please "
1119 "see datasheet for a list valid sizes.");
1120 return ERROR_COMMAND_SYNTAX_ERROR;
1121 }
1122
1123 }
1124
1125 res = samd_modify_user_row(target, code, 0, 2);
1126 } else {
1127 uint16_t val;
1128 res = target_read_u16(target, SAMD_USER_ROW, &val);
1129 if (res == ERROR_OK) {
1130 uint32_t size = (val & 0x7); /* grab size code */
1131 uint32_t nb;
1132
1133 if (size == 0x7)
1134 nb = 0;
1135 else
1136 nb = (2 << (8 - size)) * page_size;
1137
1138 /* There are 4 pages per row */
1139 command_print(CMD_CTX, "Bootloader size is %" PRIu32 " bytes (%" PRIu32 " rows)",
1140 nb, (uint32_t)(nb / (page_size * 4)));
1141 }
1142 }
1143 }
1144
1145 return res;
1146 }
1147
1148
1149
1150 COMMAND_HANDLER(samd_handle_reset_deassert)
1151 {
1152 struct target *target = get_current_target(CMD_CTX);
1153 int retval = ERROR_OK;
1154 enum reset_types jtag_reset_config = jtag_get_reset_config();
1155
1156 /* If the target has been unresponsive before, try to re-establish
1157 * communication now - CPU is held in reset by DSU, DAP is working */
1158 if (!target_was_examined(target))
1159 target_examine_one(target);
1160 target_poll(target);
1161
1162 /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
1163 * so we just release reset held by DSU
1164 *
1165 * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
1166 *
1167 * After vectreset DSU release is not needed however makes no harm
1168 */
1169 if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
1170 retval = target_write_u32(target, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
1171 if (retval == ERROR_OK)
1172 retval = target_write_u32(target, DCB_DEMCR,
1173 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1174 /* do not return on error here, releasing DSU reset is more important */
1175 }
1176
1177 /* clear CPU Reset Phase Extension bit */
1178 int retval2 = target_write_u8(target, SAMD_DSU + SAMD_DSU_STATUSA, (1<<1));
1179 if (retval2 != ERROR_OK)
1180 return retval2;
1181
1182 return retval;
1183 }
1184
1185 static const struct command_registration at91samd_exec_command_handlers[] = {
1186 {
1187 .name = "dsu_reset_deassert",
1188 .handler = samd_handle_reset_deassert,
1189 .mode = COMMAND_EXEC,
1190 .help = "Deasert internal reset held by DSU."
1191 },
1192 {
1193 .name = "info",
1194 .handler = samd_handle_info_command,
1195 .mode = COMMAND_EXEC,
1196 .help = "Print information about the current at91samd chip "
1197 "and its flash configuration.",
1198 },
1199 {
1200 .name = "chip-erase",
1201 .handler = samd_handle_chip_erase_command,
1202 .mode = COMMAND_EXEC,
1203 .help = "Erase the entire Flash by using the Chip-"
1204 "Erase feature in the Device Service Unit (DSU).",
1205 },
1206 {
1207 .name = "set-security",
1208 .handler = samd_handle_set_security_command,
1209 .mode = COMMAND_EXEC,
1210 .help = "Secure the chip's Flash by setting the Security Bit. "
1211 "This makes it impossible to read the Flash contents. "
1212 "The only way to undo this is to issue the chip-erase "
1213 "command.",
1214 },
1215 {
1216 .name = "eeprom",
1217 .usage = "[size_in_bytes]",
1218 .handler = samd_handle_eeprom_command,
1219 .mode = COMMAND_EXEC,
1220 .help = "Show or set the EEPROM size setting, stored in the User Row. "
1221 "Please see Table 20-3 of the SAMD20 datasheet for allowed values. "
1222 "Changes are stored immediately but take affect after the MCU is "
1223 "reset.",
1224 },
1225 {
1226 .name = "bootloader",
1227 .usage = "[size_in_bytes]",
1228 .handler = samd_handle_bootloader_command,
1229 .mode = COMMAND_EXEC,
1230 .help = "Show or set the bootloader size, stored in the User Row. "
1231 "Please see Table 20-2 of the SAMD20 datasheet for allowed values. "
1232 "Changes are stored immediately but take affect after the MCU is "
1233 "reset.",
1234 },
1235 {
1236 .name = "nvmuserrow",
1237 .usage = "[value] [mask]",
1238 .handler = samd_handle_nvmuserrow_command,
1239 .mode = COMMAND_EXEC,
1240 .help = "Show or set the nvmuserrow register. It is 64 bit wide "
1241 "and located at address 0x804000. Use the optional mask argument "
1242 "to prevent changes at positions where the bitvalue is zero. "
1243 "For security reasons the lock- and reserved-bits are masked out "
1244 "in background and therefore cannot be changed.",
1245 },
1246 COMMAND_REGISTRATION_DONE
1247 };
1248
1249 static const struct command_registration at91samd_command_handlers[] = {
1250 {
1251 .name = "at91samd",
1252 .mode = COMMAND_ANY,
1253 .help = "at91samd flash command group",
1254 .usage = "",
1255 .chain = at91samd_exec_command_handlers,
1256 },
1257 COMMAND_REGISTRATION_DONE
1258 };
1259
1260 struct flash_driver at91samd_flash = {
1261 .name = "at91samd",
1262 .commands = at91samd_command_handlers,
1263 .flash_bank_command = samd_flash_bank_command,
1264 .erase = samd_erase,
1265 .protect = samd_protect,
1266 .write = samd_write,
1267 .read = default_flash_read,
1268 .probe = samd_probe,
1269 .auto_probe = samd_probe,
1270 .erase_check = default_flash_blank_check,
1271 .protect_check = samd_protect_check,
1272 .free_driver_priv = default_flash_free_driver_priv,
1273 };