24ca303781eb7de813cbd2745ed079867fd03345
[openocd.git] / src / flash / nor / at91samd.c
1 /***************************************************************************
2 * Copyright (C) 2013 by Andrey Yurovsky *
3 * Andrey Yurovsky <yurovsky@gmail.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18
19 #ifdef HAVE_CONFIG_H
20 #include "config.h"
21 #endif
22
23 #include "imp.h"
24 #include "helper/binarybuffer.h"
25
26 #include <target/cortex_m.h>
27
28 #define SAMD_NUM_PROT_BLOCKS 16
29 #define SAMD_PAGE_SIZE_MAX 1024
30
31 #define SAMD_FLASH ((uint32_t)0x00000000) /* physical Flash memory */
32 #define SAMD_USER_ROW ((uint32_t)0x00804000) /* User Row of Flash */
33 #define SAMD_PAC1 0x41000000 /* Peripheral Access Control 1 */
34 #define SAMD_DSU 0x41002000 /* Device Service Unit */
35 #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
36
37 #define SAMD_DSU_STATUSA 1 /* DSU status register */
38 #define SAMD_DSU_DID 0x18 /* Device ID register */
39 #define SAMD_DSU_CTRL_EXT 0x100 /* CTRL register, external access */
40
41 #define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
42 #define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
43 #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
44 #define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interupt Flag Status & Clear */
45 #define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
46 #define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
47 #define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
48
49 #define SAMD_CMDEX_KEY 0xA5UL
50 #define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
51
52 /* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */
53 #define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
54 #define SAMD_NVM_CMD_WP 0x04 /* Write Page */
55 #define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxilary Row */
56 #define SAMD_NVM_CMD_WAP 0x06 /* Write Auxilary Page */
57 #define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
58 #define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
59 #define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */
60 #define SAMD_NVM_CMD_CPRM 0x43 /* Clear Power Reduction Mode */
61 #define SAMD_NVM_CMD_PBC 0x44 /* Page Buffer Clear */
62 #define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */
63 #define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */
64
65 /* NVMCTRL bits */
66 #define SAMD_NVM_CTRLB_MANW 0x80
67
68 /* Known identifiers */
69 #define SAMD_PROCESSOR_M0 0x01
70 #define SAMD_FAMILY_D 0x00
71 #define SAMD_FAMILY_L 0x01
72 #define SAMD_FAMILY_C 0x02
73 #define SAMD_SERIES_20 0x00
74 #define SAMD_SERIES_21 0x01
75 #define SAMD_SERIES_22 0x02
76 #define SAMD_SERIES_10 0x02
77 #define SAMD_SERIES_11 0x03
78 #define SAMD_SERIES_09 0x04
79
80 /* Device ID macros */
81 #define SAMD_GET_PROCESSOR(id) (id >> 28)
82 #define SAMD_GET_FAMILY(id) (((id >> 23) & 0x1F))
83 #define SAMD_GET_SERIES(id) (((id >> 16) & 0x3F))
84 #define SAMD_GET_DEVSEL(id) (id & 0xFF)
85
86 /* Bits to mask out lockbits in user row */
87 #define NVMUSERROW_LOCKBIT_MASK ((uint64_t)0x0000FFFFFFFFFFFF)
88
89 struct samd_part {
90 uint8_t id;
91 const char *name;
92 uint32_t flash_kb;
93 uint32_t ram_kb;
94 };
95
96 /* Known SAMD09 parts. DID reset values missing in RM, see
97 * https://github.com/avrxml/asf/blob/master/sam0/utils/cmsis/samd09/include/ */
98 static const struct samd_part samd09_parts[] = {
99 { 0x0, "SAMD09D14A", 16, 4 },
100 { 0x7, "SAMD09C13A", 8, 4 },
101 };
102
103 /* Known SAMD10 parts */
104 static const struct samd_part samd10_parts[] = {
105 { 0x0, "SAMD10D14AMU", 16, 4 },
106 { 0x1, "SAMD10D13AMU", 8, 4 },
107 { 0x2, "SAMD10D12AMU", 4, 4 },
108 { 0x3, "SAMD10D14ASU", 16, 4 },
109 { 0x4, "SAMD10D13ASU", 8, 4 },
110 { 0x5, "SAMD10D12ASU", 4, 4 },
111 { 0x6, "SAMD10C14A", 16, 4 },
112 { 0x7, "SAMD10C13A", 8, 4 },
113 { 0x8, "SAMD10C12A", 4, 4 },
114 };
115
116 /* Known SAMD11 parts */
117 static const struct samd_part samd11_parts[] = {
118 { 0x0, "SAMD11D14AM", 16, 4 },
119 { 0x1, "SAMD11D13AMU", 8, 4 },
120 { 0x2, "SAMD11D12AMU", 4, 4 },
121 { 0x3, "SAMD11D14ASS", 16, 4 },
122 { 0x4, "SAMD11D13ASU", 8, 4 },
123 { 0x5, "SAMD11D12ASU", 4, 4 },
124 { 0x6, "SAMD11C14A", 16, 4 },
125 { 0x7, "SAMD11C13A", 8, 4 },
126 { 0x8, "SAMD11C12A", 4, 4 },
127 { 0x9, "SAMD11D14AU", 16, 4 },
128 };
129
130 /* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */
131 static const struct samd_part samd20_parts[] = {
132 { 0x0, "SAMD20J18A", 256, 32 },
133 { 0x1, "SAMD20J17A", 128, 16 },
134 { 0x2, "SAMD20J16A", 64, 8 },
135 { 0x3, "SAMD20J15A", 32, 4 },
136 { 0x4, "SAMD20J14A", 16, 2 },
137 { 0x5, "SAMD20G18A", 256, 32 },
138 { 0x6, "SAMD20G17A", 128, 16 },
139 { 0x7, "SAMD20G16A", 64, 8 },
140 { 0x8, "SAMD20G15A", 32, 4 },
141 { 0x9, "SAMD20G14A", 16, 2 },
142 { 0xA, "SAMD20E18A", 256, 32 },
143 { 0xB, "SAMD20E17A", 128, 16 },
144 { 0xC, "SAMD20E16A", 64, 8 },
145 { 0xD, "SAMD20E15A", 32, 4 },
146 { 0xE, "SAMD20E14A", 16, 2 },
147 };
148
149 /* Known SAMD21 parts. */
150 static const struct samd_part samd21_parts[] = {
151 { 0x0, "SAMD21J18A", 256, 32 },
152 { 0x1, "SAMD21J17A", 128, 16 },
153 { 0x2, "SAMD21J16A", 64, 8 },
154 { 0x3, "SAMD21J15A", 32, 4 },
155 { 0x4, "SAMD21J14A", 16, 2 },
156 { 0x5, "SAMD21G18A", 256, 32 },
157 { 0x6, "SAMD21G17A", 128, 16 },
158 { 0x7, "SAMD21G16A", 64, 8 },
159 { 0x8, "SAMD21G15A", 32, 4 },
160 { 0x9, "SAMD21G14A", 16, 2 },
161 { 0xA, "SAMD21E18A", 256, 32 },
162 { 0xB, "SAMD21E17A", 128, 16 },
163 { 0xC, "SAMD21E16A", 64, 8 },
164 { 0xD, "SAMD21E15A", 32, 4 },
165 { 0xE, "SAMD21E14A", 16, 2 },
166
167 /* SAMR21 parts have integrated SAMD21 with a radio */
168 { 0x18, "SAMR21G19A", 256, 32 }, /* with 512k of serial flash */
169 { 0x19, "SAMR21G18A", 256, 32 },
170 { 0x1A, "SAMR21G17A", 128, 32 },
171 { 0x1B, "SAMR21G16A", 64, 16 },
172 { 0x1C, "SAMR21E18A", 256, 32 },
173 { 0x1D, "SAMR21E17A", 128, 32 },
174 { 0x1E, "SAMR21E16A", 64, 16 },
175
176 /* SAMD21 B Variants (Table 3-7 from rev I of datasheet) */
177 { 0x20, "SAMD21J16B", 64, 8 },
178 { 0x21, "SAMD21J15B", 32, 4 },
179 { 0x23, "SAMD21G16B", 64, 8 },
180 { 0x24, "SAMD21G15B", 32, 4 },
181 { 0x26, "SAMD21E16B", 64, 8 },
182 { 0x27, "SAMD21E15B", 32, 4 },
183
184 /* Known SAMDA1 parts.
185 SAMD-A1 series uses the same series identifier like the SAMD21
186 taken from http://ww1.microchip.com/downloads/en/DeviceDoc/40001895A.pdf (pages 14-17) */
187 { 0x29, "SAMDA1J16A", 64, 8 },
188 { 0x2A, "SAMDA1J15A", 32, 4 },
189 { 0x2B, "SAMDA1J14A", 16, 4 },
190 { 0x2C, "SAMDA1G16A", 64, 8 },
191 { 0x2D, "SAMDA1G15A", 32, 4 },
192 { 0x2E, "SAMDA1G14A", 16, 4 },
193 { 0x2F, "SAMDA1E16A", 64, 8 },
194 { 0x30, "SAMDA1E15A", 32, 4 },
195 { 0x31, "SAMDA1E14A", 16, 4 },
196 { 0x64, "SAMDA1J16B", 64, 8 },
197 { 0x65, "SAMDA1J15B", 32, 4 },
198 { 0x66, "SAMDA1J14B", 16, 4 },
199 { 0x67, "SAMDA1G16B", 64, 8 },
200 { 0x68, "SAMDA1G15B", 32, 4 },
201 { 0x69, "SAMDA1G14B", 16, 4 },
202 { 0x6A, "SAMDA1E16B", 64, 8 },
203 { 0x6B, "SAMDA1E15B", 32, 4 },
204 { 0x6C, "SAMDA1E14B", 16, 4 },
205 };
206
207 /* Known SAML21 parts. */
208 static const struct samd_part saml21_parts[] = {
209 { 0x00, "SAML21J18A", 256, 32 },
210 { 0x01, "SAML21J17A", 128, 16 },
211 { 0x02, "SAML21J16A", 64, 8 },
212 { 0x05, "SAML21G18A", 256, 32 },
213 { 0x06, "SAML21G17A", 128, 16 },
214 { 0x07, "SAML21G16A", 64, 8 },
215 { 0x0A, "SAML21E18A", 256, 32 },
216 { 0x0B, "SAML21E17A", 128, 16 },
217 { 0x0C, "SAML21E16A", 64, 8 },
218 { 0x0D, "SAML21E15A", 32, 4 },
219 { 0x0F, "SAML21J18B", 256, 32 },
220 { 0x10, "SAML21J17B", 128, 16 },
221 { 0x11, "SAML21J16B", 64, 8 },
222 { 0x14, "SAML21G18B", 256, 32 },
223 { 0x15, "SAML21G17B", 128, 16 },
224 { 0x16, "SAML21G16B", 64, 8 },
225 { 0x19, "SAML21E18B", 256, 32 },
226 { 0x1A, "SAML21E17B", 128, 16 },
227 { 0x1B, "SAML21E16B", 64, 8 },
228 { 0x1C, "SAML21E15B", 32, 4 },
229
230 /* SAMR30 parts have integrated SAML21 with a radio */
231 { 0x1E, "SAMR30G18A", 256, 32 },
232 { 0x1F, "SAMR30E18A", 256, 32 },
233 };
234
235 /* Known SAML22 parts. */
236 static const struct samd_part saml22_parts[] = {
237 { 0x00, "SAML22N18A", 256, 32 },
238 { 0x01, "SAML22N17A", 128, 16 },
239 { 0x02, "SAML22N16A", 64, 8 },
240 { 0x05, "SAML22J18A", 256, 32 },
241 { 0x06, "SAML22J17A", 128, 16 },
242 { 0x07, "SAML22J16A", 64, 8 },
243 { 0x0A, "SAML22G18A", 256, 32 },
244 { 0x0B, "SAML22G17A", 128, 16 },
245 { 0x0C, "SAML22G16A", 64, 8 },
246 };
247
248 /* Known SAMC20 parts. */
249 static const struct samd_part samc20_parts[] = {
250 { 0x00, "SAMC20J18A", 256, 32 },
251 { 0x01, "SAMC20J17A", 128, 16 },
252 { 0x02, "SAMC20J16A", 64, 8 },
253 { 0x03, "SAMC20J15A", 32, 4 },
254 { 0x05, "SAMC20G18A", 256, 32 },
255 { 0x06, "SAMC20G17A", 128, 16 },
256 { 0x07, "SAMC20G16A", 64, 8 },
257 { 0x08, "SAMC20G15A", 32, 4 },
258 { 0x0A, "SAMC20E18A", 256, 32 },
259 { 0x0B, "SAMC20E17A", 128, 16 },
260 { 0x0C, "SAMC20E16A", 64, 8 },
261 { 0x0D, "SAMC20E15A", 32, 4 },
262 };
263
264 /* Known SAMC21 parts. */
265 static const struct samd_part samc21_parts[] = {
266 { 0x00, "SAMC21J18A", 256, 32 },
267 { 0x01, "SAMC21J17A", 128, 16 },
268 { 0x02, "SAMC21J16A", 64, 8 },
269 { 0x03, "SAMC21J15A", 32, 4 },
270 { 0x05, "SAMC21G18A", 256, 32 },
271 { 0x06, "SAMC21G17A", 128, 16 },
272 { 0x07, "SAMC21G16A", 64, 8 },
273 { 0x08, "SAMC21G15A", 32, 4 },
274 { 0x0A, "SAMC21E18A", 256, 32 },
275 { 0x0B, "SAMC21E17A", 128, 16 },
276 { 0x0C, "SAMC21E16A", 64, 8 },
277 { 0x0D, "SAMC21E15A", 32, 4 },
278 };
279
280 /* Each family of parts contains a parts table in the DEVSEL field of DID. The
281 * processor ID, family ID, and series ID are used to determine which exact
282 * family this is and then we can use the corresponding table. */
283 struct samd_family {
284 uint8_t processor;
285 uint8_t family;
286 uint8_t series;
287 const struct samd_part *parts;
288 size_t num_parts;
289 uint64_t nvm_userrow_res_mask; /* protect bits which are reserved, 0 -> protect */
290 };
291
292 /* Known SAMD families */
293 static const struct samd_family samd_families[] = {
294 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_20,
295 samd20_parts, ARRAY_SIZE(samd20_parts),
296 (uint64_t)0xFFFF01FFFE01FF77 },
297 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
298 samd21_parts, ARRAY_SIZE(samd21_parts),
299 (uint64_t)0xFFFF01FFFE01FF77 },
300 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_09,
301 samd09_parts, ARRAY_SIZE(samd09_parts),
302 (uint64_t)0xFFFF01FFFE01FF77 },
303 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_10,
304 samd10_parts, ARRAY_SIZE(samd10_parts),
305 (uint64_t)0xFFFF01FFFE01FF77 },
306 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11,
307 samd11_parts, ARRAY_SIZE(samd11_parts),
308 (uint64_t)0xFFFF01FFFE01FF77 },
309 { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_21,
310 saml21_parts, ARRAY_SIZE(saml21_parts),
311 (uint64_t)0xFFFF03FFFC01FF77 },
312 { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_22,
313 saml22_parts, ARRAY_SIZE(saml22_parts),
314 (uint64_t)0xFFFF03FFFC01FF77 },
315 { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_20,
316 samc20_parts, ARRAY_SIZE(samc20_parts),
317 (uint64_t)0xFFFF03FFFC01FF77 },
318 { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_21,
319 samc21_parts, ARRAY_SIZE(samc21_parts),
320 (uint64_t)0xFFFF03FFFC01FF77 },
321 };
322
323 struct samd_info {
324 uint32_t page_size;
325 int num_pages;
326 int sector_size;
327 int prot_block_size;
328
329 bool probed;
330 struct target *target;
331 };
332
333
334 /**
335 * Gives the family structure to specific device id.
336 * @param id The id of the device.
337 * @return On failure NULL, otherwise a pointer to the structure.
338 */
339 static const struct samd_family *samd_find_family(uint32_t id)
340 {
341 uint8_t processor = SAMD_GET_PROCESSOR(id);
342 uint8_t family = SAMD_GET_FAMILY(id);
343 uint8_t series = SAMD_GET_SERIES(id);
344
345 for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) {
346 if (samd_families[i].processor == processor &&
347 samd_families[i].series == series &&
348 samd_families[i].family == family)
349 return &samd_families[i];
350 }
351
352 return NULL;
353 }
354
355 /**
356 * Gives the part structure to specific device id.
357 * @param id The id of the device.
358 * @return On failure NULL, otherwise a pointer to the structure.
359 */
360 static const struct samd_part *samd_find_part(uint32_t id)
361 {
362 uint8_t devsel = SAMD_GET_DEVSEL(id);
363 const struct samd_family *family = samd_find_family(id);
364 if (family == NULL)
365 return NULL;
366
367 for (unsigned i = 0; i < family->num_parts; i++) {
368 if (family->parts[i].id == devsel)
369 return &family->parts[i];
370 }
371
372 return NULL;
373 }
374
375 static int samd_protect_check(struct flash_bank *bank)
376 {
377 int res, prot_block;
378 uint16_t lock;
379
380 res = target_read_u16(bank->target,
381 SAMD_NVMCTRL + SAMD_NVMCTRL_LOCK, &lock);
382 if (res != ERROR_OK)
383 return res;
384
385 /* Lock bits are active-low */
386 for (prot_block = 0; prot_block < bank->num_prot_blocks; prot_block++)
387 bank->prot_blocks[prot_block].is_protected = !(lock & (1u<<prot_block));
388
389 return ERROR_OK;
390 }
391
392 static int samd_get_flash_page_info(struct target *target,
393 uint32_t *sizep, int *nump)
394 {
395 int res;
396 uint32_t param;
397
398 res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, &param);
399 if (res == ERROR_OK) {
400 /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n)
401 * so 0 is 8KB and 7 is 1024KB. */
402 if (sizep)
403 *sizep = (8 << ((param >> 16) & 0x7));
404 /* The NVMP field (bits 15:0) indicates the total number of pages */
405 if (nump)
406 *nump = param & 0xFFFF;
407 } else {
408 LOG_ERROR("Couldn't read NVM Parameters register");
409 }
410
411 return res;
412 }
413
414 static int samd_probe(struct flash_bank *bank)
415 {
416 uint32_t id;
417 int res;
418 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
419 const struct samd_part *part;
420
421 if (chip->probed)
422 return ERROR_OK;
423
424 res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
425 if (res != ERROR_OK) {
426 LOG_ERROR("Couldn't read Device ID register");
427 return res;
428 }
429
430 part = samd_find_part(id);
431 if (part == NULL) {
432 LOG_ERROR("Couldn't find part corresponding to DID %08" PRIx32, id);
433 return ERROR_FAIL;
434 }
435
436 bank->size = part->flash_kb * 1024;
437
438 res = samd_get_flash_page_info(bank->target, &chip->page_size,
439 &chip->num_pages);
440 if (res != ERROR_OK) {
441 LOG_ERROR("Couldn't determine Flash page size");
442 return res;
443 }
444
445 /* Sanity check: the total flash size in the DSU should match the page size
446 * multiplied by the number of pages. */
447 if (bank->size != chip->num_pages * chip->page_size) {
448 LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
449 "Identified %" PRIu32 "KB Flash but NVMCTRL reports %u %" PRIu32 "B pages",
450 part->flash_kb, chip->num_pages, chip->page_size);
451 }
452
453 /* Erase granularity = 1 row = 4 pages */
454 chip->sector_size = chip->page_size * 4;
455
456 /* Allocate the sector table */
457 bank->num_sectors = chip->num_pages / 4;
458 bank->sectors = alloc_block_array(0, chip->sector_size, bank->num_sectors);
459 if (!bank->sectors)
460 return ERROR_FAIL;
461
462 /* 16 protection blocks per device */
463 chip->prot_block_size = bank->size / SAMD_NUM_PROT_BLOCKS;
464
465 /* Allocate the table of protection blocks */
466 bank->num_prot_blocks = SAMD_NUM_PROT_BLOCKS;
467 bank->prot_blocks = alloc_block_array(0, chip->prot_block_size, bank->num_prot_blocks);
468 if (!bank->prot_blocks)
469 return ERROR_FAIL;
470
471 samd_protect_check(bank);
472
473 /* Done */
474 chip->probed = true;
475
476 LOG_INFO("SAMD MCU: %s (%" PRIu32 "KB Flash, %" PRIu32 "KB RAM)", part->name,
477 part->flash_kb, part->ram_kb);
478
479 return ERROR_OK;
480 }
481
482 static int samd_check_error(struct target *target)
483 {
484 int ret, ret2;
485 uint16_t status;
486
487 ret = target_read_u16(target,
488 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status);
489 if (ret != ERROR_OK) {
490 LOG_ERROR("Can't read NVM status");
491 return ret;
492 }
493
494 if ((status & 0x001C) == 0)
495 return ERROR_OK;
496
497 if (status & (1 << 4)) { /* NVME */
498 LOG_ERROR("SAMD: NVM Error");
499 ret = ERROR_FLASH_OPERATION_FAILED;
500 }
501
502 if (status & (1 << 3)) { /* LOCKE */
503 LOG_ERROR("SAMD: NVM lock error");
504 ret = ERROR_FLASH_PROTECTED;
505 }
506
507 if (status & (1 << 2)) { /* PROGE */
508 LOG_ERROR("SAMD: NVM programming error");
509 ret = ERROR_FLASH_OPER_UNSUPPORTED;
510 }
511
512 /* Clear the error conditions by writing a one to them */
513 ret2 = target_write_u16(target,
514 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, status);
515 if (ret2 != ERROR_OK)
516 LOG_ERROR("Can't clear NVM error conditions");
517
518 return ret;
519 }
520
521 static int samd_issue_nvmctrl_command(struct target *target, uint16_t cmd)
522 {
523 int res;
524
525 if (target->state != TARGET_HALTED) {
526 LOG_ERROR("Target not halted");
527 return ERROR_TARGET_NOT_HALTED;
528 }
529
530 /* Issue the NVM command */
531 res = target_write_u16(target,
532 SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, SAMD_NVM_CMD(cmd));
533 if (res != ERROR_OK)
534 return res;
535
536 /* Check to see if the NVM command resulted in an error condition. */
537 return samd_check_error(target);
538 }
539
540 /**
541 * Erases a flash-row at the given address.
542 * @param target Pointer to the target structure.
543 * @param address The address of the row.
544 * @return On success ERROR_OK, on failure an errorcode.
545 */
546 static int samd_erase_row(struct target *target, uint32_t address)
547 {
548 int res;
549
550 /* Set an address contained in the row to be erased */
551 res = target_write_u32(target,
552 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, address >> 1);
553
554 /* Issue the Erase Row command to erase that row. */
555 if (res == ERROR_OK)
556 res = samd_issue_nvmctrl_command(target,
557 address == SAMD_USER_ROW ? SAMD_NVM_CMD_EAR : SAMD_NVM_CMD_ER);
558
559 if (res != ERROR_OK) {
560 LOG_ERROR("Failed to erase row containing %08" PRIx32, address);
561 return ERROR_FAIL;
562 }
563
564 return ERROR_OK;
565 }
566
567 /**
568 * Returns the bitmask of reserved bits in register.
569 * @param target Pointer to the target structure.
570 * @param mask Bitmask, 0 -> value stays untouched.
571 * @return On success ERROR_OK, on failure an errorcode.
572 */
573 static int samd_get_reservedmask(struct target *target, uint64_t *mask)
574 {
575 int res;
576 /* Get the devicetype */
577 uint32_t id;
578 res = target_read_u32(target, SAMD_DSU + SAMD_DSU_DID, &id);
579 if (res != ERROR_OK) {
580 LOG_ERROR("Couldn't read Device ID register");
581 return res;
582 }
583 const struct samd_family *family;
584 family = samd_find_family(id);
585 if (family == NULL) {
586 LOG_ERROR("Couldn't determine device family");
587 return ERROR_FAIL;
588 }
589 *mask = family->nvm_userrow_res_mask;
590 return ERROR_OK;
591 }
592
593 static int read_userrow(struct target *target, uint64_t *userrow)
594 {
595 int res;
596 uint8_t buffer[8];
597
598 res = target_read_memory(target, SAMD_USER_ROW, 4, 2, buffer);
599 if (res != ERROR_OK)
600 return res;
601
602 *userrow = target_buffer_get_u64(target, buffer);
603 return ERROR_OK;
604 }
605
606 /**
607 * Modify the contents of the User Row in Flash. The User Row itself
608 * has a size of one page and contains a combination of "fuses" and
609 * calibration data. Bits which have a value of zero in the mask will
610 * not be changed. Up to now devices only use the first 64 bits.
611 * @param target Pointer to the target structure.
612 * @param value_input The value to write.
613 * @param value_mask Bitmask, 0 -> value stays untouched.
614 * @return On success ERROR_OK, on failure an errorcode.
615 */
616 static int samd_modify_user_row_masked(struct target *target,
617 uint64_t value_input, uint64_t value_mask)
618 {
619 int res;
620 uint32_t nvm_ctrlb;
621 bool manual_wp = true;
622
623 /* Retrieve the MCU's page size, in bytes. This is also the size of the
624 * entire User Row. */
625 uint32_t page_size;
626 res = samd_get_flash_page_info(target, &page_size, NULL);
627 if (res != ERROR_OK) {
628 LOG_ERROR("Couldn't determine Flash page size");
629 return res;
630 }
631
632 /* Make sure the size is sane. */
633 assert(page_size <= SAMD_PAGE_SIZE_MAX &&
634 page_size >= sizeof(value_input));
635
636 uint8_t buf[SAMD_PAGE_SIZE_MAX];
637 /* Read the user row (comprising one page) by words. */
638 res = target_read_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
639 if (res != ERROR_OK)
640 return res;
641
642 uint64_t value_device;
643 res = read_userrow(target, &value_device);
644 if (res != ERROR_OK)
645 return res;
646 uint64_t value_new = (value_input & value_mask) | (value_device & ~value_mask);
647
648 /* We will need to erase before writing if the new value needs a '1' in any
649 * position for which the current value had a '0'. Otherwise we can avoid
650 * erasing. */
651 if ((~value_device) & value_new) {
652 res = samd_erase_row(target, SAMD_USER_ROW);
653 if (res != ERROR_OK) {
654 LOG_ERROR("Couldn't erase user row");
655 return res;
656 }
657 }
658
659 /* Modify */
660 target_buffer_set_u64(target, buf, value_new);
661
662 /* Write the page buffer back out to the target. */
663 res = target_write_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
664 if (res != ERROR_OK)
665 return res;
666
667 /* Check if we need to do manual page write commands */
668 res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
669 if (res == ERROR_OK)
670 manual_wp = (nvm_ctrlb & SAMD_NVM_CTRLB_MANW) != 0;
671 else {
672 LOG_ERROR("Read of NVM register CTRKB failed.");
673 return ERROR_FAIL;
674 }
675 if (manual_wp) {
676 /* Trigger flash write */
677 res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_WAP);
678 } else {
679 res = samd_check_error(target);
680 }
681
682 return res;
683 }
684
685 /**
686 * Modifies the user row register to the given value.
687 * @param target Pointer to the target structure.
688 * @param value The value to write.
689 * @param startb The bit-offset by which the given value is shifted.
690 * @param endb The bit-offset of the last bit in value to write.
691 * @return On success ERROR_OK, on failure an errorcode.
692 */
693 static int samd_modify_user_row(struct target *target, uint64_t value,
694 uint8_t startb, uint8_t endb)
695 {
696 uint64_t mask = 0;
697 int i;
698 for (i = startb ; i <= endb ; i++)
699 mask |= ((uint64_t)1) << i;
700
701 return samd_modify_user_row_masked(target, value << startb, mask);
702 }
703
704 static int samd_protect(struct flash_bank *bank, int set, int first_prot_bl, int last_prot_bl)
705 {
706 int res = ERROR_OK;
707 int prot_block;
708
709 /* We can issue lock/unlock region commands with the target running but
710 * the settings won't persist unless we're able to modify the LOCK regions
711 * and that requires the target to be halted. */
712 if (bank->target->state != TARGET_HALTED) {
713 LOG_ERROR("Target not halted");
714 return ERROR_TARGET_NOT_HALTED;
715 }
716
717 for (prot_block = first_prot_bl; prot_block <= last_prot_bl; prot_block++) {
718 if (set != bank->prot_blocks[prot_block].is_protected) {
719 /* Load an address that is within this protection block (we use offset 0) */
720 res = target_write_u32(bank->target,
721 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR,
722 bank->prot_blocks[prot_block].offset >> 1);
723 if (res != ERROR_OK)
724 goto exit;
725
726 /* Tell the controller to lock that block */
727 res = samd_issue_nvmctrl_command(bank->target,
728 set ? SAMD_NVM_CMD_LR : SAMD_NVM_CMD_UR);
729 if (res != ERROR_OK)
730 goto exit;
731 }
732 }
733
734 /* We've now applied our changes, however they will be undone by the next
735 * reset unless we also apply them to the LOCK bits in the User Page. The
736 * LOCK bits start at bit 48, corresponding to Sector 0 and end with bit 63,
737 * corresponding to Sector 15. A '1' means unlocked and a '0' means
738 * locked. See Table 9-3 in the SAMD20 datasheet for more details. */
739
740 res = samd_modify_user_row(bank->target,
741 set ? (uint64_t)0 : (uint64_t)UINT64_MAX,
742 48 + first_prot_bl, 48 + last_prot_bl);
743 if (res != ERROR_OK)
744 LOG_WARNING("SAMD: protect settings were not made persistent!");
745
746 res = ERROR_OK;
747
748 exit:
749 samd_protect_check(bank);
750
751 return res;
752 }
753
754 static int samd_erase(struct flash_bank *bank, int first_sect, int last_sect)
755 {
756 int res, s;
757 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
758
759 if (bank->target->state != TARGET_HALTED) {
760 LOG_ERROR("Target not halted");
761
762 return ERROR_TARGET_NOT_HALTED;
763 }
764
765 if (!chip->probed) {
766 if (samd_probe(bank) != ERROR_OK)
767 return ERROR_FLASH_BANK_NOT_PROBED;
768 }
769
770 /* For each sector to be erased */
771 for (s = first_sect; s <= last_sect; s++) {
772 res = samd_erase_row(bank->target, bank->sectors[s].offset);
773 if (res != ERROR_OK) {
774 LOG_ERROR("SAMD: failed to erase sector %d at 0x%08" PRIx32, s, bank->sectors[s].offset);
775 return res;
776 }
777 }
778
779 return ERROR_OK;
780 }
781
782
783 static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
784 uint32_t offset, uint32_t count)
785 {
786 int res;
787 uint32_t nvm_ctrlb;
788 uint32_t address;
789 uint32_t pg_offset;
790 uint32_t nb;
791 uint32_t nw;
792 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
793 uint8_t *pb = NULL;
794 bool manual_wp;
795
796 if (bank->target->state != TARGET_HALTED) {
797 LOG_ERROR("Target not halted");
798 return ERROR_TARGET_NOT_HALTED;
799 }
800
801 if (!chip->probed) {
802 if (samd_probe(bank) != ERROR_OK)
803 return ERROR_FLASH_BANK_NOT_PROBED;
804 }
805
806 /* Check if we need to do manual page write commands */
807 res = target_read_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
808
809 if (res != ERROR_OK)
810 return res;
811
812 if (nvm_ctrlb & SAMD_NVM_CTRLB_MANW)
813 manual_wp = true;
814 else
815 manual_wp = false;
816
817 res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_PBC);
818 if (res != ERROR_OK) {
819 LOG_ERROR("%s: %d", __func__, __LINE__);
820 return res;
821 }
822
823 while (count) {
824 nb = chip->page_size - offset % chip->page_size;
825 if (count < nb)
826 nb = count;
827
828 address = bank->base + offset;
829 pg_offset = offset % chip->page_size;
830
831 if (offset % 4 || (offset + nb) % 4) {
832 /* Either start or end of write is not word aligned */
833 if (!pb) {
834 pb = malloc(chip->page_size);
835 if (!pb)
836 return ERROR_FAIL;
837 }
838
839 /* Set temporary page buffer to 0xff and overwrite the relevant part */
840 memset(pb, 0xff, chip->page_size);
841 memcpy(pb + pg_offset, buffer, nb);
842
843 /* Align start address to a word boundary */
844 address -= offset % 4;
845 pg_offset -= offset % 4;
846 assert(pg_offset % 4 == 0);
847
848 /* Extend length to whole words */
849 nw = (nb + offset % 4 + 3) / 4;
850 assert(pg_offset + 4 * nw <= chip->page_size);
851
852 /* Now we have original data extended by 0xff bytes
853 * to the nearest word boundary on both start and end */
854 res = target_write_memory(bank->target, address, 4, nw, pb + pg_offset);
855 } else {
856 assert(nb % 4 == 0);
857 nw = nb / 4;
858 assert(pg_offset + 4 * nw <= chip->page_size);
859
860 /* Word aligned data, use direct write from buffer */
861 res = target_write_memory(bank->target, address, 4, nw, buffer);
862 }
863 if (res != ERROR_OK) {
864 LOG_ERROR("%s: %d", __func__, __LINE__);
865 goto free_pb;
866 }
867
868 /* Devices with errata 13134 have automatic page write enabled by default
869 * For other devices issue a write page CMD to the NVM
870 * If the page has not been written up to the last word
871 * then issue CMD_WP always */
872 if (manual_wp || pg_offset + 4 * nw < chip->page_size) {
873 res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_WP);
874 } else {
875 /* Access through AHB is stalled while flash is being programmed */
876 usleep(200);
877
878 res = samd_check_error(bank->target);
879 }
880
881 if (res != ERROR_OK) {
882 LOG_ERROR("%s: write failed at address 0x%08" PRIx32, __func__, address);
883 goto free_pb;
884 }
885
886 /* We're done with the page contents */
887 count -= nb;
888 offset += nb;
889 buffer += nb;
890 }
891
892 free_pb:
893 if (pb)
894 free(pb);
895
896 return res;
897 }
898
899 FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
900 {
901 if (bank->base != SAMD_FLASH) {
902 LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
903 "[at91samd series] )",
904 bank->base, SAMD_FLASH);
905 return ERROR_FAIL;
906 }
907
908 struct samd_info *chip;
909 chip = calloc(1, sizeof(*chip));
910 if (!chip) {
911 LOG_ERROR("No memory for flash bank chip info");
912 return ERROR_FAIL;
913 }
914
915 chip->target = bank->target;
916 chip->probed = false;
917
918 bank->driver_priv = chip;
919
920 return ERROR_OK;
921 }
922
923 COMMAND_HANDLER(samd_handle_info_command)
924 {
925 return ERROR_OK;
926 }
927
928 COMMAND_HANDLER(samd_handle_chip_erase_command)
929 {
930 struct target *target = get_current_target(CMD_CTX);
931 int res = ERROR_FAIL;
932
933 if (target) {
934 /* Enable access to the DSU by disabling the write protect bit */
935 target_write_u32(target, SAMD_PAC1, (1<<1));
936 /* intentionally without error checking - not accessible on secured chip */
937
938 /* Tell the DSU to perform a full chip erase. It takes about 240ms to
939 * perform the erase. */
940 res = target_write_u8(target, SAMD_DSU + SAMD_DSU_CTRL_EXT, (1<<4));
941 if (res == ERROR_OK)
942 command_print(CMD_CTX, "chip erase started");
943 else
944 command_print(CMD_CTX, "write to DSU CTRL failed");
945 }
946
947 return res;
948 }
949
950 COMMAND_HANDLER(samd_handle_set_security_command)
951 {
952 int res = ERROR_OK;
953 struct target *target = get_current_target(CMD_CTX);
954
955 if (CMD_ARGC < 1 || (CMD_ARGC >= 1 && (strcmp(CMD_ARGV[0], "enable")))) {
956 command_print(CMD_CTX, "supply the \"enable\" argument to proceed.");
957 return ERROR_COMMAND_SYNTAX_ERROR;
958 }
959
960 if (target) {
961 if (target->state != TARGET_HALTED) {
962 LOG_ERROR("Target not halted");
963 return ERROR_TARGET_NOT_HALTED;
964 }
965
966 res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_SSB);
967
968 /* Check (and clear) error conditions */
969 if (res == ERROR_OK)
970 command_print(CMD_CTX, "chip secured on next power-cycle");
971 else
972 command_print(CMD_CTX, "failed to secure chip");
973 }
974
975 return res;
976 }
977
978 COMMAND_HANDLER(samd_handle_eeprom_command)
979 {
980 int res = ERROR_OK;
981 struct target *target = get_current_target(CMD_CTX);
982
983 if (target) {
984 if (target->state != TARGET_HALTED) {
985 LOG_ERROR("Target not halted");
986 return ERROR_TARGET_NOT_HALTED;
987 }
988
989 if (CMD_ARGC >= 1) {
990 int val = atoi(CMD_ARGV[0]);
991 uint32_t code;
992
993 if (val == 0)
994 code = 7;
995 else {
996 /* Try to match size in bytes with corresponding size code */
997 for (code = 0; code <= 6; code++) {
998 if (val == (2 << (13 - code)))
999 break;
1000 }
1001
1002 if (code > 6) {
1003 command_print(CMD_CTX, "Invalid EEPROM size. Please see "
1004 "datasheet for a list valid sizes.");
1005 return ERROR_COMMAND_SYNTAX_ERROR;
1006 }
1007 }
1008
1009 res = samd_modify_user_row(target, code, 4, 6);
1010 } else {
1011 uint16_t val;
1012 res = target_read_u16(target, SAMD_USER_ROW, &val);
1013 if (res == ERROR_OK) {
1014 uint32_t size = ((val >> 4) & 0x7); /* grab size code */
1015
1016 if (size == 0x7)
1017 command_print(CMD_CTX, "EEPROM is disabled");
1018 else {
1019 /* Otherwise, 6 is 256B, 0 is 16KB */
1020 command_print(CMD_CTX, "EEPROM size is %u bytes",
1021 (2 << (13 - size)));
1022 }
1023 }
1024 }
1025 }
1026
1027 return res;
1028 }
1029
1030 static COMMAND_HELPER(get_u64_from_hexarg, unsigned int num, uint64_t *value)
1031 {
1032 if (num >= CMD_ARGC) {
1033 command_print(CMD_CTX, "Too few Arguments.");
1034 return ERROR_COMMAND_SYNTAX_ERROR;
1035 }
1036
1037 if (strlen(CMD_ARGV[num]) >= 3 &&
1038 CMD_ARGV[num][0] == '0' &&
1039 CMD_ARGV[num][1] == 'x') {
1040 char *check = NULL;
1041 *value = strtoull(&(CMD_ARGV[num][2]), &check, 16);
1042 if ((value == 0 && errno == ERANGE) ||
1043 check == NULL || *check != 0) {
1044 command_print(CMD_CTX, "Invalid 64-bit hex value in argument %d.",
1045 num + 1);
1046 return ERROR_COMMAND_SYNTAX_ERROR;
1047 }
1048 } else {
1049 command_print(CMD_CTX, "Argument %d needs to be a hex value.", num + 1);
1050 return ERROR_COMMAND_SYNTAX_ERROR;
1051 }
1052 return ERROR_OK;
1053 }
1054
1055 COMMAND_HANDLER(samd_handle_nvmuserrow_command)
1056 {
1057 int res = ERROR_OK;
1058 struct target *target = get_current_target(CMD_CTX);
1059
1060 if (target) {
1061 if (CMD_ARGC > 2) {
1062 command_print(CMD_CTX, "Too much Arguments given.");
1063 return ERROR_COMMAND_SYNTAX_ERROR;
1064 }
1065
1066 if (CMD_ARGC > 0) {
1067 if (target->state != TARGET_HALTED) {
1068 LOG_ERROR("Target not halted.");
1069 return ERROR_TARGET_NOT_HALTED;
1070 }
1071
1072 uint64_t mask;
1073 res = samd_get_reservedmask(target, &mask);
1074 if (res != ERROR_OK) {
1075 LOG_ERROR("Couldn't determine the mask for reserved bits.");
1076 return ERROR_FAIL;
1077 }
1078 mask &= NVMUSERROW_LOCKBIT_MASK;
1079
1080 uint64_t value;
1081 res = CALL_COMMAND_HANDLER(get_u64_from_hexarg, 0, &value);
1082 if (res != ERROR_OK)
1083 return res;
1084 if (CMD_ARGC == 2) {
1085 uint64_t mask_temp;
1086 res = CALL_COMMAND_HANDLER(get_u64_from_hexarg, 1, &mask_temp);
1087 if (res != ERROR_OK)
1088 return res;
1089 mask &= mask_temp;
1090 }
1091 res = samd_modify_user_row_masked(target, value, mask);
1092 if (res != ERROR_OK)
1093 return res;
1094 }
1095
1096 /* read register */
1097 uint64_t value;
1098 res = read_userrow(target, &value);
1099 if (res == ERROR_OK)
1100 command_print(CMD_CTX, "NVMUSERROW: 0x%016"PRIX64, value);
1101 else
1102 LOG_ERROR("NVMUSERROW could not be read.");
1103 }
1104 return res;
1105 }
1106
1107 COMMAND_HANDLER(samd_handle_bootloader_command)
1108 {
1109 int res = ERROR_OK;
1110 struct target *target = get_current_target(CMD_CTX);
1111
1112 if (target) {
1113 if (target->state != TARGET_HALTED) {
1114 LOG_ERROR("Target not halted");
1115 return ERROR_TARGET_NOT_HALTED;
1116 }
1117
1118 /* Retrieve the MCU's page size, in bytes. */
1119 uint32_t page_size;
1120 res = samd_get_flash_page_info(target, &page_size, NULL);
1121 if (res != ERROR_OK) {
1122 LOG_ERROR("Couldn't determine Flash page size");
1123 return res;
1124 }
1125
1126 if (CMD_ARGC >= 1) {
1127 int val = atoi(CMD_ARGV[0]);
1128 uint32_t code;
1129
1130 if (val == 0)
1131 code = 7;
1132 else {
1133 /* Try to match size in bytes with corresponding size code */
1134 for (code = 0; code <= 6; code++) {
1135 if ((unsigned int)val == (2UL << (8UL - code)) * page_size)
1136 break;
1137 }
1138
1139 if (code > 6) {
1140 command_print(CMD_CTX, "Invalid bootloader size. Please "
1141 "see datasheet for a list valid sizes.");
1142 return ERROR_COMMAND_SYNTAX_ERROR;
1143 }
1144
1145 }
1146
1147 res = samd_modify_user_row(target, code, 0, 2);
1148 } else {
1149 uint16_t val;
1150 res = target_read_u16(target, SAMD_USER_ROW, &val);
1151 if (res == ERROR_OK) {
1152 uint32_t size = (val & 0x7); /* grab size code */
1153 uint32_t nb;
1154
1155 if (size == 0x7)
1156 nb = 0;
1157 else
1158 nb = (2 << (8 - size)) * page_size;
1159
1160 /* There are 4 pages per row */
1161 command_print(CMD_CTX, "Bootloader size is %" PRIu32 " bytes (%" PRIu32 " rows)",
1162 nb, (uint32_t)(nb / (page_size * 4)));
1163 }
1164 }
1165 }
1166
1167 return res;
1168 }
1169
1170
1171
1172 COMMAND_HANDLER(samd_handle_reset_deassert)
1173 {
1174 struct target *target = get_current_target(CMD_CTX);
1175 int retval = ERROR_OK;
1176 enum reset_types jtag_reset_config = jtag_get_reset_config();
1177
1178 /* If the target has been unresponsive before, try to re-establish
1179 * communication now - CPU is held in reset by DSU, DAP is working */
1180 if (!target_was_examined(target))
1181 target_examine_one(target);
1182 target_poll(target);
1183
1184 /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
1185 * so we just release reset held by DSU
1186 *
1187 * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
1188 *
1189 * After vectreset DSU release is not needed however makes no harm
1190 */
1191 if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
1192 retval = target_write_u32(target, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
1193 if (retval == ERROR_OK)
1194 retval = target_write_u32(target, DCB_DEMCR,
1195 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1196 /* do not return on error here, releasing DSU reset is more important */
1197 }
1198
1199 /* clear CPU Reset Phase Extension bit */
1200 int retval2 = target_write_u8(target, SAMD_DSU + SAMD_DSU_STATUSA, (1<<1));
1201 if (retval2 != ERROR_OK)
1202 return retval2;
1203
1204 return retval;
1205 }
1206
1207 static const struct command_registration at91samd_exec_command_handlers[] = {
1208 {
1209 .name = "dsu_reset_deassert",
1210 .handler = samd_handle_reset_deassert,
1211 .mode = COMMAND_EXEC,
1212 .help = "Deasert internal reset held by DSU."
1213 },
1214 {
1215 .name = "info",
1216 .handler = samd_handle_info_command,
1217 .mode = COMMAND_EXEC,
1218 .help = "Print information about the current at91samd chip "
1219 "and its flash configuration.",
1220 },
1221 {
1222 .name = "chip-erase",
1223 .handler = samd_handle_chip_erase_command,
1224 .mode = COMMAND_EXEC,
1225 .help = "Erase the entire Flash by using the Chip-"
1226 "Erase feature in the Device Service Unit (DSU).",
1227 },
1228 {
1229 .name = "set-security",
1230 .handler = samd_handle_set_security_command,
1231 .mode = COMMAND_EXEC,
1232 .help = "Secure the chip's Flash by setting the Security Bit. "
1233 "This makes it impossible to read the Flash contents. "
1234 "The only way to undo this is to issue the chip-erase "
1235 "command.",
1236 },
1237 {
1238 .name = "eeprom",
1239 .usage = "[size_in_bytes]",
1240 .handler = samd_handle_eeprom_command,
1241 .mode = COMMAND_EXEC,
1242 .help = "Show or set the EEPROM size setting, stored in the User Row. "
1243 "Please see Table 20-3 of the SAMD20 datasheet for allowed values. "
1244 "Changes are stored immediately but take affect after the MCU is "
1245 "reset.",
1246 },
1247 {
1248 .name = "bootloader",
1249 .usage = "[size_in_bytes]",
1250 .handler = samd_handle_bootloader_command,
1251 .mode = COMMAND_EXEC,
1252 .help = "Show or set the bootloader size, stored in the User Row. "
1253 "Please see Table 20-2 of the SAMD20 datasheet for allowed values. "
1254 "Changes are stored immediately but take affect after the MCU is "
1255 "reset.",
1256 },
1257 {
1258 .name = "nvmuserrow",
1259 .usage = "[value] [mask]",
1260 .handler = samd_handle_nvmuserrow_command,
1261 .mode = COMMAND_EXEC,
1262 .help = "Show or set the nvmuserrow register. It is 64 bit wide "
1263 "and located at address 0x804000. Use the optional mask argument "
1264 "to prevent changes at positions where the bitvalue is zero. "
1265 "For security reasons the lock- and reserved-bits are masked out "
1266 "in background and therefore cannot be changed.",
1267 },
1268 COMMAND_REGISTRATION_DONE
1269 };
1270
1271 static const struct command_registration at91samd_command_handlers[] = {
1272 {
1273 .name = "at91samd",
1274 .mode = COMMAND_ANY,
1275 .help = "at91samd flash command group",
1276 .usage = "",
1277 .chain = at91samd_exec_command_handlers,
1278 },
1279 COMMAND_REGISTRATION_DONE
1280 };
1281
1282 struct flash_driver at91samd_flash = {
1283 .name = "at91samd",
1284 .commands = at91samd_command_handlers,
1285 .flash_bank_command = samd_flash_bank_command,
1286 .erase = samd_erase,
1287 .protect = samd_protect,
1288 .write = samd_write,
1289 .read = default_flash_read,
1290 .probe = samd_probe,
1291 .auto_probe = samd_probe,
1292 .erase_check = default_flash_blank_check,
1293 .protect_check = samd_protect_check,
1294 .free_driver_priv = default_flash_free_driver_priv,
1295 };