017d1441e9dd451120da34982689191f6bbf069a
[openocd.git] / src / flash / nor / at91samd.c
1 /***************************************************************************
2 * Copyright (C) 2013 by Andrey Yurovsky *
3 * Andrey Yurovsky <yurovsky@gmail.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18
19 #ifdef HAVE_CONFIG_H
20 #include "config.h"
21 #endif
22
23 #include "imp.h"
24 #include "helper/binarybuffer.h"
25
26 #include <target/cortex_m.h>
27
28 #define SAMD_NUM_PROT_BLOCKS 16
29 #define SAMD_PAGE_SIZE_MAX 1024
30
31 #define SAMD_FLASH ((uint32_t)0x00000000) /* physical Flash memory */
32 #define SAMD_USER_ROW ((uint32_t)0x00804000) /* User Row of Flash */
33 #define SAMD_PAC1 0x41000000 /* Peripheral Access Control 1 */
34 #define SAMD_DSU 0x41002000 /* Device Service Unit */
35 #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
36
37 #define SAMD_DSU_STATUSA 1 /* DSU status register */
38 #define SAMD_DSU_DID 0x18 /* Device ID register */
39 #define SAMD_DSU_CTRL_EXT 0x100 /* CTRL register, external access */
40
41 #define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
42 #define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
43 #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
44 #define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interupt Flag Status & Clear */
45 #define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
46 #define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
47 #define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
48
49 #define SAMD_CMDEX_KEY 0xA5UL
50 #define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
51
52 /* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */
53 #define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
54 #define SAMD_NVM_CMD_WP 0x04 /* Write Page */
55 #define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxilary Row */
56 #define SAMD_NVM_CMD_WAP 0x06 /* Write Auxilary Page */
57 #define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
58 #define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
59 #define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */
60 #define SAMD_NVM_CMD_CPRM 0x43 /* Clear Power Reduction Mode */
61 #define SAMD_NVM_CMD_PBC 0x44 /* Page Buffer Clear */
62 #define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */
63 #define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */
64
65 /* NVMCTRL bits */
66 #define SAMD_NVM_CTRLB_MANW 0x80
67
68 /* Known identifiers */
69 #define SAMD_PROCESSOR_M0 0x01
70 #define SAMD_FAMILY_D 0x00
71 #define SAMD_FAMILY_L 0x01
72 #define SAMD_FAMILY_C 0x02
73 #define SAMD_SERIES_20 0x00
74 #define SAMD_SERIES_21 0x01
75 #define SAMD_SERIES_22 0x02
76 #define SAMD_SERIES_10 0x02
77 #define SAMD_SERIES_11 0x03
78 #define SAMD_SERIES_09 0x04
79
80 /* Device ID macros */
81 #define SAMD_GET_PROCESSOR(id) (id >> 28)
82 #define SAMD_GET_FAMILY(id) (((id >> 23) & 0x1F))
83 #define SAMD_GET_SERIES(id) (((id >> 16) & 0x3F))
84 #define SAMD_GET_DEVSEL(id) (id & 0xFF)
85
86 /* Bits to mask out lockbits in user row */
87 #define NVMUSERROW_LOCKBIT_MASK ((uint64_t)0x0000FFFFFFFFFFFF)
88
89 struct samd_part {
90 uint8_t id;
91 const char *name;
92 uint32_t flash_kb;
93 uint32_t ram_kb;
94 };
95
96 /* Known SAMD09 parts. DID reset values missing in RM, see
97 * https://github.com/avrxml/asf/blob/master/sam0/utils/cmsis/samd09/include/ */
98 static const struct samd_part samd09_parts[] = {
99 { 0x0, "SAMD09D14A", 16, 4 },
100 { 0x7, "SAMD09C13A", 8, 4 },
101 };
102
103 /* Known SAMD10 parts */
104 static const struct samd_part samd10_parts[] = {
105 { 0x0, "SAMD10D14AMU", 16, 4 },
106 { 0x1, "SAMD10D13AMU", 8, 4 },
107 { 0x2, "SAMD10D12AMU", 4, 4 },
108 { 0x3, "SAMD10D14ASU", 16, 4 },
109 { 0x4, "SAMD10D13ASU", 8, 4 },
110 { 0x5, "SAMD10D12ASU", 4, 4 },
111 { 0x6, "SAMD10C14A", 16, 4 },
112 { 0x7, "SAMD10C13A", 8, 4 },
113 { 0x8, "SAMD10C12A", 4, 4 },
114 };
115
116 /* Known SAMD11 parts */
117 static const struct samd_part samd11_parts[] = {
118 { 0x0, "SAMD11D14AM", 16, 4 },
119 { 0x1, "SAMD11D13AMU", 8, 4 },
120 { 0x2, "SAMD11D12AMU", 4, 4 },
121 { 0x3, "SAMD11D14ASS", 16, 4 },
122 { 0x4, "SAMD11D13ASU", 8, 4 },
123 { 0x5, "SAMD11D12ASU", 4, 4 },
124 { 0x6, "SAMD11C14A", 16, 4 },
125 { 0x7, "SAMD11C13A", 8, 4 },
126 { 0x8, "SAMD11C12A", 4, 4 },
127 { 0x9, "SAMD11D14AU", 16, 4 },
128 };
129
130 /* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */
131 static const struct samd_part samd20_parts[] = {
132 { 0x0, "SAMD20J18A", 256, 32 },
133 { 0x1, "SAMD20J17A", 128, 16 },
134 { 0x2, "SAMD20J16A", 64, 8 },
135 { 0x3, "SAMD20J15A", 32, 4 },
136 { 0x4, "SAMD20J14A", 16, 2 },
137 { 0x5, "SAMD20G18A", 256, 32 },
138 { 0x6, "SAMD20G17A", 128, 16 },
139 { 0x7, "SAMD20G16A", 64, 8 },
140 { 0x8, "SAMD20G15A", 32, 4 },
141 { 0x9, "SAMD20G14A", 16, 2 },
142 { 0xA, "SAMD20E18A", 256, 32 },
143 { 0xB, "SAMD20E17A", 128, 16 },
144 { 0xC, "SAMD20E16A", 64, 8 },
145 { 0xD, "SAMD20E15A", 32, 4 },
146 { 0xE, "SAMD20E14A", 16, 2 },
147 };
148
149 /* Known SAMD21 parts. */
150 static const struct samd_part samd21_parts[] = {
151 { 0x0, "SAMD21J18A", 256, 32 },
152 { 0x1, "SAMD21J17A", 128, 16 },
153 { 0x2, "SAMD21J16A", 64, 8 },
154 { 0x3, "SAMD21J15A", 32, 4 },
155 { 0x4, "SAMD21J14A", 16, 2 },
156 { 0x5, "SAMD21G18A", 256, 32 },
157 { 0x6, "SAMD21G17A", 128, 16 },
158 { 0x7, "SAMD21G16A", 64, 8 },
159 { 0x8, "SAMD21G15A", 32, 4 },
160 { 0x9, "SAMD21G14A", 16, 2 },
161 { 0xA, "SAMD21E18A", 256, 32 },
162 { 0xB, "SAMD21E17A", 128, 16 },
163 { 0xC, "SAMD21E16A", 64, 8 },
164 { 0xD, "SAMD21E15A", 32, 4 },
165 { 0xE, "SAMD21E14A", 16, 2 },
166
167 /* SAMR21 parts have integrated SAMD21 with a radio */
168 { 0x19, "SAMR21G18A", 256, 32 },
169 { 0x1A, "SAMR21G17A", 128, 32 },
170 { 0x1B, "SAMR21G16A", 64, 32 },
171 { 0x1C, "SAMR21E18A", 256, 32 },
172 { 0x1D, "SAMR21E17A", 128, 32 },
173 { 0x1E, "SAMR21E16A", 64, 32 },
174
175 /* SAMD21 B Variants (Table 3-7 from rev I of datasheet) */
176 { 0x20, "SAMD21J16B", 64, 8 },
177 { 0x21, "SAMD21J15B", 32, 4 },
178 { 0x23, "SAMD21G16B", 64, 8 },
179 { 0x24, "SAMD21G15B", 32, 4 },
180 { 0x26, "SAMD21E16B", 64, 8 },
181 { 0x27, "SAMD21E15B", 32, 4 },
182 };
183
184 /* Known SAML21 parts. */
185 static const struct samd_part saml21_parts[] = {
186 { 0x00, "SAML21J18A", 256, 32 },
187 { 0x01, "SAML21J17A", 128, 16 },
188 { 0x02, "SAML21J16A", 64, 8 },
189 { 0x05, "SAML21G18A", 256, 32 },
190 { 0x06, "SAML21G17A", 128, 16 },
191 { 0x07, "SAML21G16A", 64, 8 },
192 { 0x0A, "SAML21E18A", 256, 32 },
193 { 0x0B, "SAML21E17A", 128, 16 },
194 { 0x0C, "SAML21E16A", 64, 8 },
195 { 0x0D, "SAML21E15A", 32, 4 },
196 { 0x0F, "SAML21J18B", 256, 32 },
197 { 0x10, "SAML21J17B", 128, 16 },
198 { 0x11, "SAML21J16B", 64, 8 },
199 { 0x14, "SAML21G18B", 256, 32 },
200 { 0x15, "SAML21G17B", 128, 16 },
201 { 0x16, "SAML21G16B", 64, 8 },
202 { 0x19, "SAML21E18B", 256, 32 },
203 { 0x1A, "SAML21E17B", 128, 16 },
204 { 0x1B, "SAML21E16B", 64, 8 },
205 { 0x1C, "SAML21E15B", 32, 4 },
206
207 /* SAMR30 parts have integrated SAML21 with a radio */
208 { 0x1E, "SAMR30G18A", 256, 32 },
209 { 0x1F, "SAMR30E18A", 256, 32 },
210 };
211
212 /* Known SAML22 parts. */
213 static const struct samd_part saml22_parts[] = {
214 { 0x00, "SAML22N18A", 256, 32 },
215 { 0x01, "SAML22N17A", 128, 16 },
216 { 0x02, "SAML22N16A", 64, 8 },
217 { 0x05, "SAML22J18A", 256, 32 },
218 { 0x06, "SAML22J17A", 128, 16 },
219 { 0x07, "SAML22J16A", 64, 8 },
220 { 0x0A, "SAML22G18A", 256, 32 },
221 { 0x0B, "SAML22G17A", 128, 16 },
222 { 0x0C, "SAML22G16A", 64, 8 },
223 };
224
225 /* Known SAMC20 parts. */
226 static const struct samd_part samc20_parts[] = {
227 { 0x00, "SAMC20J18A", 256, 32 },
228 { 0x01, "SAMC20J17A", 128, 16 },
229 { 0x02, "SAMC20J16A", 64, 8 },
230 { 0x03, "SAMC20J15A", 32, 4 },
231 { 0x05, "SAMC20G18A", 256, 32 },
232 { 0x06, "SAMC20G17A", 128, 16 },
233 { 0x07, "SAMC20G16A", 64, 8 },
234 { 0x08, "SAMC20G15A", 32, 4 },
235 { 0x0A, "SAMC20E18A", 256, 32 },
236 { 0x0B, "SAMC20E17A", 128, 16 },
237 { 0x0C, "SAMC20E16A", 64, 8 },
238 { 0x0D, "SAMC20E15A", 32, 4 },
239 };
240
241 /* Known SAMC21 parts. */
242 static const struct samd_part samc21_parts[] = {
243 { 0x00, "SAMC21J18A", 256, 32 },
244 { 0x01, "SAMC21J17A", 128, 16 },
245 { 0x02, "SAMC21J16A", 64, 8 },
246 { 0x03, "SAMC21J15A", 32, 4 },
247 { 0x05, "SAMC21G18A", 256, 32 },
248 { 0x06, "SAMC21G17A", 128, 16 },
249 { 0x07, "SAMC21G16A", 64, 8 },
250 { 0x08, "SAMC21G15A", 32, 4 },
251 { 0x0A, "SAMC21E18A", 256, 32 },
252 { 0x0B, "SAMC21E17A", 128, 16 },
253 { 0x0C, "SAMC21E16A", 64, 8 },
254 { 0x0D, "SAMC21E15A", 32, 4 },
255 };
256
257 /* Each family of parts contains a parts table in the DEVSEL field of DID. The
258 * processor ID, family ID, and series ID are used to determine which exact
259 * family this is and then we can use the corresponding table. */
260 struct samd_family {
261 uint8_t processor;
262 uint8_t family;
263 uint8_t series;
264 const struct samd_part *parts;
265 size_t num_parts;
266 uint64_t nvm_userrow_res_mask; /* protect bits which are reserved, 0 -> protect */
267 };
268
269 /* Known SAMD families */
270 static const struct samd_family samd_families[] = {
271 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_20,
272 samd20_parts, ARRAY_SIZE(samd20_parts),
273 (uint64_t)0xFFFF01FFFE01FF77 },
274 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
275 samd21_parts, ARRAY_SIZE(samd21_parts),
276 (uint64_t)0xFFFF01FFFE01FF77 },
277 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_09,
278 samd09_parts, ARRAY_SIZE(samd09_parts),
279 (uint64_t)0xFFFF01FFFE01FF77 },
280 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_10,
281 samd10_parts, ARRAY_SIZE(samd10_parts),
282 (uint64_t)0xFFFF01FFFE01FF77 },
283 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11,
284 samd11_parts, ARRAY_SIZE(samd11_parts),
285 (uint64_t)0xFFFF01FFFE01FF77 },
286 { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_21,
287 saml21_parts, ARRAY_SIZE(saml21_parts),
288 (uint64_t)0xFFFF03FFFC01FF77 },
289 { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_22,
290 saml22_parts, ARRAY_SIZE(saml22_parts),
291 (uint64_t)0xFFFF03FFFC01FF77 },
292 { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_20,
293 samc20_parts, ARRAY_SIZE(samc20_parts),
294 (uint64_t)0xFFFF03FFFC01FF77 },
295 { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_21,
296 samc21_parts, ARRAY_SIZE(samc21_parts),
297 (uint64_t)0xFFFF03FFFC01FF77 },
298 };
299
300 struct samd_info {
301 uint32_t page_size;
302 int num_pages;
303 int sector_size;
304 int prot_block_size;
305
306 bool probed;
307 struct target *target;
308 };
309
310
311 /**
312 * Gives the family structure to specific device id.
313 * @param id The id of the device.
314 * @return On failure NULL, otherwise a pointer to the structure.
315 */
316 static const struct samd_family *samd_find_family(uint32_t id)
317 {
318 uint8_t processor = SAMD_GET_PROCESSOR(id);
319 uint8_t family = SAMD_GET_FAMILY(id);
320 uint8_t series = SAMD_GET_SERIES(id);
321
322 for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) {
323 if (samd_families[i].processor == processor &&
324 samd_families[i].series == series &&
325 samd_families[i].family == family)
326 return &samd_families[i];
327 }
328
329 return NULL;
330 }
331
332 /**
333 * Gives the part structure to specific device id.
334 * @param id The id of the device.
335 * @return On failure NULL, otherwise a pointer to the structure.
336 */
337 static const struct samd_part *samd_find_part(uint32_t id)
338 {
339 uint8_t devsel = SAMD_GET_DEVSEL(id);
340 const struct samd_family *family = samd_find_family(id);
341 if (family == NULL)
342 return NULL;
343
344 for (unsigned i = 0; i < family->num_parts; i++) {
345 if (family->parts[i].id == devsel)
346 return &family->parts[i];
347 }
348
349 return NULL;
350 }
351
352 static int samd_protect_check(struct flash_bank *bank)
353 {
354 int res, prot_block;
355 uint16_t lock;
356
357 res = target_read_u16(bank->target,
358 SAMD_NVMCTRL + SAMD_NVMCTRL_LOCK, &lock);
359 if (res != ERROR_OK)
360 return res;
361
362 /* Lock bits are active-low */
363 for (prot_block = 0; prot_block < bank->num_prot_blocks; prot_block++)
364 bank->prot_blocks[prot_block].is_protected = !(lock & (1u<<prot_block));
365
366 return ERROR_OK;
367 }
368
369 static int samd_get_flash_page_info(struct target *target,
370 uint32_t *sizep, int *nump)
371 {
372 int res;
373 uint32_t param;
374
375 res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, &param);
376 if (res == ERROR_OK) {
377 /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n)
378 * so 0 is 8KB and 7 is 1024KB. */
379 if (sizep)
380 *sizep = (8 << ((param >> 16) & 0x7));
381 /* The NVMP field (bits 15:0) indicates the total number of pages */
382 if (nump)
383 *nump = param & 0xFFFF;
384 } else {
385 LOG_ERROR("Couldn't read NVM Parameters register");
386 }
387
388 return res;
389 }
390
391 static int samd_probe(struct flash_bank *bank)
392 {
393 uint32_t id;
394 int res;
395 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
396 const struct samd_part *part;
397
398 if (chip->probed)
399 return ERROR_OK;
400
401 res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
402 if (res != ERROR_OK) {
403 LOG_ERROR("Couldn't read Device ID register");
404 return res;
405 }
406
407 part = samd_find_part(id);
408 if (part == NULL) {
409 LOG_ERROR("Couldn't find part corresponding to DID %08" PRIx32, id);
410 return ERROR_FAIL;
411 }
412
413 bank->size = part->flash_kb * 1024;
414
415 res = samd_get_flash_page_info(bank->target, &chip->page_size,
416 &chip->num_pages);
417 if (res != ERROR_OK) {
418 LOG_ERROR("Couldn't determine Flash page size");
419 return res;
420 }
421
422 /* Sanity check: the total flash size in the DSU should match the page size
423 * multiplied by the number of pages. */
424 if (bank->size != chip->num_pages * chip->page_size) {
425 LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
426 "Identified %" PRIu32 "KB Flash but NVMCTRL reports %u %" PRIu32 "B pages",
427 part->flash_kb, chip->num_pages, chip->page_size);
428 }
429
430 /* Erase granularity = 1 row = 4 pages */
431 chip->sector_size = chip->page_size * 4;
432
433 /* Allocate the sector table */
434 bank->num_sectors = chip->num_pages / 4;
435 bank->sectors = alloc_block_array(0, chip->sector_size, bank->num_sectors);
436 if (!bank->sectors)
437 return ERROR_FAIL;
438
439 /* 16 protection blocks per device */
440 chip->prot_block_size = bank->size / SAMD_NUM_PROT_BLOCKS;
441
442 /* Allocate the table of protection blocks */
443 bank->num_prot_blocks = SAMD_NUM_PROT_BLOCKS;
444 bank->prot_blocks = alloc_block_array(0, chip->prot_block_size, bank->num_prot_blocks);
445 if (!bank->prot_blocks)
446 return ERROR_FAIL;
447
448 samd_protect_check(bank);
449
450 /* Done */
451 chip->probed = true;
452
453 LOG_INFO("SAMD MCU: %s (%" PRIu32 "KB Flash, %" PRIu32 "KB RAM)", part->name,
454 part->flash_kb, part->ram_kb);
455
456 return ERROR_OK;
457 }
458
459 static int samd_check_error(struct target *target)
460 {
461 int ret, ret2;
462 uint16_t status;
463
464 ret = target_read_u16(target,
465 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status);
466 if (ret != ERROR_OK) {
467 LOG_ERROR("Can't read NVM status");
468 return ret;
469 }
470
471 if ((status & 0x001C) == 0)
472 return ERROR_OK;
473
474 if (status & (1 << 4)) { /* NVME */
475 LOG_ERROR("SAMD: NVM Error");
476 ret = ERROR_FLASH_OPERATION_FAILED;
477 }
478
479 if (status & (1 << 3)) { /* LOCKE */
480 LOG_ERROR("SAMD: NVM lock error");
481 ret = ERROR_FLASH_PROTECTED;
482 }
483
484 if (status & (1 << 2)) { /* PROGE */
485 LOG_ERROR("SAMD: NVM programming error");
486 ret = ERROR_FLASH_OPER_UNSUPPORTED;
487 }
488
489 /* Clear the error conditions by writing a one to them */
490 ret2 = target_write_u16(target,
491 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, status);
492 if (ret2 != ERROR_OK)
493 LOG_ERROR("Can't clear NVM error conditions");
494
495 return ret;
496 }
497
498 static int samd_issue_nvmctrl_command(struct target *target, uint16_t cmd)
499 {
500 int res;
501
502 if (target->state != TARGET_HALTED) {
503 LOG_ERROR("Target not halted");
504 return ERROR_TARGET_NOT_HALTED;
505 }
506
507 /* Issue the NVM command */
508 res = target_write_u16(target,
509 SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, SAMD_NVM_CMD(cmd));
510 if (res != ERROR_OK)
511 return res;
512
513 /* Check to see if the NVM command resulted in an error condition. */
514 return samd_check_error(target);
515 }
516
517 /**
518 * Erases a flash-row at the given address.
519 * @param target Pointer to the target structure.
520 * @param address The address of the row.
521 * @return On success ERROR_OK, on failure an errorcode.
522 */
523 static int samd_erase_row(struct target *target, uint32_t address)
524 {
525 int res;
526
527 /* Set an address contained in the row to be erased */
528 res = target_write_u32(target,
529 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, address >> 1);
530
531 /* Issue the Erase Row command to erase that row. */
532 if (res == ERROR_OK)
533 res = samd_issue_nvmctrl_command(target,
534 address == SAMD_USER_ROW ? SAMD_NVM_CMD_EAR : SAMD_NVM_CMD_ER);
535
536 if (res != ERROR_OK) {
537 LOG_ERROR("Failed to erase row containing %08" PRIx32, address);
538 return ERROR_FAIL;
539 }
540
541 return ERROR_OK;
542 }
543
544 /**
545 * Returns the bitmask of reserved bits in register.
546 * @param target Pointer to the target structure.
547 * @param mask Bitmask, 0 -> value stays untouched.
548 * @return On success ERROR_OK, on failure an errorcode.
549 */
550 static int samd_get_reservedmask(struct target *target, uint64_t *mask)
551 {
552 int res;
553 /* Get the devicetype */
554 uint32_t id;
555 res = target_read_u32(target, SAMD_DSU + SAMD_DSU_DID, &id);
556 if (res != ERROR_OK) {
557 LOG_ERROR("Couldn't read Device ID register");
558 return res;
559 }
560 const struct samd_family *family;
561 family = samd_find_family(id);
562 if (family == NULL) {
563 LOG_ERROR("Couldn't determine device family");
564 return ERROR_FAIL;
565 }
566 *mask = family->nvm_userrow_res_mask;
567 return ERROR_OK;
568 }
569
570 static int read_userrow(struct target *target, uint64_t *userrow)
571 {
572 int res;
573 uint8_t buffer[8];
574
575 res = target_read_memory(target, SAMD_USER_ROW, 4, 2, buffer);
576 if (res != ERROR_OK)
577 return res;
578
579 *userrow = target_buffer_get_u64(target, buffer);
580 return ERROR_OK;
581 }
582
583 /**
584 * Modify the contents of the User Row in Flash. The User Row itself
585 * has a size of one page and contains a combination of "fuses" and
586 * calibration data. Bits which have a value of zero in the mask will
587 * not be changed. Up to now devices only use the first 64 bits.
588 * @param target Pointer to the target structure.
589 * @param value_input The value to write.
590 * @param value_mask Bitmask, 0 -> value stays untouched.
591 * @return On success ERROR_OK, on failure an errorcode.
592 */
593 static int samd_modify_user_row_masked(struct target *target,
594 uint64_t value_input, uint64_t value_mask)
595 {
596 int res;
597 uint32_t nvm_ctrlb;
598 bool manual_wp = true;
599
600 /* Retrieve the MCU's page size, in bytes. This is also the size of the
601 * entire User Row. */
602 uint32_t page_size;
603 res = samd_get_flash_page_info(target, &page_size, NULL);
604 if (res != ERROR_OK) {
605 LOG_ERROR("Couldn't determine Flash page size");
606 return res;
607 }
608
609 /* Make sure the size is sane. */
610 assert(page_size <= SAMD_PAGE_SIZE_MAX &&
611 page_size >= sizeof(value_input));
612
613 uint8_t buf[SAMD_PAGE_SIZE_MAX];
614 /* Read the user row (comprising one page) by words. */
615 res = target_read_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
616 if (res != ERROR_OK)
617 return res;
618
619 uint64_t value_device;
620 res = read_userrow(target, &value_device);
621 if (res != ERROR_OK)
622 return res;
623 uint64_t value_new = (value_input & value_mask) | (value_device & ~value_mask);
624
625 /* We will need to erase before writing if the new value needs a '1' in any
626 * position for which the current value had a '0'. Otherwise we can avoid
627 * erasing. */
628 if ((~value_device) & value_new) {
629 res = samd_erase_row(target, SAMD_USER_ROW);
630 if (res != ERROR_OK) {
631 LOG_ERROR("Couldn't erase user row");
632 return res;
633 }
634 }
635
636 /* Modify */
637 target_buffer_set_u64(target, buf, value_new);
638
639 /* Write the page buffer back out to the target. */
640 res = target_write_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
641 if (res != ERROR_OK)
642 return res;
643
644 /* Check if we need to do manual page write commands */
645 res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
646 if (res == ERROR_OK)
647 manual_wp = (nvm_ctrlb & SAMD_NVM_CTRLB_MANW) != 0;
648 else {
649 LOG_ERROR("Read of NVM register CTRKB failed.");
650 return ERROR_FAIL;
651 }
652 if (manual_wp) {
653 /* Trigger flash write */
654 res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_WAP);
655 } else {
656 res = samd_check_error(target);
657 }
658
659 return res;
660 }
661
662 /**
663 * Modifies the user row register to the given value.
664 * @param target Pointer to the target structure.
665 * @param value The value to write.
666 * @param startb The bit-offset by which the given value is shifted.
667 * @param endb The bit-offset of the last bit in value to write.
668 * @return On success ERROR_OK, on failure an errorcode.
669 */
670 static int samd_modify_user_row(struct target *target, uint64_t value,
671 uint8_t startb, uint8_t endb)
672 {
673 uint64_t mask = 0;
674 int i;
675 for (i = startb ; i <= endb ; i++)
676 mask |= ((uint64_t)1) << i;
677
678 return samd_modify_user_row_masked(target, value << startb, mask);
679 }
680
681 static int samd_protect(struct flash_bank *bank, int set, int first_prot_bl, int last_prot_bl)
682 {
683 int res = ERROR_OK;
684 int prot_block;
685
686 /* We can issue lock/unlock region commands with the target running but
687 * the settings won't persist unless we're able to modify the LOCK regions
688 * and that requires the target to be halted. */
689 if (bank->target->state != TARGET_HALTED) {
690 LOG_ERROR("Target not halted");
691 return ERROR_TARGET_NOT_HALTED;
692 }
693
694 for (prot_block = first_prot_bl; prot_block <= last_prot_bl; prot_block++) {
695 if (set != bank->prot_blocks[prot_block].is_protected) {
696 /* Load an address that is within this protection block (we use offset 0) */
697 res = target_write_u32(bank->target,
698 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR,
699 bank->prot_blocks[prot_block].offset >> 1);
700 if (res != ERROR_OK)
701 goto exit;
702
703 /* Tell the controller to lock that block */
704 res = samd_issue_nvmctrl_command(bank->target,
705 set ? SAMD_NVM_CMD_LR : SAMD_NVM_CMD_UR);
706 if (res != ERROR_OK)
707 goto exit;
708 }
709 }
710
711 /* We've now applied our changes, however they will be undone by the next
712 * reset unless we also apply them to the LOCK bits in the User Page. The
713 * LOCK bits start at bit 48, corresponding to Sector 0 and end with bit 63,
714 * corresponding to Sector 15. A '1' means unlocked and a '0' means
715 * locked. See Table 9-3 in the SAMD20 datasheet for more details. */
716
717 res = samd_modify_user_row(bank->target,
718 set ? (uint64_t)0 : (uint64_t)UINT64_MAX,
719 48 + first_prot_bl, 48 + last_prot_bl);
720 if (res != ERROR_OK)
721 LOG_WARNING("SAMD: protect settings were not made persistent!");
722
723 res = ERROR_OK;
724
725 exit:
726 samd_protect_check(bank);
727
728 return res;
729 }
730
731 static int samd_erase(struct flash_bank *bank, int first_sect, int last_sect)
732 {
733 int res, s;
734 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
735
736 if (bank->target->state != TARGET_HALTED) {
737 LOG_ERROR("Target not halted");
738
739 return ERROR_TARGET_NOT_HALTED;
740 }
741
742 if (!chip->probed) {
743 if (samd_probe(bank) != ERROR_OK)
744 return ERROR_FLASH_BANK_NOT_PROBED;
745 }
746
747 /* For each sector to be erased */
748 for (s = first_sect; s <= last_sect; s++) {
749 res = samd_erase_row(bank->target, bank->sectors[s].offset);
750 if (res != ERROR_OK) {
751 LOG_ERROR("SAMD: failed to erase sector %d at 0x%08" PRIx32, s, bank->sectors[s].offset);
752 return res;
753 }
754 }
755
756 return ERROR_OK;
757 }
758
759
760 static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
761 uint32_t offset, uint32_t count)
762 {
763 int res;
764 uint32_t nvm_ctrlb;
765 uint32_t address;
766 uint32_t pg_offset;
767 uint32_t nb;
768 uint32_t nw;
769 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
770 uint8_t *pb = NULL;
771 bool manual_wp;
772
773 if (bank->target->state != TARGET_HALTED) {
774 LOG_ERROR("Target not halted");
775 return ERROR_TARGET_NOT_HALTED;
776 }
777
778 if (!chip->probed) {
779 if (samd_probe(bank) != ERROR_OK)
780 return ERROR_FLASH_BANK_NOT_PROBED;
781 }
782
783 /* Check if we need to do manual page write commands */
784 res = target_read_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
785
786 if (res != ERROR_OK)
787 return res;
788
789 if (nvm_ctrlb & SAMD_NVM_CTRLB_MANW)
790 manual_wp = true;
791 else
792 manual_wp = false;
793
794 res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_PBC);
795 if (res != ERROR_OK) {
796 LOG_ERROR("%s: %d", __func__, __LINE__);
797 return res;
798 }
799
800 while (count) {
801 nb = chip->page_size - offset % chip->page_size;
802 if (count < nb)
803 nb = count;
804
805 address = bank->base + offset;
806 pg_offset = offset % chip->page_size;
807
808 if (offset % 4 || (offset + nb) % 4) {
809 /* Either start or end of write is not word aligned */
810 if (!pb) {
811 pb = malloc(chip->page_size);
812 if (!pb)
813 return ERROR_FAIL;
814 }
815
816 /* Set temporary page buffer to 0xff and overwrite the relevant part */
817 memset(pb, 0xff, chip->page_size);
818 memcpy(pb + pg_offset, buffer, nb);
819
820 /* Align start address to a word boundary */
821 address -= offset % 4;
822 pg_offset -= offset % 4;
823 assert(pg_offset % 4 == 0);
824
825 /* Extend length to whole words */
826 nw = (nb + offset % 4 + 3) / 4;
827 assert(pg_offset + 4 * nw <= chip->page_size);
828
829 /* Now we have original data extended by 0xff bytes
830 * to the nearest word boundary on both start and end */
831 res = target_write_memory(bank->target, address, 4, nw, pb + pg_offset);
832 } else {
833 assert(nb % 4 == 0);
834 nw = nb / 4;
835 assert(pg_offset + 4 * nw <= chip->page_size);
836
837 /* Word aligned data, use direct write from buffer */
838 res = target_write_memory(bank->target, address, 4, nw, buffer);
839 }
840 if (res != ERROR_OK) {
841 LOG_ERROR("%s: %d", __func__, __LINE__);
842 goto free_pb;
843 }
844
845 /* Devices with errata 13134 have automatic page write enabled by default
846 * For other devices issue a write page CMD to the NVM
847 * If the page has not been written up to the last word
848 * then issue CMD_WP always */
849 if (manual_wp || pg_offset + 4 * nw < chip->page_size) {
850 res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_WP);
851 } else {
852 /* Access through AHB is stalled while flash is being programmed */
853 usleep(200);
854
855 res = samd_check_error(bank->target);
856 }
857
858 if (res != ERROR_OK) {
859 LOG_ERROR("%s: write failed at address 0x%08" PRIx32, __func__, address);
860 goto free_pb;
861 }
862
863 /* We're done with the page contents */
864 count -= nb;
865 offset += nb;
866 buffer += nb;
867 }
868
869 free_pb:
870 if (pb)
871 free(pb);
872
873 return res;
874 }
875
876 FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
877 {
878 if (bank->base != SAMD_FLASH) {
879 LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
880 "[at91samd series] )",
881 bank->base, SAMD_FLASH);
882 return ERROR_FAIL;
883 }
884
885 struct samd_info *chip;
886 chip = calloc(1, sizeof(*chip));
887 if (!chip) {
888 LOG_ERROR("No memory for flash bank chip info");
889 return ERROR_FAIL;
890 }
891
892 chip->target = bank->target;
893 chip->probed = false;
894
895 bank->driver_priv = chip;
896
897 return ERROR_OK;
898 }
899
900 COMMAND_HANDLER(samd_handle_info_command)
901 {
902 return ERROR_OK;
903 }
904
905 COMMAND_HANDLER(samd_handle_chip_erase_command)
906 {
907 struct target *target = get_current_target(CMD_CTX);
908 int res = ERROR_FAIL;
909
910 if (target) {
911 /* Enable access to the DSU by disabling the write protect bit */
912 target_write_u32(target, SAMD_PAC1, (1<<1));
913 /* intentionally without error checking - not accessible on secured chip */
914
915 /* Tell the DSU to perform a full chip erase. It takes about 240ms to
916 * perform the erase. */
917 res = target_write_u8(target, SAMD_DSU + SAMD_DSU_CTRL_EXT, (1<<4));
918 if (res == ERROR_OK)
919 command_print(CMD_CTX, "chip erase started");
920 else
921 command_print(CMD_CTX, "write to DSU CTRL failed");
922 }
923
924 return res;
925 }
926
927 COMMAND_HANDLER(samd_handle_set_security_command)
928 {
929 int res = ERROR_OK;
930 struct target *target = get_current_target(CMD_CTX);
931
932 if (CMD_ARGC < 1 || (CMD_ARGC >= 1 && (strcmp(CMD_ARGV[0], "enable")))) {
933 command_print(CMD_CTX, "supply the \"enable\" argument to proceed.");
934 return ERROR_COMMAND_SYNTAX_ERROR;
935 }
936
937 if (target) {
938 if (target->state != TARGET_HALTED) {
939 LOG_ERROR("Target not halted");
940 return ERROR_TARGET_NOT_HALTED;
941 }
942
943 res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_SSB);
944
945 /* Check (and clear) error conditions */
946 if (res == ERROR_OK)
947 command_print(CMD_CTX, "chip secured on next power-cycle");
948 else
949 command_print(CMD_CTX, "failed to secure chip");
950 }
951
952 return res;
953 }
954
955 COMMAND_HANDLER(samd_handle_eeprom_command)
956 {
957 int res = ERROR_OK;
958 struct target *target = get_current_target(CMD_CTX);
959
960 if (target) {
961 if (target->state != TARGET_HALTED) {
962 LOG_ERROR("Target not halted");
963 return ERROR_TARGET_NOT_HALTED;
964 }
965
966 if (CMD_ARGC >= 1) {
967 int val = atoi(CMD_ARGV[0]);
968 uint32_t code;
969
970 if (val == 0)
971 code = 7;
972 else {
973 /* Try to match size in bytes with corresponding size code */
974 for (code = 0; code <= 6; code++) {
975 if (val == (2 << (13 - code)))
976 break;
977 }
978
979 if (code > 6) {
980 command_print(CMD_CTX, "Invalid EEPROM size. Please see "
981 "datasheet for a list valid sizes.");
982 return ERROR_COMMAND_SYNTAX_ERROR;
983 }
984 }
985
986 res = samd_modify_user_row(target, code, 4, 6);
987 } else {
988 uint16_t val;
989 res = target_read_u16(target, SAMD_USER_ROW, &val);
990 if (res == ERROR_OK) {
991 uint32_t size = ((val >> 4) & 0x7); /* grab size code */
992
993 if (size == 0x7)
994 command_print(CMD_CTX, "EEPROM is disabled");
995 else {
996 /* Otherwise, 6 is 256B, 0 is 16KB */
997 command_print(CMD_CTX, "EEPROM size is %u bytes",
998 (2 << (13 - size)));
999 }
1000 }
1001 }
1002 }
1003
1004 return res;
1005 }
1006
1007 static COMMAND_HELPER(get_u64_from_hexarg, unsigned int num, uint64_t *value)
1008 {
1009 if (num >= CMD_ARGC) {
1010 command_print(CMD_CTX, "Too few Arguments.");
1011 return ERROR_COMMAND_SYNTAX_ERROR;
1012 }
1013
1014 if (strlen(CMD_ARGV[num]) >= 3 &&
1015 CMD_ARGV[num][0] == '0' &&
1016 CMD_ARGV[num][1] == 'x') {
1017 char *check = NULL;
1018 *value = strtoull(&(CMD_ARGV[num][2]), &check, 16);
1019 if ((value == 0 && errno == ERANGE) ||
1020 check == NULL || *check != 0) {
1021 command_print(CMD_CTX, "Invalid 64-bit hex value in argument %d.",
1022 num + 1);
1023 return ERROR_COMMAND_SYNTAX_ERROR;
1024 }
1025 } else {
1026 command_print(CMD_CTX, "Argument %d needs to be a hex value.", num + 1);
1027 return ERROR_COMMAND_SYNTAX_ERROR;
1028 }
1029 return ERROR_OK;
1030 }
1031
1032 COMMAND_HANDLER(samd_handle_nvmuserrow_command)
1033 {
1034 int res = ERROR_OK;
1035 struct target *target = get_current_target(CMD_CTX);
1036
1037 if (target) {
1038 if (CMD_ARGC > 2) {
1039 command_print(CMD_CTX, "Too much Arguments given.");
1040 return ERROR_COMMAND_SYNTAX_ERROR;
1041 }
1042
1043 if (CMD_ARGC > 0) {
1044 if (target->state != TARGET_HALTED) {
1045 LOG_ERROR("Target not halted.");
1046 return ERROR_TARGET_NOT_HALTED;
1047 }
1048
1049 uint64_t mask;
1050 res = samd_get_reservedmask(target, &mask);
1051 if (res != ERROR_OK) {
1052 LOG_ERROR("Couldn't determine the mask for reserved bits.");
1053 return ERROR_FAIL;
1054 }
1055 mask &= NVMUSERROW_LOCKBIT_MASK;
1056
1057 uint64_t value;
1058 res = CALL_COMMAND_HANDLER(get_u64_from_hexarg, 0, &value);
1059 if (res != ERROR_OK)
1060 return res;
1061 if (CMD_ARGC == 2) {
1062 uint64_t mask_temp;
1063 res = CALL_COMMAND_HANDLER(get_u64_from_hexarg, 1, &mask_temp);
1064 if (res != ERROR_OK)
1065 return res;
1066 mask &= mask_temp;
1067 }
1068 res = samd_modify_user_row_masked(target, value, mask);
1069 if (res != ERROR_OK)
1070 return res;
1071 }
1072
1073 /* read register */
1074 uint64_t value;
1075 res = read_userrow(target, &value);
1076 if (res == ERROR_OK)
1077 command_print(CMD_CTX, "NVMUSERROW: 0x%016"PRIX64, value);
1078 else
1079 LOG_ERROR("NVMUSERROW could not be read.");
1080 }
1081 return res;
1082 }
1083
1084 COMMAND_HANDLER(samd_handle_bootloader_command)
1085 {
1086 int res = ERROR_OK;
1087 struct target *target = get_current_target(CMD_CTX);
1088
1089 if (target) {
1090 if (target->state != TARGET_HALTED) {
1091 LOG_ERROR("Target not halted");
1092 return ERROR_TARGET_NOT_HALTED;
1093 }
1094
1095 /* Retrieve the MCU's page size, in bytes. */
1096 uint32_t page_size;
1097 res = samd_get_flash_page_info(target, &page_size, NULL);
1098 if (res != ERROR_OK) {
1099 LOG_ERROR("Couldn't determine Flash page size");
1100 return res;
1101 }
1102
1103 if (CMD_ARGC >= 1) {
1104 int val = atoi(CMD_ARGV[0]);
1105 uint32_t code;
1106
1107 if (val == 0)
1108 code = 7;
1109 else {
1110 /* Try to match size in bytes with corresponding size code */
1111 for (code = 0; code <= 6; code++) {
1112 if ((unsigned int)val == (2UL << (8UL - code)) * page_size)
1113 break;
1114 }
1115
1116 if (code > 6) {
1117 command_print(CMD_CTX, "Invalid bootloader size. Please "
1118 "see datasheet for a list valid sizes.");
1119 return ERROR_COMMAND_SYNTAX_ERROR;
1120 }
1121
1122 }
1123
1124 res = samd_modify_user_row(target, code, 0, 2);
1125 } else {
1126 uint16_t val;
1127 res = target_read_u16(target, SAMD_USER_ROW, &val);
1128 if (res == ERROR_OK) {
1129 uint32_t size = (val & 0x7); /* grab size code */
1130 uint32_t nb;
1131
1132 if (size == 0x7)
1133 nb = 0;
1134 else
1135 nb = (2 << (8 - size)) * page_size;
1136
1137 /* There are 4 pages per row */
1138 command_print(CMD_CTX, "Bootloader size is %" PRIu32 " bytes (%" PRIu32 " rows)",
1139 nb, (uint32_t)(nb / (page_size * 4)));
1140 }
1141 }
1142 }
1143
1144 return res;
1145 }
1146
1147
1148
1149 COMMAND_HANDLER(samd_handle_reset_deassert)
1150 {
1151 struct target *target = get_current_target(CMD_CTX);
1152 int retval = ERROR_OK;
1153 enum reset_types jtag_reset_config = jtag_get_reset_config();
1154
1155 /* If the target has been unresponsive before, try to re-establish
1156 * communication now - CPU is held in reset by DSU, DAP is working */
1157 if (!target_was_examined(target))
1158 target_examine_one(target);
1159 target_poll(target);
1160
1161 /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
1162 * so we just release reset held by DSU
1163 *
1164 * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
1165 *
1166 * After vectreset DSU release is not needed however makes no harm
1167 */
1168 if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
1169 retval = target_write_u32(target, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
1170 if (retval == ERROR_OK)
1171 retval = target_write_u32(target, DCB_DEMCR,
1172 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1173 /* do not return on error here, releasing DSU reset is more important */
1174 }
1175
1176 /* clear CPU Reset Phase Extension bit */
1177 int retval2 = target_write_u8(target, SAMD_DSU + SAMD_DSU_STATUSA, (1<<1));
1178 if (retval2 != ERROR_OK)
1179 return retval2;
1180
1181 return retval;
1182 }
1183
1184 static const struct command_registration at91samd_exec_command_handlers[] = {
1185 {
1186 .name = "dsu_reset_deassert",
1187 .handler = samd_handle_reset_deassert,
1188 .mode = COMMAND_EXEC,
1189 .help = "Deasert internal reset held by DSU."
1190 },
1191 {
1192 .name = "info",
1193 .handler = samd_handle_info_command,
1194 .mode = COMMAND_EXEC,
1195 .help = "Print information about the current at91samd chip "
1196 "and its flash configuration.",
1197 },
1198 {
1199 .name = "chip-erase",
1200 .handler = samd_handle_chip_erase_command,
1201 .mode = COMMAND_EXEC,
1202 .help = "Erase the entire Flash by using the Chip-"
1203 "Erase feature in the Device Service Unit (DSU).",
1204 },
1205 {
1206 .name = "set-security",
1207 .handler = samd_handle_set_security_command,
1208 .mode = COMMAND_EXEC,
1209 .help = "Secure the chip's Flash by setting the Security Bit. "
1210 "This makes it impossible to read the Flash contents. "
1211 "The only way to undo this is to issue the chip-erase "
1212 "command.",
1213 },
1214 {
1215 .name = "eeprom",
1216 .usage = "[size_in_bytes]",
1217 .handler = samd_handle_eeprom_command,
1218 .mode = COMMAND_EXEC,
1219 .help = "Show or set the EEPROM size setting, stored in the User Row. "
1220 "Please see Table 20-3 of the SAMD20 datasheet for allowed values. "
1221 "Changes are stored immediately but take affect after the MCU is "
1222 "reset.",
1223 },
1224 {
1225 .name = "bootloader",
1226 .usage = "[size_in_bytes]",
1227 .handler = samd_handle_bootloader_command,
1228 .mode = COMMAND_EXEC,
1229 .help = "Show or set the bootloader size, stored in the User Row. "
1230 "Please see Table 20-2 of the SAMD20 datasheet for allowed values. "
1231 "Changes are stored immediately but take affect after the MCU is "
1232 "reset.",
1233 },
1234 {
1235 .name = "nvmuserrow",
1236 .usage = "[value] [mask]",
1237 .handler = samd_handle_nvmuserrow_command,
1238 .mode = COMMAND_EXEC,
1239 .help = "Show or set the nvmuserrow register. It is 64 bit wide "
1240 "and located at address 0x804000. Use the optional mask argument "
1241 "to prevent changes at positions where the bitvalue is zero. "
1242 "For security reasons the lock- and reserved-bits are masked out "
1243 "in background and therefore cannot be changed.",
1244 },
1245 COMMAND_REGISTRATION_DONE
1246 };
1247
1248 static const struct command_registration at91samd_command_handlers[] = {
1249 {
1250 .name = "at91samd",
1251 .mode = COMMAND_ANY,
1252 .help = "at91samd flash command group",
1253 .usage = "",
1254 .chain = at91samd_exec_command_handlers,
1255 },
1256 COMMAND_REGISTRATION_DONE
1257 };
1258
1259 struct flash_driver at91samd_flash = {
1260 .name = "at91samd",
1261 .commands = at91samd_command_handlers,
1262 .flash_bank_command = samd_flash_bank_command,
1263 .erase = samd_erase,
1264 .protect = samd_protect,
1265 .write = samd_write,
1266 .read = default_flash_read,
1267 .probe = samd_probe,
1268 .auto_probe = samd_probe,
1269 .erase_check = default_flash_blank_check,
1270 .protect_check = samd_protect_check,
1271 .free_driver_priv = default_flash_free_driver_priv,
1272 };