1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-Source-Code)
4 * Copyright (C) 2009 by Duane Ellis <openocd@duaneellis.com>
7 * Copyright (C) 2010 by Olaf Lüke <olaf@uni-paderborn.de>
9 * at91sam3x* & at91sam4 support
10 * Copyright (C) 2011 by Olivier Schonken, Jim Norris
12 * Some of the lower level code was based on code supplied by
13 * ATMEL under BSD-Source-Code License and this copyright.
14 * ATMEL Microcontroller Software Support
15 * Copyright (c) 2009, Atmel Corporation. All rights reserved.
23 #include <helper/time_support.h>
25 #define REG_NAME_WIDTH (12)
27 /* at91sam4s/at91sam4e/at91sam4c series (has always one flash bank)*/
28 #define FLASH_BANK_BASE_S 0x00400000
29 #define FLASH_BANK_BASE_C 0x01000000
31 /* at91sam4sd series (two one flash banks), first bank address */
32 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
33 /* at91sam4sd16x, second bank address */
34 #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
35 /* at91sam4sd32x, second bank address */
36 #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
38 /* at91sam4c32x, first and second bank address */
39 #define FLASH_BANK0_BASE_C32 FLASH_BANK_BASE_C
40 #define FLASH_BANK1_BASE_C32 (FLASH_BANK_BASE_C+(2048*1024/2))
42 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
43 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
44 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
45 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
46 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
47 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
48 /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
49 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
50 #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
51 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
52 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
53 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
54 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
55 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
56 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
57 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
58 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
60 #define OFFSET_EFC_FMR 0
61 #define OFFSET_EFC_FCR 4
62 #define OFFSET_EFC_FSR 8
63 #define OFFSET_EFC_FRR 12
65 static float _tomhz(uint32_t freq_hz
)
69 f
= ((float)(freq_hz
)) / 1000000.0;
73 /* How the chip is configured. */
75 uint32_t unique_id
[4];
79 uint32_t mainosc_freq
;
89 #define SAM4_CHIPID_CIDR (0x400E0740)
91 #define SAM4_CHIPID_EXID (0x400E0744)
94 #define SAM4_PMC_BASE (0x400E0400)
95 #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
97 #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
99 #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
101 #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
103 #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
105 #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
107 #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
109 #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
111 #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
113 #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
115 #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
117 #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
119 #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
121 #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
125 struct sam4_bank_private
{
127 /* DANGER: THERE ARE DRAGONS HERE.. */
128 /* NOTE: If you add more 'ghost' pointers */
129 /* be aware that you must *manually* update */
130 /* these pointers in the function sam4_get_details() */
131 /* See the comment "Here there be dragons" */
133 /* so we can find the chip we belong to */
134 struct sam4_chip
*chip
;
135 /* so we can find the original bank pointer */
136 struct flash_bank
*bank
;
137 unsigned bank_number
;
138 uint32_t controller_address
;
139 uint32_t base_address
;
140 uint32_t flash_wait_states
;
144 unsigned sector_size
;
148 struct sam4_chip_details
{
149 /* THERE ARE DRAGONS HERE.. */
150 /* note: If you add pointers here */
151 /* be careful about them as they */
152 /* may need to be updated inside */
153 /* the function: "sam4_get_details() */
154 /* which copy/overwrites the */
155 /* 'runtime' copy of this structure */
156 uint32_t chipid_cidr
;
160 #define SAM4_N_NVM_BITS 3
161 unsigned gpnvm
[SAM4_N_NVM_BITS
];
162 unsigned total_flash_size
;
163 unsigned total_sram_size
;
165 #define SAM4_MAX_FLASH_BANKS 2
166 /* these are "initialized" from the global const data */
167 struct sam4_bank_private bank
[SAM4_MAX_FLASH_BANKS
];
171 struct sam4_chip
*next
;
174 /* this is "initialized" from the global const structure */
175 struct sam4_chip_details details
;
176 struct target
*target
;
181 struct sam4_reg_list
{
182 uint32_t address
; size_t struct_offset
; const char *name
;
183 void (*explain_func
)(struct sam4_chip
*chip
);
186 static struct sam4_chip
*all_sam4_chips
;
188 static struct sam4_chip
*get_current_sam4(struct command_invocation
*cmd
)
191 static struct sam4_chip
*p
;
193 t
= get_current_target(cmd
->ctx
);
195 command_print_sameline(cmd
, "No current target?\n");
201 /* this should not happen */
202 /* the command is not registered until the chip is created? */
203 command_print_sameline(cmd
, "No SAM4 chips exist?\n");
212 command_print_sameline(cmd
, "Cannot find SAM4 chip?\n");
216 /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
217 /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
218 /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
219 /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
221 /* these are used to *initialize* the "chip->details" structure. */
222 static const struct sam4_chip_details all_sam4_details
[] = {
223 /* Start at91sam4c* series */
224 /* at91sam4c32e - LQFP144 */
226 .chipid_cidr
= 0xA66D0EE0,
227 .name
= "at91sam4c32e",
228 .total_flash_size
= 2024 * 1024,
229 .total_sram_size
= 256 * 1024,
239 .base_address
= FLASH_BANK0_BASE_C32
,
240 .controller_address
= 0x400e0a00,
241 .flash_wait_states
= 5,
243 .size_bytes
= 1024 * 1024,
254 .base_address
= FLASH_BANK1_BASE_C32
,
255 .controller_address
= 0x400e0c00,
256 .flash_wait_states
= 5,
258 .size_bytes
= 1024 * 1024,
265 /* at91sam4c32c - LQFP100 */
267 .chipid_cidr
= 0xA64D0EE0,
268 .name
= "at91sam4c32c",
269 .total_flash_size
= 2024 * 1024,
270 .total_sram_size
= 256 * 1024,
280 .base_address
= FLASH_BANK0_BASE_C32
,
281 .controller_address
= 0x400e0a00,
282 .flash_wait_states
= 5,
284 .size_bytes
= 1024 * 1024,
295 .base_address
= FLASH_BANK1_BASE_C32
,
296 .controller_address
= 0x400e0c00,
297 .flash_wait_states
= 5,
299 .size_bytes
= 1024 * 1024,
306 /* at91sam4c16c - LQFP100 */
308 .chipid_cidr
= 0xA64C0CE0,
309 .name
= "at91sam4c16c",
310 .total_flash_size
= 1024 * 1024,
311 .total_sram_size
= 128 * 1024,
321 .base_address
= FLASH_BANK_BASE_C
,
322 .controller_address
= 0x400e0a00,
323 .flash_wait_states
= 5,
325 .size_bytes
= 1024 * 1024,
339 /* at91sam4c8c - LQFP100 */
341 .chipid_cidr
= 0xA64C0AE0,
342 .name
= "at91sam4c8c",
343 .total_flash_size
= 512 * 1024,
344 .total_sram_size
= 128 * 1024,
354 .base_address
= FLASH_BANK_BASE_C
,
355 .controller_address
= 0x400e0a00,
356 .flash_wait_states
= 5,
358 .size_bytes
= 512 * 1024,
372 /* at91sam4c4c (rev B) - LQFP100 */
374 .chipid_cidr
= 0xA64C0CE5,
375 .name
= "at91sam4c4c",
376 .total_flash_size
= 256 * 1024,
377 .total_sram_size
= 128 * 1024,
387 .base_address
= FLASH_BANK_BASE_C
,
388 .controller_address
= 0x400e0a00,
389 .flash_wait_states
= 5,
391 .size_bytes
= 256 * 1024,
406 /* Start at91sam4e* series */
407 /*atsam4e16e - LQFP144/LFBGA144*/
409 .chipid_cidr
= 0xA3CC0CE0,
410 .name
= "at91sam4e16e",
411 .total_flash_size
= 1024 * 1024,
412 .total_sram_size
= 128 * 1024,
422 .base_address
= FLASH_BANK_BASE_S
,
423 .controller_address
= 0x400e0a00,
424 .flash_wait_states
= 5,
426 .size_bytes
= 1024 * 1024,
441 /* Start at91sam4n* series */
442 /*atsam4n8a - LQFP48/QFN48*/
444 .chipid_cidr
= 0x293B0AE0,
445 .name
= "at91sam4n8a",
446 .total_flash_size
= 512 * 1024,
447 .total_sram_size
= 64 * 1024,
457 .base_address
= FLASH_BANK_BASE_S
,
458 .controller_address
= 0x400e0a00,
459 .flash_wait_states
= 5,
461 .size_bytes
= 512 * 1024,
475 /*atsam4n8b - LQFP64/QFN64*/
477 .chipid_cidr
= 0x294B0AE0,
478 .name
= "at91sam4n8b",
479 .total_flash_size
= 512 * 1024,
480 .total_sram_size
= 64 * 1024,
490 .base_address
= FLASH_BANK_BASE_S
,
491 .controller_address
= 0x400e0a00,
492 .flash_wait_states
= 5,
494 .size_bytes
= 512 * 1024,
508 /*atsam4n8c - LQFP100/TFBGA100/VFBGA100*/
510 .chipid_cidr
= 0x295B0AE0,
511 .name
= "at91sam4n8c",
512 .total_flash_size
= 512 * 1024,
513 .total_sram_size
= 64 * 1024,
523 .base_address
= FLASH_BANK_BASE_S
,
524 .controller_address
= 0x400e0a00,
525 .flash_wait_states
= 5,
527 .size_bytes
= 512 * 1024,
541 /*atsam4n16b - LQFP64/QFN64*/
543 .chipid_cidr
= 0x29460CE0,
544 .name
= "at91sam4n16b",
545 .total_flash_size
= 1024 * 1024,
546 .total_sram_size
= 80 * 1024,
556 .base_address
= FLASH_BANK_BASE_S
,
557 .controller_address
= 0x400e0a00,
558 .flash_wait_states
= 5,
560 .size_bytes
= 1024 * 1024,
574 /*atsam4n16c - LQFP100/TFBGA100/VFBGA100*/
576 .chipid_cidr
= 0x29560CE0,
577 .name
= "at91sam4n16c",
578 .total_flash_size
= 1024 * 1024,
579 .total_sram_size
= 80 * 1024,
589 .base_address
= FLASH_BANK_BASE_S
,
590 .controller_address
= 0x400e0a00,
591 .flash_wait_states
= 5,
593 .size_bytes
= 1024 * 1024,
608 /* Start at91sam4s* series */
609 /*atsam4s16c - LQFP100/BGA100*/
611 .chipid_cidr
= 0x28AC0CE0,
612 .name
= "at91sam4s16c",
613 .total_flash_size
= 1024 * 1024,
614 .total_sram_size
= 128 * 1024,
624 .base_address
= FLASH_BANK_BASE_S
,
625 .controller_address
= 0x400e0a00,
626 .flash_wait_states
= 5,
628 .size_bytes
= 1024 * 1024,
642 /*at91sam4sa16c - TFBGA100/VFBGA100/LQFP100*/
644 .chipid_cidr
= 0x28a70ce0,
645 .name
= "at91sam4sa16c",
646 .total_flash_size
= 1024 * 1024,
647 .total_sram_size
= 160 * 1024,
658 .base_address
= FLASH_BANK_BASE_S
,
659 .controller_address
= 0x400e0a00,
660 .flash_wait_states
= 5,
662 .size_bytes
= 1024 * 1024,
676 /*atsam4s16b - LQFP64/QFN64/WLCSP64*/
678 .chipid_cidr
= 0x289C0CE0,
679 .name
= "at91sam4s16b",
680 .total_flash_size
= 1024 * 1024,
681 .total_sram_size
= 128 * 1024,
691 .base_address
= FLASH_BANK_BASE_S
,
692 .controller_address
= 0x400e0a00,
693 .flash_wait_states
= 5,
695 .size_bytes
= 1024 * 1024,
709 /*atsam4sa16b - LQFP64/QFN64*/
711 .chipid_cidr
= 0x28970CE0,
712 .name
= "at91sam4sa16b",
713 .total_flash_size
= 1024 * 1024,
714 .total_sram_size
= 160 * 1024,
724 .base_address
= FLASH_BANK_BASE_S
,
725 .controller_address
= 0x400e0a00,
726 .flash_wait_states
= 5,
728 .size_bytes
= 1024 * 1024,
742 /*atsam4s16a - LQFP48/QFN48*/
744 .chipid_cidr
= 0x288C0CE0,
745 .name
= "at91sam4s16a",
746 .total_flash_size
= 1024 * 1024,
747 .total_sram_size
= 128 * 1024,
757 .base_address
= FLASH_BANK_BASE_S
,
758 .controller_address
= 0x400e0a00,
759 .flash_wait_states
= 5,
761 .size_bytes
= 1024 * 1024,
775 /*atsam4s8c - LQFP100/BGA100*/
777 .chipid_cidr
= 0x28AC0AE0,
778 .name
= "at91sam4s8c",
779 .total_flash_size
= 512 * 1024,
780 .total_sram_size
= 128 * 1024,
790 .base_address
= FLASH_BANK_BASE_S
,
791 .controller_address
= 0x400e0a00,
792 .flash_wait_states
= 5,
794 .size_bytes
= 512 * 1024,
808 /*atsam4s8b - LQFP64/QFN64/WLCSP64*/
810 .chipid_cidr
= 0x289C0AE0,
811 .name
= "at91sam4s8b",
812 .total_flash_size
= 512 * 1024,
813 .total_sram_size
= 128 * 1024,
823 .base_address
= FLASH_BANK_BASE_S
,
824 .controller_address
= 0x400e0a00,
825 .flash_wait_states
= 5,
827 .size_bytes
= 512 * 1024,
841 /*atsam4s8a - LQFP48/BGA48*/
843 .chipid_cidr
= 0x288C0AE0,
844 .name
= "at91sam4s8a",
845 .total_flash_size
= 512 * 1024,
846 .total_sram_size
= 128 * 1024,
856 .base_address
= FLASH_BANK_BASE_S
,
857 .controller_address
= 0x400e0a00,
858 .flash_wait_states
= 5,
860 .size_bytes
= 512 * 1024,
875 /*atsam4s4c - LQFP100/BGA100*/
877 .chipid_cidr
= 0x28ab09e0,
878 .name
= "at91sam4s4c",
879 .total_flash_size
= 256 * 1024,
880 .total_sram_size
= 64 * 1024,
890 .base_address
= FLASH_BANK_BASE_S
,
891 .controller_address
= 0x400e0a00,
892 .flash_wait_states
= 5,
894 .size_bytes
= 256 * 1024,
909 /*atsam4s4b - LQFP64/QFN64/WLCSP64*/
911 .chipid_cidr
= 0x289b09e0,
912 .name
= "at91sam4s4b",
913 .total_flash_size
= 256 * 1024,
914 .total_sram_size
= 64 * 1024,
924 .base_address
= FLASH_BANK_BASE_S
,
925 .controller_address
= 0x400e0a00,
926 .flash_wait_states
= 5,
928 .size_bytes
= 256 * 1024,
943 /*atsam4s4a - LQFP48/QFN48*/
945 .chipid_cidr
= 0x288b09e0,
946 .name
= "at91sam4s4a",
947 .total_flash_size
= 256 * 1024,
948 .total_sram_size
= 64 * 1024,
958 .base_address
= FLASH_BANK_BASE_S
,
959 .controller_address
= 0x400e0a00,
960 .flash_wait_states
= 5,
962 .size_bytes
= 256 * 1024,
977 /*atsam4s2c - LQFP100/BGA100*/
979 .chipid_cidr
= 0x28ab07e0,
980 .name
= "at91sam4s2c",
981 .total_flash_size
= 128 * 1024,
982 .total_sram_size
= 64 * 1024,
992 .base_address
= FLASH_BANK_BASE_S
,
993 .controller_address
= 0x400e0a00,
994 .flash_wait_states
= 5,
996 .size_bytes
= 128 * 1024,
1011 /*atsam4s2b - LQPF64/QFN64/WLCSP64*/
1013 .chipid_cidr
= 0x289b07e0,
1014 .name
= "at91sam4s2b",
1015 .total_flash_size
= 128 * 1024,
1016 .total_sram_size
= 64 * 1024,
1026 .base_address
= FLASH_BANK_BASE_S
,
1027 .controller_address
= 0x400e0a00,
1028 .flash_wait_states
= 5,
1030 .size_bytes
= 128 * 1024,
1032 .sector_size
= 8192,
1045 /*atsam4s2a - LQFP48/QFN48*/
1047 .chipid_cidr
= 0x288b07e0,
1048 .name
= "at91sam4s2a",
1049 .total_flash_size
= 128 * 1024,
1050 .total_sram_size
= 64 * 1024,
1060 .base_address
= FLASH_BANK_BASE_S
,
1061 .controller_address
= 0x400e0a00,
1062 .flash_wait_states
= 5,
1064 .size_bytes
= 128 * 1024,
1066 .sector_size
= 8192,
1079 /*at91sam4sd32c - LQFP100/BGA100*/
1081 .chipid_cidr
= 0x29a70ee0,
1082 .name
= "at91sam4sd32c",
1083 .total_flash_size
= 2048 * 1024,
1084 .total_sram_size
= 160 * 1024,
1095 .base_address
= FLASH_BANK0_BASE_SD
,
1096 .controller_address
= 0x400e0a00,
1097 .flash_wait_states
= 5,
1099 .size_bytes
= 1024 * 1024,
1101 .sector_size
= 8192,
1111 .base_address
= FLASH_BANK1_BASE_2048K_SD
,
1112 .controller_address
= 0x400e0c00,
1113 .flash_wait_states
= 5,
1115 .size_bytes
= 1024 * 1024,
1117 .sector_size
= 8192,
1123 /*at91sam4sd32b - LQFP64/BGA64*/
1125 .chipid_cidr
= 0x29970ee0,
1126 .name
= "at91sam4sd32b",
1127 .total_flash_size
= 2048 * 1024,
1128 .total_sram_size
= 160 * 1024,
1139 .base_address
= FLASH_BANK0_BASE_SD
,
1140 .controller_address
= 0x400e0a00,
1141 .flash_wait_states
= 5,
1143 .size_bytes
= 1024 * 1024,
1145 .sector_size
= 8192,
1155 .base_address
= FLASH_BANK1_BASE_2048K_SD
,
1156 .controller_address
= 0x400e0c00,
1157 .flash_wait_states
= 5,
1159 .size_bytes
= 1024 * 1024,
1161 .sector_size
= 8192,
1167 /*at91sam4sd16c - LQFP100/BGA100*/
1169 .chipid_cidr
= 0x29a70ce0,
1170 .name
= "at91sam4sd16c",
1171 .total_flash_size
= 1024 * 1024,
1172 .total_sram_size
= 160 * 1024,
1183 .base_address
= FLASH_BANK0_BASE_SD
,
1184 .controller_address
= 0x400e0a00,
1185 .flash_wait_states
= 5,
1187 .size_bytes
= 512 * 1024,
1189 .sector_size
= 8192,
1199 .base_address
= FLASH_BANK1_BASE_1024K_SD
,
1200 .controller_address
= 0x400e0c00,
1201 .flash_wait_states
= 5,
1203 .size_bytes
= 512 * 1024,
1205 .sector_size
= 8192,
1211 /*at91sam4sd16b - LQFP64/BGA64*/
1213 .chipid_cidr
= 0x29970ce0,
1214 .name
= "at91sam4sd16b",
1215 .total_flash_size
= 1024 * 1024,
1216 .total_sram_size
= 160 * 1024,
1227 .base_address
= FLASH_BANK0_BASE_SD
,
1228 .controller_address
= 0x400e0a00,
1229 .flash_wait_states
= 5,
1231 .size_bytes
= 512 * 1024,
1233 .sector_size
= 8192,
1243 .base_address
= FLASH_BANK1_BASE_1024K_SD
,
1244 .controller_address
= 0x400e0c00,
1245 .flash_wait_states
= 5,
1247 .size_bytes
= 512 * 1024,
1249 .sector_size
= 8192,
1257 .chipid_cidr
= 0x247e0ae0,
1258 .name
= "atsamg53n19",
1259 .total_flash_size
= 512 * 1024,
1260 .total_sram_size
= 96 * 1024,
1271 .base_address
= FLASH_BANK_BASE_S
,
1272 .controller_address
= 0x400e0a00,
1273 .flash_wait_states
= 5,
1275 .size_bytes
= 512 * 1024,
1277 .sector_size
= 8192,
1290 /* atsamg55g19 Rev.A */
1292 .chipid_cidr
= 0x24470ae0,
1293 .name
= "atsamg55g19",
1294 .total_flash_size
= 512 * 1024,
1295 .total_sram_size
= 160 * 1024,
1306 .base_address
= FLASH_BANK_BASE_S
,
1307 .controller_address
= 0x400e0a00,
1308 .flash_wait_states
= 5,
1310 .size_bytes
= 512 * 1024,
1312 .sector_size
= 8192,
1324 /* atsamg55g19 Rev.B */
1326 .chipid_cidr
= 0x24470ae1,
1327 .name
= "atsamg55g19b",
1328 .total_flash_size
= 512 * 1024,
1329 .total_sram_size
= 160 * 1024,
1340 .base_address
= FLASH_BANK_BASE_S
,
1341 .controller_address
= 0x400e0a00,
1342 .flash_wait_states
= 5,
1344 .size_bytes
= 512 * 1024,
1346 .sector_size
= 8192,
1358 /* atsamg55j19 Rev.A */
1360 .chipid_cidr
= 0x24570ae0,
1361 .name
= "atsamg55j19",
1362 .total_flash_size
= 512 * 1024,
1363 .total_sram_size
= 160 * 1024,
1374 .base_address
= FLASH_BANK_BASE_S
,
1375 .controller_address
= 0x400e0a00,
1376 .flash_wait_states
= 5,
1378 .size_bytes
= 512 * 1024,
1380 .sector_size
= 8192,
1392 /* atsamg55j19 Rev.B */
1394 .chipid_cidr
= 0x24570ae1,
1395 .name
= "atsamg55j19b",
1396 .total_flash_size
= 512 * 1024,
1397 .total_sram_size
= 160 * 1024,
1408 .base_address
= FLASH_BANK_BASE_S
,
1409 .controller_address
= 0x400e0a00,
1410 .flash_wait_states
= 5,
1412 .size_bytes
= 512 * 1024,
1414 .sector_size
= 8192,
1434 /***********************************************************************
1435 **********************************************************************
1436 **********************************************************************
1437 **********************************************************************
1438 **********************************************************************
1439 **********************************************************************/
1440 /* *ATMEL* style code - from the SAM4 driver code */
1443 * Get the current status of the EEFC and
1444 * the value of some status bits (LOCKE, PROGE).
1445 * @param private - info about the bank
1446 * @param v - result goes here
1448 static int efc_get_status(struct sam4_bank_private
*private, uint32_t *v
)
1451 r
= target_read_u32(private->chip
->target
,
1452 private->controller_address
+ OFFSET_EFC_FSR
,
1454 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1456 ((unsigned int)((*v
>> 2) & 1)),
1457 ((unsigned int)((*v
>> 1) & 1)),
1458 ((unsigned int)((*v
>> 0) & 1)));
1464 * Get the result of the last executed command.
1465 * @param private - info about the bank
1466 * @param v - result goes here
1468 static int efc_get_result(struct sam4_bank_private
*private, uint32_t *v
)
1472 r
= target_read_u32(private->chip
->target
,
1473 private->controller_address
+ OFFSET_EFC_FRR
,
1477 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv
)));
1481 static int efc_start_command(struct sam4_bank_private
*private,
1482 unsigned command
, unsigned argument
)
1491 /* Check command & argument */
1494 case AT91C_EFC_FCMD_WP
:
1495 case AT91C_EFC_FCMD_WPL
:
1496 case AT91C_EFC_FCMD_EWP
:
1497 case AT91C_EFC_FCMD_EWPL
:
1498 /* case AT91C_EFC_FCMD_EPL: */
1499 case AT91C_EFC_FCMD_EPA
:
1500 case AT91C_EFC_FCMD_SLB
:
1501 case AT91C_EFC_FCMD_CLB
:
1502 n
= (private->size_bytes
/ private->page_size
);
1504 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n
));
1507 case AT91C_EFC_FCMD_SFB
:
1508 case AT91C_EFC_FCMD_CFB
:
1509 if (argument
>= private->chip
->details
.n_gpnvms
) {
1510 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1511 private->chip
->details
.n_gpnvms
);
1515 case AT91C_EFC_FCMD_GETD
:
1516 case AT91C_EFC_FCMD_EA
:
1517 case AT91C_EFC_FCMD_GLB
:
1518 case AT91C_EFC_FCMD_GFB
:
1519 case AT91C_EFC_FCMD_STUI
:
1520 case AT91C_EFC_FCMD_SPUI
:
1522 LOG_ERROR("Argument is meaningless for cmd: %d", command
);
1525 LOG_ERROR("Unknown command %d", command
);
1529 if (command
== AT91C_EFC_FCMD_SPUI
) {
1530 /* this is a very special situation. */
1531 /* Situation (1) - error/retry - see below */
1532 /* And we are being called recursively */
1533 /* Situation (2) - normal, finished reading unique id */
1535 /* it should be "ready" */
1536 efc_get_status(private, &v
);
1538 /* then it is ready */
1542 /* we have done this before */
1543 /* the controller is not responding. */
1544 LOG_ERROR("flash controller(%d) is not ready! Error",
1545 private->bank_number
);
1549 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1550 private->bank_number
);
1551 /* we do that by issuing the *STOP* command */
1552 efc_start_command(private, AT91C_EFC_FCMD_SPUI
, 0);
1553 /* above is recursive, and further recursion is blocked by */
1554 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1560 v
= (0x5A << 24) | (argument
<< 8) | command
;
1561 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v
)));
1562 r
= target_write_u32(private->bank
->target
,
1563 private->controller_address
+ OFFSET_EFC_FCR
, v
);
1565 LOG_DEBUG("Error Write failed");
1570 * Performs the given command and wait until its completion (or an error).
1571 * @param private - info about the bank
1572 * @param command - Command to perform.
1573 * @param argument - Optional command argument.
1574 * @param status - put command status bits here
1576 static int efc_perform_command(struct sam4_bank_private
*private,
1584 int64_t ms_now
, ms_end
;
1590 r
= efc_start_command(private, command
, argument
);
1594 ms_end
= 10000 + timeval_ms();
1597 r
= efc_get_status(private, &v
);
1600 ms_now
= timeval_ms();
1601 if (ms_now
> ms_end
) {
1603 LOG_ERROR("Command timeout");
1606 } while ((v
& 1) == 0);
1610 *status
= (v
& 0x6);
1616 * Read the unique ID.
1617 * @param private - info about the bank
1618 * The unique ID is stored in the 'private' structure.
1620 static int flashd_read_uid(struct sam4_bank_private
*private)
1626 private->chip
->cfg
.unique_id
[0] = 0;
1627 private->chip
->cfg
.unique_id
[1] = 0;
1628 private->chip
->cfg
.unique_id
[2] = 0;
1629 private->chip
->cfg
.unique_id
[3] = 0;
1632 r
= efc_start_command(private, AT91C_EFC_FCMD_STUI
, 0);
1636 for (x
= 0; x
< 4; x
++) {
1637 r
= target_read_u32(private->chip
->target
,
1638 private->bank
->base
+ (x
* 4),
1642 private->chip
->cfg
.unique_id
[x
] = v
;
1645 r
= efc_perform_command(private, AT91C_EFC_FCMD_SPUI
, 0, NULL
);
1646 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1648 (unsigned int)(private->chip
->cfg
.unique_id
[0]),
1649 (unsigned int)(private->chip
->cfg
.unique_id
[1]),
1650 (unsigned int)(private->chip
->cfg
.unique_id
[2]),
1651 (unsigned int)(private->chip
->cfg
.unique_id
[3]));
1657 * Erases the entire flash.
1658 * @param private - the info about the bank.
1660 static int flashd_erase_entire_bank(struct sam4_bank_private
*private)
1663 return efc_perform_command(private, AT91C_EFC_FCMD_EA
, 0, NULL
);
1667 * Erases the entire flash.
1668 * @param private - the info about the bank.
1673 static int flashd_erase_pages(struct sam4_bank_private
*private,
1679 uint8_t erase_pages
;
1680 switch (num_pages
) {
1698 /* AT91C_EFC_FCMD_EPA
1699 * According to the datasheet FARG[15:2] defines the page from which
1700 * the erase will start.This page must be modulo 4, 8, 16 or 32
1701 * according to the number of pages to erase. FARG[1:0] defines the
1702 * number of pages to be erased. Previously (firstpage << 2) was used
1703 * to conform to this, seems it should not be shifted...
1705 return efc_perform_command(private,
1706 /* send Erase Page */
1708 (first_page
) | erase_pages
,
1713 * Gets current GPNVM state.
1714 * @param private - info about the bank.
1715 * @param gpnvm - GPNVM bit index.
1716 * @param puthere - result stored here.
1718 /* ------------------------------------------------------------------------------ */
1719 static int flashd_get_gpnvm(struct sam4_bank_private
*private, unsigned gpnvm
, unsigned *puthere
)
1725 if (private->bank_number
!= 0) {
1726 LOG_ERROR("GPNVM only works with Bank0");
1730 if (gpnvm
>= private->chip
->details
.n_gpnvms
) {
1731 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1732 gpnvm
, private->chip
->details
.n_gpnvms
);
1736 /* Get GPNVMs status */
1737 r
= efc_perform_command(private, AT91C_EFC_FCMD_GFB
, 0, NULL
);
1738 if (r
!= ERROR_OK
) {
1739 LOG_ERROR("Failed");
1743 r
= efc_get_result(private, &v
);
1746 /* Check if GPNVM is set */
1747 /* get the bit and make it a 0/1 */
1748 *puthere
= (v
>> gpnvm
) & 1;
1755 * Clears the selected GPNVM bit.
1756 * @param private info about the bank
1757 * @param gpnvm GPNVM index.
1758 * @returns 0 if successful; otherwise returns an error code.
1760 static int flashd_clr_gpnvm(struct sam4_bank_private
*private, unsigned gpnvm
)
1766 if (private->bank_number
!= 0) {
1767 LOG_ERROR("GPNVM only works with Bank0");
1771 if (gpnvm
>= private->chip
->details
.n_gpnvms
) {
1772 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1773 gpnvm
, private->chip
->details
.n_gpnvms
);
1777 r
= flashd_get_gpnvm(private, gpnvm
, &v
);
1778 if (r
!= ERROR_OK
) {
1779 LOG_DEBUG("Failed: %d", r
);
1782 r
= efc_perform_command(private, AT91C_EFC_FCMD_CFB
, gpnvm
, NULL
);
1783 LOG_DEBUG("End: %d", r
);
1788 * Sets the selected GPNVM bit.
1789 * @param private info about the bank
1790 * @param gpnvm GPNVM index.
1792 static int flashd_set_gpnvm(struct sam4_bank_private
*private, unsigned gpnvm
)
1797 if (private->bank_number
!= 0) {
1798 LOG_ERROR("GPNVM only works with Bank0");
1802 if (gpnvm
>= private->chip
->details
.n_gpnvms
) {
1803 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1804 gpnvm
, private->chip
->details
.n_gpnvms
);
1808 r
= flashd_get_gpnvm(private, gpnvm
, &v
);
1816 r
= efc_perform_command(private, AT91C_EFC_FCMD_SFB
, gpnvm
, NULL
);
1822 * Returns a bit field (at most 64) of locked regions within a page.
1823 * @param private info about the bank
1824 * @param v where to store locked bits
1826 static int flashd_get_lock_bits(struct sam4_bank_private
*private, uint32_t *v
)
1830 r
= efc_perform_command(private, AT91C_EFC_FCMD_GLB
, 0, NULL
);
1831 if (r
== ERROR_OK
) {
1832 efc_get_result(private, v
);
1833 efc_get_result(private, v
);
1834 efc_get_result(private, v
);
1835 r
= efc_get_result(private, v
);
1837 LOG_DEBUG("End: %d", r
);
1842 * Unlocks all the regions in the given address range.
1843 * @param private info about the bank
1844 * @param start_sector first sector to unlock
1845 * @param end_sector last (inclusive) to unlock
1848 static int flashd_unlock(struct sam4_bank_private
*private,
1849 unsigned start_sector
,
1850 unsigned end_sector
)
1855 uint32_t pages_per_sector
;
1857 pages_per_sector
= private->sector_size
/ private->page_size
;
1859 /* Unlock all pages */
1860 while (start_sector
<= end_sector
) {
1861 pg
= start_sector
* pages_per_sector
;
1863 r
= efc_perform_command(private, AT91C_EFC_FCMD_CLB
, pg
, &status
);
1874 * @param private - info about the bank
1875 * @param start_sector - first sector to lock
1876 * @param end_sector - last sector (inclusive) to lock
1878 static int flashd_lock(struct sam4_bank_private
*private,
1879 unsigned start_sector
,
1880 unsigned end_sector
)
1884 uint32_t pages_per_sector
;
1887 pages_per_sector
= private->sector_size
/ private->page_size
;
1889 /* Lock all pages */
1890 while (start_sector
<= end_sector
) {
1891 pg
= start_sector
* pages_per_sector
;
1893 r
= efc_perform_command(private, AT91C_EFC_FCMD_SLB
, pg
, &status
);
1901 /****** END SAM4 CODE ********/
1903 /* begin helpful debug code */
1904 /* print the fieldname, the field value, in dec & hex, and return field value */
1905 static uint32_t sam4_reg_fieldname(struct sam4_chip
*chip
,
1906 const char *regname
,
1915 /* extract the field */
1917 v
= v
& ((1 << width
)-1);
1926 /* show the basics */
1927 LOG_USER_N("\t%*s: %*" PRIu32
" [0x%0*" PRIx32
"] ",
1928 REG_NAME_WIDTH
, regname
,
1934 static const char _unknown
[] = "unknown";
1935 static const char *const eproc_names
[] = {
1936 "Cortex-M7", /* 0 */
1939 "Cortex-M3", /* 3 */
1941 "arm926ejs", /* 5 */
1942 "Cortex-A5", /* 6 */
1943 "Cortex-M4", /* 7 */
1954 #define nvpsize2 nvpsize /* these two tables are identical */
1955 static const char *const nvpsize
[] = {
1958 "16K bytes", /* 2 */
1959 "32K bytes", /* 3 */
1961 "64K bytes", /* 5 */
1963 "128K bytes", /* 7 */
1964 "160K bytes", /* 8 */
1965 "256K bytes", /* 9 */
1966 "512K bytes", /* 10 */
1968 "1024K bytes", /* 12 */
1970 "2048K bytes", /* 14 */
1974 static const char *const sramsize
[] = {
1975 "48K Bytes", /* 0 */
1979 "112K Bytes", /* 4 */
1981 "80K Bytes", /* 6 */
1982 "160K Bytes", /* 7 */
1984 "16K Bytes", /* 9 */
1985 "32K Bytes", /* 10 */
1986 "64K Bytes", /* 11 */
1987 "128K Bytes", /* 12 */
1988 "256K Bytes", /* 13 */
1989 "96K Bytes", /* 14 */
1990 "512K Bytes", /* 15 */
1994 static const struct archnames
{ unsigned value
; const char *name
; } archnames
[] = {
1995 { 0x19, "AT91SAM9xx Series" },
1996 { 0x29, "AT91SAM9XExx Series" },
1997 { 0x34, "AT91x34 Series" },
1998 { 0x37, "CAP7 Series" },
1999 { 0x39, "CAP9 Series" },
2000 { 0x3B, "CAP11 Series" },
2001 { 0x3C, "ATSAM4E" },
2002 { 0x40, "AT91x40 Series" },
2003 { 0x42, "AT91x42 Series" },
2004 { 0x43, "SAMG51 Series"
2006 { 0x44, "SAMG55 Series (49-pin WLCSP)" },
2007 { 0x45, "SAMG55 Series (64-pin)" },
2008 { 0x47, "SAMG53 Series"
2010 { 0x55, "AT91x55 Series" },
2011 { 0x60, "AT91SAM7Axx Series" },
2012 { 0x61, "AT91SAM7AQxx Series" },
2013 { 0x63, "AT91x63 Series" },
2014 { 0x64, "SAM4CxxC (100-pin version)" },
2015 { 0x66, "SAM4CxxE (144-pin version)" },
2016 { 0x70, "AT91SAM7Sxx Series" },
2017 { 0x71, "AT91SAM7XCxx Series" },
2018 { 0x72, "AT91SAM7SExx Series" },
2019 { 0x73, "AT91SAM7Lxx Series" },
2020 { 0x75, "AT91SAM7Xxx Series" },
2021 { 0x76, "AT91SAM7SLxx Series" },
2022 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2023 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2024 { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
2025 { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
2026 { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
2027 { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
2028 { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
2029 { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
2030 { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
2031 { 0x92, "AT91x92 Series" },
2032 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2033 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2034 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2035 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2036 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2037 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2038 { 0xA5, "ATSAM5A" },
2039 { 0xF0, "AT75Cxx Series" },
2043 static const char *const nvptype
[] = {
2045 "romless or onchip flash", /* 1 */
2046 "embedded flash memory",/* 2 */
2047 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2048 "sram emulating flash", /* 4 */
2054 static const char *_yes_or_no(uint32_t v
)
2062 static const char *const _rc_freq
[] = {
2063 "4 MHz", "8 MHz", "12 MHz", "reserved"
2066 static void sam4_explain_ckgr_mor(struct sam4_chip
*chip
)
2071 v
= sam4_reg_fieldname(chip
, "MOSCXTEN", chip
->cfg
.CKGR_MOR
, 0, 1);
2072 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v
));
2073 v
= sam4_reg_fieldname(chip
, "MOSCXTBY", chip
->cfg
.CKGR_MOR
, 1, 1);
2074 LOG_USER("(main osc bypass: %s)", _yes_or_no(v
));
2075 rcen
= sam4_reg_fieldname(chip
, "MOSCRCEN", chip
->cfg
.CKGR_MOR
, 3, 1);
2076 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen
));
2077 v
= sam4_reg_fieldname(chip
, "MOSCRCF", chip
->cfg
.CKGR_MOR
, 4, 3);
2078 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq
[v
]);
2080 chip
->cfg
.rc_freq
= 0;
2084 chip
->cfg
.rc_freq
= 0;
2087 chip
->cfg
.rc_freq
= 4 * 1000 * 1000;
2090 chip
->cfg
.rc_freq
= 8 * 1000 * 1000;
2093 chip
->cfg
.rc_freq
= 12 * 1000 * 1000;
2098 v
= sam4_reg_fieldname(chip
, "MOSCXTST", chip
->cfg
.CKGR_MOR
, 8, 8);
2099 LOG_USER("(startup clks, time= %f uSecs)",
2100 ((float)(v
* 1000000)) / ((float)(chip
->cfg
.slow_freq
)));
2101 v
= sam4_reg_fieldname(chip
, "MOSCSEL", chip
->cfg
.CKGR_MOR
, 24, 1);
2102 LOG_USER("(mainosc source: %s)",
2103 v
? "external xtal" : "internal RC");
2105 v
= sam4_reg_fieldname(chip
, "CFDEN", chip
->cfg
.CKGR_MOR
, 25, 1);
2106 LOG_USER("(clock failure enabled: %s)",
2110 static void sam4_explain_chipid_cidr(struct sam4_chip
*chip
)
2116 sam4_reg_fieldname(chip
, "Version", chip
->cfg
.CHIPID_CIDR
, 0, 5);
2119 v
= sam4_reg_fieldname(chip
, "EPROC", chip
->cfg
.CHIPID_CIDR
, 5, 3);
2120 LOG_USER("%s", eproc_names
[v
]);
2122 v
= sam4_reg_fieldname(chip
, "NVPSIZE", chip
->cfg
.CHIPID_CIDR
, 8, 4);
2123 LOG_USER("%s", nvpsize
[v
]);
2125 v
= sam4_reg_fieldname(chip
, "NVPSIZE2", chip
->cfg
.CHIPID_CIDR
, 12, 4);
2126 LOG_USER("%s", nvpsize2
[v
]);
2128 v
= sam4_reg_fieldname(chip
, "SRAMSIZE", chip
->cfg
.CHIPID_CIDR
, 16, 4);
2129 LOG_USER("%s", sramsize
[v
]);
2131 v
= sam4_reg_fieldname(chip
, "ARCH", chip
->cfg
.CHIPID_CIDR
, 20, 8);
2133 for (x
= 0; archnames
[x
].name
; x
++) {
2134 if (v
== archnames
[x
].value
) {
2135 cp
= archnames
[x
].name
;
2142 v
= sam4_reg_fieldname(chip
, "NVPTYP", chip
->cfg
.CHIPID_CIDR
, 28, 3);
2143 LOG_USER("%s", nvptype
[v
]);
2145 v
= sam4_reg_fieldname(chip
, "EXTID", chip
->cfg
.CHIPID_CIDR
, 31, 1);
2146 LOG_USER("(exists: %s)", _yes_or_no(v
));
2149 static void sam4_explain_ckgr_mcfr(struct sam4_chip
*chip
)
2153 v
= sam4_reg_fieldname(chip
, "MAINFRDY", chip
->cfg
.CKGR_MCFR
, 16, 1);
2154 LOG_USER("(main ready: %s)", _yes_or_no(v
));
2156 v
= sam4_reg_fieldname(chip
, "MAINF", chip
->cfg
.CKGR_MCFR
, 0, 16);
2158 v
= (v
* chip
->cfg
.slow_freq
) / 16;
2159 chip
->cfg
.mainosc_freq
= v
;
2161 LOG_USER("(%3.03f Mhz (%" PRIu32
".%03" PRIu32
"khz slowclk)",
2163 (uint32_t)(chip
->cfg
.slow_freq
/ 1000),
2164 (uint32_t)(chip
->cfg
.slow_freq
% 1000));
2167 static void sam4_explain_ckgr_plla(struct sam4_chip
*chip
)
2169 uint32_t mula
, diva
;
2171 diva
= sam4_reg_fieldname(chip
, "DIVA", chip
->cfg
.CKGR_PLLAR
, 0, 8);
2173 mula
= sam4_reg_fieldname(chip
, "MULA", chip
->cfg
.CKGR_PLLAR
, 16, 11);
2175 chip
->cfg
.plla_freq
= 0;
2177 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2179 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2180 else if (diva
>= 1) {
2181 chip
->cfg
.plla_freq
= (chip
->cfg
.mainosc_freq
* (mula
+ 1) / diva
);
2182 LOG_USER("\tPLLA Freq: %3.03f MHz",
2183 _tomhz(chip
->cfg
.plla_freq
));
2187 static void sam4_explain_mckr(struct sam4_chip
*chip
)
2189 uint32_t css
, pres
, fin
= 0;
2191 const char *cp
= NULL
;
2193 css
= sam4_reg_fieldname(chip
, "CSS", chip
->cfg
.PMC_MCKR
, 0, 2);
2196 fin
= chip
->cfg
.slow_freq
;
2200 fin
= chip
->cfg
.mainosc_freq
;
2204 fin
= chip
->cfg
.plla_freq
;
2208 if (chip
->cfg
.CKGR_UCKR
& (1 << 16)) {
2209 fin
= 480 * 1000 * 1000;
2213 cp
= "upll (*ERROR* UPLL is disabled)";
2221 LOG_USER("%s (%3.03f Mhz)",
2224 pres
= sam4_reg_fieldname(chip
, "PRES", chip
->cfg
.PMC_MCKR
, 4, 3);
2225 switch (pres
& 0x07) {
2228 cp
= "selected clock";
2262 LOG_USER("(%s)", cp
);
2264 /* sam4 has a *SINGLE* clock - */
2265 /* other at91 series parts have divisors for these. */
2266 chip
->cfg
.cpu_freq
= fin
;
2267 chip
->cfg
.mclk_freq
= fin
;
2268 chip
->cfg
.fclk_freq
= fin
;
2269 LOG_USER("\t\tResult CPU Freq: %3.03f",
2274 static struct sam4_chip
*target2sam4(struct target
*target
)
2276 struct sam4_chip
*chip
;
2281 chip
= all_sam4_chips
;
2283 if (chip
->target
== target
)
2284 break; /* return below */
2292 static uint32_t *sam4_get_reg_ptr(struct sam4_cfg
*cfg
, const struct sam4_reg_list
*list
)
2294 /* this function exists to help */
2295 /* keep funky offsetof() errors */
2296 /* and casting from causing bugs */
2298 /* By using prototypes - we can detect what would */
2299 /* be casting errors. */
2301 return (uint32_t *)(void *)(((char *)(cfg
)) + list
->struct_offset
);
2305 #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
2307 NAME), # NAME, FUNC }
2308 static const struct sam4_reg_list sam4_all_regs
[] = {
2309 SAM4_ENTRY(CKGR_MOR
, sam4_explain_ckgr_mor
),
2310 SAM4_ENTRY(CKGR_MCFR
, sam4_explain_ckgr_mcfr
),
2311 SAM4_ENTRY(CKGR_PLLAR
, sam4_explain_ckgr_plla
),
2312 SAM4_ENTRY(CKGR_UCKR
, NULL
),
2313 SAM4_ENTRY(PMC_FSMR
, NULL
),
2314 SAM4_ENTRY(PMC_FSPR
, NULL
),
2315 SAM4_ENTRY(PMC_IMR
, NULL
),
2316 SAM4_ENTRY(PMC_MCKR
, sam4_explain_mckr
),
2317 SAM4_ENTRY(PMC_PCK0
, NULL
),
2318 SAM4_ENTRY(PMC_PCK1
, NULL
),
2319 SAM4_ENTRY(PMC_PCK2
, NULL
),
2320 SAM4_ENTRY(PMC_PCSR
, NULL
),
2321 SAM4_ENTRY(PMC_SCSR
, NULL
),
2322 SAM4_ENTRY(PMC_SR
, NULL
),
2323 SAM4_ENTRY(CHIPID_CIDR
, sam4_explain_chipid_cidr
),
2324 SAM4_ENTRY(CHIPID_EXID
, NULL
),
2325 /* TERMINATE THE LIST */
2330 static struct sam4_bank_private
*get_sam4_bank_private(struct flash_bank
*bank
)
2332 return bank
->driver_priv
;
2336 * Given a pointer to where it goes in the structure,
2337 * determine the register name, address from the all registers table.
2339 static const struct sam4_reg_list
*sam4_get_reg(struct sam4_chip
*chip
, uint32_t *goes_here
)
2341 const struct sam4_reg_list
*reg
;
2343 reg
= &(sam4_all_regs
[0]);
2347 /* calculate where this one go.. */
2348 /* it is "possibly" this register. */
2350 possible
= ((uint32_t *)(void *)(((char *)(&(chip
->cfg
))) + reg
->struct_offset
));
2352 /* well? Is it this register */
2353 if (possible
== goes_here
) {
2361 /* This is *TOTAL*PANIC* - we are totally screwed. */
2362 LOG_ERROR("INVALID SAM4 REGISTER");
2366 static int sam4_read_this_reg(struct sam4_chip
*chip
, uint32_t *goes_here
)
2368 const struct sam4_reg_list
*reg
;
2371 reg
= sam4_get_reg(chip
, goes_here
);
2375 r
= target_read_u32(chip
->target
, reg
->address
, goes_here
);
2376 if (r
!= ERROR_OK
) {
2377 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
2378 reg
->name
, (unsigned)(reg
->address
), r
);
2383 static int sam4_read_all_regs(struct sam4_chip
*chip
)
2386 const struct sam4_reg_list
*reg
;
2388 reg
= &(sam4_all_regs
[0]);
2390 r
= sam4_read_this_reg(chip
,
2391 sam4_get_reg_ptr(&(chip
->cfg
), reg
));
2392 if (r
!= ERROR_OK
) {
2393 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
2394 reg
->name
, ((unsigned)(reg
->address
)), r
);
2403 static int sam4_get_info(struct sam4_chip
*chip
)
2405 const struct sam4_reg_list
*reg
;
2409 r
= sam4_read_all_regs(chip
);
2413 reg
= &(sam4_all_regs
[0]);
2415 /* display all regs */
2416 LOG_DEBUG("Start: %s", reg
->name
);
2417 regval
= *sam4_get_reg_ptr(&(chip
->cfg
), reg
);
2418 LOG_USER("%*s: [0x%08" PRIx32
"] -> 0x%08" PRIx32
,
2423 if (reg
->explain_func
)
2424 (*(reg
->explain_func
))(chip
);
2425 LOG_DEBUG("End: %s", reg
->name
);
2428 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(chip
->cfg
.rc_freq
));
2429 LOG_USER(" mainosc: %3.03f MHz", _tomhz(chip
->cfg
.mainosc_freq
));
2430 LOG_USER(" plla: %3.03f MHz", _tomhz(chip
->cfg
.plla_freq
));
2431 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(chip
->cfg
.cpu_freq
));
2432 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(chip
->cfg
.mclk_freq
));
2434 LOG_USER(" UniqueId: 0x%08" PRIx32
" 0x%08" PRIx32
" 0x%08" PRIx32
" 0x%08"PRIx32
,
2435 chip
->cfg
.unique_id
[0],
2436 chip
->cfg
.unique_id
[1],
2437 chip
->cfg
.unique_id
[2],
2438 chip
->cfg
.unique_id
[3]);
2443 static int sam4_protect_check(struct flash_bank
*bank
)
2446 uint32_t v
[4] = {0};
2448 struct sam4_bank_private
*private;
2451 if (bank
->target
->state
!= TARGET_HALTED
) {
2452 LOG_ERROR("Target not halted");
2453 return ERROR_TARGET_NOT_HALTED
;
2456 private = get_sam4_bank_private(bank
);
2458 LOG_ERROR("no private for this bank?");
2461 if (!(private->probed
))
2462 return ERROR_FLASH_BANK_NOT_PROBED
;
2464 r
= flashd_get_lock_bits(private, v
);
2465 if (r
!= ERROR_OK
) {
2466 LOG_DEBUG("Failed: %d", r
);
2470 for (x
= 0; x
< private->nsectors
; x
++)
2471 bank
->sectors
[x
].is_protected
= (!!(v
[x
>> 5] & (1 << (x
% 32))));
2476 FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command
)
2478 struct sam4_chip
*chip
;
2480 chip
= all_sam4_chips
;
2482 /* is this an existing chip? */
2484 if (chip
->target
== bank
->target
)
2490 /* this is a *NEW* chip */
2491 chip
= calloc(1, sizeof(struct sam4_chip
));
2493 LOG_ERROR("NO RAM!");
2496 chip
->target
= bank
->target
;
2497 /* insert at head */
2498 chip
->next
= all_sam4_chips
;
2499 all_sam4_chips
= chip
;
2500 chip
->target
= bank
->target
;
2501 /* assumption is this runs at 32khz */
2502 chip
->cfg
.slow_freq
= 32768;
2503 chip
->probed
= false;
2506 switch (bank
->base
) {
2508 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
2509 "[at91sam4s series] )",
2510 ((unsigned int)(bank
->base
)),
2511 ((unsigned int)(FLASH_BANK_BASE_S
)));
2514 /* at91sam4s series only has bank 0*/
2515 /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
2516 case FLASH_BANK_BASE_S
:
2517 case FLASH_BANK_BASE_C
:
2518 bank
->driver_priv
= &(chip
->details
.bank
[0]);
2519 bank
->bank_number
= 0;
2520 chip
->details
.bank
[0].chip
= chip
;
2521 chip
->details
.bank
[0].bank
= bank
;
2524 /* Bank 1 of at91sam4sd/at91sam4c32 series */
2525 case FLASH_BANK1_BASE_1024K_SD
:
2526 case FLASH_BANK1_BASE_2048K_SD
:
2527 case FLASH_BANK1_BASE_C32
:
2528 bank
->driver_priv
= &(chip
->details
.bank
[1]);
2529 bank
->bank_number
= 1;
2530 chip
->details
.bank
[1].chip
= chip
;
2531 chip
->details
.bank
[1].bank
= bank
;
2535 /* we initialize after probing. */
2540 * Remove all chips from the internal list without distinguishing which one
2541 * is owned by this bank. This simplification works only for one shot
2542 * deallocation like current flash_free_all_banks()
2544 static void sam4_free_driver_priv(struct flash_bank
*bank
)
2546 struct sam4_chip
*chip
= all_sam4_chips
;
2548 struct sam4_chip
*next
= chip
->next
;
2552 all_sam4_chips
= NULL
;
2555 static int sam4_get_details(struct sam4_bank_private
*private)
2557 const struct sam4_chip_details
*details
;
2558 struct sam4_chip
*chip
;
2559 struct flash_bank
*saved_banks
[SAM4_MAX_FLASH_BANKS
];
2563 details
= all_sam4_details
;
2564 while (details
->name
) {
2565 /* Compare cidr without version bits */
2566 if (details
->chipid_cidr
== (private->chip
->cfg
.CHIPID_CIDR
& 0xFFFFFFE0))
2571 if (!details
->name
) {
2572 LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2573 (unsigned int)(private->chip
->cfg
.CHIPID_CIDR
));
2574 /* Help the victim, print details about the chip */
2575 LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32
" decodes as follows",
2576 private->chip
->cfg
.CHIPID_CIDR
);
2577 sam4_explain_chipid_cidr(private->chip
);
2580 LOG_DEBUG("SAM4 Found chip %s, CIDR 0x%08" PRIx32
, details
->name
, details
->chipid_cidr
);
2583 /* DANGER: THERE ARE DRAGONS HERE */
2585 /* get our chip - it is going */
2586 /* to be over-written shortly */
2587 chip
= private->chip
;
2589 /* Note that, in reality: */
2591 /* private = &(chip->details.bank[0]) */
2592 /* or private = &(chip->details.bank[1]) */
2595 /* save the "bank" pointers */
2596 for (x
= 0; x
< SAM4_MAX_FLASH_BANKS
; x
++)
2597 saved_banks
[x
] = chip
->details
.bank
[x
].bank
;
2599 /* Overwrite the "details" structure. */
2600 memcpy(&(private->chip
->details
),
2602 sizeof(private->chip
->details
));
2604 /* now fix the ghosted pointers */
2605 for (x
= 0; x
< SAM4_MAX_FLASH_BANKS
; x
++) {
2606 chip
->details
.bank
[x
].chip
= chip
;
2607 chip
->details
.bank
[x
].bank
= saved_banks
[x
];
2610 /* update the *BANK*SIZE* */
2616 static int sam4_info(struct flash_bank
*bank
, struct command_invocation
*cmd
)
2618 struct sam4_bank_private
*private;
2619 int k
= bank
->size
/ 1024;
2621 private = get_sam4_bank_private(bank
);
2625 command_print_sameline(cmd
, "%s bank %d: %d kB at " TARGET_ADDR_FMT
,
2626 private->chip
->details
.name
,
2627 private->bank_number
,
2634 static int sam4_probe(struct flash_bank
*bank
)
2637 struct sam4_bank_private
*private;
2640 LOG_DEBUG("Begin: Bank: %u", bank
->bank_number
);
2641 if (bank
->target
->state
!= TARGET_HALTED
) {
2642 LOG_ERROR("Target not halted");
2643 return ERROR_TARGET_NOT_HALTED
;
2646 private = get_sam4_bank_private(bank
);
2648 LOG_ERROR("Invalid/unknown bank number");
2652 r
= sam4_read_all_regs(private->chip
);
2657 if (private->chip
->probed
)
2658 r
= sam4_get_info(private->chip
);
2660 r
= sam4_get_details(private);
2664 /* update the flash bank size */
2665 for (unsigned int x
= 0; x
< SAM4_MAX_FLASH_BANKS
; x
++) {
2666 if (bank
->base
== private->chip
->details
.bank
[x
].base_address
) {
2667 bank
->size
= private->chip
->details
.bank
[x
].size_bytes
;
2668 LOG_DEBUG("SAM4 Set flash bank to " TARGET_ADDR_FMT
" - "
2669 TARGET_ADDR_FMT
", idx %d", bank
->base
,
2670 bank
->base
+ bank
->size
, x
);
2675 if (!bank
->sectors
) {
2676 bank
->sectors
= calloc(private->nsectors
, (sizeof((bank
->sectors
)[0])));
2677 if (!bank
->sectors
) {
2678 LOG_ERROR("No memory!");
2681 bank
->num_sectors
= private->nsectors
;
2683 for (unsigned int x
= 0; x
< bank
->num_sectors
; x
++) {
2684 bank
->sectors
[x
].size
= private->sector_size
;
2685 bank
->sectors
[x
].offset
= x
* (private->sector_size
);
2686 /* mark as unknown */
2687 bank
->sectors
[x
].is_erased
= -1;
2688 bank
->sectors
[x
].is_protected
= -1;
2692 private->probed
= true;
2694 r
= sam4_protect_check(bank
);
2698 LOG_DEBUG("Bank = %d, nbanks = %d",
2699 private->bank_number
, private->chip
->details
.n_banks
);
2700 if ((private->bank_number
+ 1) == private->chip
->details
.n_banks
) {
2701 /* read unique id, */
2702 /* it appears to be associated with the *last* flash bank. */
2703 flashd_read_uid(private);
2709 static int sam4_auto_probe(struct flash_bank
*bank
)
2711 struct sam4_bank_private
*private;
2713 private = get_sam4_bank_private(bank
);
2714 if (private && private->probed
)
2717 return sam4_probe(bank
);
2720 static int sam4_erase(struct flash_bank
*bank
, unsigned int first
,
2723 struct sam4_bank_private
*private;
2726 /*16 pages equals 8KB - Same size as a lock region*/
2731 if (bank
->target
->state
!= TARGET_HALTED
) {
2732 LOG_ERROR("Target not halted");
2733 return ERROR_TARGET_NOT_HALTED
;
2736 r
= sam4_auto_probe(bank
);
2737 if (r
!= ERROR_OK
) {
2738 LOG_DEBUG("Here,r=%d", r
);
2742 private = get_sam4_bank_private(bank
);
2743 if (!(private->probed
))
2744 return ERROR_FLASH_BANK_NOT_PROBED
;
2746 if ((first
== 0) && ((last
+ 1) == private->nsectors
)) {
2749 return flashd_erase_entire_bank(private);
2751 LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
2752 LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", first
, last
);
2753 for (unsigned int i
= first
; i
<= last
; i
++) {
2754 /*16 pages equals 8KB - Same size as a lock region*/
2755 r
= flashd_erase_pages(private, (i
* page_count
), page_count
, &status
);
2756 LOG_INFO("Erasing sector: 0x%08x", i
);
2758 LOG_ERROR("SAM4: Error performing Erase page @ lock region number %u",
2760 if (status
& (1 << 2)) {
2761 LOG_ERROR("SAM4: Lock Region %u is locked", i
);
2764 if (status
& (1 << 1)) {
2765 LOG_ERROR("SAM4: Flash Command error @lock region %u", i
);
2773 static int sam4_protect(struct flash_bank
*bank
, int set
, unsigned int first
,
2776 struct sam4_bank_private
*private;
2780 if (bank
->target
->state
!= TARGET_HALTED
) {
2781 LOG_ERROR("Target not halted");
2782 return ERROR_TARGET_NOT_HALTED
;
2785 private = get_sam4_bank_private(bank
);
2786 if (!(private->probed
))
2787 return ERROR_FLASH_BANK_NOT_PROBED
;
2790 r
= flashd_lock(private, first
, last
);
2792 r
= flashd_unlock(private, first
, last
);
2793 LOG_DEBUG("End: r=%d", r
);
2799 static int sam4_page_read(struct sam4_bank_private
*private, unsigned pagenum
, uint8_t *buf
)
2804 adr
= pagenum
* private->page_size
;
2805 adr
= adr
+ private->base_address
;
2807 r
= target_read_memory(private->chip
->target
,
2809 4, /* THIS*MUST*BE* in 32bit values */
2810 private->page_size
/ 4,
2813 LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
2814 (unsigned int)(adr
));
2818 static int sam4_set_wait(struct sam4_bank_private
*private)
2820 uint32_t fmr
; /* EEFC Flash Mode Register */
2823 /* Get flash mode register value */
2824 r
= target_read_u32(private->chip
->target
, private->controller_address
, &fmr
);
2825 if (r
!= ERROR_OK
) {
2826 LOG_ERROR("Error Read failed: read flash mode register");
2830 /* Clear flash wait state field */
2833 /* set FWS (flash wait states) field in the FMR (flash mode register) */
2834 fmr
|= (private->flash_wait_states
<< 8);
2836 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr
)));
2837 r
= target_write_u32(private->bank
->target
, private->controller_address
, fmr
);
2839 LOG_ERROR("Error Write failed: set flash mode register");
2844 static int sam4_page_write(struct sam4_bank_private
*private, unsigned pagenum
, const uint8_t *buf
)
2850 adr
= pagenum
* private->page_size
;
2851 adr
= (adr
+ private->base_address
);
2853 /* 1st sector 8kBytes - page 0 - 15*/
2854 /* 2nd sector 8kBytes - page 16 - 30*/
2855 /* 3rd sector 48kBytes - page 31 - 127*/
2856 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum
, (unsigned int)(adr
));
2857 r
= target_write_memory(private->chip
->target
,
2859 4, /* THIS*MUST*BE* in 32bit values */
2860 private->page_size
/ 4,
2862 if (r
!= ERROR_OK
) {
2863 LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
2864 (unsigned int)(adr
));
2868 r
= efc_perform_command(private,
2869 /* send Erase & Write Page */
2870 AT91C_EFC_FCMD_WP
, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
2875 LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
2876 (unsigned int)(adr
));
2877 if (status
& (1 << 2)) {
2878 LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr
));
2881 if (status
& (1 << 1)) {
2882 LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr
));
2888 static int sam4_write(struct flash_bank
*bank
,
2889 const uint8_t *buffer
,
2897 unsigned page_offset
;
2898 struct sam4_bank_private
*private;
2899 uint8_t *pagebuffer
;
2901 /* in case we bail further below, set this to null */
2904 /* ignore dumb requests */
2910 if (bank
->target
->state
!= TARGET_HALTED
) {
2911 LOG_ERROR("Target not halted");
2912 r
= ERROR_TARGET_NOT_HALTED
;
2916 private = get_sam4_bank_private(bank
);
2917 if (!(private->probed
)) {
2918 r
= ERROR_FLASH_BANK_NOT_PROBED
;
2922 if ((offset
+ count
) > private->size_bytes
) {
2923 LOG_ERROR("Flash write error - past end of bank");
2924 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2925 (unsigned int)(offset
),
2926 (unsigned int)(count
),
2927 (unsigned int)(private->size_bytes
));
2932 pagebuffer
= malloc(private->page_size
);
2934 LOG_ERROR("No memory for %d Byte page buffer", (int)(private->page_size
));
2939 r
= sam4_set_wait(private);
2943 /* what page do we start & end in? */
2944 page_cur
= offset
/ private->page_size
;
2945 page_end
= (offset
+ count
- 1) / private->page_size
;
2947 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset
), (unsigned int)(count
));
2948 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur
), (int)(page_end
));
2950 /* Special case: all one page */
2953 /* (1) non-aligned start */
2954 /* (2) body pages */
2955 /* (3) non-aligned end. */
2957 /* Handle special case - all one page. */
2958 if (page_cur
== page_end
) {
2959 LOG_DEBUG("Special case, all in one page");
2960 r
= sam4_page_read(private, page_cur
, pagebuffer
);
2964 page_offset
= (offset
& (private->page_size
-1));
2965 memcpy(pagebuffer
+ page_offset
,
2969 r
= sam4_page_write(private, page_cur
, pagebuffer
);
2976 /* non-aligned start */
2977 page_offset
= offset
& (private->page_size
- 1);
2979 LOG_DEBUG("Not-Aligned start");
2980 /* read the partial */
2981 r
= sam4_page_read(private, page_cur
, pagebuffer
);
2985 /* over-write with new data */
2986 n
= (private->page_size
- page_offset
);
2987 memcpy(pagebuffer
+ page_offset
,
2991 r
= sam4_page_write(private, page_cur
, pagebuffer
);
3001 /* By checking that offset is correct here, we also
3002 fix a clang warning */
3003 assert(offset
% private->page_size
== 0);
3005 /* intermediate large pages */
3006 /* also - the final *terminal* */
3007 /* if that terminal page is a full page */
3008 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3009 (int)page_cur
, (int)page_end
, (unsigned int)(count
));
3011 while ((page_cur
< page_end
) &&
3012 (count
>= private->page_size
)) {
3013 r
= sam4_page_write(private, page_cur
, buffer
);
3016 count
-= private->page_size
;
3017 buffer
+= private->page_size
;
3021 /* terminal partial page? */
3023 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count
));
3024 /* we have a partial page */
3025 r
= sam4_page_read(private, page_cur
, pagebuffer
);
3028 /* data goes at start */
3029 memcpy(pagebuffer
, buffer
, count
);
3030 r
= sam4_page_write(private, page_cur
, pagebuffer
);
3041 COMMAND_HANDLER(sam4_handle_info_command
)
3043 struct sam4_chip
*chip
;
3044 chip
= get_current_sam4(CMD
);
3051 /* bank0 must exist before we can do anything */
3052 if (!chip
->details
.bank
[0].bank
) {
3056 "Please define bank %d via command: flash bank %s ... ",
3058 at91sam4_flash
.name
);
3062 /* if bank 0 is not probed, then probe it */
3063 if (!(chip
->details
.bank
[0].probed
)) {
3064 r
= sam4_auto_probe(chip
->details
.bank
[0].bank
);
3068 /* above guarantees the "chip details" structure is valid */
3069 /* and thus, bank private areas are valid */
3070 /* and we have a SAM4 chip, what a concept! */
3072 /* auto-probe other banks, 0 done above */
3073 for (x
= 1; x
< SAM4_MAX_FLASH_BANKS
; x
++) {
3074 /* skip banks not present */
3075 if (!(chip
->details
.bank
[x
].present
))
3078 if (!chip
->details
.bank
[x
].bank
)
3081 if (chip
->details
.bank
[x
].probed
)
3084 r
= sam4_auto_probe(chip
->details
.bank
[x
].bank
);
3089 r
= sam4_get_info(chip
);
3090 if (r
!= ERROR_OK
) {
3091 LOG_DEBUG("Sam4Info, Failed %d", r
);
3098 COMMAND_HANDLER(sam4_handle_gpnvm_command
)
3102 struct sam4_chip
*chip
;
3104 chip
= get_current_sam4(CMD
);
3108 if (chip
->target
->state
!= TARGET_HALTED
) {
3109 LOG_ERROR("sam4 - target not halted");
3110 return ERROR_TARGET_NOT_HALTED
;
3113 if (!chip
->details
.bank
[0].bank
) {
3114 command_print(CMD
, "Bank0 must be defined first via: flash bank %s ...",
3115 at91sam4_flash
.name
);
3118 if (!chip
->details
.bank
[0].probed
) {
3119 r
= sam4_auto_probe(chip
->details
.bank
[0].bank
);
3126 return ERROR_COMMAND_SYNTAX_ERROR
;
3133 if ((strcmp(CMD_ARGV
[0], "show") == 0) && (strcmp(CMD_ARGV
[1], "all") == 0))
3137 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], v32
);
3143 if (strcmp("show", CMD_ARGV
[0]) == 0) {
3147 for (x
= 0; x
< chip
->details
.n_gpnvms
; x
++) {
3148 r
= flashd_get_gpnvm(&(chip
->details
.bank
[0]), x
, &v
);
3151 command_print(CMD
, "sam4-gpnvm%u: %u", x
, v
);
3155 if ((who
>= 0) && (((unsigned)(who
)) < chip
->details
.n_gpnvms
)) {
3156 r
= flashd_get_gpnvm(&(chip
->details
.bank
[0]), who
, &v
);
3158 command_print(CMD
, "sam4-gpnvm%u: %u", who
, v
);
3161 command_print(CMD
, "sam4-gpnvm invalid GPNVM: %u", who
);
3162 return ERROR_COMMAND_SYNTAX_ERROR
;
3167 command_print(CMD
, "Missing GPNVM number");
3168 return ERROR_COMMAND_SYNTAX_ERROR
;
3171 if (strcmp("set", CMD_ARGV
[0]) == 0)
3172 r
= flashd_set_gpnvm(&(chip
->details
.bank
[0]), who
);
3173 else if ((strcmp("clr", CMD_ARGV
[0]) == 0) ||
3174 (strcmp("clear", CMD_ARGV
[0]) == 0)) /* quietly accept both */
3175 r
= flashd_clr_gpnvm(&(chip
->details
.bank
[0]), who
);
3177 command_print(CMD
, "Unknown command: %s", CMD_ARGV
[0]);
3178 r
= ERROR_COMMAND_SYNTAX_ERROR
;
3183 COMMAND_HANDLER(sam4_handle_slowclk_command
)
3185 struct sam4_chip
*chip
;
3187 chip
= get_current_sam4(CMD
);
3199 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], v
);
3201 /* absurd slow clock of 200Khz? */
3202 command_print(CMD
, "Absurd/illegal slow clock freq: %d\n", (int)(v
));
3203 return ERROR_COMMAND_SYNTAX_ERROR
;
3205 chip
->cfg
.slow_freq
= v
;
3210 command_print(CMD
, "Too many parameters");
3211 return ERROR_COMMAND_SYNTAX_ERROR
;
3213 command_print(CMD
, "Slowclk freq: %d.%03dkhz",
3214 (int)(chip
->cfg
.slow_freq
/ 1000),
3215 (int)(chip
->cfg
.slow_freq
% 1000));
3219 static const struct command_registration at91sam4_exec_command_handlers
[] = {
3222 .handler
= sam4_handle_gpnvm_command
,
3223 .mode
= COMMAND_EXEC
,
3224 .usage
= "[('clr'|'set'|'show') bitnum]",
3225 .help
= "Without arguments, shows all bits in the gpnvm "
3226 "register. Otherwise, clears, sets, or shows one "
3227 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3231 .handler
= sam4_handle_info_command
,
3232 .mode
= COMMAND_EXEC
,
3233 .help
= "Print information about the current at91sam4 chip "
3234 "and its flash configuration.",
3239 .handler
= sam4_handle_slowclk_command
,
3240 .mode
= COMMAND_EXEC
,
3241 .usage
= "[clock_hz]",
3242 .help
= "Display or set the slowclock frequency "
3243 "(default 32768 Hz).",
3245 COMMAND_REGISTRATION_DONE
3247 static const struct command_registration at91sam4_command_handlers
[] = {
3250 .mode
= COMMAND_ANY
,
3251 .help
= "at91sam4 flash command group",
3253 .chain
= at91sam4_exec_command_handlers
,
3255 COMMAND_REGISTRATION_DONE
3258 const struct flash_driver at91sam4_flash
= {
3260 .commands
= at91sam4_command_handlers
,
3261 .flash_bank_command
= sam4_flash_bank_command
,
3262 .erase
= sam4_erase
,
3263 .protect
= sam4_protect
,
3264 .write
= sam4_write
,
3265 .read
= default_flash_read
,
3266 .probe
= sam4_probe
,
3267 .auto_probe
= sam4_auto_probe
,
3268 .erase_check
= default_flash_blank_check
,
3269 .protect_check
= sam4_protect_check
,
3271 .free_driver_priv
= sam4_free_driver_priv
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)