Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
flash/nor/at91sam4: fix sam4sa16c flash banks and its gpnvms count
[openocd.git] / src / flash / nor / at91sam4.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
4 * *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
7 * *
8 * Copyright (C) 2011 by Olivier Schonken, Jim Norris *
9 * (at91sam3x* & at91sam4 support)* *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ****************************************************************************/
24
25 /* Some of the the lower level code was based on code supplied by
26 * ATMEL under this copyright. */
27
28 /* BEGIN ATMEL COPYRIGHT */
29 /* ----------------------------------------------------------------------------
30 * ATMEL Microcontroller Software Support
31 * ----------------------------------------------------------------------------
32 * Copyright (c) 2009, Atmel Corporation
33 *
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions are met:
38 *
39 * - Redistributions of source code must retain the above copyright notice,
40 * this list of conditions and the disclaimer below.
41 *
42 * Atmel's name may not be used to endorse or promote products derived from
43 * this software without specific prior written permission.
44 *
45 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
48 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
51 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
52 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
53 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
54 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 * ----------------------------------------------------------------------------
56 */
57 /* END ATMEL COPYRIGHT */
58
59 #ifdef HAVE_CONFIG_H
60 #include "config.h"
61 #endif
62
63 #include "imp.h"
64 #include <helper/time_support.h>
65
66 #define REG_NAME_WIDTH (12)
67
68 /* at91sam4s/at91sam4e/at91sam4c series (has always one flash bank)*/
69 #define FLASH_BANK_BASE_S 0x00400000
70 #define FLASH_BANK_BASE_C 0x01000000
71
72 /* at91sam4sd series (two one flash banks), first bank address */
73 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
74 /* at91sam4sd16x, second bank address */
75 #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
76 /* at91sam4sd32x, second bank address */
77 #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
78
79 /* at91sam4c32x, first and second bank address */
80 #define FLASH_BANK0_BASE_C32 FLASH_BANK_BASE_C
81 #define FLASH_BANK1_BASE_C32 (FLASH_BANK_BASE_C+(2048*1024/2))
82
83 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
84 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
85 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
86 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
87 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
88 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
89 /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
90 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
91 #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
92 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
93 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
94 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
95 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
96 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
97 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
98 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
99 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
100
101 #define offset_EFC_FMR 0
102 #define offset_EFC_FCR 4
103 #define offset_EFC_FSR 8
104 #define offset_EFC_FRR 12
105
106 extern struct flash_driver at91sam4_flash;
107
108 static float _tomhz(uint32_t freq_hz)
109 {
110 float f;
111
112 f = ((float)(freq_hz)) / 1000000.0;
113 return f;
114 }
115
116 /* How the chip is configured. */
117 struct sam4_cfg {
118 uint32_t unique_id[4];
119
120 uint32_t slow_freq;
121 uint32_t rc_freq;
122 uint32_t mainosc_freq;
123 uint32_t plla_freq;
124 uint32_t mclk_freq;
125 uint32_t cpu_freq;
126 uint32_t fclk_freq;
127 uint32_t pclk0_freq;
128 uint32_t pclk1_freq;
129 uint32_t pclk2_freq;
130
131
132 #define SAM4_CHIPID_CIDR (0x400E0740)
133 uint32_t CHIPID_CIDR;
134 #define SAM4_CHIPID_EXID (0x400E0744)
135 uint32_t CHIPID_EXID;
136
137 #define SAM4_PMC_BASE (0x400E0400)
138 #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
139 uint32_t PMC_SCSR;
140 #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
141 uint32_t PMC_PCSR;
142 #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
143 uint32_t CKGR_UCKR;
144 #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
145 uint32_t CKGR_MOR;
146 #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
147 uint32_t CKGR_MCFR;
148 #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
149 uint32_t CKGR_PLLAR;
150 #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
151 uint32_t PMC_MCKR;
152 #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
153 uint32_t PMC_PCK0;
154 #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
155 uint32_t PMC_PCK1;
156 #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
157 uint32_t PMC_PCK2;
158 #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
159 uint32_t PMC_SR;
160 #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
161 uint32_t PMC_IMR;
162 #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
163 uint32_t PMC_FSMR;
164 #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
165 uint32_t PMC_FSPR;
166 };
167
168 struct sam4_bank_private {
169 int probed;
170 /* DANGER: THERE ARE DRAGONS HERE.. */
171 /* NOTE: If you add more 'ghost' pointers */
172 /* be aware that you must *manually* update */
173 /* these pointers in the function sam4_GetDetails() */
174 /* See the comment "Here there be dragons" */
175
176 /* so we can find the chip we belong to */
177 struct sam4_chip *pChip;
178 /* so we can find the original bank pointer */
179 struct flash_bank *pBank;
180 unsigned bank_number;
181 uint32_t controller_address;
182 uint32_t base_address;
183 uint32_t flash_wait_states;
184 bool present;
185 unsigned size_bytes;
186 unsigned nsectors;
187 unsigned sector_size;
188 unsigned page_size;
189 };
190
191 struct sam4_chip_details {
192 /* THERE ARE DRAGONS HERE.. */
193 /* note: If you add pointers here */
194 /* be careful about them as they */
195 /* may need to be updated inside */
196 /* the function: "sam4_GetDetails() */
197 /* which copy/overwrites the */
198 /* 'runtime' copy of this structure */
199 uint32_t chipid_cidr;
200 const char *name;
201
202 unsigned n_gpnvms;
203 #define SAM4_N_NVM_BITS 3
204 unsigned gpnvm[SAM4_N_NVM_BITS];
205 unsigned total_flash_size;
206 unsigned total_sram_size;
207 unsigned n_banks;
208 #define SAM4_MAX_FLASH_BANKS 2
209 /* these are "initialized" from the global const data */
210 struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS];
211 };
212
213 struct sam4_chip {
214 struct sam4_chip *next;
215 int probed;
216
217 /* this is "initialized" from the global const structure */
218 struct sam4_chip_details details;
219 struct target *target;
220 struct sam4_cfg cfg;
221 };
222
223
224 struct sam4_reg_list {
225 uint32_t address; size_t struct_offset; const char *name;
226 void (*explain_func)(struct sam4_chip *pInfo);
227 };
228
229 static struct sam4_chip *all_sam4_chips;
230
231 static struct sam4_chip *get_current_sam4(struct command_context *cmd_ctx)
232 {
233 struct target *t;
234 static struct sam4_chip *p;
235
236 t = get_current_target(cmd_ctx);
237 if (!t) {
238 command_print(cmd_ctx, "No current target?");
239 return NULL;
240 }
241
242 p = all_sam4_chips;
243 if (!p) {
244 /* this should not happen */
245 /* the command is not registered until the chip is created? */
246 command_print(cmd_ctx, "No SAM4 chips exist?");
247 return NULL;
248 }
249
250 while (p) {
251 if (p->target == t)
252 return p;
253 p = p->next;
254 }
255 command_print(cmd_ctx, "Cannot find SAM4 chip?");
256 return NULL;
257 }
258
259 /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
260 /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
261 /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
262 /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
263
264 /* these are used to *initialize* the "pChip->details" structure. */
265 static const struct sam4_chip_details all_sam4_details[] = {
266 /* Start at91sam4c* series */
267 /* at91sam4c32e - LQFP144 */
268 {
269 .chipid_cidr = 0xA66D0EE0,
270 .name = "at91sam4c32e",
271 .total_flash_size = 2024 * 1024,
272 .total_sram_size = 256 * 1024,
273 .n_gpnvms = 3,
274 .n_banks = 2,
275 /* .bank[0] = { */
276 {
277 {
278 .probed = 0,
279 .pChip = NULL,
280 .pBank = NULL,
281 .bank_number = 0,
282 .base_address = FLASH_BANK0_BASE_C32,
283 .controller_address = 0x400e0a00,
284 .flash_wait_states = 5,
285 .present = 1,
286 .size_bytes = 1024 * 1024,
287 .nsectors = 128,
288 .sector_size = 8192,
289 .page_size = 512,
290 },
291 /* .bank[1] = { */
292 {
293 .probed = 0,
294 .pChip = NULL,
295 .pBank = NULL,
296 .bank_number = 1,
297 .base_address = FLASH_BANK1_BASE_C32,
298 .controller_address = 0x400e0c00,
299 .flash_wait_states = 5,
300 .present = 1,
301 .size_bytes = 1024 * 1024,
302 .nsectors = 128,
303 .sector_size = 8192,
304 .page_size = 512,
305 },
306 },
307 },
308 /* at91sam4c32c - LQFP100 */
309 {
310 .chipid_cidr = 0xA64D0EE0,
311 .name = "at91sam4c32c",
312 .total_flash_size = 2024 * 1024,
313 .total_sram_size = 256 * 1024,
314 .n_gpnvms = 3,
315 .n_banks = 2,
316 /* .bank[0] = { */
317 {
318 {
319 .probed = 0,
320 .pChip = NULL,
321 .pBank = NULL,
322 .bank_number = 0,
323 .base_address = FLASH_BANK0_BASE_C32,
324 .controller_address = 0x400e0a00,
325 .flash_wait_states = 5,
326 .present = 1,
327 .size_bytes = 1024 * 1024,
328 .nsectors = 128,
329 .sector_size = 8192,
330 .page_size = 512,
331 },
332 /* .bank[1] = { */
333 {
334 .probed = 0,
335 .pChip = NULL,
336 .pBank = NULL,
337 .bank_number = 1,
338 .base_address = FLASH_BANK1_BASE_C32,
339 .controller_address = 0x400e0c00,
340 .flash_wait_states = 5,
341 .present = 1,
342 .size_bytes = 1024 * 1024,
343 .nsectors = 128,
344 .sector_size = 8192,
345 .page_size = 512,
346 },
347 },
348 },
349 /* at91sam4c16c - LQFP100 */
350 {
351 .chipid_cidr = 0xA64C0CE0,
352 .name = "at91sam4c16c",
353 .total_flash_size = 1024 * 1024,
354 .total_sram_size = 128 * 1024,
355 .n_gpnvms = 2,
356 .n_banks = 1,
357 {
358 /* .bank[0] = {*/
359 {
360 .probed = 0,
361 .pChip = NULL,
362 .pBank = NULL,
363 .bank_number = 0,
364 .base_address = FLASH_BANK_BASE_C,
365 .controller_address = 0x400e0a00,
366 .flash_wait_states = 5,
367 .present = 1,
368 .size_bytes = 1024 * 1024,
369 .nsectors = 128,
370 .sector_size = 8192,
371 .page_size = 512,
372 },
373 /* .bank[1] = {*/
374 {
375 .present = 0,
376 .probed = 0,
377 .bank_number = 1,
378
379 },
380 },
381 },
382 /* at91sam4c8c - LQFP100 */
383 {
384 .chipid_cidr = 0xA64C0AE0,
385 .name = "at91sam4c8c",
386 .total_flash_size = 512 * 1024,
387 .total_sram_size = 128 * 1024,
388 .n_gpnvms = 2,
389 .n_banks = 1,
390 {
391 /* .bank[0] = {*/
392 {
393 .probed = 0,
394 .pChip = NULL,
395 .pBank = NULL,
396 .bank_number = 0,
397 .base_address = FLASH_BANK_BASE_C,
398 .controller_address = 0x400e0a00,
399 .flash_wait_states = 5,
400 .present = 1,
401 .size_bytes = 512 * 1024,
402 .nsectors = 64,
403 .sector_size = 8192,
404 .page_size = 512,
405 },
406 /* .bank[1] = {*/
407 {
408 .present = 0,
409 .probed = 0,
410 .bank_number = 1,
411
412 },
413 },
414 },
415 /* at91sam4c4c (rev B) - LQFP100 */
416 {
417 .chipid_cidr = 0xA64C0CE5,
418 .name = "at91sam4c4c",
419 .total_flash_size = 256 * 1024,
420 .total_sram_size = 128 * 1024,
421 .n_gpnvms = 2,
422 .n_banks = 1,
423 {
424 /* .bank[0] = {*/
425 {
426 .probed = 0,
427 .pChip = NULL,
428 .pBank = NULL,
429 .bank_number = 0,
430 .base_address = FLASH_BANK_BASE_C,
431 .controller_address = 0x400e0a00,
432 .flash_wait_states = 5,
433 .present = 1,
434 .size_bytes = 256 * 1024,
435 .nsectors = 32,
436 .sector_size = 8192,
437 .page_size = 512,
438 },
439 /* .bank[1] = {*/
440 {
441 .present = 0,
442 .probed = 0,
443 .bank_number = 1,
444
445 },
446 },
447 },
448
449 /* Start at91sam4e* series */
450 /*atsam4e16e - LQFP144/LFBGA144*/
451 {
452 .chipid_cidr = 0xA3CC0CE0,
453 .name = "at91sam4e16e",
454 .total_flash_size = 1024 * 1024,
455 .total_sram_size = 128 * 1024,
456 .n_gpnvms = 2,
457 .n_banks = 1,
458 {
459 /* .bank[0] = {*/
460 {
461 .probed = 0,
462 .pChip = NULL,
463 .pBank = NULL,
464 .bank_number = 0,
465 .base_address = FLASH_BANK_BASE_S,
466 .controller_address = 0x400e0a00,
467 .flash_wait_states = 5,
468 .present = 1,
469 .size_bytes = 1024 * 1024,
470 .nsectors = 128,
471 .sector_size = 8192,
472 .page_size = 512,
473 },
474 /* .bank[1] = {*/
475 {
476 .present = 0,
477 .probed = 0,
478 .bank_number = 1,
479
480 },
481 },
482 },
483
484 /* Start at91sam4n* series */
485 /*atsam4n8a - LQFP48/QFN48*/
486 {
487 .chipid_cidr = 0x293B0AE0,
488 .name = "at91sam4n8a",
489 .total_flash_size = 512 * 1024,
490 .total_sram_size = 64 * 1024,
491 .n_gpnvms = 2,
492 .n_banks = 1,
493 {
494 /* .bank[0] = {*/
495 {
496 .probed = 0,
497 .pChip = NULL,
498 .pBank = NULL,
499 .bank_number = 0,
500 .base_address = FLASH_BANK_BASE_S,
501 .controller_address = 0x400e0a00,
502 .flash_wait_states = 5,
503 .present = 1,
504 .size_bytes = 512 * 1024,
505 .nsectors = 64,
506 .sector_size = 8192,
507 .page_size = 512,
508 },
509 /* .bank[1] = {*/
510 {
511 .present = 0,
512 .probed = 0,
513 .bank_number = 1,
514
515 },
516 },
517 },
518 /*atsam4n8b - LQFP64/QFN64*/
519 {
520 .chipid_cidr = 0x294B0AE0,
521 .name = "at91sam4n8b",
522 .total_flash_size = 512 * 1024,
523 .total_sram_size = 64 * 1024,
524 .n_gpnvms = 2,
525 .n_banks = 1,
526 {
527 /* .bank[0] = {*/
528 {
529 .probed = 0,
530 .pChip = NULL,
531 .pBank = NULL,
532 .bank_number = 0,
533 .base_address = FLASH_BANK_BASE_S,
534 .controller_address = 0x400e0a00,
535 .flash_wait_states = 5,
536 .present = 1,
537 .size_bytes = 512 * 1024,
538 .nsectors = 64,
539 .sector_size = 8192,
540 .page_size = 512,
541 },
542 /* .bank[1] = {*/
543 {
544 .present = 0,
545 .probed = 0,
546 .bank_number = 1,
547
548 },
549 },
550 },
551 /*atsam4n8c - LQFP100/TFBGA100/VFBGA100*/
552 {
553 .chipid_cidr = 0x295B0AE0,
554 .name = "at91sam4n8c",
555 .total_flash_size = 512 * 1024,
556 .total_sram_size = 64 * 1024,
557 .n_gpnvms = 2,
558 .n_banks = 1,
559 {
560 /* .bank[0] = {*/
561 {
562 .probed = 0,
563 .pChip = NULL,
564 .pBank = NULL,
565 .bank_number = 0,
566 .base_address = FLASH_BANK_BASE_S,
567 .controller_address = 0x400e0a00,
568 .flash_wait_states = 5,
569 .present = 1,
570 .size_bytes = 512 * 1024,
571 .nsectors = 64,
572 .sector_size = 8192,
573 .page_size = 512,
574 },
575 /* .bank[1] = {*/
576 {
577 .present = 0,
578 .probed = 0,
579 .bank_number = 1,
580
581 },
582 },
583 },
584 /*atsam4n16b - LQFP64/QFN64*/
585 {
586 .chipid_cidr = 0x29460CE0,
587 .name = "at91sam4n16b",
588 .total_flash_size = 1024 * 1024,
589 .total_sram_size = 80 * 1024,
590 .n_gpnvms = 2,
591 .n_banks = 1,
592 {
593 /* .bank[0] = {*/
594 {
595 .probed = 0,
596 .pChip = NULL,
597 .pBank = NULL,
598 .bank_number = 0,
599 .base_address = FLASH_BANK_BASE_S,
600 .controller_address = 0x400e0a00,
601 .flash_wait_states = 5,
602 .present = 1,
603 .size_bytes = 1024 * 1024,
604 .nsectors = 128,
605 .sector_size = 8192,
606 .page_size = 512,
607 },
608 /* .bank[1] = {*/
609 {
610 .present = 0,
611 .probed = 0,
612 .bank_number = 1,
613
614 },
615 },
616 },
617 /*atsam4n16c - LQFP100/TFBGA100/VFBGA100*/
618 {
619 .chipid_cidr = 0x29560CE0,
620 .name = "at91sam4n16c",
621 .total_flash_size = 1024 * 1024,
622 .total_sram_size = 80 * 1024,
623 .n_gpnvms = 2,
624 .n_banks = 1,
625 {
626 /* .bank[0] = {*/
627 {
628 .probed = 0,
629 .pChip = NULL,
630 .pBank = NULL,
631 .bank_number = 0,
632 .base_address = FLASH_BANK_BASE_S,
633 .controller_address = 0x400e0a00,
634 .flash_wait_states = 5,
635 .present = 1,
636 .size_bytes = 1024 * 1024,
637 .nsectors = 128,
638 .sector_size = 8192,
639 .page_size = 512,
640 },
641 /* .bank[1] = {*/
642 {
643 .present = 0,
644 .probed = 0,
645 .bank_number = 1,
646
647 },
648 },
649 },
650
651 /* Start at91sam4s* series */
652 /*atsam4s16c - LQFP100/BGA100*/
653 {
654 .chipid_cidr = 0x28AC0CE0,
655 .name = "at91sam4s16c",
656 .total_flash_size = 1024 * 1024,
657 .total_sram_size = 128 * 1024,
658 .n_gpnvms = 2,
659 .n_banks = 1,
660 {
661 /* .bank[0] = {*/
662 {
663 .probed = 0,
664 .pChip = NULL,
665 .pBank = NULL,
666 .bank_number = 0,
667 .base_address = FLASH_BANK_BASE_S,
668 .controller_address = 0x400e0a00,
669 .flash_wait_states = 5,
670 .present = 1,
671 .size_bytes = 1024 * 1024,
672 .nsectors = 128,
673 .sector_size = 8192,
674 .page_size = 512,
675 },
676 /* .bank[1] = {*/
677 {
678 .present = 0,
679 .probed = 0,
680 .bank_number = 1,
681
682 },
683 },
684 },
685 /*at91sam4sa16c - TFBGA100/VFBGA100/LQFP100*/
686 {
687 .chipid_cidr = 0x28a70ce0,
688 .name = "at91sam4sa16c",
689 .total_flash_size = 1024 * 1024,
690 .total_sram_size = 160 * 1024,
691 .n_gpnvms = 2,
692 .n_banks = 1,
693
694 /* .bank[0] = { */
695 {
696 {
697 .probed = 0,
698 .pChip = NULL,
699 .pBank = NULL,
700 .bank_number = 0,
701 .base_address = FLASH_BANK_BASE_S,
702 .controller_address = 0x400e0a00,
703 .flash_wait_states = 5,
704 .present = 1,
705 .size_bytes = 1024 * 1024,
706 .nsectors = 128,
707 .sector_size = 8192,
708 .page_size = 512,
709 },
710 /* .bank[1] = {*/
711 {
712 .present = 0,
713 .probed = 0,
714 .bank_number = 1,
715
716 },
717 },
718 },
719 /*atsam4s16b - LQFP64/QFN64/WLCSP64*/
720 {
721 .chipid_cidr = 0x289C0CE0,
722 .name = "at91sam4s16b",
723 .total_flash_size = 1024 * 1024,
724 .total_sram_size = 128 * 1024,
725 .n_gpnvms = 2,
726 .n_banks = 1,
727 {
728 /* .bank[0] = {*/
729 {
730 .probed = 0,
731 .pChip = NULL,
732 .pBank = NULL,
733 .bank_number = 0,
734 .base_address = FLASH_BANK_BASE_S,
735 .controller_address = 0x400e0a00,
736 .flash_wait_states = 5,
737 .present = 1,
738 .size_bytes = 1024 * 1024,
739 .nsectors = 128,
740 .sector_size = 8192,
741 .page_size = 512,
742 },
743 /* .bank[1] = {*/
744 {
745 .present = 0,
746 .probed = 0,
747 .bank_number = 1,
748
749 },
750 },
751 },
752 /*atsam4sa16b - LQFP64/QFN64*/
753 {
754 .chipid_cidr = 0x28970CE0,
755 .name = "at91sam4sa16b",
756 .total_flash_size = 1024 * 1024,
757 .total_sram_size = 160 * 1024,
758 .n_gpnvms = 2,
759 .n_banks = 1,
760 {
761 /* .bank[0] = {*/
762 {
763 .probed = 0,
764 .pChip = NULL,
765 .pBank = NULL,
766 .bank_number = 0,
767 .base_address = FLASH_BANK_BASE_S,
768 .controller_address = 0x400e0a00,
769 .flash_wait_states = 5,
770 .present = 1,
771 .size_bytes = 1024 * 1024,
772 .nsectors = 128,
773 .sector_size = 8192,
774 .page_size = 512,
775 },
776 /* .bank[1] = {*/
777 {
778 .present = 0,
779 .probed = 0,
780 .bank_number = 1,
781
782 },
783 },
784 },
785 /*atsam4s16a - LQFP48/QFN48*/
786 {
787 .chipid_cidr = 0x288C0CE0,
788 .name = "at91sam4s16a",
789 .total_flash_size = 1024 * 1024,
790 .total_sram_size = 128 * 1024,
791 .n_gpnvms = 2,
792 .n_banks = 1,
793 {
794 /* .bank[0] = {*/
795 {
796 .probed = 0,
797 .pChip = NULL,
798 .pBank = NULL,
799 .bank_number = 0,
800 .base_address = FLASH_BANK_BASE_S,
801 .controller_address = 0x400e0a00,
802 .flash_wait_states = 5,
803 .present = 1,
804 .size_bytes = 1024 * 1024,
805 .nsectors = 128,
806 .sector_size = 8192,
807 .page_size = 512,
808 },
809 /* .bank[1] = {*/
810 {
811 .present = 0,
812 .probed = 0,
813 .bank_number = 1,
814
815 },
816 },
817 },
818 /*atsam4s8c - LQFP100/BGA100*/
819 {
820 .chipid_cidr = 0x28AC0AE0,
821 .name = "at91sam4s8c",
822 .total_flash_size = 512 * 1024,
823 .total_sram_size = 128 * 1024,
824 .n_gpnvms = 2,
825 .n_banks = 1,
826 {
827 /* .bank[0] = {*/
828 {
829 .probed = 0,
830 .pChip = NULL,
831 .pBank = NULL,
832 .bank_number = 0,
833 .base_address = FLASH_BANK_BASE_S,
834 .controller_address = 0x400e0a00,
835 .flash_wait_states = 5,
836 .present = 1,
837 .size_bytes = 512 * 1024,
838 .nsectors = 64,
839 .sector_size = 8192,
840 .page_size = 512,
841 },
842 /* .bank[1] = {*/
843 {
844 .present = 0,
845 .probed = 0,
846 .bank_number = 1,
847
848 },
849 },
850 },
851 /*atsam4s8b - LQFP64/QFN64/WLCSP64*/
852 {
853 .chipid_cidr = 0x289C0AE0,
854 .name = "at91sam4s8b",
855 .total_flash_size = 512 * 1024,
856 .total_sram_size = 128 * 1024,
857 .n_gpnvms = 2,
858 .n_banks = 1,
859 {
860 /* .bank[0] = {*/
861 {
862 .probed = 0,
863 .pChip = NULL,
864 .pBank = NULL,
865 .bank_number = 0,
866 .base_address = FLASH_BANK_BASE_S,
867 .controller_address = 0x400e0a00,
868 .flash_wait_states = 5,
869 .present = 1,
870 .size_bytes = 512 * 1024,
871 .nsectors = 64,
872 .sector_size = 8192,
873 .page_size = 512,
874 },
875 /* .bank[1] = {*/
876 {
877 .present = 0,
878 .probed = 0,
879 .bank_number = 1,
880
881 },
882 },
883 },
884 /*atsam4s8a - LQFP48/BGA48*/
885 {
886 .chipid_cidr = 0x288C0AE0,
887 .name = "at91sam4s8a",
888 .total_flash_size = 512 * 1024,
889 .total_sram_size = 128 * 1024,
890 .n_gpnvms = 2,
891 .n_banks = 1,
892 {
893 /* .bank[0] = {*/
894 {
895 .probed = 0,
896 .pChip = NULL,
897 .pBank = NULL,
898 .bank_number = 0,
899 .base_address = FLASH_BANK_BASE_S,
900 .controller_address = 0x400e0a00,
901 .flash_wait_states = 5,
902 .present = 1,
903 .size_bytes = 512 * 1024,
904 .nsectors = 64,
905 .sector_size = 8192,
906 .page_size = 512,
907 },
908 /* .bank[1] = {*/
909 {
910 .present = 0,
911 .probed = 0,
912 .bank_number = 1,
913
914 },
915 },
916 },
917
918 /*atsam4s4c - LQFP100/BGA100*/
919 {
920 .chipid_cidr = 0x28ab09e0,
921 .name = "at91sam4s4c",
922 .total_flash_size = 256 * 1024,
923 .total_sram_size = 64 * 1024,
924 .n_gpnvms = 2,
925 .n_banks = 1,
926 {
927 /* .bank[0] = {*/
928 {
929 .probed = 0,
930 .pChip = NULL,
931 .pBank = NULL,
932 .bank_number = 0,
933 .base_address = FLASH_BANK_BASE_S,
934 .controller_address = 0x400e0a00,
935 .flash_wait_states = 5,
936 .present = 1,
937 .size_bytes = 256 * 1024,
938 .nsectors = 32,
939 .sector_size = 8192,
940 .page_size = 512,
941 },
942 /* .bank[1] = {*/
943 {
944 .present = 0,
945 .probed = 0,
946 .bank_number = 1,
947
948 },
949 },
950 },
951
952 /*atsam4s4b - LQFP64/QFN64/WLCSP64*/
953 {
954 .chipid_cidr = 0x289b09e0,
955 .name = "at91sam4s4b",
956 .total_flash_size = 256 * 1024,
957 .total_sram_size = 64 * 1024,
958 .n_gpnvms = 2,
959 .n_banks = 1,
960 {
961 /* .bank[0] = {*/
962 {
963 .probed = 0,
964 .pChip = NULL,
965 .pBank = NULL,
966 .bank_number = 0,
967 .base_address = FLASH_BANK_BASE_S,
968 .controller_address = 0x400e0a00,
969 .flash_wait_states = 5,
970 .present = 1,
971 .size_bytes = 256 * 1024,
972 .nsectors = 32,
973 .sector_size = 8192,
974 .page_size = 512,
975 },
976 /* .bank[1] = {*/
977 {
978 .present = 0,
979 .probed = 0,
980 .bank_number = 1,
981
982 },
983 },
984 },
985
986 /*atsam4s4a - LQFP48/QFN48*/
987 {
988 .chipid_cidr = 0x288b09e0,
989 .name = "at91sam4s4a",
990 .total_flash_size = 256 * 1024,
991 .total_sram_size = 64 * 1024,
992 .n_gpnvms = 2,
993 .n_banks = 1,
994 {
995 /* .bank[0] = {*/
996 {
997 .probed = 0,
998 .pChip = NULL,
999 .pBank = NULL,
1000 .bank_number = 0,
1001 .base_address = FLASH_BANK_BASE_S,
1002 .controller_address = 0x400e0a00,
1003 .flash_wait_states = 5,
1004 .present = 1,
1005 .size_bytes = 256 * 1024,
1006 .nsectors = 32,
1007 .sector_size = 8192,
1008 .page_size = 512,
1009 },
1010 /* .bank[1] = {*/
1011 {
1012 .present = 0,
1013 .probed = 0,
1014 .bank_number = 1,
1015
1016 },
1017 },
1018 },
1019
1020 /*atsam4s2c - LQFP100/BGA100*/
1021 {
1022 .chipid_cidr = 0x28ab07e0,
1023 .name = "at91sam4s2c",
1024 .total_flash_size = 128 * 1024,
1025 .total_sram_size = 64 * 1024,
1026 .n_gpnvms = 2,
1027 .n_banks = 1,
1028 {
1029 /* .bank[0] = {*/
1030 {
1031 .probed = 0,
1032 .pChip = NULL,
1033 .pBank = NULL,
1034 .bank_number = 0,
1035 .base_address = FLASH_BANK_BASE_S,
1036 .controller_address = 0x400e0a00,
1037 .flash_wait_states = 5,
1038 .present = 1,
1039 .size_bytes = 128 * 1024,
1040 .nsectors = 16,
1041 .sector_size = 8192,
1042 .page_size = 512,
1043 },
1044 /* .bank[1] = {*/
1045 {
1046 .present = 0,
1047 .probed = 0,
1048 .bank_number = 1,
1049
1050 },
1051 },
1052 },
1053
1054 /*atsam4s2b - LQPF64/QFN64/WLCSP64*/
1055 {
1056 .chipid_cidr = 0x289b07e0,
1057 .name = "at91sam4s2b",
1058 .total_flash_size = 128 * 1024,
1059 .total_sram_size = 64 * 1024,
1060 .n_gpnvms = 2,
1061 .n_banks = 1,
1062 {
1063 /* .bank[0] = {*/
1064 {
1065 .probed = 0,
1066 .pChip = NULL,
1067 .pBank = NULL,
1068 .bank_number = 0,
1069 .base_address = FLASH_BANK_BASE_S,
1070 .controller_address = 0x400e0a00,
1071 .flash_wait_states = 5,
1072 .present = 1,
1073 .size_bytes = 128 * 1024,
1074 .nsectors = 16,
1075 .sector_size = 8192,
1076 .page_size = 512,
1077 },
1078 /* .bank[1] = {*/
1079 {
1080 .present = 0,
1081 .probed = 0,
1082 .bank_number = 1,
1083
1084 },
1085 },
1086 },
1087
1088 /*atsam4s2a - LQFP48/QFN48*/
1089 {
1090 .chipid_cidr = 0x288b07e0,
1091 .name = "at91sam4s2a",
1092 .total_flash_size = 128 * 1024,
1093 .total_sram_size = 64 * 1024,
1094 .n_gpnvms = 2,
1095 .n_banks = 1,
1096 {
1097 /* .bank[0] = {*/
1098 {
1099 .probed = 0,
1100 .pChip = NULL,
1101 .pBank = NULL,
1102 .bank_number = 0,
1103 .base_address = FLASH_BANK_BASE_S,
1104 .controller_address = 0x400e0a00,
1105 .flash_wait_states = 5,
1106 .present = 1,
1107 .size_bytes = 128 * 1024,
1108 .nsectors = 16,
1109 .sector_size = 8192,
1110 .page_size = 512,
1111 },
1112 /* .bank[1] = {*/
1113 {
1114 .present = 0,
1115 .probed = 0,
1116 .bank_number = 1,
1117
1118 },
1119 },
1120 },
1121
1122 /*at91sam4sd32c - LQFP100/BGA100*/
1123 {
1124 .chipid_cidr = 0x29a70ee0,
1125 .name = "at91sam4sd32c",
1126 .total_flash_size = 2048 * 1024,
1127 .total_sram_size = 160 * 1024,
1128 .n_gpnvms = 3,
1129 .n_banks = 2,
1130
1131 /* .bank[0] = { */
1132 {
1133 {
1134 .probed = 0,
1135 .pChip = NULL,
1136 .pBank = NULL,
1137 .bank_number = 0,
1138 .base_address = FLASH_BANK0_BASE_SD,
1139 .controller_address = 0x400e0a00,
1140 .flash_wait_states = 5,
1141 .present = 1,
1142 .size_bytes = 1024 * 1024,
1143 .nsectors = 128,
1144 .sector_size = 8192,
1145 .page_size = 512,
1146 },
1147
1148 /* .bank[1] = { */
1149 {
1150 .probed = 0,
1151 .pChip = NULL,
1152 .pBank = NULL,
1153 .bank_number = 1,
1154 .base_address = FLASH_BANK1_BASE_2048K_SD,
1155 .controller_address = 0x400e0c00,
1156 .flash_wait_states = 5,
1157 .present = 1,
1158 .size_bytes = 1024 * 1024,
1159 .nsectors = 128,
1160 .sector_size = 8192,
1161 .page_size = 512,
1162 },
1163 },
1164 },
1165
1166 /*at91sam4sd32b - LQFP64/BGA64*/
1167 {
1168 .chipid_cidr = 0x29970ee0,
1169 .name = "at91sam4sd32b",
1170 .total_flash_size = 2048 * 1024,
1171 .total_sram_size = 160 * 1024,
1172 .n_gpnvms = 3,
1173 .n_banks = 2,
1174
1175 /* .bank[0] = { */
1176 {
1177 {
1178 .probed = 0,
1179 .pChip = NULL,
1180 .pBank = NULL,
1181 .bank_number = 0,
1182 .base_address = FLASH_BANK0_BASE_SD,
1183 .controller_address = 0x400e0a00,
1184 .flash_wait_states = 5,
1185 .present = 1,
1186 .size_bytes = 1024 * 1024,
1187 .nsectors = 128,
1188 .sector_size = 8192,
1189 .page_size = 512,
1190 },
1191
1192 /* .bank[1] = { */
1193 {
1194 .probed = 0,
1195 .pChip = NULL,
1196 .pBank = NULL,
1197 .bank_number = 1,
1198 .base_address = FLASH_BANK1_BASE_2048K_SD,
1199 .controller_address = 0x400e0c00,
1200 .flash_wait_states = 5,
1201 .present = 1,
1202 .size_bytes = 1024 * 1024,
1203 .nsectors = 128,
1204 .sector_size = 8192,
1205 .page_size = 512,
1206 },
1207 },
1208 },
1209
1210 /*at91sam4sd16c - LQFP100/BGA100*/
1211 {
1212 .chipid_cidr = 0x29a70ce0,
1213 .name = "at91sam4sd16c",
1214 .total_flash_size = 1024 * 1024,
1215 .total_sram_size = 160 * 1024,
1216 .n_gpnvms = 3,
1217 .n_banks = 2,
1218
1219 /* .bank[0] = { */
1220 {
1221 {
1222 .probed = 0,
1223 .pChip = NULL,
1224 .pBank = NULL,
1225 .bank_number = 0,
1226 .base_address = FLASH_BANK0_BASE_SD,
1227 .controller_address = 0x400e0a00,
1228 .flash_wait_states = 5,
1229 .present = 1,
1230 .size_bytes = 512 * 1024,
1231 .nsectors = 64,
1232 .sector_size = 8192,
1233 .page_size = 512,
1234 },
1235
1236 /* .bank[1] = { */
1237 {
1238 .probed = 0,
1239 .pChip = NULL,
1240 .pBank = NULL,
1241 .bank_number = 1,
1242 .base_address = FLASH_BANK1_BASE_1024K_SD,
1243 .controller_address = 0x400e0c00,
1244 .flash_wait_states = 5,
1245 .present = 1,
1246 .size_bytes = 512 * 1024,
1247 .nsectors = 64,
1248 .sector_size = 8192,
1249 .page_size = 512,
1250 },
1251 },
1252 },
1253
1254 /*at91sam4sd16b - LQFP64/BGA64*/
1255 {
1256 .chipid_cidr = 0x29970ce0,
1257 .name = "at91sam4sd16b",
1258 .total_flash_size = 1024 * 1024,
1259 .total_sram_size = 160 * 1024,
1260 .n_gpnvms = 3,
1261 .n_banks = 2,
1262
1263 /* .bank[0] = { */
1264 {
1265 {
1266 .probed = 0,
1267 .pChip = NULL,
1268 .pBank = NULL,
1269 .bank_number = 0,
1270 .base_address = FLASH_BANK0_BASE_SD,
1271 .controller_address = 0x400e0a00,
1272 .flash_wait_states = 5,
1273 .present = 1,
1274 .size_bytes = 512 * 1024,
1275 .nsectors = 64,
1276 .sector_size = 8192,
1277 .page_size = 512,
1278 },
1279
1280 /* .bank[1] = { */
1281 {
1282 .probed = 0,
1283 .pChip = NULL,
1284 .pBank = NULL,
1285 .bank_number = 1,
1286 .base_address = FLASH_BANK1_BASE_1024K_SD,
1287 .controller_address = 0x400e0c00,
1288 .flash_wait_states = 5,
1289 .present = 1,
1290 .size_bytes = 512 * 1024,
1291 .nsectors = 64,
1292 .sector_size = 8192,
1293 .page_size = 512,
1294 },
1295 },
1296 },
1297
1298 /* atsamg53n19 */
1299 {
1300 .chipid_cidr = 0x247e0ae0,
1301 .name = "atsamg53n19",
1302 .total_flash_size = 512 * 1024,
1303 .total_sram_size = 96 * 1024,
1304 .n_gpnvms = 2,
1305 .n_banks = 1,
1306
1307 /* .bank[0] = {*/
1308 {
1309 {
1310 .probed = 0,
1311 .pChip = NULL,
1312 .pBank = NULL,
1313 .bank_number = 0,
1314 .base_address = FLASH_BANK_BASE_S,
1315 .controller_address = 0x400e0a00,
1316 .flash_wait_states = 5,
1317 .present = 1,
1318 .size_bytes = 512 * 1024,
1319 .nsectors = 64,
1320 .sector_size = 8192,
1321 .page_size = 512,
1322 },
1323 /* .bank[1] = {*/
1324 {
1325 .present = 0,
1326 .probed = 0,
1327 .bank_number = 1,
1328
1329 },
1330 }
1331 },
1332
1333 /* atsamg55g19 */
1334 {
1335 .chipid_cidr = 0x24470ae0,
1336 .name = "atsamg55g19",
1337 .total_flash_size = 512 * 1024,
1338 .total_sram_size = 160 * 1024,
1339 .n_gpnvms = 2,
1340 .n_banks = 1,
1341
1342 {
1343 /* .bank[0] = */
1344 {
1345 .probed = 0,
1346 .pChip = NULL,
1347 .pBank = NULL,
1348 .bank_number = 0,
1349 .base_address = FLASH_BANK_BASE_S,
1350 .controller_address = 0x400e0a00,
1351 .flash_wait_states = 5,
1352 .present = 1,
1353 .size_bytes = 512 * 1024,
1354 .nsectors = 64,
1355 .sector_size = 8192,
1356 .page_size = 512,
1357 },
1358 /* .bank[1] = */
1359 {
1360 .present = 0,
1361 .probed = 0,
1362 .bank_number = 1,
1363 },
1364 }
1365 },
1366
1367 /* atsamg55j19 */
1368 {
1369 .chipid_cidr = 0x24570ae0,
1370 .name = "atsamg55j19",
1371 .total_flash_size = 512 * 1024,
1372 .total_sram_size = 160 * 1024,
1373 .n_gpnvms = 2,
1374 .n_banks = 1,
1375
1376 {
1377 /* .bank[0] = */
1378 {
1379 .probed = 0,
1380 .pChip = NULL,
1381 .pBank = NULL,
1382 .bank_number = 0,
1383 .base_address = FLASH_BANK_BASE_S,
1384 .controller_address = 0x400e0a00,
1385 .flash_wait_states = 5,
1386 .present = 1,
1387 .size_bytes = 512 * 1024,
1388 .nsectors = 64,
1389 .sector_size = 8192,
1390 .page_size = 512,
1391 },
1392 /* .bank[1] = */
1393 {
1394 .present = 0,
1395 .probed = 0,
1396 .bank_number = 1,
1397 },
1398 }
1399 },
1400
1401 /* terminate */
1402 {
1403 .chipid_cidr = 0,
1404 .name = NULL,
1405 }
1406 };
1407
1408 /* Globals above */
1409 /***********************************************************************
1410 **********************************************************************
1411 **********************************************************************
1412 **********************************************************************
1413 **********************************************************************
1414 **********************************************************************/
1415 /* *ATMEL* style code - from the SAM4 driver code */
1416
1417 /**
1418 * Get the current status of the EEFC and
1419 * the value of some status bits (LOCKE, PROGE).
1420 * @param pPrivate - info about the bank
1421 * @param v - result goes here
1422 */
1423 static int EFC_GetStatus(struct sam4_bank_private *pPrivate, uint32_t *v)
1424 {
1425 int r;
1426 r = target_read_u32(pPrivate->pChip->target,
1427 pPrivate->controller_address + offset_EFC_FSR,
1428 v);
1429 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1430 (unsigned int)(*v),
1431 ((unsigned int)((*v >> 2) & 1)),
1432 ((unsigned int)((*v >> 1) & 1)),
1433 ((unsigned int)((*v >> 0) & 1)));
1434
1435 return r;
1436 }
1437
1438 /**
1439 * Get the result of the last executed command.
1440 * @param pPrivate - info about the bank
1441 * @param v - result goes here
1442 */
1443 static int EFC_GetResult(struct sam4_bank_private *pPrivate, uint32_t *v)
1444 {
1445 int r;
1446 uint32_t rv;
1447 r = target_read_u32(pPrivate->pChip->target,
1448 pPrivate->controller_address + offset_EFC_FRR,
1449 &rv);
1450 if (v)
1451 *v = rv;
1452 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
1453 return r;
1454 }
1455
1456 static int EFC_StartCommand(struct sam4_bank_private *pPrivate,
1457 unsigned command, unsigned argument)
1458 {
1459 uint32_t n, v;
1460 int r;
1461 int retry;
1462
1463 retry = 0;
1464 do_retry:
1465
1466 /* Check command & argument */
1467 switch (command) {
1468
1469 case AT91C_EFC_FCMD_WP:
1470 case AT91C_EFC_FCMD_WPL:
1471 case AT91C_EFC_FCMD_EWP:
1472 case AT91C_EFC_FCMD_EWPL:
1473 /* case AT91C_EFC_FCMD_EPL: */
1474 case AT91C_EFC_FCMD_EPA:
1475 case AT91C_EFC_FCMD_SLB:
1476 case AT91C_EFC_FCMD_CLB:
1477 n = (pPrivate->size_bytes / pPrivate->page_size);
1478 if (argument >= n)
1479 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
1480 break;
1481
1482 case AT91C_EFC_FCMD_SFB:
1483 case AT91C_EFC_FCMD_CFB:
1484 if (argument >= pPrivate->pChip->details.n_gpnvms) {
1485 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1486 pPrivate->pChip->details.n_gpnvms);
1487 }
1488 break;
1489
1490 case AT91C_EFC_FCMD_GETD:
1491 case AT91C_EFC_FCMD_EA:
1492 case AT91C_EFC_FCMD_GLB:
1493 case AT91C_EFC_FCMD_GFB:
1494 case AT91C_EFC_FCMD_STUI:
1495 case AT91C_EFC_FCMD_SPUI:
1496 if (argument != 0)
1497 LOG_ERROR("Argument is meaningless for cmd: %d", command);
1498 break;
1499 default:
1500 LOG_ERROR("Unknown command %d", command);
1501 break;
1502 }
1503
1504 if (command == AT91C_EFC_FCMD_SPUI) {
1505 /* this is a very special situation. */
1506 /* Situation (1) - error/retry - see below */
1507 /* And we are being called recursively */
1508 /* Situation (2) - normal, finished reading unique id */
1509 } else {
1510 /* it should be "ready" */
1511 EFC_GetStatus(pPrivate, &v);
1512 if (v & 1) {
1513 /* then it is ready */
1514 /* we go on */
1515 } else {
1516 if (retry) {
1517 /* we have done this before */
1518 /* the controller is not responding. */
1519 LOG_ERROR("flash controller(%d) is not ready! Error",
1520 pPrivate->bank_number);
1521 return ERROR_FAIL;
1522 } else {
1523 retry++;
1524 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1525 pPrivate->bank_number);
1526 /* we do that by issuing the *STOP* command */
1527 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
1528 /* above is recursive, and further recursion is blocked by */
1529 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1530 goto do_retry;
1531 }
1532 }
1533 }
1534
1535 v = (0x5A << 24) | (argument << 8) | command;
1536 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
1537 r = target_write_u32(pPrivate->pBank->target,
1538 pPrivate->controller_address + offset_EFC_FCR, v);
1539 if (r != ERROR_OK)
1540 LOG_DEBUG("Error Write failed");
1541 return r;
1542 }
1543
1544 /**
1545 * Performs the given command and wait until its completion (or an error).
1546 * @param pPrivate - info about the bank
1547 * @param command - Command to perform.
1548 * @param argument - Optional command argument.
1549 * @param status - put command status bits here
1550 */
1551 static int EFC_PerformCommand(struct sam4_bank_private *pPrivate,
1552 unsigned command,
1553 unsigned argument,
1554 uint32_t *status)
1555 {
1556
1557 int r;
1558 uint32_t v;
1559 int64_t ms_now, ms_end;
1560
1561 /* default */
1562 if (status)
1563 *status = 0;
1564
1565 r = EFC_StartCommand(pPrivate, command, argument);
1566 if (r != ERROR_OK)
1567 return r;
1568
1569 ms_end = 10000 + timeval_ms();
1570
1571 do {
1572 r = EFC_GetStatus(pPrivate, &v);
1573 if (r != ERROR_OK)
1574 return r;
1575 ms_now = timeval_ms();
1576 if (ms_now > ms_end) {
1577 /* error */
1578 LOG_ERROR("Command timeout");
1579 return ERROR_FAIL;
1580 }
1581 } while ((v & 1) == 0);
1582
1583 /* error bits.. */
1584 if (status)
1585 *status = (v & 0x6);
1586 return ERROR_OK;
1587
1588 }
1589
1590 /**
1591 * Read the unique ID.
1592 * @param pPrivate - info about the bank
1593 * The unique ID is stored in the 'pPrivate' structure.
1594 */
1595 static int FLASHD_ReadUniqueID(struct sam4_bank_private *pPrivate)
1596 {
1597 int r;
1598 uint32_t v;
1599 int x;
1600 /* assume 0 */
1601 pPrivate->pChip->cfg.unique_id[0] = 0;
1602 pPrivate->pChip->cfg.unique_id[1] = 0;
1603 pPrivate->pChip->cfg.unique_id[2] = 0;
1604 pPrivate->pChip->cfg.unique_id[3] = 0;
1605
1606 LOG_DEBUG("Begin");
1607 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
1608 if (r < 0)
1609 return r;
1610
1611 for (x = 0; x < 4; x++) {
1612 r = target_read_u32(pPrivate->pChip->target,
1613 pPrivate->pBank->base + (x * 4),
1614 &v);
1615 if (r < 0)
1616 return r;
1617 pPrivate->pChip->cfg.unique_id[x] = v;
1618 }
1619
1620 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
1621 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1622 r,
1623 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
1624 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
1625 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
1626 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
1627 return r;
1628
1629 }
1630
1631 /**
1632 * Erases the entire flash.
1633 * @param pPrivate - the info about the bank.
1634 */
1635 static int FLASHD_EraseEntireBank(struct sam4_bank_private *pPrivate)
1636 {
1637 LOG_DEBUG("Here");
1638 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
1639 }
1640
1641 /**
1642 * Erases the entire flash.
1643 * @param pPrivate - the info about the bank.
1644 */
1645 static int FLASHD_ErasePages(struct sam4_bank_private *pPrivate,
1646 int firstPage,
1647 int numPages,
1648 uint32_t *status)
1649 {
1650 LOG_DEBUG("Here");
1651 uint8_t erasePages;
1652 switch (numPages) {
1653 case 4:
1654 erasePages = 0x00;
1655 break;
1656 case 8:
1657 erasePages = 0x01;
1658 break;
1659 case 16:
1660 erasePages = 0x02;
1661 break;
1662 case 32:
1663 erasePages = 0x03;
1664 break;
1665 default:
1666 erasePages = 0x00;
1667 break;
1668 }
1669
1670 /* AT91C_EFC_FCMD_EPA
1671 * According to the datasheet FARG[15:2] defines the page from which
1672 * the erase will start.This page must be modulo 4, 8, 16 or 32
1673 * according to the number of pages to erase. FARG[1:0] defines the
1674 * number of pages to be erased. Previously (firstpage << 2) was used
1675 * to conform to this, seems it should not be shifted...
1676 */
1677 return EFC_PerformCommand(pPrivate,
1678 /* send Erase Page */
1679 AT91C_EFC_FCMD_EPA,
1680 (firstPage) | erasePages,
1681 status);
1682 }
1683
1684 /**
1685 * Gets current GPNVM state.
1686 * @param pPrivate - info about the bank.
1687 * @param gpnvm - GPNVM bit index.
1688 * @param puthere - result stored here.
1689 */
1690 /* ------------------------------------------------------------------------------ */
1691 static int FLASHD_GetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
1692 {
1693 uint32_t v;
1694 int r;
1695
1696 LOG_DEBUG("Here");
1697 if (pPrivate->bank_number != 0) {
1698 LOG_ERROR("GPNVM only works with Bank0");
1699 return ERROR_FAIL;
1700 }
1701
1702 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1703 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1704 gpnvm, pPrivate->pChip->details.n_gpnvms);
1705 return ERROR_FAIL;
1706 }
1707
1708 /* Get GPNVMs status */
1709 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
1710 if (r != ERROR_OK) {
1711 LOG_ERROR("Failed");
1712 return r;
1713 }
1714
1715 r = EFC_GetResult(pPrivate, &v);
1716
1717 if (puthere) {
1718 /* Check if GPNVM is set */
1719 /* get the bit and make it a 0/1 */
1720 *puthere = (v >> gpnvm) & 1;
1721 }
1722
1723 return r;
1724 }
1725
1726 /**
1727 * Clears the selected GPNVM bit.
1728 * @param pPrivate info about the bank
1729 * @param gpnvm GPNVM index.
1730 * @returns 0 if successful; otherwise returns an error code.
1731 */
1732 static int FLASHD_ClrGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
1733 {
1734 int r;
1735 unsigned v;
1736
1737 LOG_DEBUG("Here");
1738 if (pPrivate->bank_number != 0) {
1739 LOG_ERROR("GPNVM only works with Bank0");
1740 return ERROR_FAIL;
1741 }
1742
1743 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1744 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1745 gpnvm, pPrivate->pChip->details.n_gpnvms);
1746 return ERROR_FAIL;
1747 }
1748
1749 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1750 if (r != ERROR_OK) {
1751 LOG_DEBUG("Failed: %d", r);
1752 return r;
1753 }
1754 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
1755 LOG_DEBUG("End: %d", r);
1756 return r;
1757 }
1758
1759 /**
1760 * Sets the selected GPNVM bit.
1761 * @param pPrivate info about the bank
1762 * @param gpnvm GPNVM index.
1763 */
1764 static int FLASHD_SetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
1765 {
1766 int r;
1767 unsigned v;
1768
1769 if (pPrivate->bank_number != 0) {
1770 LOG_ERROR("GPNVM only works with Bank0");
1771 return ERROR_FAIL;
1772 }
1773
1774 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1775 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1776 gpnvm, pPrivate->pChip->details.n_gpnvms);
1777 return ERROR_FAIL;
1778 }
1779
1780 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1781 if (r != ERROR_OK)
1782 return r;
1783 if (v) {
1784 /* already set */
1785 r = ERROR_OK;
1786 } else {
1787 /* set it */
1788 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
1789 }
1790 return r;
1791 }
1792
1793 /**
1794 * Returns a bit field (at most 64) of locked regions within a page.
1795 * @param pPrivate info about the bank
1796 * @param v where to store locked bits
1797 */
1798 static int FLASHD_GetLockBits(struct sam4_bank_private *pPrivate, uint32_t *v)
1799 {
1800 int r;
1801 LOG_DEBUG("Here");
1802 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
1803 if (r == ERROR_OK) {
1804 EFC_GetResult(pPrivate, v);
1805 EFC_GetResult(pPrivate, v);
1806 EFC_GetResult(pPrivate, v);
1807 r = EFC_GetResult(pPrivate, v);
1808 }
1809 LOG_DEBUG("End: %d", r);
1810 return r;
1811 }
1812
1813 /**
1814 * Unlocks all the regions in the given address range.
1815 * @param pPrivate info about the bank
1816 * @param start_sector first sector to unlock
1817 * @param end_sector last (inclusive) to unlock
1818 */
1819
1820 static int FLASHD_Unlock(struct sam4_bank_private *pPrivate,
1821 unsigned start_sector,
1822 unsigned end_sector)
1823 {
1824 int r;
1825 uint32_t status;
1826 uint32_t pg;
1827 uint32_t pages_per_sector;
1828
1829 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1830
1831 /* Unlock all pages */
1832 while (start_sector <= end_sector) {
1833 pg = start_sector * pages_per_sector;
1834
1835 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
1836 if (r != ERROR_OK)
1837 return r;
1838 start_sector++;
1839 }
1840
1841 return ERROR_OK;
1842 }
1843
1844 /**
1845 * Locks regions
1846 * @param pPrivate - info about the bank
1847 * @param start_sector - first sector to lock
1848 * @param end_sector - last sector (inclusive) to lock
1849 */
1850 static int FLASHD_Lock(struct sam4_bank_private *pPrivate,
1851 unsigned start_sector,
1852 unsigned end_sector)
1853 {
1854 uint32_t status;
1855 uint32_t pg;
1856 uint32_t pages_per_sector;
1857 int r;
1858
1859 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1860
1861 /* Lock all pages */
1862 while (start_sector <= end_sector) {
1863 pg = start_sector * pages_per_sector;
1864
1865 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
1866 if (r != ERROR_OK)
1867 return r;
1868 start_sector++;
1869 }
1870 return ERROR_OK;
1871 }
1872
1873 /****** END SAM4 CODE ********/
1874
1875 /* begin helpful debug code */
1876 /* print the fieldname, the field value, in dec & hex, and return field value */
1877 static uint32_t sam4_reg_fieldname(struct sam4_chip *pChip,
1878 const char *regname,
1879 uint32_t value,
1880 unsigned shift,
1881 unsigned width)
1882 {
1883 uint32_t v;
1884 int hwidth, dwidth;
1885
1886
1887 /* extract the field */
1888 v = value >> shift;
1889 v = v & ((1 << width)-1);
1890 if (width <= 16) {
1891 hwidth = 4;
1892 dwidth = 5;
1893 } else {
1894 hwidth = 8;
1895 dwidth = 12;
1896 }
1897
1898 /* show the basics */
1899 LOG_USER_N("\t%*s: %*" PRId32 " [0x%0*" PRIx32 "] ",
1900 REG_NAME_WIDTH, regname,
1901 dwidth, v,
1902 hwidth, v);
1903 return v;
1904 }
1905
1906 static const char _unknown[] = "unknown";
1907 static const char *const eproc_names[] = {
1908 "Cortex-M7", /* 0 */
1909 "arm946es", /* 1 */
1910 "arm7tdmi", /* 2 */
1911 "Cortex-M3", /* 3 */
1912 "arm920t", /* 4 */
1913 "arm926ejs", /* 5 */
1914 "Cortex-A5", /* 6 */
1915 "Cortex-M4", /* 7 */
1916 _unknown, /* 8 */
1917 _unknown, /* 9 */
1918 _unknown, /* 10 */
1919 _unknown, /* 11 */
1920 _unknown, /* 12 */
1921 _unknown, /* 13 */
1922 _unknown, /* 14 */
1923 _unknown, /* 15 */
1924 };
1925
1926 #define nvpsize2 nvpsize /* these two tables are identical */
1927 static const char *const nvpsize[] = {
1928 "none", /* 0 */
1929 "8K bytes", /* 1 */
1930 "16K bytes", /* 2 */
1931 "32K bytes", /* 3 */
1932 _unknown, /* 4 */
1933 "64K bytes", /* 5 */
1934 _unknown, /* 6 */
1935 "128K bytes", /* 7 */
1936 "160K bytes", /* 8 */
1937 "256K bytes", /* 9 */
1938 "512K bytes", /* 10 */
1939 _unknown, /* 11 */
1940 "1024K bytes", /* 12 */
1941 _unknown, /* 13 */
1942 "2048K bytes", /* 14 */
1943 _unknown, /* 15 */
1944 };
1945
1946 static const char *const sramsize[] = {
1947 "48K Bytes", /* 0 */
1948 "1K Bytes", /* 1 */
1949 "2K Bytes", /* 2 */
1950 "6K Bytes", /* 3 */
1951 "112K Bytes", /* 4 */
1952 "4K Bytes", /* 5 */
1953 "80K Bytes", /* 6 */
1954 "160K Bytes", /* 7 */
1955 "8K Bytes", /* 8 */
1956 "16K Bytes", /* 9 */
1957 "32K Bytes", /* 10 */
1958 "64K Bytes", /* 11 */
1959 "128K Bytes", /* 12 */
1960 "256K Bytes", /* 13 */
1961 "96K Bytes", /* 14 */
1962 "512K Bytes", /* 15 */
1963
1964 };
1965
1966 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1967 { 0x19, "AT91SAM9xx Series" },
1968 { 0x29, "AT91SAM9XExx Series" },
1969 { 0x34, "AT91x34 Series" },
1970 { 0x37, "CAP7 Series" },
1971 { 0x39, "CAP9 Series" },
1972 { 0x3B, "CAP11 Series" },
1973 { 0x3C, "ATSAM4E" },
1974 { 0x40, "AT91x40 Series" },
1975 { 0x42, "AT91x42 Series" },
1976 { 0x43, "SAMG51 Series"
1977 },
1978 { 0x44, "SAMG55 Series (49-pin WLCSP)" },
1979 { 0x45, "SAMG55 Series (64-pin)" },
1980 { 0x47, "SAMG53 Series"
1981 },
1982 { 0x55, "AT91x55 Series" },
1983 { 0x60, "AT91SAM7Axx Series" },
1984 { 0x61, "AT91SAM7AQxx Series" },
1985 { 0x63, "AT91x63 Series" },
1986 { 0x64, "SAM4CxxC (100-pin version)" },
1987 { 0x66, "SAM4CxxE (144-pin version)" },
1988 { 0x70, "AT91SAM7Sxx Series" },
1989 { 0x71, "AT91SAM7XCxx Series" },
1990 { 0x72, "AT91SAM7SExx Series" },
1991 { 0x73, "AT91SAM7Lxx Series" },
1992 { 0x75, "AT91SAM7Xxx Series" },
1993 { 0x76, "AT91SAM7SLxx Series" },
1994 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1995 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1996 { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
1997 { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
1998 { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
1999 { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
2000 { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
2001 { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
2002 { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
2003 { 0x92, "AT91x92 Series" },
2004 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2005 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2006 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2007 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2008 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2009 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2010 { 0xA5, "ATSAM5A" },
2011 { 0xF0, "AT75Cxx Series" },
2012 { -1, NULL },
2013 };
2014
2015 static const char *const nvptype[] = {
2016 "rom", /* 0 */
2017 "romless or onchip flash", /* 1 */
2018 "embedded flash memory",/* 2 */
2019 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2020 "sram emulating flash", /* 4 */
2021 _unknown, /* 5 */
2022 _unknown, /* 6 */
2023 _unknown, /* 7 */
2024 };
2025
2026 static const char *_yes_or_no(uint32_t v)
2027 {
2028 if (v)
2029 return "YES";
2030 else
2031 return "NO";
2032 }
2033
2034 static const char *const _rc_freq[] = {
2035 "4 MHz", "8 MHz", "12 MHz", "reserved"
2036 };
2037
2038 static void sam4_explain_ckgr_mor(struct sam4_chip *pChip)
2039 {
2040 uint32_t v;
2041 uint32_t rcen;
2042
2043 v = sam4_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
2044 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2045 v = sam4_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
2046 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2047 rcen = sam4_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
2048 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2049 v = sam4_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
2050 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2051
2052 pChip->cfg.rc_freq = 0;
2053 if (rcen) {
2054 switch (v) {
2055 default:
2056 pChip->cfg.rc_freq = 0;
2057 break;
2058 case 0:
2059 pChip->cfg.rc_freq = 4 * 1000 * 1000;
2060 break;
2061 case 1:
2062 pChip->cfg.rc_freq = 8 * 1000 * 1000;
2063 break;
2064 case 2:
2065 pChip->cfg.rc_freq = 12 * 1000 * 1000;
2066 break;
2067 }
2068 }
2069
2070 v = sam4_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
2071 LOG_USER("(startup clks, time= %f uSecs)",
2072 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
2073 v = sam4_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
2074 LOG_USER("(mainosc source: %s)",
2075 v ? "external xtal" : "internal RC");
2076
2077 v = sam4_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
2078 LOG_USER("(clock failure enabled: %s)",
2079 _yes_or_no(v));
2080 }
2081
2082 static void sam4_explain_chipid_cidr(struct sam4_chip *pChip)
2083 {
2084 int x;
2085 uint32_t v;
2086 const char *cp;
2087
2088 sam4_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
2089 LOG_USER_N("\n");
2090
2091 v = sam4_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
2092 LOG_USER("%s", eproc_names[v]);
2093
2094 v = sam4_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
2095 LOG_USER("%s", nvpsize[v]);
2096
2097 v = sam4_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
2098 LOG_USER("%s", nvpsize2[v]);
2099
2100 v = sam4_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
2101 LOG_USER("%s", sramsize[v]);
2102
2103 v = sam4_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
2104 cp = _unknown;
2105 for (x = 0; archnames[x].name; x++) {
2106 if (v == archnames[x].value) {
2107 cp = archnames[x].name;
2108 break;
2109 }
2110 }
2111
2112 LOG_USER("%s", cp);
2113
2114 v = sam4_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
2115 LOG_USER("%s", nvptype[v]);
2116
2117 v = sam4_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
2118 LOG_USER("(exists: %s)", _yes_or_no(v));
2119 }
2120
2121 static void sam4_explain_ckgr_mcfr(struct sam4_chip *pChip)
2122 {
2123 uint32_t v;
2124
2125 v = sam4_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
2126 LOG_USER("(main ready: %s)", _yes_or_no(v));
2127
2128 v = sam4_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
2129
2130 v = (v * pChip->cfg.slow_freq) / 16;
2131 pChip->cfg.mainosc_freq = v;
2132
2133 LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
2134 _tomhz(v),
2135 (uint32_t)(pChip->cfg.slow_freq / 1000),
2136 (uint32_t)(pChip->cfg.slow_freq % 1000));
2137 }
2138
2139 static void sam4_explain_ckgr_plla(struct sam4_chip *pChip)
2140 {
2141 uint32_t mula, diva;
2142
2143 diva = sam4_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
2144 LOG_USER_N("\n");
2145 mula = sam4_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
2146 LOG_USER_N("\n");
2147 pChip->cfg.plla_freq = 0;
2148 if (mula == 0)
2149 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2150 else if (diva == 0)
2151 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2152 else if (diva >= 1) {
2153 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
2154 LOG_USER("\tPLLA Freq: %3.03f MHz",
2155 _tomhz(pChip->cfg.plla_freq));
2156 }
2157 }
2158
2159 static void sam4_explain_mckr(struct sam4_chip *pChip)
2160 {
2161 uint32_t css, pres, fin = 0;
2162 int pdiv = 0;
2163 const char *cp = NULL;
2164
2165 css = sam4_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
2166 switch (css & 3) {
2167 case 0:
2168 fin = pChip->cfg.slow_freq;
2169 cp = "slowclk";
2170 break;
2171 case 1:
2172 fin = pChip->cfg.mainosc_freq;
2173 cp = "mainosc";
2174 break;
2175 case 2:
2176 fin = pChip->cfg.plla_freq;
2177 cp = "plla";
2178 break;
2179 case 3:
2180 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
2181 fin = 480 * 1000 * 1000;
2182 cp = "upll";
2183 } else {
2184 fin = 0;
2185 cp = "upll (*ERROR* UPLL is disabled)";
2186 }
2187 break;
2188 default:
2189 assert(0);
2190 break;
2191 }
2192
2193 LOG_USER("%s (%3.03f Mhz)",
2194 cp,
2195 _tomhz(fin));
2196 pres = sam4_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
2197 switch (pres & 0x07) {
2198 case 0:
2199 pdiv = 1;
2200 cp = "selected clock";
2201 break;
2202 case 1:
2203 pdiv = 2;
2204 cp = "clock/2";
2205 break;
2206 case 2:
2207 pdiv = 4;
2208 cp = "clock/4";
2209 break;
2210 case 3:
2211 pdiv = 8;
2212 cp = "clock/8";
2213 break;
2214 case 4:
2215 pdiv = 16;
2216 cp = "clock/16";
2217 break;
2218 case 5:
2219 pdiv = 32;
2220 cp = "clock/32";
2221 break;
2222 case 6:
2223 pdiv = 64;
2224 cp = "clock/64";
2225 break;
2226 case 7:
2227 pdiv = 6;
2228 cp = "clock/6";
2229 break;
2230 default:
2231 assert(0);
2232 break;
2233 }
2234 LOG_USER("(%s)", cp);
2235 fin = fin / pdiv;
2236 /* sam4 has a *SINGLE* clock - */
2237 /* other at91 series parts have divisors for these. */
2238 pChip->cfg.cpu_freq = fin;
2239 pChip->cfg.mclk_freq = fin;
2240 pChip->cfg.fclk_freq = fin;
2241 LOG_USER("\t\tResult CPU Freq: %3.03f",
2242 _tomhz(fin));
2243 }
2244
2245 #if 0
2246 static struct sam4_chip *target2sam4(struct target *pTarget)
2247 {
2248 struct sam4_chip *pChip;
2249
2250 if (pTarget == NULL)
2251 return NULL;
2252
2253 pChip = all_sam4_chips;
2254 while (pChip) {
2255 if (pChip->target == pTarget)
2256 break; /* return below */
2257 else
2258 pChip = pChip->next;
2259 }
2260 return pChip;
2261 }
2262 #endif
2263
2264 static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *pCfg, const struct sam4_reg_list *pList)
2265 {
2266 /* this function exists to help */
2267 /* keep funky offsetof() errors */
2268 /* and casting from causing bugs */
2269
2270 /* By using prototypes - we can detect what would */
2271 /* be casting errors. */
2272
2273 return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
2274 }
2275
2276
2277 #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
2278 struct sam4_cfg, \
2279 NAME), # NAME, FUNC }
2280 static const struct sam4_reg_list sam4_all_regs[] = {
2281 SAM4_ENTRY(CKGR_MOR, sam4_explain_ckgr_mor),
2282 SAM4_ENTRY(CKGR_MCFR, sam4_explain_ckgr_mcfr),
2283 SAM4_ENTRY(CKGR_PLLAR, sam4_explain_ckgr_plla),
2284 SAM4_ENTRY(CKGR_UCKR, NULL),
2285 SAM4_ENTRY(PMC_FSMR, NULL),
2286 SAM4_ENTRY(PMC_FSPR, NULL),
2287 SAM4_ENTRY(PMC_IMR, NULL),
2288 SAM4_ENTRY(PMC_MCKR, sam4_explain_mckr),
2289 SAM4_ENTRY(PMC_PCK0, NULL),
2290 SAM4_ENTRY(PMC_PCK1, NULL),
2291 SAM4_ENTRY(PMC_PCK2, NULL),
2292 SAM4_ENTRY(PMC_PCSR, NULL),
2293 SAM4_ENTRY(PMC_SCSR, NULL),
2294 SAM4_ENTRY(PMC_SR, NULL),
2295 SAM4_ENTRY(CHIPID_CIDR, sam4_explain_chipid_cidr),
2296 SAM4_ENTRY(CHIPID_EXID, NULL),
2297 /* TERMINATE THE LIST */
2298 { .name = NULL }
2299 };
2300 #undef SAM4_ENTRY
2301
2302 static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
2303 {
2304 return bank->driver_priv;
2305 }
2306
2307 /**
2308 * Given a pointer to where it goes in the structure,
2309 * determine the register name, address from the all registers table.
2310 */
2311 static const struct sam4_reg_list *sam4_GetReg(struct sam4_chip *pChip, uint32_t *goes_here)
2312 {
2313 const struct sam4_reg_list *pReg;
2314
2315 pReg = &(sam4_all_regs[0]);
2316 while (pReg->name) {
2317 uint32_t *pPossible;
2318
2319 /* calculate where this one go.. */
2320 /* it is "possibly" this register. */
2321
2322 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
2323
2324 /* well? Is it this register */
2325 if (pPossible == goes_here) {
2326 /* Jump for joy! */
2327 return pReg;
2328 }
2329
2330 /* next... */
2331 pReg++;
2332 }
2333 /* This is *TOTAL*PANIC* - we are totally screwed. */
2334 LOG_ERROR("INVALID SAM4 REGISTER");
2335 return NULL;
2336 }
2337
2338 static int sam4_ReadThisReg(struct sam4_chip *pChip, uint32_t *goes_here)
2339 {
2340 const struct sam4_reg_list *pReg;
2341 int r;
2342
2343 pReg = sam4_GetReg(pChip, goes_here);
2344 if (!pReg)
2345 return ERROR_FAIL;
2346
2347 r = target_read_u32(pChip->target, pReg->address, goes_here);
2348 if (r != ERROR_OK) {
2349 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
2350 pReg->name, (unsigned)(pReg->address), r);
2351 }
2352 return r;
2353 }
2354
2355 static int sam4_ReadAllRegs(struct sam4_chip *pChip)
2356 {
2357 int r;
2358 const struct sam4_reg_list *pReg;
2359
2360 pReg = &(sam4_all_regs[0]);
2361 while (pReg->name) {
2362 r = sam4_ReadThisReg(pChip,
2363 sam4_get_reg_ptr(&(pChip->cfg), pReg));
2364 if (r != ERROR_OK) {
2365 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
2366 pReg->name, ((unsigned)(pReg->address)), r);
2367 return r;
2368 }
2369 pReg++;
2370 }
2371
2372 return ERROR_OK;
2373 }
2374
2375 static int sam4_GetInfo(struct sam4_chip *pChip)
2376 {
2377 const struct sam4_reg_list *pReg;
2378 uint32_t regval;
2379
2380 pReg = &(sam4_all_regs[0]);
2381 while (pReg->name) {
2382 /* display all regs */
2383 LOG_DEBUG("Start: %s", pReg->name);
2384 regval = *sam4_get_reg_ptr(&(pChip->cfg), pReg);
2385 LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
2386 REG_NAME_WIDTH,
2387 pReg->name,
2388 pReg->address,
2389 regval);
2390 if (pReg->explain_func)
2391 (*(pReg->explain_func))(pChip);
2392 LOG_DEBUG("End: %s", pReg->name);
2393 pReg++;
2394 }
2395 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
2396 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
2397 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
2398 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
2399 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
2400
2401 LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32,
2402 pChip->cfg.unique_id[0],
2403 pChip->cfg.unique_id[1],
2404 pChip->cfg.unique_id[2],
2405 pChip->cfg.unique_id[3]);
2406
2407 return ERROR_OK;
2408 }
2409
2410 static int sam4_protect_check(struct flash_bank *bank)
2411 {
2412 int r;
2413 uint32_t v[4] = {0};
2414 unsigned x;
2415 struct sam4_bank_private *pPrivate;
2416
2417 LOG_DEBUG("Begin");
2418 if (bank->target->state != TARGET_HALTED) {
2419 LOG_ERROR("Target not halted");
2420 return ERROR_TARGET_NOT_HALTED;
2421 }
2422
2423 pPrivate = get_sam4_bank_private(bank);
2424 if (!pPrivate) {
2425 LOG_ERROR("no private for this bank?");
2426 return ERROR_FAIL;
2427 }
2428 if (!(pPrivate->probed))
2429 return ERROR_FLASH_BANK_NOT_PROBED;
2430
2431 r = FLASHD_GetLockBits(pPrivate, v);
2432 if (r != ERROR_OK) {
2433 LOG_DEBUG("Failed: %d", r);
2434 return r;
2435 }
2436
2437 for (x = 0; x < pPrivate->nsectors; x++)
2438 bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
2439 LOG_DEBUG("Done");
2440 return ERROR_OK;
2441 }
2442
2443 FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
2444 {
2445 struct sam4_chip *pChip;
2446
2447 pChip = all_sam4_chips;
2448
2449 /* is this an existing chip? */
2450 while (pChip) {
2451 if (pChip->target == bank->target)
2452 break;
2453 pChip = pChip->next;
2454 }
2455
2456 if (!pChip) {
2457 /* this is a *NEW* chip */
2458 pChip = calloc(1, sizeof(struct sam4_chip));
2459 if (!pChip) {
2460 LOG_ERROR("NO RAM!");
2461 return ERROR_FAIL;
2462 }
2463 pChip->target = bank->target;
2464 /* insert at head */
2465 pChip->next = all_sam4_chips;
2466 all_sam4_chips = pChip;
2467 pChip->target = bank->target;
2468 /* assumption is this runs at 32khz */
2469 pChip->cfg.slow_freq = 32768;
2470 pChip->probed = 0;
2471 }
2472
2473 switch (bank->base) {
2474 default:
2475 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
2476 "[at91sam4s series] )",
2477 ((unsigned int)(bank->base)),
2478 ((unsigned int)(FLASH_BANK_BASE_S)));
2479 return ERROR_FAIL;
2480 break;
2481
2482 /* at91sam4s series only has bank 0*/
2483 /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
2484 case FLASH_BANK_BASE_S:
2485 case FLASH_BANK_BASE_C:
2486 bank->driver_priv = &(pChip->details.bank[0]);
2487 bank->bank_number = 0;
2488 pChip->details.bank[0].pChip = pChip;
2489 pChip->details.bank[0].pBank = bank;
2490 break;
2491
2492 /* Bank 1 of at91sam4sd/at91sam4c32 series */
2493 case FLASH_BANK1_BASE_1024K_SD:
2494 case FLASH_BANK1_BASE_2048K_SD:
2495 case FLASH_BANK1_BASE_C32:
2496 bank->driver_priv = &(pChip->details.bank[1]);
2497 bank->bank_number = 1;
2498 pChip->details.bank[1].pChip = pChip;
2499 pChip->details.bank[1].pBank = bank;
2500 break;
2501 }
2502
2503 /* we initialize after probing. */
2504 return ERROR_OK;
2505 }
2506
2507 /**
2508 * Remove all chips from the internal list without distingushing which one
2509 * is owned by this bank. This simplification works only for one shot
2510 * deallocation like current flash_free_all_banks()
2511 */
2512 static void sam4_free_driver_priv(struct flash_bank *bank)
2513 {
2514 struct sam4_chip *chip = all_sam4_chips;
2515 while (chip) {
2516 struct sam4_chip *next = chip->next;
2517 free(chip);
2518 chip = next;
2519 }
2520 all_sam4_chips = NULL;
2521 }
2522
2523 static int sam4_GetDetails(struct sam4_bank_private *pPrivate)
2524 {
2525 const struct sam4_chip_details *pDetails;
2526 struct sam4_chip *pChip;
2527 struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS];
2528 unsigned x;
2529
2530 LOG_DEBUG("Begin");
2531 pDetails = all_sam4_details;
2532 while (pDetails->name) {
2533 /* Compare cidr without version bits */
2534 if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2535 break;
2536 else
2537 pDetails++;
2538 }
2539 if (pDetails->name == NULL) {
2540 LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2541 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
2542 /* Help the victim, print details about the chip */
2543 LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
2544 pPrivate->pChip->cfg.CHIPID_CIDR);
2545 sam4_explain_chipid_cidr(pPrivate->pChip);
2546 return ERROR_FAIL;
2547 } else {
2548 LOG_INFO("SAM4 Found chip %s, CIDR 0x%08x", pDetails->name, pDetails->chipid_cidr);
2549 }
2550
2551 /* DANGER: THERE ARE DRAGONS HERE */
2552
2553 /* get our pChip - it is going */
2554 /* to be over-written shortly */
2555 pChip = pPrivate->pChip;
2556
2557 /* Note that, in reality: */
2558 /* */
2559 /* pPrivate = &(pChip->details.bank[0]) */
2560 /* or pPrivate = &(pChip->details.bank[1]) */
2561 /* */
2562
2563 /* save the "bank" pointers */
2564 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++)
2565 saved_banks[x] = pChip->details.bank[x].pBank;
2566
2567 /* Overwrite the "details" structure. */
2568 memcpy(&(pPrivate->pChip->details),
2569 pDetails,
2570 sizeof(pPrivate->pChip->details));
2571
2572 /* now fix the ghosted pointers */
2573 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2574 pChip->details.bank[x].pChip = pChip;
2575 pChip->details.bank[x].pBank = saved_banks[x];
2576 }
2577
2578 /* update the *BANK*SIZE* */
2579
2580 LOG_DEBUG("End");
2581 return ERROR_OK;
2582 }
2583
2584 static int _sam4_probe(struct flash_bank *bank, int noise)
2585 {
2586 unsigned x;
2587 int r;
2588 struct sam4_bank_private *pPrivate;
2589
2590
2591 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
2592 if (bank->target->state != TARGET_HALTED) {
2593 LOG_ERROR("Target not halted");
2594 return ERROR_TARGET_NOT_HALTED;
2595 }
2596
2597 pPrivate = get_sam4_bank_private(bank);
2598 if (!pPrivate) {
2599 LOG_ERROR("Invalid/unknown bank number");
2600 return ERROR_FAIL;
2601 }
2602
2603 r = sam4_ReadAllRegs(pPrivate->pChip);
2604 if (r != ERROR_OK)
2605 return r;
2606
2607 LOG_DEBUG("Here");
2608 if (pPrivate->pChip->probed)
2609 r = sam4_GetInfo(pPrivate->pChip);
2610 else
2611 r = sam4_GetDetails(pPrivate);
2612 if (r != ERROR_OK)
2613 return r;
2614
2615 /* update the flash bank size */
2616 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2617 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
2618 bank->size = pPrivate->pChip->details.bank[x].size_bytes;
2619 LOG_INFO("SAM4 Set flash bank to %08X - %08X, idx %d", bank->base, bank->base + bank->size, x);
2620 break;
2621 }
2622 }
2623
2624 if (bank->sectors == NULL) {
2625 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
2626 if (bank->sectors == NULL) {
2627 LOG_ERROR("No memory!");
2628 return ERROR_FAIL;
2629 }
2630 bank->num_sectors = pPrivate->nsectors;
2631
2632 for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
2633 bank->sectors[x].size = pPrivate->sector_size;
2634 bank->sectors[x].offset = x * (pPrivate->sector_size);
2635 /* mark as unknown */
2636 bank->sectors[x].is_erased = -1;
2637 bank->sectors[x].is_protected = -1;
2638 }
2639 }
2640
2641 pPrivate->probed = 1;
2642
2643 r = sam4_protect_check(bank);
2644 if (r != ERROR_OK)
2645 return r;
2646
2647 LOG_DEBUG("Bank = %d, nbanks = %d",
2648 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
2649 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
2650 /* read unique id, */
2651 /* it appears to be associated with the *last* flash bank. */
2652 FLASHD_ReadUniqueID(pPrivate);
2653 }
2654
2655 return r;
2656 }
2657
2658 static int sam4_probe(struct flash_bank *bank)
2659 {
2660 return _sam4_probe(bank, 1);
2661 }
2662
2663 static int sam4_auto_probe(struct flash_bank *bank)
2664 {
2665 return _sam4_probe(bank, 0);
2666 }
2667
2668 static int sam4_erase(struct flash_bank *bank, int first, int last)
2669 {
2670 struct sam4_bank_private *pPrivate;
2671 int r;
2672 int i;
2673 int pageCount;
2674 /*16 pages equals 8KB - Same size as a lock region*/
2675 pageCount = 16;
2676 uint32_t status;
2677
2678 LOG_DEBUG("Here");
2679 if (bank->target->state != TARGET_HALTED) {
2680 LOG_ERROR("Target not halted");
2681 return ERROR_TARGET_NOT_HALTED;
2682 }
2683
2684 r = sam4_auto_probe(bank);
2685 if (r != ERROR_OK) {
2686 LOG_DEBUG("Here,r=%d", r);
2687 return r;
2688 }
2689
2690 pPrivate = get_sam4_bank_private(bank);
2691 if (!(pPrivate->probed))
2692 return ERROR_FLASH_BANK_NOT_PROBED;
2693
2694 if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
2695 /* whole chip */
2696 LOG_DEBUG("Here");
2697 return FLASHD_EraseEntireBank(pPrivate);
2698 }
2699 LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
2700 LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", (unsigned int)(first), (unsigned int)(last));
2701 for (i = first; i <= last; i++) {
2702 /*16 pages equals 8KB - Same size as a lock region*/
2703 r = FLASHD_ErasePages(pPrivate, (i * pageCount), pageCount, &status);
2704 LOG_INFO("Erasing sector: 0x%08x", (unsigned int)(i));
2705 if (r != ERROR_OK)
2706 LOG_ERROR("SAM4: Error performing Erase page @ lock region number %d",
2707 (unsigned int)(i));
2708 if (status & (1 << 2)) {
2709 LOG_ERROR("SAM4: Lock Region %d is locked", (unsigned int)(i));
2710 return ERROR_FAIL;
2711 }
2712 if (status & (1 << 1)) {
2713 LOG_ERROR("SAM4: Flash Command error @lock region %d", (unsigned int)(i));
2714 return ERROR_FAIL;
2715 }
2716 }
2717
2718 return ERROR_OK;
2719 }
2720
2721 static int sam4_protect(struct flash_bank *bank, int set, int first, int last)
2722 {
2723 struct sam4_bank_private *pPrivate;
2724 int r;
2725
2726 LOG_DEBUG("Here");
2727 if (bank->target->state != TARGET_HALTED) {
2728 LOG_ERROR("Target not halted");
2729 return ERROR_TARGET_NOT_HALTED;
2730 }
2731
2732 pPrivate = get_sam4_bank_private(bank);
2733 if (!(pPrivate->probed))
2734 return ERROR_FLASH_BANK_NOT_PROBED;
2735
2736 if (set)
2737 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
2738 else
2739 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
2740 LOG_DEBUG("End: r=%d", r);
2741
2742 return r;
2743
2744 }
2745
2746 static int sam4_page_read(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2747 {
2748 uint32_t adr;
2749 int r;
2750
2751 adr = pagenum * pPrivate->page_size;
2752 adr = adr + pPrivate->base_address;
2753
2754 r = target_read_memory(pPrivate->pChip->target,
2755 adr,
2756 4, /* THIS*MUST*BE* in 32bit values */
2757 pPrivate->page_size / 4,
2758 buf);
2759 if (r != ERROR_OK)
2760 LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
2761 (unsigned int)(adr));
2762 return r;
2763 }
2764
2765 static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
2766 {
2767 uint32_t adr;
2768 uint32_t status;
2769 uint32_t fmr; /* EEFC Flash Mode Register */
2770 int r;
2771
2772 adr = pagenum * pPrivate->page_size;
2773 adr = (adr + pPrivate->base_address);
2774
2775 /* Get flash mode register value */
2776 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
2777 if (r != ERROR_OK)
2778 LOG_DEBUG("Error Read failed: read flash mode register");
2779
2780 /* Clear flash wait state field */
2781 fmr &= 0xfffff0ff;
2782
2783 /* set FWS (flash wait states) field in the FMR (flash mode register) */
2784 fmr |= (pPrivate->flash_wait_states << 8);
2785
2786 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
2787 r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
2788 if (r != ERROR_OK)
2789 LOG_DEBUG("Error Write failed: set flash mode register");
2790
2791 /* 1st sector 8kBytes - page 0 - 15*/
2792 /* 2nd sector 8kBytes - page 16 - 30*/
2793 /* 3rd sector 48kBytes - page 31 - 127*/
2794 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2795 r = target_write_memory(pPrivate->pChip->target,
2796 adr,
2797 4, /* THIS*MUST*BE* in 32bit values */
2798 pPrivate->page_size / 4,
2799 buf);
2800 if (r != ERROR_OK) {
2801 LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
2802 (unsigned int)(adr));
2803 return r;
2804 }
2805
2806 r = EFC_PerformCommand(pPrivate,
2807 /* send Erase & Write Page */
2808 AT91C_EFC_FCMD_WP, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
2809 pagenum,
2810 &status);
2811
2812 if (r != ERROR_OK)
2813 LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
2814 (unsigned int)(adr));
2815 if (status & (1 << 2)) {
2816 LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2817 return ERROR_FAIL;
2818 }
2819 if (status & (1 << 1)) {
2820 LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2821 return ERROR_FAIL;
2822 }
2823 return ERROR_OK;
2824 }
2825
2826 static int sam4_write(struct flash_bank *bank,
2827 const uint8_t *buffer,
2828 uint32_t offset,
2829 uint32_t count)
2830 {
2831 int n;
2832 unsigned page_cur;
2833 unsigned page_end;
2834 int r;
2835 unsigned page_offset;
2836 struct sam4_bank_private *pPrivate;
2837 uint8_t *pagebuffer;
2838
2839 /* incase we bail further below, set this to null */
2840 pagebuffer = NULL;
2841
2842 /* ignore dumb requests */
2843 if (count == 0) {
2844 r = ERROR_OK;
2845 goto done;
2846 }
2847
2848 if (bank->target->state != TARGET_HALTED) {
2849 LOG_ERROR("Target not halted");
2850 r = ERROR_TARGET_NOT_HALTED;
2851 goto done;
2852 }
2853
2854 pPrivate = get_sam4_bank_private(bank);
2855 if (!(pPrivate->probed)) {
2856 r = ERROR_FLASH_BANK_NOT_PROBED;
2857 goto done;
2858 }
2859
2860 if ((offset + count) > pPrivate->size_bytes) {
2861 LOG_ERROR("Flash write error - past end of bank");
2862 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2863 (unsigned int)(offset),
2864 (unsigned int)(count),
2865 (unsigned int)(pPrivate->size_bytes));
2866 r = ERROR_FAIL;
2867 goto done;
2868 }
2869
2870 pagebuffer = malloc(pPrivate->page_size);
2871 if (!pagebuffer) {
2872 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
2873 r = ERROR_FAIL;
2874 goto done;
2875 }
2876
2877 /* what page do we start & end in? */
2878 page_cur = offset / pPrivate->page_size;
2879 page_end = (offset + count - 1) / pPrivate->page_size;
2880
2881 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2882 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2883
2884 /* Special case: all one page */
2885 /* */
2886 /* Otherwise: */
2887 /* (1) non-aligned start */
2888 /* (2) body pages */
2889 /* (3) non-aligned end. */
2890
2891 /* Handle special case - all one page. */
2892 if (page_cur == page_end) {
2893 LOG_DEBUG("Special case, all in one page");
2894 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2895 if (r != ERROR_OK)
2896 goto done;
2897
2898 page_offset = (offset & (pPrivate->page_size-1));
2899 memcpy(pagebuffer + page_offset,
2900 buffer,
2901 count);
2902
2903 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2904 if (r != ERROR_OK)
2905 goto done;
2906 r = ERROR_OK;
2907 goto done;
2908 }
2909
2910 /* non-aligned start */
2911 page_offset = offset & (pPrivate->page_size - 1);
2912 if (page_offset) {
2913 LOG_DEBUG("Not-Aligned start");
2914 /* read the partial */
2915 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2916 if (r != ERROR_OK)
2917 goto done;
2918
2919 /* over-write with new data */
2920 n = (pPrivate->page_size - page_offset);
2921 memcpy(pagebuffer + page_offset,
2922 buffer,
2923 n);
2924
2925 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2926 if (r != ERROR_OK)
2927 goto done;
2928
2929 count -= n;
2930 offset += n;
2931 buffer += n;
2932 page_cur++;
2933 }
2934
2935 /* By checking that offset is correct here, we also
2936 fix a clang warning */
2937 assert(offset % pPrivate->page_size == 0);
2938
2939 /* intermediate large pages */
2940 /* also - the final *terminal* */
2941 /* if that terminal page is a full page */
2942 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2943 (int)page_cur, (int)page_end, (unsigned int)(count));
2944
2945 while ((page_cur < page_end) &&
2946 (count >= pPrivate->page_size)) {
2947 r = sam4_page_write(pPrivate, page_cur, buffer);
2948 if (r != ERROR_OK)
2949 goto done;
2950 count -= pPrivate->page_size;
2951 buffer += pPrivate->page_size;
2952 page_cur += 1;
2953 }
2954
2955 /* terminal partial page? */
2956 if (count) {
2957 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
2958 /* we have a partial page */
2959 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2960 if (r != ERROR_OK)
2961 goto done;
2962 /* data goes at start */
2963 memcpy(pagebuffer, buffer, count);
2964 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2965 if (r != ERROR_OK)
2966 goto done;
2967 }
2968 LOG_DEBUG("Done!");
2969 r = ERROR_OK;
2970 done:
2971 if (pagebuffer)
2972 free(pagebuffer);
2973 return r;
2974 }
2975
2976 COMMAND_HANDLER(sam4_handle_info_command)
2977 {
2978 struct sam4_chip *pChip;
2979 pChip = get_current_sam4(CMD_CTX);
2980 if (!pChip)
2981 return ERROR_OK;
2982
2983 unsigned x;
2984 int r;
2985
2986 /* bank0 must exist before we can do anything */
2987 if (pChip->details.bank[0].pBank == NULL) {
2988 x = 0;
2989 need_define:
2990 command_print(CMD_CTX,
2991 "Please define bank %d via command: flash bank %s ... ",
2992 x,
2993 at91sam4_flash.name);
2994 return ERROR_FAIL;
2995 }
2996
2997 /* if bank 0 is not probed, then probe it */
2998 if (!(pChip->details.bank[0].probed)) {
2999 r = sam4_auto_probe(pChip->details.bank[0].pBank);
3000 if (r != ERROR_OK)
3001 return ERROR_FAIL;
3002 }
3003 /* above guarantees the "chip details" structure is valid */
3004 /* and thus, bank private areas are valid */
3005 /* and we have a SAM4 chip, what a concept! */
3006
3007 /* auto-probe other banks, 0 done above */
3008 for (x = 1; x < SAM4_MAX_FLASH_BANKS; x++) {
3009 /* skip banks not present */
3010 if (!(pChip->details.bank[x].present))
3011 continue;
3012
3013 if (pChip->details.bank[x].pBank == NULL)
3014 goto need_define;
3015
3016 if (pChip->details.bank[x].probed)
3017 continue;
3018
3019 r = sam4_auto_probe(pChip->details.bank[x].pBank);
3020 if (r != ERROR_OK)
3021 return r;
3022 }
3023
3024 r = sam4_GetInfo(pChip);
3025 if (r != ERROR_OK) {
3026 LOG_DEBUG("Sam4Info, Failed %d", r);
3027 return r;
3028 }
3029
3030 return ERROR_OK;
3031 }
3032
3033 COMMAND_HANDLER(sam4_handle_gpnvm_command)
3034 {
3035 unsigned x, v;
3036 int r, who;
3037 struct sam4_chip *pChip;
3038
3039 pChip = get_current_sam4(CMD_CTX);
3040 if (!pChip)
3041 return ERROR_OK;
3042
3043 if (pChip->target->state != TARGET_HALTED) {
3044 LOG_ERROR("sam4 - target not halted");
3045 return ERROR_TARGET_NOT_HALTED;
3046 }
3047
3048 if (pChip->details.bank[0].pBank == NULL) {
3049 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
3050 at91sam4_flash.name);
3051 return ERROR_FAIL;
3052 }
3053 if (!pChip->details.bank[0].probed) {
3054 r = sam4_auto_probe(pChip->details.bank[0].pBank);
3055 if (r != ERROR_OK)
3056 return r;
3057 }
3058
3059 switch (CMD_ARGC) {
3060 default:
3061 return ERROR_COMMAND_SYNTAX_ERROR;
3062 break;
3063 case 0:
3064 goto showall;
3065 break;
3066 case 1:
3067 who = -1;
3068 break;
3069 case 2:
3070 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
3071 who = -1;
3072 else {
3073 uint32_t v32;
3074 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3075 who = v32;
3076 }
3077 break;
3078 }
3079
3080 if (0 == strcmp("show", CMD_ARGV[0])) {
3081 if (who == -1) {
3082 showall:
3083 r = ERROR_OK;
3084 for (x = 0; x < pChip->details.n_gpnvms; x++) {
3085 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
3086 if (r != ERROR_OK)
3087 break;
3088 command_print(CMD_CTX, "sam4-gpnvm%u: %u", x, v);
3089 }
3090 return r;
3091 }
3092 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
3093 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
3094 command_print(CMD_CTX, "sam4-gpnvm%u: %u", who, v);
3095 return r;
3096 } else {
3097 command_print(CMD_CTX, "sam4-gpnvm invalid GPNVM: %u", who);
3098 return ERROR_COMMAND_SYNTAX_ERROR;
3099 }
3100 }
3101
3102 if (who == -1) {
3103 command_print(CMD_CTX, "Missing GPNVM number");
3104 return ERROR_COMMAND_SYNTAX_ERROR;
3105 }
3106
3107 if (0 == strcmp("set", CMD_ARGV[0]))
3108 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
3109 else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
3110 (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
3111 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
3112 else {
3113 command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
3114 r = ERROR_COMMAND_SYNTAX_ERROR;
3115 }
3116 return r;
3117 }
3118
3119 COMMAND_HANDLER(sam4_handle_slowclk_command)
3120 {
3121 struct sam4_chip *pChip;
3122
3123 pChip = get_current_sam4(CMD_CTX);
3124 if (!pChip)
3125 return ERROR_OK;
3126
3127 switch (CMD_ARGC) {
3128 case 0:
3129 /* show */
3130 break;
3131 case 1:
3132 {
3133 /* set */
3134 uint32_t v;
3135 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3136 if (v > 200000) {
3137 /* absurd slow clock of 200Khz? */
3138 command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3139 return ERROR_COMMAND_SYNTAX_ERROR;
3140 }
3141 pChip->cfg.slow_freq = v;
3142 break;
3143 }
3144 default:
3145 /* error */
3146 command_print(CMD_CTX, "Too many parameters");
3147 return ERROR_COMMAND_SYNTAX_ERROR;
3148 break;
3149 }
3150 command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
3151 (int)(pChip->cfg.slow_freq / 1000),
3152 (int)(pChip->cfg.slow_freq % 1000));
3153 return ERROR_OK;
3154 }
3155
3156 static const struct command_registration at91sam4_exec_command_handlers[] = {
3157 {
3158 .name = "gpnvm",
3159 .handler = sam4_handle_gpnvm_command,
3160 .mode = COMMAND_EXEC,
3161 .usage = "[('clr'|'set'|'show') bitnum]",
3162 .help = "Without arguments, shows all bits in the gpnvm "
3163 "register. Otherwise, clears, sets, or shows one "
3164 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3165 },
3166 {
3167 .name = "info",
3168 .handler = sam4_handle_info_command,
3169 .mode = COMMAND_EXEC,
3170 .help = "Print information about the current at91sam4 chip"
3171 "and its flash configuration.",
3172 },
3173 {
3174 .name = "slowclk",
3175 .handler = sam4_handle_slowclk_command,
3176 .mode = COMMAND_EXEC,
3177 .usage = "[clock_hz]",
3178 .help = "Display or set the slowclock frequency "
3179 "(default 32768 Hz).",
3180 },
3181 COMMAND_REGISTRATION_DONE
3182 };
3183 static const struct command_registration at91sam4_command_handlers[] = {
3184 {
3185 .name = "at91sam4",
3186 .mode = COMMAND_ANY,
3187 .help = "at91sam4 flash command group",
3188 .usage = "",
3189 .chain = at91sam4_exec_command_handlers,
3190 },
3191 COMMAND_REGISTRATION_DONE
3192 };
3193
3194 struct flash_driver at91sam4_flash = {
3195 .name = "at91sam4",
3196 .commands = at91sam4_command_handlers,
3197 .flash_bank_command = sam4_flash_bank_command,
3198 .erase = sam4_erase,
3199 .protect = sam4_protect,
3200 .write = sam4_write,
3201 .read = default_flash_read,
3202 .probe = sam4_probe,
3203 .auto_probe = sam4_auto_probe,
3204 .erase_check = default_flash_blank_check,
3205 .protect_check = sam4_protect_check,
3206 .free_driver_priv = sam4_free_driver_priv,
3207 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)