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at91sam4: Add missing SAM4S family CHIPIDs and remove FWS=6.
[openocd.git] / src / flash / nor / at91sam4.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
4 * *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
7 * *
8 * Copyright (C) 2011 by Olivier Schonken, Jim Norris *
9 * (at91sam3x* & at91sam4 support)* *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ****************************************************************************/
24
25 /* Some of the the lower level code was based on code supplied by
26 * ATMEL under this copyright. */
27
28 /* BEGIN ATMEL COPYRIGHT */
29 /* ----------------------------------------------------------------------------
30 * ATMEL Microcontroller Software Support
31 * ----------------------------------------------------------------------------
32 * Copyright (c) 2009, Atmel Corporation
33 *
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions are met:
38 *
39 * - Redistributions of source code must retain the above copyright notice,
40 * this list of conditions and the disclaimer below.
41 *
42 * Atmel's name may not be used to endorse or promote products derived from
43 * this software without specific prior written permission.
44 *
45 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
48 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
51 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
52 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
53 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
54 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 * ----------------------------------------------------------------------------
56 */
57 /* END ATMEL COPYRIGHT */
58
59 #ifdef HAVE_CONFIG_H
60 #include "config.h"
61 #endif
62
63 #include "imp.h"
64 #include <helper/time_support.h>
65
66 #define REG_NAME_WIDTH (12)
67
68 /* at91sam4s/at91sam4e/at91sam4c series (has always one flash bank)*/
69 #define FLASH_BANK_BASE_S 0x00400000
70 #define FLASH_BANK_BASE_C 0x01000000
71
72 /* at91sam4sd series (two one flash banks), first bank address */
73 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
74 /* at91sam4sd16x, second bank address */
75 #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
76 /* at91sam4sd32x, second bank address */
77 #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
78
79 /* at91sam4c32x, first and second bank address */
80 #define FLASH_BANK0_BASE_C32 FLASH_BANK_BASE_C
81 #define FLASH_BANK1_BASE_C32 (FLASH_BANK_BASE_C+(2048*1024/2))
82
83 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
84 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
85 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
86 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
87 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
88 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
89 /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
90 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
91 #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
92 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
93 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
94 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
95 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
96 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
97 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
98 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
99 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
100
101 #define offset_EFC_FMR 0
102 #define offset_EFC_FCR 4
103 #define offset_EFC_FSR 8
104 #define offset_EFC_FRR 12
105
106 extern struct flash_driver at91sam4_flash;
107
108 static float _tomhz(uint32_t freq_hz)
109 {
110 float f;
111
112 f = ((float)(freq_hz)) / 1000000.0;
113 return f;
114 }
115
116 /* How the chip is configured. */
117 struct sam4_cfg {
118 uint32_t unique_id[4];
119
120 uint32_t slow_freq;
121 uint32_t rc_freq;
122 uint32_t mainosc_freq;
123 uint32_t plla_freq;
124 uint32_t mclk_freq;
125 uint32_t cpu_freq;
126 uint32_t fclk_freq;
127 uint32_t pclk0_freq;
128 uint32_t pclk1_freq;
129 uint32_t pclk2_freq;
130
131
132 #define SAM4_CHIPID_CIDR (0x400E0740)
133 uint32_t CHIPID_CIDR;
134 #define SAM4_CHIPID_EXID (0x400E0744)
135 uint32_t CHIPID_EXID;
136
137 #define SAM4_PMC_BASE (0x400E0400)
138 #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
139 uint32_t PMC_SCSR;
140 #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
141 uint32_t PMC_PCSR;
142 #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
143 uint32_t CKGR_UCKR;
144 #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
145 uint32_t CKGR_MOR;
146 #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
147 uint32_t CKGR_MCFR;
148 #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
149 uint32_t CKGR_PLLAR;
150 #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
151 uint32_t PMC_MCKR;
152 #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
153 uint32_t PMC_PCK0;
154 #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
155 uint32_t PMC_PCK1;
156 #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
157 uint32_t PMC_PCK2;
158 #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
159 uint32_t PMC_SR;
160 #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
161 uint32_t PMC_IMR;
162 #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
163 uint32_t PMC_FSMR;
164 #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
165 uint32_t PMC_FSPR;
166 };
167
168 struct sam4_bank_private {
169 int probed;
170 /* DANGER: THERE ARE DRAGONS HERE.. */
171 /* NOTE: If you add more 'ghost' pointers */
172 /* be aware that you must *manually* update */
173 /* these pointers in the function sam4_GetDetails() */
174 /* See the comment "Here there be dragons" */
175
176 /* so we can find the chip we belong to */
177 struct sam4_chip *pChip;
178 /* so we can find the original bank pointer */
179 struct flash_bank *pBank;
180 unsigned bank_number;
181 uint32_t controller_address;
182 uint32_t base_address;
183 uint32_t flash_wait_states;
184 bool present;
185 unsigned size_bytes;
186 unsigned nsectors;
187 unsigned sector_size;
188 unsigned page_size;
189 };
190
191 struct sam4_chip_details {
192 /* THERE ARE DRAGONS HERE.. */
193 /* note: If you add pointers here */
194 /* be careful about them as they */
195 /* may need to be updated inside */
196 /* the function: "sam4_GetDetails() */
197 /* which copy/overwrites the */
198 /* 'runtime' copy of this structure */
199 uint32_t chipid_cidr;
200 const char *name;
201
202 unsigned n_gpnvms;
203 #define SAM4_N_NVM_BITS 3
204 unsigned gpnvm[SAM4_N_NVM_BITS];
205 unsigned total_flash_size;
206 unsigned total_sram_size;
207 unsigned n_banks;
208 #define SAM4_MAX_FLASH_BANKS 2
209 /* these are "initialized" from the global const data */
210 struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS];
211 };
212
213 struct sam4_chip {
214 struct sam4_chip *next;
215 int probed;
216
217 /* this is "initialized" from the global const structure */
218 struct sam4_chip_details details;
219 struct target *target;
220 struct sam4_cfg cfg;
221 };
222
223
224 struct sam4_reg_list {
225 uint32_t address; size_t struct_offset; const char *name;
226 void (*explain_func)(struct sam4_chip *pInfo);
227 };
228
229 static struct sam4_chip *all_sam4_chips;
230
231 static struct sam4_chip *get_current_sam4(struct command_context *cmd_ctx)
232 {
233 struct target *t;
234 static struct sam4_chip *p;
235
236 t = get_current_target(cmd_ctx);
237 if (!t) {
238 command_print(cmd_ctx, "No current target?");
239 return NULL;
240 }
241
242 p = all_sam4_chips;
243 if (!p) {
244 /* this should not happen */
245 /* the command is not registered until the chip is created? */
246 command_print(cmd_ctx, "No SAM4 chips exist?");
247 return NULL;
248 }
249
250 while (p) {
251 if (p->target == t)
252 return p;
253 p = p->next;
254 }
255 command_print(cmd_ctx, "Cannot find SAM4 chip?");
256 return NULL;
257 }
258
259 /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
260 /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
261 /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
262 /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
263
264 /* these are used to *initialize* the "pChip->details" structure. */
265 static const struct sam4_chip_details all_sam4_details[] = {
266 /* Start at91sam4c* series */
267 /* at91sam4c32e - LQFP144 */
268 {
269 .chipid_cidr = 0xA66D0EE0,
270 .name = "at91sam4c32e",
271 .total_flash_size = 2024 * 1024,
272 .total_sram_size = 256 * 1024,
273 .n_gpnvms = 3,
274 .n_banks = 2,
275 /* .bank[0] = { */
276 {
277 {
278 .probed = 0,
279 .pChip = NULL,
280 .pBank = NULL,
281 .bank_number = 0,
282 .base_address = FLASH_BANK0_BASE_C32,
283 .controller_address = 0x400e0a00,
284 .flash_wait_states = 5,
285 .present = 1,
286 .size_bytes = 1024 * 1024,
287 .nsectors = 128,
288 .sector_size = 8192,
289 .page_size = 512,
290 },
291 /* .bank[1] = { */
292 {
293 .probed = 0,
294 .pChip = NULL,
295 .pBank = NULL,
296 .bank_number = 1,
297 .base_address = FLASH_BANK1_BASE_C32,
298 .controller_address = 0x400e0c00,
299 .flash_wait_states = 5,
300 .present = 1,
301 .size_bytes = 1024 * 1024,
302 .nsectors = 128,
303 .sector_size = 8192,
304 .page_size = 512,
305 },
306 },
307 },
308 /* at91sam4c32c - LQFP100 */
309 {
310 .chipid_cidr = 0xA64D0EE0,
311 .name = "at91sam4c32c",
312 .total_flash_size = 2024 * 1024,
313 .total_sram_size = 256 * 1024,
314 .n_gpnvms = 3,
315 .n_banks = 2,
316 /* .bank[0] = { */
317 {
318 {
319 .probed = 0,
320 .pChip = NULL,
321 .pBank = NULL,
322 .bank_number = 0,
323 .base_address = FLASH_BANK0_BASE_C32,
324 .controller_address = 0x400e0a00,
325 .flash_wait_states = 5,
326 .present = 1,
327 .size_bytes = 1024 * 1024,
328 .nsectors = 128,
329 .sector_size = 8192,
330 .page_size = 512,
331 },
332 /* .bank[1] = { */
333 {
334 .probed = 0,
335 .pChip = NULL,
336 .pBank = NULL,
337 .bank_number = 1,
338 .base_address = FLASH_BANK1_BASE_C32,
339 .controller_address = 0x400e0c00,
340 .flash_wait_states = 5,
341 .present = 1,
342 .size_bytes = 1024 * 1024,
343 .nsectors = 128,
344 .sector_size = 8192,
345 .page_size = 512,
346 },
347 },
348 },
349 /* at91sam4c16c - LQFP100 */
350 {
351 .chipid_cidr = 0xA64C0CE0,
352 .name = "at91sam4c16c",
353 .total_flash_size = 1024 * 1024,
354 .total_sram_size = 128 * 1024,
355 .n_gpnvms = 2,
356 .n_banks = 1,
357 {
358 /* .bank[0] = {*/
359 {
360 .probed = 0,
361 .pChip = NULL,
362 .pBank = NULL,
363 .bank_number = 0,
364 .base_address = FLASH_BANK_BASE_C,
365 .controller_address = 0x400e0a00,
366 .flash_wait_states = 5,
367 .present = 1,
368 .size_bytes = 1024 * 1024,
369 .nsectors = 128,
370 .sector_size = 8192,
371 .page_size = 512,
372 },
373 /* .bank[1] = {*/
374 {
375 .present = 0,
376 .probed = 0,
377 .bank_number = 1,
378
379 },
380 },
381 },
382 /* at91sam4c8c - LQFP100 */
383 {
384 .chipid_cidr = 0xA64C0AE0,
385 .name = "at91sam4c8c",
386 .total_flash_size = 512 * 1024,
387 .total_sram_size = 128 * 1024,
388 .n_gpnvms = 2,
389 .n_banks = 1,
390 {
391 /* .bank[0] = {*/
392 {
393 .probed = 0,
394 .pChip = NULL,
395 .pBank = NULL,
396 .bank_number = 0,
397 .base_address = FLASH_BANK_BASE_C,
398 .controller_address = 0x400e0a00,
399 .flash_wait_states = 5,
400 .present = 1,
401 .size_bytes = 512 * 1024,
402 .nsectors = 64,
403 .sector_size = 8192,
404 .page_size = 512,
405 },
406 /* .bank[1] = {*/
407 {
408 .present = 0,
409 .probed = 0,
410 .bank_number = 1,
411
412 },
413 },
414 },
415 /* at91sam4c4c (rev B) - LQFP100 */
416 {
417 .chipid_cidr = 0xA64C0CE5,
418 .name = "at91sam4c4c",
419 .total_flash_size = 256 * 1024,
420 .total_sram_size = 128 * 1024,
421 .n_gpnvms = 2,
422 .n_banks = 1,
423 {
424 /* .bank[0] = {*/
425 {
426 .probed = 0,
427 .pChip = NULL,
428 .pBank = NULL,
429 .bank_number = 0,
430 .base_address = FLASH_BANK_BASE_C,
431 .controller_address = 0x400e0a00,
432 .flash_wait_states = 5,
433 .present = 1,
434 .size_bytes = 256 * 1024,
435 .nsectors = 32,
436 .sector_size = 8192,
437 .page_size = 512,
438 },
439 /* .bank[1] = {*/
440 {
441 .present = 0,
442 .probed = 0,
443 .bank_number = 1,
444
445 },
446 },
447 },
448
449 /* Start at91sam4e* series */
450 /*atsam4e16e - LQFP144/LFBGA144*/
451 {
452 .chipid_cidr = 0xA3CC0CE0,
453 .name = "at91sam4e16e",
454 .total_flash_size = 1024 * 1024,
455 .total_sram_size = 128 * 1024,
456 .n_gpnvms = 2,
457 .n_banks = 1,
458 {
459 /* .bank[0] = {*/
460 {
461 .probed = 0,
462 .pChip = NULL,
463 .pBank = NULL,
464 .bank_number = 0,
465 .base_address = FLASH_BANK_BASE_S,
466 .controller_address = 0x400e0a00,
467 .flash_wait_states = 6, /* workaround silicon bug */
468 .present = 1,
469 .size_bytes = 1024 * 1024,
470 .nsectors = 128,
471 .sector_size = 8192,
472 .page_size = 512,
473 },
474 /* .bank[1] = {*/
475 {
476 .present = 0,
477 .probed = 0,
478 .bank_number = 1,
479
480 },
481 },
482 },
483
484 /* Start at91sam4n* series */
485 /*atsam4n8a - LQFP48/QFN48*/
486 {
487 .chipid_cidr = 0x293B0AE0,
488 .name = "at91sam4n8a",
489 .total_flash_size = 512 * 1024,
490 .total_sram_size = 64 * 1024,
491 .n_gpnvms = 2,
492 .n_banks = 1,
493 {
494 /* .bank[0] = {*/
495 {
496 .probed = 0,
497 .pChip = NULL,
498 .pBank = NULL,
499 .bank_number = 0,
500 .base_address = FLASH_BANK_BASE_S,
501 .controller_address = 0x400e0a00,
502 .flash_wait_states = 6, /* workaround silicon bug */
503 .present = 1,
504 .size_bytes = 512 * 1024,
505 .nsectors = 64,
506 .sector_size = 8192,
507 .page_size = 512,
508 },
509 /* .bank[1] = {*/
510 {
511 .present = 0,
512 .probed = 0,
513 .bank_number = 1,
514
515 },
516 },
517 },
518 /*atsam4n8b - LQFP64/QFN64*/
519 {
520 .chipid_cidr = 0x294B0AE0,
521 .name = "at91sam4n8b",
522 .total_flash_size = 512 * 1024,
523 .total_sram_size = 64 * 1024,
524 .n_gpnvms = 2,
525 .n_banks = 1,
526 {
527 /* .bank[0] = {*/
528 {
529 .probed = 0,
530 .pChip = NULL,
531 .pBank = NULL,
532 .bank_number = 0,
533 .base_address = FLASH_BANK_BASE_S,
534 .controller_address = 0x400e0a00,
535 .flash_wait_states = 6, /* workaround silicon bug */
536 .present = 1,
537 .size_bytes = 512 * 1024,
538 .nsectors = 64,
539 .sector_size = 8192,
540 .page_size = 512,
541 },
542 /* .bank[1] = {*/
543 {
544 .present = 0,
545 .probed = 0,
546 .bank_number = 1,
547
548 },
549 },
550 },
551 /*atsam4n8c - LQFP100/TFBGA100/VFBGA100*/
552 {
553 .chipid_cidr = 0x295B0AE0,
554 .name = "at91sam4n8c",
555 .total_flash_size = 512 * 1024,
556 .total_sram_size = 64 * 1024,
557 .n_gpnvms = 2,
558 .n_banks = 1,
559 {
560 /* .bank[0] = {*/
561 {
562 .probed = 0,
563 .pChip = NULL,
564 .pBank = NULL,
565 .bank_number = 0,
566 .base_address = FLASH_BANK_BASE_S,
567 .controller_address = 0x400e0a00,
568 .flash_wait_states = 6, /* workaround silicon bug */
569 .present = 1,
570 .size_bytes = 512 * 1024,
571 .nsectors = 64,
572 .sector_size = 8192,
573 .page_size = 512,
574 },
575 /* .bank[1] = {*/
576 {
577 .present = 0,
578 .probed = 0,
579 .bank_number = 1,
580
581 },
582 },
583 },
584 /*atsam4n16b - LQFP64/QFN64*/
585 {
586 .chipid_cidr = 0x29460CE0,
587 .name = "at91sam4n16b",
588 .total_flash_size = 1024 * 1024,
589 .total_sram_size = 80 * 1024,
590 .n_gpnvms = 2,
591 .n_banks = 1,
592 {
593 /* .bank[0] = {*/
594 {
595 .probed = 0,
596 .pChip = NULL,
597 .pBank = NULL,
598 .bank_number = 0,
599 .base_address = FLASH_BANK_BASE_S,
600 .controller_address = 0x400e0a00,
601 .flash_wait_states = 6, /* workaround silicon bug */
602 .present = 1,
603 .size_bytes = 1024 * 1024,
604 .nsectors = 128,
605 .sector_size = 8192,
606 .page_size = 512,
607 },
608 /* .bank[1] = {*/
609 {
610 .present = 0,
611 .probed = 0,
612 .bank_number = 1,
613
614 },
615 },
616 },
617 /*atsam4n16c - LQFP100/TFBGA100/VFBGA100*/
618 {
619 .chipid_cidr = 0x29560CE0,
620 .name = "at91sam4n16c",
621 .total_flash_size = 1024 * 1024,
622 .total_sram_size = 80 * 1024,
623 .n_gpnvms = 2,
624 .n_banks = 1,
625 {
626 /* .bank[0] = {*/
627 {
628 .probed = 0,
629 .pChip = NULL,
630 .pBank = NULL,
631 .bank_number = 0,
632 .base_address = FLASH_BANK_BASE_S,
633 .controller_address = 0x400e0a00,
634 .flash_wait_states = 6, /* workaround silicon bug */
635 .present = 1,
636 .size_bytes = 1024 * 1024,
637 .nsectors = 128,
638 .sector_size = 8192,
639 .page_size = 512,
640 },
641 /* .bank[1] = {*/
642 {
643 .present = 0,
644 .probed = 0,
645 .bank_number = 1,
646
647 },
648 },
649 },
650
651 /* Start at91sam4s* series */
652 /*atsam4s16c - LQFP100/BGA100*/
653 {
654 .chipid_cidr = 0x28AC0CE0,
655 .name = "at91sam4s16c",
656 .total_flash_size = 1024 * 1024,
657 .total_sram_size = 128 * 1024,
658 .n_gpnvms = 2,
659 .n_banks = 1,
660 {
661 /* .bank[0] = {*/
662 {
663 .probed = 0,
664 .pChip = NULL,
665 .pBank = NULL,
666 .bank_number = 0,
667 .base_address = FLASH_BANK_BASE_S,
668 .controller_address = 0x400e0a00,
669 .flash_wait_states = 5,
670 .present = 1,
671 .size_bytes = 1024 * 1024,
672 .nsectors = 128,
673 .sector_size = 8192,
674 .page_size = 512,
675 },
676 /* .bank[1] = {*/
677 {
678 .present = 0,
679 .probed = 0,
680 .bank_number = 1,
681
682 },
683 },
684 },
685 /*atsam4s16b - LQFP64/QFN64/WLCSP64*/
686 {
687 .chipid_cidr = 0x289C0CE0,
688 .name = "at91sam4s16b",
689 .total_flash_size = 1024 * 1024,
690 .total_sram_size = 128 * 1024,
691 .n_gpnvms = 2,
692 .n_banks = 1,
693 {
694 /* .bank[0] = {*/
695 {
696 .probed = 0,
697 .pChip = NULL,
698 .pBank = NULL,
699 .bank_number = 0,
700 .base_address = FLASH_BANK_BASE_S,
701 .controller_address = 0x400e0a00,
702 .flash_wait_states = 5,
703 .present = 1,
704 .size_bytes = 1024 * 1024,
705 .nsectors = 128,
706 .sector_size = 8192,
707 .page_size = 512,
708 },
709 /* .bank[1] = {*/
710 {
711 .present = 0,
712 .probed = 0,
713 .bank_number = 1,
714
715 },
716 },
717 },
718 /*atsam4sa16b - LQFP64/QFN64*/
719 {
720 .chipid_cidr = 0x28970CE0,
721 .name = "at91sam4sa16b",
722 .total_flash_size = 1024 * 1024,
723 .total_sram_size = 160 * 1024,
724 .n_gpnvms = 2,
725 .n_banks = 1,
726 {
727 /* .bank[0] = {*/
728 {
729 .probed = 0,
730 .pChip = NULL,
731 .pBank = NULL,
732 .bank_number = 0,
733 .base_address = FLASH_BANK_BASE_S,
734 .controller_address = 0x400e0a00,
735 .flash_wait_states = 5,
736 .present = 1,
737 .size_bytes = 1024 * 1024,
738 .nsectors = 128,
739 .sector_size = 8192,
740 .page_size = 512,
741 },
742 /* .bank[1] = {*/
743 {
744 .present = 0,
745 .probed = 0,
746 .bank_number = 1,
747
748 },
749 },
750 },
751 /*atsam4s16a - LQFP48/QFN48*/
752 {
753 .chipid_cidr = 0x288C0CE0,
754 .name = "at91sam4s16a",
755 .total_flash_size = 1024 * 1024,
756 .total_sram_size = 128 * 1024,
757 .n_gpnvms = 2,
758 .n_banks = 1,
759 {
760 /* .bank[0] = {*/
761 {
762 .probed = 0,
763 .pChip = NULL,
764 .pBank = NULL,
765 .bank_number = 0,
766 .base_address = FLASH_BANK_BASE_S,
767 .controller_address = 0x400e0a00,
768 .flash_wait_states = 5,
769 .present = 1,
770 .size_bytes = 1024 * 1024,
771 .nsectors = 128,
772 .sector_size = 8192,
773 .page_size = 512,
774 },
775 /* .bank[1] = {*/
776 {
777 .present = 0,
778 .probed = 0,
779 .bank_number = 1,
780
781 },
782 },
783 },
784 /*atsam4s8c - LQFP100/BGA100*/
785 {
786 .chipid_cidr = 0x28AC0AE0,
787 .name = "at91sam4s8c",
788 .total_flash_size = 512 * 1024,
789 .total_sram_size = 128 * 1024,
790 .n_gpnvms = 2,
791 .n_banks = 1,
792 {
793 /* .bank[0] = {*/
794 {
795 .probed = 0,
796 .pChip = NULL,
797 .pBank = NULL,
798 .bank_number = 0,
799 .base_address = FLASH_BANK_BASE_S,
800 .controller_address = 0x400e0a00,
801 .flash_wait_states = 5,
802 .present = 1,
803 .size_bytes = 512 * 1024,
804 .nsectors = 64,
805 .sector_size = 8192,
806 .page_size = 512,
807 },
808 /* .bank[1] = {*/
809 {
810 .present = 0,
811 .probed = 0,
812 .bank_number = 1,
813
814 },
815 },
816 },
817 /*atsam4s8b - LQFP64/QFN64/WLCSP64*/
818 {
819 .chipid_cidr = 0x289C0AE0,
820 .name = "at91sam4s8b",
821 .total_flash_size = 512 * 1024,
822 .total_sram_size = 128 * 1024,
823 .n_gpnvms = 2,
824 .n_banks = 1,
825 {
826 /* .bank[0] = {*/
827 {
828 .probed = 0,
829 .pChip = NULL,
830 .pBank = NULL,
831 .bank_number = 0,
832 .base_address = FLASH_BANK_BASE_S,
833 .controller_address = 0x400e0a00,
834 .flash_wait_states = 5,
835 .present = 1,
836 .size_bytes = 512 * 1024,
837 .nsectors = 64,
838 .sector_size = 8192,
839 .page_size = 512,
840 },
841 /* .bank[1] = {*/
842 {
843 .present = 0,
844 .probed = 0,
845 .bank_number = 1,
846
847 },
848 },
849 },
850 /*atsam4s8a - LQFP48/BGA48*/
851 {
852 .chipid_cidr = 0x288C0AE0,
853 .name = "at91sam4s8a",
854 .total_flash_size = 512 * 1024,
855 .total_sram_size = 128 * 1024,
856 .n_gpnvms = 2,
857 .n_banks = 1,
858 {
859 /* .bank[0] = {*/
860 {
861 .probed = 0,
862 .pChip = NULL,
863 .pBank = NULL,
864 .bank_number = 0,
865 .base_address = FLASH_BANK_BASE_S,
866 .controller_address = 0x400e0a00,
867 .flash_wait_states = 5,
868 .present = 1,
869 .size_bytes = 512 * 1024,
870 .nsectors = 64,
871 .sector_size = 8192,
872 .page_size = 512,
873 },
874 /* .bank[1] = {*/
875 {
876 .present = 0,
877 .probed = 0,
878 .bank_number = 1,
879
880 },
881 },
882 },
883
884 /*atsam4s4c - LQFP100/BGA100*/
885 {
886 .chipid_cidr = 0x28ab09e0,
887 .name = "at91sam4s4c",
888 .total_flash_size = 256 * 1024,
889 .total_sram_size = 64 * 1024,
890 .n_gpnvms = 2,
891 .n_banks = 1,
892 {
893 /* .bank[0] = {*/
894 {
895 .probed = 0,
896 .pChip = NULL,
897 .pBank = NULL,
898 .bank_number = 0,
899 .base_address = FLASH_BANK_BASE_S,
900 .controller_address = 0x400e0a00,
901 .flash_wait_states = 5,
902 .present = 1,
903 .size_bytes = 256 * 1024,
904 .nsectors = 32,
905 .sector_size = 8192,
906 .page_size = 512,
907 },
908 /* .bank[1] = {*/
909 {
910 .present = 0,
911 .probed = 0,
912 .bank_number = 1,
913
914 },
915 },
916 },
917
918 /*atsam4s4b - LQFP64/QFN64/WLCSP64*/
919 {
920 .chipid_cidr = 0x289b09e0,
921 .name = "at91sam4s4b",
922 .total_flash_size = 256 * 1024,
923 .total_sram_size = 64 * 1024,
924 .n_gpnvms = 2,
925 .n_banks = 1,
926 {
927 /* .bank[0] = {*/
928 {
929 .probed = 0,
930 .pChip = NULL,
931 .pBank = NULL,
932 .bank_number = 0,
933 .base_address = FLASH_BANK_BASE_S,
934 .controller_address = 0x400e0a00,
935 .flash_wait_states = 5,
936 .present = 1,
937 .size_bytes = 256 * 1024,
938 .nsectors = 32,
939 .sector_size = 8192,
940 .page_size = 512,
941 },
942 /* .bank[1] = {*/
943 {
944 .present = 0,
945 .probed = 0,
946 .bank_number = 1,
947
948 },
949 },
950 },
951
952 /*atsam4s4a - LQFP48/QFN48*/
953 {
954 .chipid_cidr = 0x288b09e0,
955 .name = "at91sam4s4a",
956 .total_flash_size = 256 * 1024,
957 .total_sram_size = 64 * 1024,
958 .n_gpnvms = 2,
959 .n_banks = 1,
960 {
961 /* .bank[0] = {*/
962 {
963 .probed = 0,
964 .pChip = NULL,
965 .pBank = NULL,
966 .bank_number = 0,
967 .base_address = FLASH_BANK_BASE_S,
968 .controller_address = 0x400e0a00,
969 .flash_wait_states = 5,
970 .present = 1,
971 .size_bytes = 256 * 1024,
972 .nsectors = 32,
973 .sector_size = 8192,
974 .page_size = 512,
975 },
976 /* .bank[1] = {*/
977 {
978 .present = 0,
979 .probed = 0,
980 .bank_number = 1,
981
982 },
983 },
984 },
985
986 /*atsam4s2c - LQFP100/BGA100*/
987 {
988 .chipid_cidr = 0x28ab07e0,
989 .name = "at91sam4s2c",
990 .total_flash_size = 128 * 1024,
991 .total_sram_size = 64 * 1024,
992 .n_gpnvms = 2,
993 .n_banks = 1,
994 {
995 /* .bank[0] = {*/
996 {
997 .probed = 0,
998 .pChip = NULL,
999 .pBank = NULL,
1000 .bank_number = 0,
1001 .base_address = FLASH_BANK_BASE_S,
1002 .controller_address = 0x400e0a00,
1003 .flash_wait_states = 5,
1004 .present = 1,
1005 .size_bytes = 128 * 1024,
1006 .nsectors = 16,
1007 .sector_size = 8192,
1008 .page_size = 512,
1009 },
1010 /* .bank[1] = {*/
1011 {
1012 .present = 0,
1013 .probed = 0,
1014 .bank_number = 1,
1015
1016 },
1017 },
1018 },
1019
1020 /*atsam4s2b - LQPF64/QFN64/WLCSP64*/
1021 {
1022 .chipid_cidr = 0x289b07e0,
1023 .name = "at91sam4s2b",
1024 .total_flash_size = 128 * 1024,
1025 .total_sram_size = 64 * 1024,
1026 .n_gpnvms = 2,
1027 .n_banks = 1,
1028 {
1029 /* .bank[0] = {*/
1030 {
1031 .probed = 0,
1032 .pChip = NULL,
1033 .pBank = NULL,
1034 .bank_number = 0,
1035 .base_address = FLASH_BANK_BASE_S,
1036 .controller_address = 0x400e0a00,
1037 .flash_wait_states = 5,
1038 .present = 1,
1039 .size_bytes = 128 * 1024,
1040 .nsectors = 16,
1041 .sector_size = 8192,
1042 .page_size = 512,
1043 },
1044 /* .bank[1] = {*/
1045 {
1046 .present = 0,
1047 .probed = 0,
1048 .bank_number = 1,
1049
1050 },
1051 },
1052 },
1053
1054 /*atsam4s2a - LQFP48/QFN48*/
1055 {
1056 .chipid_cidr = 0x288b07e0,
1057 .name = "at91sam4s2a",
1058 .total_flash_size = 128 * 1024,
1059 .total_sram_size = 64 * 1024,
1060 .n_gpnvms = 2,
1061 .n_banks = 1,
1062 {
1063 /* .bank[0] = {*/
1064 {
1065 .probed = 0,
1066 .pChip = NULL,
1067 .pBank = NULL,
1068 .bank_number = 0,
1069 .base_address = FLASH_BANK_BASE_S,
1070 .controller_address = 0x400e0a00,
1071 .flash_wait_states = 5,
1072 .present = 1,
1073 .size_bytes = 128 * 1024,
1074 .nsectors = 16,
1075 .sector_size = 8192,
1076 .page_size = 512,
1077 },
1078 /* .bank[1] = {*/
1079 {
1080 .present = 0,
1081 .probed = 0,
1082 .bank_number = 1,
1083
1084 },
1085 },
1086 },
1087
1088 /*at91sam4sd32c - LQFP100/BGA100*/
1089 {
1090 .chipid_cidr = 0x29a70ee0,
1091 .name = "at91sam4sd32c",
1092 .total_flash_size = 2048 * 1024,
1093 .total_sram_size = 160 * 1024,
1094 .n_gpnvms = 3,
1095 .n_banks = 2,
1096
1097 /* .bank[0] = { */
1098 {
1099 {
1100 .probed = 0,
1101 .pChip = NULL,
1102 .pBank = NULL,
1103 .bank_number = 0,
1104 .base_address = FLASH_BANK0_BASE_SD,
1105 .controller_address = 0x400e0a00,
1106 .flash_wait_states = 5,
1107 .present = 1,
1108 .size_bytes = 1024 * 1024,
1109 .nsectors = 128,
1110 .sector_size = 8192,
1111 .page_size = 512,
1112 },
1113
1114 /* .bank[1] = { */
1115 {
1116 .probed = 0,
1117 .pChip = NULL,
1118 .pBank = NULL,
1119 .bank_number = 1,
1120 .base_address = FLASH_BANK1_BASE_2048K_SD,
1121 .controller_address = 0x400e0c00,
1122 .flash_wait_states = 5,
1123 .present = 1,
1124 .size_bytes = 1024 * 1024,
1125 .nsectors = 128,
1126 .sector_size = 8192,
1127 .page_size = 512,
1128 },
1129 },
1130 },
1131
1132 /*at91sam4sd32b - LQFP64/BGA64*/
1133 {
1134 .chipid_cidr = 0x29970ee0,
1135 .name = "at91sam4sd32b",
1136 .total_flash_size = 2048 * 1024,
1137 .total_sram_size = 160 * 1024,
1138 .n_gpnvms = 3,
1139 .n_banks = 2,
1140
1141 /* .bank[0] = { */
1142 {
1143 {
1144 .probed = 0,
1145 .pChip = NULL,
1146 .pBank = NULL,
1147 .bank_number = 0,
1148 .base_address = FLASH_BANK0_BASE_SD,
1149 .controller_address = 0x400e0a00,
1150 .flash_wait_states = 5,
1151 .present = 1,
1152 .size_bytes = 1024 * 1024,
1153 .nsectors = 128,
1154 .sector_size = 8192,
1155 .page_size = 512,
1156 },
1157
1158 /* .bank[1] = { */
1159 {
1160 .probed = 0,
1161 .pChip = NULL,
1162 .pBank = NULL,
1163 .bank_number = 1,
1164 .base_address = FLASH_BANK1_BASE_2048K_SD,
1165 .controller_address = 0x400e0c00,
1166 .flash_wait_states = 5,
1167 .present = 1,
1168 .size_bytes = 1024 * 1024,
1169 .nsectors = 128,
1170 .sector_size = 8192,
1171 .page_size = 512,
1172 },
1173 },
1174 },
1175
1176 /*at91sam4sd16c - LQFP100/BGA100*/
1177 {
1178 .chipid_cidr = 0x29a70ce0,
1179 .name = "at91sam4sd16c",
1180 .total_flash_size = 1024 * 1024,
1181 .total_sram_size = 160 * 1024,
1182 .n_gpnvms = 3,
1183 .n_banks = 2,
1184
1185 /* .bank[0] = { */
1186 {
1187 {
1188 .probed = 0,
1189 .pChip = NULL,
1190 .pBank = NULL,
1191 .bank_number = 0,
1192 .base_address = FLASH_BANK0_BASE_SD,
1193 .controller_address = 0x400e0a00,
1194 .flash_wait_states = 5,
1195 .present = 1,
1196 .size_bytes = 512 * 1024,
1197 .nsectors = 64,
1198 .sector_size = 8192,
1199 .page_size = 512,
1200 },
1201
1202 /* .bank[1] = { */
1203 {
1204 .probed = 0,
1205 .pChip = NULL,
1206 .pBank = NULL,
1207 .bank_number = 1,
1208 .base_address = FLASH_BANK1_BASE_1024K_SD,
1209 .controller_address = 0x400e0c00,
1210 .flash_wait_states = 5,
1211 .present = 1,
1212 .size_bytes = 512 * 1024,
1213 .nsectors = 64,
1214 .sector_size = 8192,
1215 .page_size = 512,
1216 },
1217 },
1218 },
1219
1220 /*at91sam4sd16b - LQFP64/BGA64*/
1221 {
1222 .chipid_cidr = 0x29970ce0,
1223 .name = "at91sam4sd16b",
1224 .total_flash_size = 1024 * 1024,
1225 .total_sram_size = 160 * 1024,
1226 .n_gpnvms = 3,
1227 .n_banks = 2,
1228
1229 /* .bank[0] = { */
1230 {
1231 {
1232 .probed = 0,
1233 .pChip = NULL,
1234 .pBank = NULL,
1235 .bank_number = 0,
1236 .base_address = FLASH_BANK0_BASE_SD,
1237 .controller_address = 0x400e0a00,
1238 .flash_wait_states = 5,
1239 .present = 1,
1240 .size_bytes = 512 * 1024,
1241 .nsectors = 64,
1242 .sector_size = 8192,
1243 .page_size = 512,
1244 },
1245
1246 /* .bank[1] = { */
1247 {
1248 .probed = 0,
1249 .pChip = NULL,
1250 .pBank = NULL,
1251 .bank_number = 1,
1252 .base_address = FLASH_BANK1_BASE_1024K_SD,
1253 .controller_address = 0x400e0c00,
1254 .flash_wait_states = 5,
1255 .present = 1,
1256 .size_bytes = 512 * 1024,
1257 .nsectors = 64,
1258 .sector_size = 8192,
1259 .page_size = 512,
1260 },
1261 },
1262 },
1263
1264 /*at91sam4sa16c*/
1265 {
1266 .chipid_cidr = 0x28a70ce0,
1267 .name = "at91sam4sa16c",
1268 .total_flash_size = 1024 * 1024,
1269 .total_sram_size = 160 * 1024,
1270 .n_gpnvms = 3,
1271 .n_banks = 2,
1272
1273 /* .bank[0] = { */
1274 {
1275 {
1276 .probed = 0,
1277 .pChip = NULL,
1278 .pBank = NULL,
1279 .bank_number = 0,
1280 .base_address = FLASH_BANK0_BASE_SD,
1281 .controller_address = 0x400e0a00,
1282 .flash_wait_states = 6, /* workaround silicon bug */
1283 .present = 1,
1284 .size_bytes = 512 * 1024,
1285 .nsectors = 64,
1286 .sector_size = 8192,
1287 .page_size = 512,
1288 },
1289
1290 /* .bank[1] = { */
1291 {
1292 .probed = 0,
1293 .pChip = NULL,
1294 .pBank = NULL,
1295 .bank_number = 1,
1296 .base_address = FLASH_BANK1_BASE_1024K_SD,
1297 .controller_address = 0x400e0c00,
1298 .flash_wait_states = 6, /* workaround silicon bug */
1299 .present = 1,
1300 .size_bytes = 512 * 1024,
1301 .nsectors = 64,
1302 .sector_size = 8192,
1303 .page_size = 512,
1304 },
1305 },
1306 },
1307
1308 /* at91samg53n19 */
1309 {
1310 .chipid_cidr = 0x247e0ae0,
1311 .name = "at91samg53n19",
1312 .total_flash_size = 512 * 1024,
1313 .total_sram_size = 96 * 1024,
1314 .n_gpnvms = 2,
1315 .n_banks = 1,
1316
1317 /* .bank[0] = {*/
1318 {
1319 {
1320 .probed = 0,
1321 .pChip = NULL,
1322 .pBank = NULL,
1323 .bank_number = 0,
1324 .base_address = FLASH_BANK_BASE_S,
1325 .controller_address = 0x400e0a00,
1326 .flash_wait_states = 6, /* workaround silicon bug */
1327 .present = 1,
1328 .size_bytes = 512 * 1024,
1329 .nsectors = 64,
1330 .sector_size = 8192,
1331 .page_size = 512,
1332 },
1333 /* .bank[1] = {*/
1334 {
1335 .present = 0,
1336 .probed = 0,
1337 .bank_number = 1,
1338
1339 },
1340 }
1341 },
1342
1343 /* terminate */
1344 {
1345 .chipid_cidr = 0,
1346 .name = NULL,
1347 }
1348 };
1349
1350 /* Globals above */
1351 /***********************************************************************
1352 **********************************************************************
1353 **********************************************************************
1354 **********************************************************************
1355 **********************************************************************
1356 **********************************************************************/
1357 /* *ATMEL* style code - from the SAM4 driver code */
1358
1359 /**
1360 * Get the current status of the EEFC and
1361 * the value of some status bits (LOCKE, PROGE).
1362 * @param pPrivate - info about the bank
1363 * @param v - result goes here
1364 */
1365 static int EFC_GetStatus(struct sam4_bank_private *pPrivate, uint32_t *v)
1366 {
1367 int r;
1368 r = target_read_u32(pPrivate->pChip->target,
1369 pPrivate->controller_address + offset_EFC_FSR,
1370 v);
1371 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1372 (unsigned int)(*v),
1373 ((unsigned int)((*v >> 2) & 1)),
1374 ((unsigned int)((*v >> 1) & 1)),
1375 ((unsigned int)((*v >> 0) & 1)));
1376
1377 return r;
1378 }
1379
1380 /**
1381 * Get the result of the last executed command.
1382 * @param pPrivate - info about the bank
1383 * @param v - result goes here
1384 */
1385 static int EFC_GetResult(struct sam4_bank_private *pPrivate, uint32_t *v)
1386 {
1387 int r;
1388 uint32_t rv;
1389 r = target_read_u32(pPrivate->pChip->target,
1390 pPrivate->controller_address + offset_EFC_FRR,
1391 &rv);
1392 if (v)
1393 *v = rv;
1394 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
1395 return r;
1396 }
1397
1398 static int EFC_StartCommand(struct sam4_bank_private *pPrivate,
1399 unsigned command, unsigned argument)
1400 {
1401 uint32_t n, v;
1402 int r;
1403 int retry;
1404
1405 retry = 0;
1406 do_retry:
1407
1408 /* Check command & argument */
1409 switch (command) {
1410
1411 case AT91C_EFC_FCMD_WP:
1412 case AT91C_EFC_FCMD_WPL:
1413 case AT91C_EFC_FCMD_EWP:
1414 case AT91C_EFC_FCMD_EWPL:
1415 /* case AT91C_EFC_FCMD_EPL: */
1416 case AT91C_EFC_FCMD_EPA:
1417 case AT91C_EFC_FCMD_SLB:
1418 case AT91C_EFC_FCMD_CLB:
1419 n = (pPrivate->size_bytes / pPrivate->page_size);
1420 if (argument >= n)
1421 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
1422 break;
1423
1424 case AT91C_EFC_FCMD_SFB:
1425 case AT91C_EFC_FCMD_CFB:
1426 if (argument >= pPrivate->pChip->details.n_gpnvms) {
1427 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1428 pPrivate->pChip->details.n_gpnvms);
1429 }
1430 break;
1431
1432 case AT91C_EFC_FCMD_GETD:
1433 case AT91C_EFC_FCMD_EA:
1434 case AT91C_EFC_FCMD_GLB:
1435 case AT91C_EFC_FCMD_GFB:
1436 case AT91C_EFC_FCMD_STUI:
1437 case AT91C_EFC_FCMD_SPUI:
1438 if (argument != 0)
1439 LOG_ERROR("Argument is meaningless for cmd: %d", command);
1440 break;
1441 default:
1442 LOG_ERROR("Unknown command %d", command);
1443 break;
1444 }
1445
1446 if (command == AT91C_EFC_FCMD_SPUI) {
1447 /* this is a very special situation. */
1448 /* Situation (1) - error/retry - see below */
1449 /* And we are being called recursively */
1450 /* Situation (2) - normal, finished reading unique id */
1451 } else {
1452 /* it should be "ready" */
1453 EFC_GetStatus(pPrivate, &v);
1454 if (v & 1) {
1455 /* then it is ready */
1456 /* we go on */
1457 } else {
1458 if (retry) {
1459 /* we have done this before */
1460 /* the controller is not responding. */
1461 LOG_ERROR("flash controller(%d) is not ready! Error",
1462 pPrivate->bank_number);
1463 return ERROR_FAIL;
1464 } else {
1465 retry++;
1466 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1467 pPrivate->bank_number);
1468 /* we do that by issuing the *STOP* command */
1469 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
1470 /* above is recursive, and further recursion is blocked by */
1471 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1472 goto do_retry;
1473 }
1474 }
1475 }
1476
1477 v = (0x5A << 24) | (argument << 8) | command;
1478 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
1479 r = target_write_u32(pPrivate->pBank->target,
1480 pPrivate->controller_address + offset_EFC_FCR, v);
1481 if (r != ERROR_OK)
1482 LOG_DEBUG("Error Write failed");
1483 return r;
1484 }
1485
1486 /**
1487 * Performs the given command and wait until its completion (or an error).
1488 * @param pPrivate - info about the bank
1489 * @param command - Command to perform.
1490 * @param argument - Optional command argument.
1491 * @param status - put command status bits here
1492 */
1493 static int EFC_PerformCommand(struct sam4_bank_private *pPrivate,
1494 unsigned command,
1495 unsigned argument,
1496 uint32_t *status)
1497 {
1498
1499 int r;
1500 uint32_t v;
1501 int64_t ms_now, ms_end;
1502
1503 /* default */
1504 if (status)
1505 *status = 0;
1506
1507 r = EFC_StartCommand(pPrivate, command, argument);
1508 if (r != ERROR_OK)
1509 return r;
1510
1511 ms_end = 10000 + timeval_ms();
1512
1513 do {
1514 r = EFC_GetStatus(pPrivate, &v);
1515 if (r != ERROR_OK)
1516 return r;
1517 ms_now = timeval_ms();
1518 if (ms_now > ms_end) {
1519 /* error */
1520 LOG_ERROR("Command timeout");
1521 return ERROR_FAIL;
1522 }
1523 } while ((v & 1) == 0);
1524
1525 /* error bits.. */
1526 if (status)
1527 *status = (v & 0x6);
1528 return ERROR_OK;
1529
1530 }
1531
1532 /**
1533 * Read the unique ID.
1534 * @param pPrivate - info about the bank
1535 * The unique ID is stored in the 'pPrivate' structure.
1536 */
1537 static int FLASHD_ReadUniqueID(struct sam4_bank_private *pPrivate)
1538 {
1539 int r;
1540 uint32_t v;
1541 int x;
1542 /* assume 0 */
1543 pPrivate->pChip->cfg.unique_id[0] = 0;
1544 pPrivate->pChip->cfg.unique_id[1] = 0;
1545 pPrivate->pChip->cfg.unique_id[2] = 0;
1546 pPrivate->pChip->cfg.unique_id[3] = 0;
1547
1548 LOG_DEBUG("Begin");
1549 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
1550 if (r < 0)
1551 return r;
1552
1553 for (x = 0; x < 4; x++) {
1554 r = target_read_u32(pPrivate->pChip->target,
1555 pPrivate->pBank->base + (x * 4),
1556 &v);
1557 if (r < 0)
1558 return r;
1559 pPrivate->pChip->cfg.unique_id[x] = v;
1560 }
1561
1562 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
1563 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1564 r,
1565 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
1566 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
1567 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
1568 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
1569 return r;
1570
1571 }
1572
1573 /**
1574 * Erases the entire flash.
1575 * @param pPrivate - the info about the bank.
1576 */
1577 static int FLASHD_EraseEntireBank(struct sam4_bank_private *pPrivate)
1578 {
1579 LOG_DEBUG("Here");
1580 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
1581 }
1582
1583 /**
1584 * Erases the entire flash.
1585 * @param pPrivate - the info about the bank.
1586 */
1587 static int FLASHD_ErasePages(struct sam4_bank_private *pPrivate,
1588 int firstPage,
1589 int numPages,
1590 uint32_t *status)
1591 {
1592 LOG_DEBUG("Here");
1593 uint8_t erasePages;
1594 switch (numPages) {
1595 case 4:
1596 erasePages = 0x00;
1597 break;
1598 case 8:
1599 erasePages = 0x01;
1600 break;
1601 case 16:
1602 erasePages = 0x02;
1603 break;
1604 case 32:
1605 erasePages = 0x03;
1606 break;
1607 default:
1608 erasePages = 0x00;
1609 break;
1610 }
1611
1612 /* AT91C_EFC_FCMD_EPA
1613 * According to the datasheet FARG[15:2] defines the page from which
1614 * the erase will start.This page must be modulo 4, 8, 16 or 32
1615 * according to the number of pages to erase. FARG[1:0] defines the
1616 * number of pages to be erased. Previously (firstpage << 2) was used
1617 * to conform to this, seems it should not be shifted...
1618 */
1619 return EFC_PerformCommand(pPrivate,
1620 /* send Erase Page */
1621 AT91C_EFC_FCMD_EPA,
1622 (firstPage) | erasePages,
1623 status);
1624 }
1625
1626 /**
1627 * Gets current GPNVM state.
1628 * @param pPrivate - info about the bank.
1629 * @param gpnvm - GPNVM bit index.
1630 * @param puthere - result stored here.
1631 */
1632 /* ------------------------------------------------------------------------------ */
1633 static int FLASHD_GetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
1634 {
1635 uint32_t v;
1636 int r;
1637
1638 LOG_DEBUG("Here");
1639 if (pPrivate->bank_number != 0) {
1640 LOG_ERROR("GPNVM only works with Bank0");
1641 return ERROR_FAIL;
1642 }
1643
1644 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1645 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1646 gpnvm, pPrivate->pChip->details.n_gpnvms);
1647 return ERROR_FAIL;
1648 }
1649
1650 /* Get GPNVMs status */
1651 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
1652 if (r != ERROR_OK) {
1653 LOG_ERROR("Failed");
1654 return r;
1655 }
1656
1657 r = EFC_GetResult(pPrivate, &v);
1658
1659 if (puthere) {
1660 /* Check if GPNVM is set */
1661 /* get the bit and make it a 0/1 */
1662 *puthere = (v >> gpnvm) & 1;
1663 }
1664
1665 return r;
1666 }
1667
1668 /**
1669 * Clears the selected GPNVM bit.
1670 * @param pPrivate info about the bank
1671 * @param gpnvm GPNVM index.
1672 * @returns 0 if successful; otherwise returns an error code.
1673 */
1674 static int FLASHD_ClrGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
1675 {
1676 int r;
1677 unsigned v;
1678
1679 LOG_DEBUG("Here");
1680 if (pPrivate->bank_number != 0) {
1681 LOG_ERROR("GPNVM only works with Bank0");
1682 return ERROR_FAIL;
1683 }
1684
1685 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1686 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1687 gpnvm, pPrivate->pChip->details.n_gpnvms);
1688 return ERROR_FAIL;
1689 }
1690
1691 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1692 if (r != ERROR_OK) {
1693 LOG_DEBUG("Failed: %d", r);
1694 return r;
1695 }
1696 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
1697 LOG_DEBUG("End: %d", r);
1698 return r;
1699 }
1700
1701 /**
1702 * Sets the selected GPNVM bit.
1703 * @param pPrivate info about the bank
1704 * @param gpnvm GPNVM index.
1705 */
1706 static int FLASHD_SetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
1707 {
1708 int r;
1709 unsigned v;
1710
1711 if (pPrivate->bank_number != 0) {
1712 LOG_ERROR("GPNVM only works with Bank0");
1713 return ERROR_FAIL;
1714 }
1715
1716 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1717 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1718 gpnvm, pPrivate->pChip->details.n_gpnvms);
1719 return ERROR_FAIL;
1720 }
1721
1722 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1723 if (r != ERROR_OK)
1724 return r;
1725 if (v) {
1726 /* already set */
1727 r = ERROR_OK;
1728 } else {
1729 /* set it */
1730 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
1731 }
1732 return r;
1733 }
1734
1735 /**
1736 * Returns a bit field (at most 64) of locked regions within a page.
1737 * @param pPrivate info about the bank
1738 * @param v where to store locked bits
1739 */
1740 static int FLASHD_GetLockBits(struct sam4_bank_private *pPrivate, uint32_t *v)
1741 {
1742 int r;
1743 LOG_DEBUG("Here");
1744 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
1745 if (r == ERROR_OK) {
1746 EFC_GetResult(pPrivate, v);
1747 EFC_GetResult(pPrivate, v);
1748 EFC_GetResult(pPrivate, v);
1749 r = EFC_GetResult(pPrivate, v);
1750 }
1751 LOG_DEBUG("End: %d", r);
1752 return r;
1753 }
1754
1755 /**
1756 * Unlocks all the regions in the given address range.
1757 * @param pPrivate info about the bank
1758 * @param start_sector first sector to unlock
1759 * @param end_sector last (inclusive) to unlock
1760 */
1761
1762 static int FLASHD_Unlock(struct sam4_bank_private *pPrivate,
1763 unsigned start_sector,
1764 unsigned end_sector)
1765 {
1766 int r;
1767 uint32_t status;
1768 uint32_t pg;
1769 uint32_t pages_per_sector;
1770
1771 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1772
1773 /* Unlock all pages */
1774 while (start_sector <= end_sector) {
1775 pg = start_sector * pages_per_sector;
1776
1777 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
1778 if (r != ERROR_OK)
1779 return r;
1780 start_sector++;
1781 }
1782
1783 return ERROR_OK;
1784 }
1785
1786 /**
1787 * Locks regions
1788 * @param pPrivate - info about the bank
1789 * @param start_sector - first sector to lock
1790 * @param end_sector - last sector (inclusive) to lock
1791 */
1792 static int FLASHD_Lock(struct sam4_bank_private *pPrivate,
1793 unsigned start_sector,
1794 unsigned end_sector)
1795 {
1796 uint32_t status;
1797 uint32_t pg;
1798 uint32_t pages_per_sector;
1799 int r;
1800
1801 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1802
1803 /* Lock all pages */
1804 while (start_sector <= end_sector) {
1805 pg = start_sector * pages_per_sector;
1806
1807 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
1808 if (r != ERROR_OK)
1809 return r;
1810 start_sector++;
1811 }
1812 return ERROR_OK;
1813 }
1814
1815 /****** END SAM4 CODE ********/
1816
1817 /* begin helpful debug code */
1818 /* print the fieldname, the field value, in dec & hex, and return field value */
1819 static uint32_t sam4_reg_fieldname(struct sam4_chip *pChip,
1820 const char *regname,
1821 uint32_t value,
1822 unsigned shift,
1823 unsigned width)
1824 {
1825 uint32_t v;
1826 int hwidth, dwidth;
1827
1828
1829 /* extract the field */
1830 v = value >> shift;
1831 v = v & ((1 << width)-1);
1832 if (width <= 16) {
1833 hwidth = 4;
1834 dwidth = 5;
1835 } else {
1836 hwidth = 8;
1837 dwidth = 12;
1838 }
1839
1840 /* show the basics */
1841 LOG_USER_N("\t%*s: %*" PRId32 " [0x%0*" PRIx32 "] ",
1842 REG_NAME_WIDTH, regname,
1843 dwidth, v,
1844 hwidth, v);
1845 return v;
1846 }
1847
1848 static const char _unknown[] = "unknown";
1849 static const char *const eproc_names[] = {
1850 "Cortex-M7", /* 0 */
1851 "arm946es", /* 1 */
1852 "arm7tdmi", /* 2 */
1853 "Cortex-M3", /* 3 */
1854 "arm920t", /* 4 */
1855 "arm926ejs", /* 5 */
1856 "Cortex-A5", /* 6 */
1857 "Cortex-M4", /* 7 */
1858 _unknown, /* 8 */
1859 _unknown, /* 9 */
1860 _unknown, /* 10 */
1861 _unknown, /* 11 */
1862 _unknown, /* 12 */
1863 _unknown, /* 13 */
1864 _unknown, /* 14 */
1865 _unknown, /* 15 */
1866 };
1867
1868 #define nvpsize2 nvpsize /* these two tables are identical */
1869 static const char *const nvpsize[] = {
1870 "none", /* 0 */
1871 "8K bytes", /* 1 */
1872 "16K bytes", /* 2 */
1873 "32K bytes", /* 3 */
1874 _unknown, /* 4 */
1875 "64K bytes", /* 5 */
1876 _unknown, /* 6 */
1877 "128K bytes", /* 7 */
1878 "160K bytes", /* 8 */
1879 "256K bytes", /* 9 */
1880 "512K bytes", /* 10 */
1881 _unknown, /* 11 */
1882 "1024K bytes", /* 12 */
1883 _unknown, /* 13 */
1884 "2048K bytes", /* 14 */
1885 _unknown, /* 15 */
1886 };
1887
1888 static const char *const sramsize[] = {
1889 "48K Bytes", /* 0 */
1890 "1K Bytes", /* 1 */
1891 "2K Bytes", /* 2 */
1892 "6K Bytes", /* 3 */
1893 "112K Bytes", /* 4 */
1894 "4K Bytes", /* 5 */
1895 "80K Bytes", /* 6 */
1896 "160K Bytes", /* 7 */
1897 "8K Bytes", /* 8 */
1898 "16K Bytes", /* 9 */
1899 "32K Bytes", /* 10 */
1900 "64K Bytes", /* 11 */
1901 "128K Bytes", /* 12 */
1902 "256K Bytes", /* 13 */
1903 "96K Bytes", /* 14 */
1904 "512K Bytes", /* 15 */
1905
1906 };
1907
1908 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1909 { 0x19, "AT91SAM9xx Series" },
1910 { 0x29, "AT91SAM9XExx Series" },
1911 { 0x34, "AT91x34 Series" },
1912 { 0x37, "CAP7 Series" },
1913 { 0x39, "CAP9 Series" },
1914 { 0x3B, "CAP11 Series" },
1915 { 0x3C, "ATSAM4E" },
1916 { 0x40, "AT91x40 Series" },
1917 { 0x42, "AT91x42 Series" },
1918 { 0x43, "SAMG51 Series"
1919 },
1920 { 0x47, "SAMG53 Series"
1921 },
1922 { 0x55, "AT91x55 Series" },
1923 { 0x60, "AT91SAM7Axx Series" },
1924 { 0x61, "AT91SAM7AQxx Series" },
1925 { 0x63, "AT91x63 Series" },
1926 { 0x64, "SAM4CxxC (100-pin version)" },
1927 { 0x66, "SAM4CxxE (144-pin version)" },
1928 { 0x70, "AT91SAM7Sxx Series" },
1929 { 0x71, "AT91SAM7XCxx Series" },
1930 { 0x72, "AT91SAM7SExx Series" },
1931 { 0x73, "AT91SAM7Lxx Series" },
1932 { 0x75, "AT91SAM7Xxx Series" },
1933 { 0x76, "AT91SAM7SLxx Series" },
1934 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1935 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1936 { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
1937 { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
1938 { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
1939 { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
1940 { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
1941 { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
1942 { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
1943 { 0x92, "AT91x92 Series" },
1944 { 0x93, "ATSAM3NxA Series (48-pin version)" },
1945 { 0x94, "ATSAM3NxB Series (64-pin version)" },
1946 { 0x95, "ATSAM3NxC Series (100-pin version)" },
1947 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
1948 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
1949 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
1950 { 0xA5, "ATSAM5A" },
1951 { 0xF0, "AT75Cxx Series" },
1952 { -1, NULL },
1953 };
1954
1955 static const char *const nvptype[] = {
1956 "rom", /* 0 */
1957 "romless or onchip flash", /* 1 */
1958 "embedded flash memory",/* 2 */
1959 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
1960 "sram emulating flash", /* 4 */
1961 _unknown, /* 5 */
1962 _unknown, /* 6 */
1963 _unknown, /* 7 */
1964 };
1965
1966 static const char *_yes_or_no(uint32_t v)
1967 {
1968 if (v)
1969 return "YES";
1970 else
1971 return "NO";
1972 }
1973
1974 static const char *const _rc_freq[] = {
1975 "4 MHz", "8 MHz", "12 MHz", "reserved"
1976 };
1977
1978 static void sam4_explain_ckgr_mor(struct sam4_chip *pChip)
1979 {
1980 uint32_t v;
1981 uint32_t rcen;
1982
1983 v = sam4_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
1984 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
1985 v = sam4_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
1986 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
1987 rcen = sam4_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
1988 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
1989 v = sam4_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
1990 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
1991
1992 pChip->cfg.rc_freq = 0;
1993 if (rcen) {
1994 switch (v) {
1995 default:
1996 pChip->cfg.rc_freq = 0;
1997 break;
1998 case 0:
1999 pChip->cfg.rc_freq = 4 * 1000 * 1000;
2000 break;
2001 case 1:
2002 pChip->cfg.rc_freq = 8 * 1000 * 1000;
2003 break;
2004 case 2:
2005 pChip->cfg.rc_freq = 12 * 1000 * 1000;
2006 break;
2007 }
2008 }
2009
2010 v = sam4_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
2011 LOG_USER("(startup clks, time= %f uSecs)",
2012 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
2013 v = sam4_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
2014 LOG_USER("(mainosc source: %s)",
2015 v ? "external xtal" : "internal RC");
2016
2017 v = sam4_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
2018 LOG_USER("(clock failure enabled: %s)",
2019 _yes_or_no(v));
2020 }
2021
2022 static void sam4_explain_chipid_cidr(struct sam4_chip *pChip)
2023 {
2024 int x;
2025 uint32_t v;
2026 const char *cp;
2027
2028 sam4_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
2029 LOG_USER_N("\n");
2030
2031 v = sam4_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
2032 LOG_USER("%s", eproc_names[v]);
2033
2034 v = sam4_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
2035 LOG_USER("%s", nvpsize[v]);
2036
2037 v = sam4_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
2038 LOG_USER("%s", nvpsize2[v]);
2039
2040 v = sam4_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
2041 LOG_USER("%s", sramsize[v]);
2042
2043 v = sam4_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
2044 cp = _unknown;
2045 for (x = 0; archnames[x].name; x++) {
2046 if (v == archnames[x].value) {
2047 cp = archnames[x].name;
2048 break;
2049 }
2050 }
2051
2052 LOG_USER("%s", cp);
2053
2054 v = sam4_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
2055 LOG_USER("%s", nvptype[v]);
2056
2057 v = sam4_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
2058 LOG_USER("(exists: %s)", _yes_or_no(v));
2059 }
2060
2061 static void sam4_explain_ckgr_mcfr(struct sam4_chip *pChip)
2062 {
2063 uint32_t v;
2064
2065 v = sam4_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
2066 LOG_USER("(main ready: %s)", _yes_or_no(v));
2067
2068 v = sam4_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
2069
2070 v = (v * pChip->cfg.slow_freq) / 16;
2071 pChip->cfg.mainosc_freq = v;
2072
2073 LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
2074 _tomhz(v),
2075 (uint32_t)(pChip->cfg.slow_freq / 1000),
2076 (uint32_t)(pChip->cfg.slow_freq % 1000));
2077 }
2078
2079 static void sam4_explain_ckgr_plla(struct sam4_chip *pChip)
2080 {
2081 uint32_t mula, diva;
2082
2083 diva = sam4_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
2084 LOG_USER_N("\n");
2085 mula = sam4_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
2086 LOG_USER_N("\n");
2087 pChip->cfg.plla_freq = 0;
2088 if (mula == 0)
2089 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2090 else if (diva == 0)
2091 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2092 else if (diva >= 1) {
2093 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
2094 LOG_USER("\tPLLA Freq: %3.03f MHz",
2095 _tomhz(pChip->cfg.plla_freq));
2096 }
2097 }
2098
2099 static void sam4_explain_mckr(struct sam4_chip *pChip)
2100 {
2101 uint32_t css, pres, fin = 0;
2102 int pdiv = 0;
2103 const char *cp = NULL;
2104
2105 css = sam4_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
2106 switch (css & 3) {
2107 case 0:
2108 fin = pChip->cfg.slow_freq;
2109 cp = "slowclk";
2110 break;
2111 case 1:
2112 fin = pChip->cfg.mainosc_freq;
2113 cp = "mainosc";
2114 break;
2115 case 2:
2116 fin = pChip->cfg.plla_freq;
2117 cp = "plla";
2118 break;
2119 case 3:
2120 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
2121 fin = 480 * 1000 * 1000;
2122 cp = "upll";
2123 } else {
2124 fin = 0;
2125 cp = "upll (*ERROR* UPLL is disabled)";
2126 }
2127 break;
2128 default:
2129 assert(0);
2130 break;
2131 }
2132
2133 LOG_USER("%s (%3.03f Mhz)",
2134 cp,
2135 _tomhz(fin));
2136 pres = sam4_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
2137 switch (pres & 0x07) {
2138 case 0:
2139 pdiv = 1;
2140 cp = "selected clock";
2141 break;
2142 case 1:
2143 pdiv = 2;
2144 cp = "clock/2";
2145 break;
2146 case 2:
2147 pdiv = 4;
2148 cp = "clock/4";
2149 break;
2150 case 3:
2151 pdiv = 8;
2152 cp = "clock/8";
2153 break;
2154 case 4:
2155 pdiv = 16;
2156 cp = "clock/16";
2157 break;
2158 case 5:
2159 pdiv = 32;
2160 cp = "clock/32";
2161 break;
2162 case 6:
2163 pdiv = 64;
2164 cp = "clock/64";
2165 break;
2166 case 7:
2167 pdiv = 6;
2168 cp = "clock/6";
2169 break;
2170 default:
2171 assert(0);
2172 break;
2173 }
2174 LOG_USER("(%s)", cp);
2175 fin = fin / pdiv;
2176 /* sam4 has a *SINGLE* clock - */
2177 /* other at91 series parts have divisors for these. */
2178 pChip->cfg.cpu_freq = fin;
2179 pChip->cfg.mclk_freq = fin;
2180 pChip->cfg.fclk_freq = fin;
2181 LOG_USER("\t\tResult CPU Freq: %3.03f",
2182 _tomhz(fin));
2183 }
2184
2185 #if 0
2186 static struct sam4_chip *target2sam4(struct target *pTarget)
2187 {
2188 struct sam4_chip *pChip;
2189
2190 if (pTarget == NULL)
2191 return NULL;
2192
2193 pChip = all_sam4_chips;
2194 while (pChip) {
2195 if (pChip->target == pTarget)
2196 break; /* return below */
2197 else
2198 pChip = pChip->next;
2199 }
2200 return pChip;
2201 }
2202 #endif
2203
2204 static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *pCfg, const struct sam4_reg_list *pList)
2205 {
2206 /* this function exists to help */
2207 /* keep funky offsetof() errors */
2208 /* and casting from causing bugs */
2209
2210 /* By using prototypes - we can detect what would */
2211 /* be casting errors. */
2212
2213 return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
2214 }
2215
2216
2217 #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
2218 struct sam4_cfg, \
2219 NAME), # NAME, FUNC }
2220 static const struct sam4_reg_list sam4_all_regs[] = {
2221 SAM4_ENTRY(CKGR_MOR, sam4_explain_ckgr_mor),
2222 SAM4_ENTRY(CKGR_MCFR, sam4_explain_ckgr_mcfr),
2223 SAM4_ENTRY(CKGR_PLLAR, sam4_explain_ckgr_plla),
2224 SAM4_ENTRY(CKGR_UCKR, NULL),
2225 SAM4_ENTRY(PMC_FSMR, NULL),
2226 SAM4_ENTRY(PMC_FSPR, NULL),
2227 SAM4_ENTRY(PMC_IMR, NULL),
2228 SAM4_ENTRY(PMC_MCKR, sam4_explain_mckr),
2229 SAM4_ENTRY(PMC_PCK0, NULL),
2230 SAM4_ENTRY(PMC_PCK1, NULL),
2231 SAM4_ENTRY(PMC_PCK2, NULL),
2232 SAM4_ENTRY(PMC_PCSR, NULL),
2233 SAM4_ENTRY(PMC_SCSR, NULL),
2234 SAM4_ENTRY(PMC_SR, NULL),
2235 SAM4_ENTRY(CHIPID_CIDR, sam4_explain_chipid_cidr),
2236 SAM4_ENTRY(CHIPID_EXID, NULL),
2237 /* TERMINATE THE LIST */
2238 { .name = NULL }
2239 };
2240 #undef SAM4_ENTRY
2241
2242 static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
2243 {
2244 return bank->driver_priv;
2245 }
2246
2247 /**
2248 * Given a pointer to where it goes in the structure,
2249 * determine the register name, address from the all registers table.
2250 */
2251 static const struct sam4_reg_list *sam4_GetReg(struct sam4_chip *pChip, uint32_t *goes_here)
2252 {
2253 const struct sam4_reg_list *pReg;
2254
2255 pReg = &(sam4_all_regs[0]);
2256 while (pReg->name) {
2257 uint32_t *pPossible;
2258
2259 /* calculate where this one go.. */
2260 /* it is "possibly" this register. */
2261
2262 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
2263
2264 /* well? Is it this register */
2265 if (pPossible == goes_here) {
2266 /* Jump for joy! */
2267 return pReg;
2268 }
2269
2270 /* next... */
2271 pReg++;
2272 }
2273 /* This is *TOTAL*PANIC* - we are totally screwed. */
2274 LOG_ERROR("INVALID SAM4 REGISTER");
2275 return NULL;
2276 }
2277
2278 static int sam4_ReadThisReg(struct sam4_chip *pChip, uint32_t *goes_here)
2279 {
2280 const struct sam4_reg_list *pReg;
2281 int r;
2282
2283 pReg = sam4_GetReg(pChip, goes_here);
2284 if (!pReg)
2285 return ERROR_FAIL;
2286
2287 r = target_read_u32(pChip->target, pReg->address, goes_here);
2288 if (r != ERROR_OK) {
2289 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
2290 pReg->name, (unsigned)(pReg->address), r);
2291 }
2292 return r;
2293 }
2294
2295 static int sam4_ReadAllRegs(struct sam4_chip *pChip)
2296 {
2297 int r;
2298 const struct sam4_reg_list *pReg;
2299
2300 pReg = &(sam4_all_regs[0]);
2301 while (pReg->name) {
2302 r = sam4_ReadThisReg(pChip,
2303 sam4_get_reg_ptr(&(pChip->cfg), pReg));
2304 if (r != ERROR_OK) {
2305 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
2306 pReg->name, ((unsigned)(pReg->address)), r);
2307 return r;
2308 }
2309 pReg++;
2310 }
2311
2312 return ERROR_OK;
2313 }
2314
2315 static int sam4_GetInfo(struct sam4_chip *pChip)
2316 {
2317 const struct sam4_reg_list *pReg;
2318 uint32_t regval;
2319
2320 pReg = &(sam4_all_regs[0]);
2321 while (pReg->name) {
2322 /* display all regs */
2323 LOG_DEBUG("Start: %s", pReg->name);
2324 regval = *sam4_get_reg_ptr(&(pChip->cfg), pReg);
2325 LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
2326 REG_NAME_WIDTH,
2327 pReg->name,
2328 pReg->address,
2329 regval);
2330 if (pReg->explain_func)
2331 (*(pReg->explain_func))(pChip);
2332 LOG_DEBUG("End: %s", pReg->name);
2333 pReg++;
2334 }
2335 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
2336 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
2337 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
2338 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
2339 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
2340
2341 LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32,
2342 pChip->cfg.unique_id[0],
2343 pChip->cfg.unique_id[1],
2344 pChip->cfg.unique_id[2],
2345 pChip->cfg.unique_id[3]);
2346
2347 return ERROR_OK;
2348 }
2349
2350 static int sam4_protect_check(struct flash_bank *bank)
2351 {
2352 int r;
2353 uint32_t v[4] = {0};
2354 unsigned x;
2355 struct sam4_bank_private *pPrivate;
2356
2357 LOG_DEBUG("Begin");
2358 if (bank->target->state != TARGET_HALTED) {
2359 LOG_ERROR("Target not halted");
2360 return ERROR_TARGET_NOT_HALTED;
2361 }
2362
2363 pPrivate = get_sam4_bank_private(bank);
2364 if (!pPrivate) {
2365 LOG_ERROR("no private for this bank?");
2366 return ERROR_FAIL;
2367 }
2368 if (!(pPrivate->probed))
2369 return ERROR_FLASH_BANK_NOT_PROBED;
2370
2371 r = FLASHD_GetLockBits(pPrivate, v);
2372 if (r != ERROR_OK) {
2373 LOG_DEBUG("Failed: %d", r);
2374 return r;
2375 }
2376
2377 for (x = 0; x < pPrivate->nsectors; x++)
2378 bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
2379 LOG_DEBUG("Done");
2380 return ERROR_OK;
2381 }
2382
2383 FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
2384 {
2385 struct sam4_chip *pChip;
2386
2387 pChip = all_sam4_chips;
2388
2389 /* is this an existing chip? */
2390 while (pChip) {
2391 if (pChip->target == bank->target)
2392 break;
2393 pChip = pChip->next;
2394 }
2395
2396 if (!pChip) {
2397 /* this is a *NEW* chip */
2398 pChip = calloc(1, sizeof(struct sam4_chip));
2399 if (!pChip) {
2400 LOG_ERROR("NO RAM!");
2401 return ERROR_FAIL;
2402 }
2403 pChip->target = bank->target;
2404 /* insert at head */
2405 pChip->next = all_sam4_chips;
2406 all_sam4_chips = pChip;
2407 pChip->target = bank->target;
2408 /* assumption is this runs at 32khz */
2409 pChip->cfg.slow_freq = 32768;
2410 pChip->probed = 0;
2411 }
2412
2413 switch (bank->base) {
2414 default:
2415 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
2416 "[at91sam4s series] )",
2417 ((unsigned int)(bank->base)),
2418 ((unsigned int)(FLASH_BANK_BASE_S)));
2419 return ERROR_FAIL;
2420 break;
2421
2422 /* at91sam4s series only has bank 0*/
2423 /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
2424 case FLASH_BANK_BASE_S:
2425 case FLASH_BANK_BASE_C:
2426 bank->driver_priv = &(pChip->details.bank[0]);
2427 bank->bank_number = 0;
2428 pChip->details.bank[0].pChip = pChip;
2429 pChip->details.bank[0].pBank = bank;
2430 break;
2431
2432 /* Bank 1 of at91sam4sd/at91sam4c32 series */
2433 case FLASH_BANK1_BASE_1024K_SD:
2434 case FLASH_BANK1_BASE_2048K_SD:
2435 case FLASH_BANK1_BASE_C32:
2436 bank->driver_priv = &(pChip->details.bank[1]);
2437 bank->bank_number = 1;
2438 pChip->details.bank[1].pChip = pChip;
2439 pChip->details.bank[1].pBank = bank;
2440 break;
2441 }
2442
2443 /* we initialize after probing. */
2444 return ERROR_OK;
2445 }
2446
2447 static int sam4_GetDetails(struct sam4_bank_private *pPrivate)
2448 {
2449 const struct sam4_chip_details *pDetails;
2450 struct sam4_chip *pChip;
2451 struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS];
2452 unsigned x;
2453
2454 LOG_DEBUG("Begin");
2455 pDetails = all_sam4_details;
2456 while (pDetails->name) {
2457 /* Compare cidr without version bits */
2458 if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2459 break;
2460 else
2461 pDetails++;
2462 }
2463 if (pDetails->name == NULL) {
2464 LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2465 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
2466 /* Help the victim, print details about the chip */
2467 LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
2468 pPrivate->pChip->cfg.CHIPID_CIDR);
2469 sam4_explain_chipid_cidr(pPrivate->pChip);
2470 return ERROR_FAIL;
2471 }
2472
2473 /* DANGER: THERE ARE DRAGONS HERE */
2474
2475 /* get our pChip - it is going */
2476 /* to be over-written shortly */
2477 pChip = pPrivate->pChip;
2478
2479 /* Note that, in reality: */
2480 /* */
2481 /* pPrivate = &(pChip->details.bank[0]) */
2482 /* or pPrivate = &(pChip->details.bank[1]) */
2483 /* */
2484
2485 /* save the "bank" pointers */
2486 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++)
2487 saved_banks[x] = pChip->details.bank[x].pBank;
2488
2489 /* Overwrite the "details" structure. */
2490 memcpy(&(pPrivate->pChip->details),
2491 pDetails,
2492 sizeof(pPrivate->pChip->details));
2493
2494 /* now fix the ghosted pointers */
2495 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2496 pChip->details.bank[x].pChip = pChip;
2497 pChip->details.bank[x].pBank = saved_banks[x];
2498 }
2499
2500 /* update the *BANK*SIZE* */
2501
2502 LOG_DEBUG("End");
2503 return ERROR_OK;
2504 }
2505
2506 static int _sam4_probe(struct flash_bank *bank, int noise)
2507 {
2508 unsigned x;
2509 int r;
2510 struct sam4_bank_private *pPrivate;
2511
2512
2513 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
2514 if (bank->target->state != TARGET_HALTED) {
2515 LOG_ERROR("Target not halted");
2516 return ERROR_TARGET_NOT_HALTED;
2517 }
2518
2519 pPrivate = get_sam4_bank_private(bank);
2520 if (!pPrivate) {
2521 LOG_ERROR("Invalid/unknown bank number");
2522 return ERROR_FAIL;
2523 }
2524
2525 r = sam4_ReadAllRegs(pPrivate->pChip);
2526 if (r != ERROR_OK)
2527 return r;
2528
2529 LOG_DEBUG("Here");
2530 if (pPrivate->pChip->probed)
2531 r = sam4_GetInfo(pPrivate->pChip);
2532 else
2533 r = sam4_GetDetails(pPrivate);
2534 if (r != ERROR_OK)
2535 return r;
2536
2537 /* update the flash bank size */
2538 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2539 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
2540 bank->size = pPrivate->pChip->details.bank[x].size_bytes;
2541 break;
2542 }
2543 }
2544
2545 if (bank->sectors == NULL) {
2546 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
2547 if (bank->sectors == NULL) {
2548 LOG_ERROR("No memory!");
2549 return ERROR_FAIL;
2550 }
2551 bank->num_sectors = pPrivate->nsectors;
2552
2553 for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
2554 bank->sectors[x].size = pPrivate->sector_size;
2555 bank->sectors[x].offset = x * (pPrivate->sector_size);
2556 /* mark as unknown */
2557 bank->sectors[x].is_erased = -1;
2558 bank->sectors[x].is_protected = -1;
2559 }
2560 }
2561
2562 pPrivate->probed = 1;
2563
2564 r = sam4_protect_check(bank);
2565 if (r != ERROR_OK)
2566 return r;
2567
2568 LOG_DEBUG("Bank = %d, nbanks = %d",
2569 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
2570 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
2571 /* read unique id, */
2572 /* it appears to be associated with the *last* flash bank. */
2573 FLASHD_ReadUniqueID(pPrivate);
2574 }
2575
2576 return r;
2577 }
2578
2579 static int sam4_probe(struct flash_bank *bank)
2580 {
2581 return _sam4_probe(bank, 1);
2582 }
2583
2584 static int sam4_auto_probe(struct flash_bank *bank)
2585 {
2586 return _sam4_probe(bank, 0);
2587 }
2588
2589 static int sam4_erase(struct flash_bank *bank, int first, int last)
2590 {
2591 struct sam4_bank_private *pPrivate;
2592 int r;
2593 int i;
2594 int pageCount;
2595 /*16 pages equals 8KB - Same size as a lock region*/
2596 pageCount = 16;
2597 uint32_t status;
2598
2599 LOG_DEBUG("Here");
2600 if (bank->target->state != TARGET_HALTED) {
2601 LOG_ERROR("Target not halted");
2602 return ERROR_TARGET_NOT_HALTED;
2603 }
2604
2605 r = sam4_auto_probe(bank);
2606 if (r != ERROR_OK) {
2607 LOG_DEBUG("Here,r=%d", r);
2608 return r;
2609 }
2610
2611 pPrivate = get_sam4_bank_private(bank);
2612 if (!(pPrivate->probed))
2613 return ERROR_FLASH_BANK_NOT_PROBED;
2614
2615 if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
2616 /* whole chip */
2617 LOG_DEBUG("Here");
2618 return FLASHD_EraseEntireBank(pPrivate);
2619 }
2620 LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
2621 LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", (unsigned int)(first), (unsigned int)(last));
2622 for (i = first; i <= last; i++) {
2623 /*16 pages equals 8KB - Same size as a lock region*/
2624 r = FLASHD_ErasePages(pPrivate, (i * pageCount), pageCount, &status);
2625 LOG_INFO("Erasing sector: 0x%08x", (unsigned int)(i));
2626 if (r != ERROR_OK)
2627 LOG_ERROR("SAM4: Error performing Erase page @ lock region number %d",
2628 (unsigned int)(i));
2629 if (status & (1 << 2)) {
2630 LOG_ERROR("SAM4: Lock Region %d is locked", (unsigned int)(i));
2631 return ERROR_FAIL;
2632 }
2633 if (status & (1 << 1)) {
2634 LOG_ERROR("SAM4: Flash Command error @lock region %d", (unsigned int)(i));
2635 return ERROR_FAIL;
2636 }
2637 }
2638
2639 return ERROR_OK;
2640 }
2641
2642 static int sam4_protect(struct flash_bank *bank, int set, int first, int last)
2643 {
2644 struct sam4_bank_private *pPrivate;
2645 int r;
2646
2647 LOG_DEBUG("Here");
2648 if (bank->target->state != TARGET_HALTED) {
2649 LOG_ERROR("Target not halted");
2650 return ERROR_TARGET_NOT_HALTED;
2651 }
2652
2653 pPrivate = get_sam4_bank_private(bank);
2654 if (!(pPrivate->probed))
2655 return ERROR_FLASH_BANK_NOT_PROBED;
2656
2657 if (set)
2658 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
2659 else
2660 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
2661 LOG_DEBUG("End: r=%d", r);
2662
2663 return r;
2664
2665 }
2666
2667 static int sam4_page_read(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2668 {
2669 uint32_t adr;
2670 int r;
2671
2672 adr = pagenum * pPrivate->page_size;
2673 adr = adr + pPrivate->base_address;
2674
2675 r = target_read_memory(pPrivate->pChip->target,
2676 adr,
2677 4, /* THIS*MUST*BE* in 32bit values */
2678 pPrivate->page_size / 4,
2679 buf);
2680 if (r != ERROR_OK)
2681 LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
2682 (unsigned int)(adr));
2683 return r;
2684 }
2685
2686 static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
2687 {
2688 uint32_t adr;
2689 uint32_t status;
2690 uint32_t fmr; /* EEFC Flash Mode Register */
2691 int r;
2692
2693 adr = pagenum * pPrivate->page_size;
2694 adr = (adr + pPrivate->base_address);
2695
2696 /* Get flash mode register value */
2697 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
2698 if (r != ERROR_OK)
2699 LOG_DEBUG("Error Read failed: read flash mode register");
2700
2701 /* Clear flash wait state field */
2702 fmr &= 0xfffff0ff;
2703
2704 /* set FWS (flash wait states) field in the FMR (flash mode register) */
2705 fmr |= (pPrivate->flash_wait_states << 8);
2706
2707 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
2708 r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
2709 if (r != ERROR_OK)
2710 LOG_DEBUG("Error Write failed: set flash mode register");
2711
2712 /* 1st sector 8kBytes - page 0 - 15*/
2713 /* 2nd sector 8kBytes - page 16 - 30*/
2714 /* 3rd sector 48kBytes - page 31 - 127*/
2715 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2716 r = target_write_memory(pPrivate->pChip->target,
2717 adr,
2718 4, /* THIS*MUST*BE* in 32bit values */
2719 pPrivate->page_size / 4,
2720 buf);
2721 if (r != ERROR_OK) {
2722 LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
2723 (unsigned int)(adr));
2724 return r;
2725 }
2726
2727 r = EFC_PerformCommand(pPrivate,
2728 /* send Erase & Write Page */
2729 AT91C_EFC_FCMD_WP, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
2730 pagenum,
2731 &status);
2732
2733 if (r != ERROR_OK)
2734 LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
2735 (unsigned int)(adr));
2736 if (status & (1 << 2)) {
2737 LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2738 return ERROR_FAIL;
2739 }
2740 if (status & (1 << 1)) {
2741 LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2742 return ERROR_FAIL;
2743 }
2744 return ERROR_OK;
2745 }
2746
2747 static int sam4_write(struct flash_bank *bank,
2748 const uint8_t *buffer,
2749 uint32_t offset,
2750 uint32_t count)
2751 {
2752 int n;
2753 unsigned page_cur;
2754 unsigned page_end;
2755 int r;
2756 unsigned page_offset;
2757 struct sam4_bank_private *pPrivate;
2758 uint8_t *pagebuffer;
2759
2760 /* incase we bail further below, set this to null */
2761 pagebuffer = NULL;
2762
2763 /* ignore dumb requests */
2764 if (count == 0) {
2765 r = ERROR_OK;
2766 goto done;
2767 }
2768
2769 if (bank->target->state != TARGET_HALTED) {
2770 LOG_ERROR("Target not halted");
2771 r = ERROR_TARGET_NOT_HALTED;
2772 goto done;
2773 }
2774
2775 pPrivate = get_sam4_bank_private(bank);
2776 if (!(pPrivate->probed)) {
2777 r = ERROR_FLASH_BANK_NOT_PROBED;
2778 goto done;
2779 }
2780
2781 if ((offset + count) > pPrivate->size_bytes) {
2782 LOG_ERROR("Flash write error - past end of bank");
2783 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2784 (unsigned int)(offset),
2785 (unsigned int)(count),
2786 (unsigned int)(pPrivate->size_bytes));
2787 r = ERROR_FAIL;
2788 goto done;
2789 }
2790
2791 pagebuffer = malloc(pPrivate->page_size);
2792 if (!pagebuffer) {
2793 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
2794 r = ERROR_FAIL;
2795 goto done;
2796 }
2797
2798 /* what page do we start & end in? */
2799 page_cur = offset / pPrivate->page_size;
2800 page_end = (offset + count - 1) / pPrivate->page_size;
2801
2802 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2803 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2804
2805 /* Special case: all one page */
2806 /* */
2807 /* Otherwise: */
2808 /* (1) non-aligned start */
2809 /* (2) body pages */
2810 /* (3) non-aligned end. */
2811
2812 /* Handle special case - all one page. */
2813 if (page_cur == page_end) {
2814 LOG_DEBUG("Special case, all in one page");
2815 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2816 if (r != ERROR_OK)
2817 goto done;
2818
2819 page_offset = (offset & (pPrivate->page_size-1));
2820 memcpy(pagebuffer + page_offset,
2821 buffer,
2822 count);
2823
2824 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2825 if (r != ERROR_OK)
2826 goto done;
2827 r = ERROR_OK;
2828 goto done;
2829 }
2830
2831 /* non-aligned start */
2832 page_offset = offset & (pPrivate->page_size - 1);
2833 if (page_offset) {
2834 LOG_DEBUG("Not-Aligned start");
2835 /* read the partial */
2836 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2837 if (r != ERROR_OK)
2838 goto done;
2839
2840 /* over-write with new data */
2841 n = (pPrivate->page_size - page_offset);
2842 memcpy(pagebuffer + page_offset,
2843 buffer,
2844 n);
2845
2846 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2847 if (r != ERROR_OK)
2848 goto done;
2849
2850 count -= n;
2851 offset += n;
2852 buffer += n;
2853 page_cur++;
2854 }
2855
2856 /* By checking that offset is correct here, we also
2857 fix a clang warning */
2858 assert(offset % pPrivate->page_size == 0);
2859
2860 /* intermediate large pages */
2861 /* also - the final *terminal* */
2862 /* if that terminal page is a full page */
2863 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2864 (int)page_cur, (int)page_end, (unsigned int)(count));
2865
2866 while ((page_cur < page_end) &&
2867 (count >= pPrivate->page_size)) {
2868 r = sam4_page_write(pPrivate, page_cur, buffer);
2869 if (r != ERROR_OK)
2870 goto done;
2871 count -= pPrivate->page_size;
2872 buffer += pPrivate->page_size;
2873 page_cur += 1;
2874 }
2875
2876 /* terminal partial page? */
2877 if (count) {
2878 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
2879 /* we have a partial page */
2880 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2881 if (r != ERROR_OK)
2882 goto done;
2883 /* data goes at start */
2884 memcpy(pagebuffer, buffer, count);
2885 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2886 if (r != ERROR_OK)
2887 goto done;
2888 }
2889 LOG_DEBUG("Done!");
2890 r = ERROR_OK;
2891 done:
2892 if (pagebuffer)
2893 free(pagebuffer);
2894 return r;
2895 }
2896
2897 COMMAND_HANDLER(sam4_handle_info_command)
2898 {
2899 struct sam4_chip *pChip;
2900 pChip = get_current_sam4(CMD_CTX);
2901 if (!pChip)
2902 return ERROR_OK;
2903
2904 unsigned x;
2905 int r;
2906
2907 /* bank0 must exist before we can do anything */
2908 if (pChip->details.bank[0].pBank == NULL) {
2909 x = 0;
2910 need_define:
2911 command_print(CMD_CTX,
2912 "Please define bank %d via command: flash bank %s ... ",
2913 x,
2914 at91sam4_flash.name);
2915 return ERROR_FAIL;
2916 }
2917
2918 /* if bank 0 is not probed, then probe it */
2919 if (!(pChip->details.bank[0].probed)) {
2920 r = sam4_auto_probe(pChip->details.bank[0].pBank);
2921 if (r != ERROR_OK)
2922 return ERROR_FAIL;
2923 }
2924 /* above guarantees the "chip details" structure is valid */
2925 /* and thus, bank private areas are valid */
2926 /* and we have a SAM4 chip, what a concept! */
2927
2928 /* auto-probe other banks, 0 done above */
2929 for (x = 1; x < SAM4_MAX_FLASH_BANKS; x++) {
2930 /* skip banks not present */
2931 if (!(pChip->details.bank[x].present))
2932 continue;
2933
2934 if (pChip->details.bank[x].pBank == NULL)
2935 goto need_define;
2936
2937 if (pChip->details.bank[x].probed)
2938 continue;
2939
2940 r = sam4_auto_probe(pChip->details.bank[x].pBank);
2941 if (r != ERROR_OK)
2942 return r;
2943 }
2944
2945 r = sam4_GetInfo(pChip);
2946 if (r != ERROR_OK) {
2947 LOG_DEBUG("Sam4Info, Failed %d", r);
2948 return r;
2949 }
2950
2951 return ERROR_OK;
2952 }
2953
2954 COMMAND_HANDLER(sam4_handle_gpnvm_command)
2955 {
2956 unsigned x, v;
2957 int r, who;
2958 struct sam4_chip *pChip;
2959
2960 pChip = get_current_sam4(CMD_CTX);
2961 if (!pChip)
2962 return ERROR_OK;
2963
2964 if (pChip->target->state != TARGET_HALTED) {
2965 LOG_ERROR("sam4 - target not halted");
2966 return ERROR_TARGET_NOT_HALTED;
2967 }
2968
2969 if (pChip->details.bank[0].pBank == NULL) {
2970 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
2971 at91sam4_flash.name);
2972 return ERROR_FAIL;
2973 }
2974 if (!pChip->details.bank[0].probed) {
2975 r = sam4_auto_probe(pChip->details.bank[0].pBank);
2976 if (r != ERROR_OK)
2977 return r;
2978 }
2979
2980 switch (CMD_ARGC) {
2981 default:
2982 return ERROR_COMMAND_SYNTAX_ERROR;
2983 break;
2984 case 0:
2985 goto showall;
2986 break;
2987 case 1:
2988 who = -1;
2989 break;
2990 case 2:
2991 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
2992 who = -1;
2993 else {
2994 uint32_t v32;
2995 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
2996 who = v32;
2997 }
2998 break;
2999 }
3000
3001 if (0 == strcmp("show", CMD_ARGV[0])) {
3002 if (who == -1) {
3003 showall:
3004 r = ERROR_OK;
3005 for (x = 0; x < pChip->details.n_gpnvms; x++) {
3006 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
3007 if (r != ERROR_OK)
3008 break;
3009 command_print(CMD_CTX, "sam4-gpnvm%u: %u", x, v);
3010 }
3011 return r;
3012 }
3013 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
3014 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
3015 command_print(CMD_CTX, "sam4-gpnvm%u: %u", who, v);
3016 return r;
3017 } else {
3018 command_print(CMD_CTX, "sam4-gpnvm invalid GPNVM: %u", who);
3019 return ERROR_COMMAND_SYNTAX_ERROR;
3020 }
3021 }
3022
3023 if (who == -1) {
3024 command_print(CMD_CTX, "Missing GPNVM number");
3025 return ERROR_COMMAND_SYNTAX_ERROR;
3026 }
3027
3028 if (0 == strcmp("set", CMD_ARGV[0]))
3029 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
3030 else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
3031 (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
3032 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
3033 else {
3034 command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
3035 r = ERROR_COMMAND_SYNTAX_ERROR;
3036 }
3037 return r;
3038 }
3039
3040 COMMAND_HANDLER(sam4_handle_slowclk_command)
3041 {
3042 struct sam4_chip *pChip;
3043
3044 pChip = get_current_sam4(CMD_CTX);
3045 if (!pChip)
3046 return ERROR_OK;
3047
3048 switch (CMD_ARGC) {
3049 case 0:
3050 /* show */
3051 break;
3052 case 1:
3053 {
3054 /* set */
3055 uint32_t v;
3056 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3057 if (v > 200000) {
3058 /* absurd slow clock of 200Khz? */
3059 command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3060 return ERROR_COMMAND_SYNTAX_ERROR;
3061 }
3062 pChip->cfg.slow_freq = v;
3063 break;
3064 }
3065 default:
3066 /* error */
3067 command_print(CMD_CTX, "Too many parameters");
3068 return ERROR_COMMAND_SYNTAX_ERROR;
3069 break;
3070 }
3071 command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
3072 (int)(pChip->cfg.slow_freq / 1000),
3073 (int)(pChip->cfg.slow_freq % 1000));
3074 return ERROR_OK;
3075 }
3076
3077 static const struct command_registration at91sam4_exec_command_handlers[] = {
3078 {
3079 .name = "gpnvm",
3080 .handler = sam4_handle_gpnvm_command,
3081 .mode = COMMAND_EXEC,
3082 .usage = "[('clr'|'set'|'show') bitnum]",
3083 .help = "Without arguments, shows all bits in the gpnvm "
3084 "register. Otherwise, clears, sets, or shows one "
3085 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3086 },
3087 {
3088 .name = "info",
3089 .handler = sam4_handle_info_command,
3090 .mode = COMMAND_EXEC,
3091 .help = "Print information about the current at91sam4 chip"
3092 "and its flash configuration.",
3093 },
3094 {
3095 .name = "slowclk",
3096 .handler = sam4_handle_slowclk_command,
3097 .mode = COMMAND_EXEC,
3098 .usage = "[clock_hz]",
3099 .help = "Display or set the slowclock frequency "
3100 "(default 32768 Hz).",
3101 },
3102 COMMAND_REGISTRATION_DONE
3103 };
3104 static const struct command_registration at91sam4_command_handlers[] = {
3105 {
3106 .name = "at91sam4",
3107 .mode = COMMAND_ANY,
3108 .help = "at91sam4 flash command group",
3109 .usage = "",
3110 .chain = at91sam4_exec_command_handlers,
3111 },
3112 COMMAND_REGISTRATION_DONE
3113 };
3114
3115 struct flash_driver at91sam4_flash = {
3116 .name = "at91sam4",
3117 .commands = at91sam4_command_handlers,
3118 .flash_bank_command = sam4_flash_bank_command,
3119 .erase = sam4_erase,
3120 .protect = sam4_protect,
3121 .write = sam4_write,
3122 .read = default_flash_read,
3123 .probe = sam4_probe,
3124 .auto_probe = sam4_auto_probe,
3125 .erase_check = default_flash_blank_check,
3126 .protect_check = sam4_protect_check,
3127 };
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