1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
17 * GNU General public License for more details. *
19 * You should have received a copy of the GNU General public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ****************************************************************************/
25 /* Some of the the lower level code was based on code supplied by
26 * ATMEL under this copyright. */
28 /* BEGIN ATMEL COPYRIGHT */
29 /* ----------------------------------------------------------------------------
30 * ATMEL Microcontroller Software Support
31 * ----------------------------------------------------------------------------
32 * Copyright (c) 2009, Atmel Corporation
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions are met:
39 * - Redistributions of source code must retain the above copyright notice,
40 * this list of conditions and the disclaimer below.
42 * Atmel's name may not be used to endorse or promote products derived from
43 * this software without specific prior written permission.
45 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
48 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
51 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
52 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
53 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
54 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 * ----------------------------------------------------------------------------
57 /* END ATMEL COPYRIGHT */
65 #include <helper/time_support.h>
67 #define REG_NAME_WIDTH (12)
69 // at91sam3u series (has one or two flash banks)
70 #define FLASH_BANK0_BASE_U 0x00080000
71 #define FLASH_BANK1_BASE_U 0x00100000
73 // at91sam3s series (has always one flash bank)
74 #define FLASH_BANK_BASE_S 0x00400000
76 #define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor
77 #define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
78 #define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock
79 #define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page
80 #define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock
81 #define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All
82 // cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2
83 // #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane?
84 // cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2
85 // #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages?
86 #define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit
87 #define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit
88 #define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit
89 #define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit
90 #define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit
91 #define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit
92 #define AT91C_EFC_FCMD_STUI (0xE) // (EFC) Start Read Unique ID
93 #define AT91C_EFC_FCMD_SPUI (0xF) // (EFC) Stop Read Unique ID
95 #define offset_EFC_FMR 0
96 #define offset_EFC_FCR 4
97 #define offset_EFC_FSR 8
98 #define offset_EFC_FRR 12
101 extern struct flash_driver at91sam3_flash
;
104 _tomhz(uint32_t freq_hz
)
108 f
= ((float)(freq_hz
)) / 1000000.0;
112 // How the chip is configured.
114 uint32_t unique_id
[4];
118 uint32_t mainosc_freq
;
128 #define SAM3_CHIPID_CIDR (0x400E0740)
129 uint32_t CHIPID_CIDR
;
130 #define SAM3_CHIPID_EXID (0x400E0744)
131 uint32_t CHIPID_EXID
;
133 #define SAM3_SUPC_CR (0x400E1210)
136 #define SAM3_PMC_BASE (0x400E0400)
137 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
139 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
141 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
143 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
145 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
147 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
149 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
151 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
153 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
155 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
157 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
159 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
161 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
163 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
168 struct sam3_bank_private
{
170 // DANGER: THERE ARE DRAGONS HERE..
171 // NOTE: If you add more 'ghost' pointers
172 // be aware that you must *manually* update
173 // these pointers in the function sam3_GetDetails()
174 // See the comment "Here there be dragons"
176 // so we can find the chip we belong to
177 struct sam3_chip
*pChip
;
178 // so we can find the orginal bank pointer
179 struct flash_bank
*pBank
;
180 unsigned bank_number
;
181 uint32_t controller_address
;
182 uint32_t base_address
;
186 unsigned sector_size
;
190 struct sam3_chip_details
{
191 // THERE ARE DRAGONS HERE..
192 // note: If you add pointers here
193 // becareful about them as they
194 // may need to be updated inside
195 // the function: "sam3_GetDetails()
196 // which copy/overwrites the
197 // 'runtime' copy of this structure
198 uint32_t chipid_cidr
;
202 #define SAM3_N_NVM_BITS 3
203 unsigned gpnvm
[SAM3_N_NVM_BITS
];
204 unsigned total_flash_size
;
205 unsigned total_sram_size
;
207 #define SAM3_MAX_FLASH_BANKS 2
208 // these are "initialized" from the global const data
209 struct sam3_bank_private bank
[SAM3_MAX_FLASH_BANKS
];
214 struct sam3_chip
*next
;
217 // this is "initialized" from the global const structure
218 struct sam3_chip_details details
;
219 struct target
*target
;
224 struct sam3_reg_list
{
225 uint32_t address
; size_t struct_offset
; const char *name
;
226 void (*explain_func
)(struct sam3_chip
*pInfo
);
230 static struct sam3_chip
*all_sam3_chips
;
232 static struct sam3_chip
*
233 get_current_sam3(struct command_context
*cmd_ctx
)
236 static struct sam3_chip
*p
;
238 t
= get_current_target(cmd_ctx
);
240 command_print(cmd_ctx
, "No current target?");
246 // this should not happen
247 // the command is not registered until the chip is created?
248 command_print(cmd_ctx
, "No SAM3 chips exist?");
253 if (p
->target
== t
) {
258 command_print(cmd_ctx
, "Cannot find SAM3 chip?");
263 // these are used to *initialize* the "pChip->details" structure.
264 static const struct sam3_chip_details all_sam3_details
[] = {
265 // Start at91sam3u* series
267 .chipid_cidr
= 0x28100960,
268 .name
= "at91sam3u4e",
269 .total_flash_size
= 256 * 1024,
270 .total_sram_size
= 52 * 1024,
274 // System boots at address 0x0
275 // gpnvm[1] = selects boot code
277 // boot is via "SAMBA" (rom)
280 // Selection is via gpnvm[2]
283 // NOTE: banks 0 & 1 switch places
285 // Bank0 is the boot rom
287 // Bank1 is the boot rom
296 .base_address
= FLASH_BANK0_BASE_U
,
297 .controller_address
= 0x400e0800,
299 .size_bytes
= 128 * 1024,
311 .base_address
= FLASH_BANK1_BASE_U
,
312 .controller_address
= 0x400e0a00,
314 .size_bytes
= 128 * 1024,
323 .chipid_cidr
= 0x281a0760,
324 .name
= "at91sam3u2e",
325 .total_flash_size
= 128 * 1024,
326 .total_sram_size
= 36 * 1024,
330 // System boots at address 0x0
331 // gpnvm[1] = selects boot code
333 // boot is via "SAMBA" (rom)
336 // Selection is via gpnvm[2]
345 .base_address
= FLASH_BANK0_BASE_U
,
346 .controller_address
= 0x400e0800,
348 .size_bytes
= 128 * 1024,
362 .chipid_cidr
= 0x28190560,
363 .name
= "at91sam3u1e",
364 .total_flash_size
= 64 * 1024,
365 .total_sram_size
= 20 * 1024,
369 // System boots at address 0x0
370 // gpnvm[1] = selects boot code
372 // boot is via "SAMBA" (rom)
375 // Selection is via gpnvm[2]
386 .base_address
= FLASH_BANK0_BASE_U
,
387 .controller_address
= 0x400e0800,
389 .size_bytes
= 64 * 1024,
405 .chipid_cidr
= 0x28000960,
406 .name
= "at91sam3u4c",
407 .total_flash_size
= 256 * 1024,
408 .total_sram_size
= 52 * 1024,
412 // System boots at address 0x0
413 // gpnvm[1] = selects boot code
415 // boot is via "SAMBA" (rom)
418 // Selection is via gpnvm[2]
421 // NOTE: banks 0 & 1 switch places
423 // Bank0 is the boot rom
425 // Bank1 is the boot rom
434 .base_address
= FLASH_BANK0_BASE_U
,
435 .controller_address
= 0x400e0800,
437 .size_bytes
= 128 * 1024,
448 .base_address
= FLASH_BANK1_BASE_U
,
449 .controller_address
= 0x400e0a00,
451 .size_bytes
= 128 * 1024,
460 .chipid_cidr
= 0x280a0760,
461 .name
= "at91sam3u2c",
462 .total_flash_size
= 128 * 1024,
463 .total_sram_size
= 36 * 1024,
467 // System boots at address 0x0
468 // gpnvm[1] = selects boot code
470 // boot is via "SAMBA" (rom)
473 // Selection is via gpnvm[2]
482 .base_address
= FLASH_BANK0_BASE_U
,
483 .controller_address
= 0x400e0800,
485 .size_bytes
= 128 * 1024,
499 .chipid_cidr
= 0x28090560,
500 .name
= "at91sam3u1c",
501 .total_flash_size
= 64 * 1024,
502 .total_sram_size
= 20 * 1024,
506 // System boots at address 0x0
507 // gpnvm[1] = selects boot code
509 // boot is via "SAMBA" (rom)
512 // Selection is via gpnvm[2]
523 .base_address
= FLASH_BANK0_BASE_U
,
524 .controller_address
= 0x400e0800,
526 .size_bytes
= 64 * 1024,
541 // Start at91sam3s* series
543 // Note: The preliminary at91sam3s datasheet says on page 302
544 // that the flash controller is at address 0x400E0800.
545 // This is _not_ the case, the controller resides at address 0x400e0a0.
547 .chipid_cidr
= 0x28A00960,
548 .name
= "at91sam3s4c",
549 .total_flash_size
= 256 * 1024,
550 .total_sram_size
= 48 * 1024,
560 .base_address
= FLASH_BANK_BASE_S
,
562 .controller_address
= 0x400e0a00,
564 .size_bytes
= 256 * 1024,
580 .chipid_cidr
= 0x28900960,
581 .name
= "at91sam3s4b",
582 .total_flash_size
= 256 * 1024,
583 .total_sram_size
= 48 * 1024,
593 .base_address
= FLASH_BANK_BASE_S
,
595 .controller_address
= 0x400e0a00,
597 .size_bytes
= 256 * 1024,
612 .chipid_cidr
= 0x28800960,
613 .name
= "at91sam3s4a",
614 .total_flash_size
= 256 * 1024,
615 .total_sram_size
= 48 * 1024,
625 .base_address
= FLASH_BANK_BASE_S
,
627 .controller_address
= 0x400e0a00,
629 .size_bytes
= 256 * 1024,
644 .chipid_cidr
= 0x28AA0760,
645 .name
= "at91sam3s2c",
646 .total_flash_size
= 128 * 1024,
647 .total_sram_size
= 32 * 1024,
657 .base_address
= FLASH_BANK_BASE_S
,
659 .controller_address
= 0x400e0a00,
661 .size_bytes
= 128 * 1024,
676 .chipid_cidr
= 0x289A0760,
677 .name
= "at91sam3s2b",
678 .total_flash_size
= 128 * 1024,
679 .total_sram_size
= 32 * 1024,
689 .base_address
= FLASH_BANK_BASE_S
,
691 .controller_address
= 0x400e0a00,
693 .size_bytes
= 128 * 1024,
708 .chipid_cidr
= 0x288A0760,
709 .name
= "at91sam3s2a",
710 .total_flash_size
= 128 * 1024,
711 .total_sram_size
= 32 * 1024,
721 .base_address
= FLASH_BANK_BASE_S
,
723 .controller_address
= 0x400e0a00,
725 .size_bytes
= 128 * 1024,
740 .chipid_cidr
= 0x28A90560,
741 .name
= "at91sam3s1c",
742 .total_flash_size
= 64 * 1024,
743 .total_sram_size
= 16 * 1024,
753 .base_address
= FLASH_BANK_BASE_S
,
755 .controller_address
= 0x400e0a00,
757 .size_bytes
= 64 * 1024,
772 .chipid_cidr
= 0x28990560,
773 .name
= "at91sam3s1b",
774 .total_flash_size
= 64 * 1024,
775 .total_sram_size
= 16 * 1024,
785 .base_address
= FLASH_BANK_BASE_S
,
787 .controller_address
= 0x400e0a00,
789 .size_bytes
= 64 * 1024,
804 .chipid_cidr
= 0x28890560,
805 .name
= "at91sam3s1a",
806 .total_flash_size
= 64 * 1024,
807 .total_sram_size
= 16 * 1024,
817 .base_address
= FLASH_BANK_BASE_S
,
819 .controller_address
= 0x400e0a00,
821 .size_bytes
= 64 * 1024,
843 /***********************************************************************
844 **********************************************************************
845 **********************************************************************
846 **********************************************************************
847 **********************************************************************
848 **********************************************************************/
849 /* *ATMEL* style code - from the SAM3 driver code */
852 * Get the current status of the EEFC and
853 * the value of some status bits (LOCKE, PROGE).
854 * @param pPrivate - info about the bank
855 * @param v - result goes here
858 EFC_GetStatus(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
861 r
= target_read_u32(pPrivate
->pChip
->target
, pPrivate
->controller_address
+ offset_EFC_FSR
, v
);
862 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
864 ((unsigned int)((*v
>> 2) & 1)),
865 ((unsigned int)((*v
>> 1) & 1)),
866 ((unsigned int)((*v
>> 0) & 1)));
872 * Get the result of the last executed command.
873 * @param pPrivate - info about the bank
874 * @param v - result goes here
877 EFC_GetResult(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
881 r
= target_read_u32(pPrivate
->pChip
->target
, pPrivate
->controller_address
+ offset_EFC_FRR
, &rv
);
885 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv
)));
890 EFC_StartCommand(struct sam3_bank_private
*pPrivate
,
891 unsigned command
, unsigned argument
)
900 // Check command & argument
903 case AT91C_EFC_FCMD_WP
:
904 case AT91C_EFC_FCMD_WPL
:
905 case AT91C_EFC_FCMD_EWP
:
906 case AT91C_EFC_FCMD_EWPL
:
907 // case AT91C_EFC_FCMD_EPL:
908 // case AT91C_EFC_FCMD_EPA:
909 case AT91C_EFC_FCMD_SLB
:
910 case AT91C_EFC_FCMD_CLB
:
911 n
= (pPrivate
->size_bytes
/ pPrivate
->page_size
);
913 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n
));
917 case AT91C_EFC_FCMD_SFB
:
918 case AT91C_EFC_FCMD_CFB
:
919 if (argument
>= pPrivate
->pChip
->details
.n_gpnvms
) {
920 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
921 pPrivate
->pChip
->details
.n_gpnvms
);
925 case AT91C_EFC_FCMD_GETD
:
926 case AT91C_EFC_FCMD_EA
:
927 case AT91C_EFC_FCMD_GLB
:
928 case AT91C_EFC_FCMD_GFB
:
929 case AT91C_EFC_FCMD_STUI
:
930 case AT91C_EFC_FCMD_SPUI
:
932 LOG_ERROR("Argument is meaningless for cmd: %d", command
);
936 LOG_ERROR("Unknown command %d", command
);
940 if (command
== AT91C_EFC_FCMD_SPUI
) {
941 // this is a very special situation.
942 // Situation (1) - error/retry - see below
943 // And we are being called recursively
944 // Situation (2) - normal, finished reading unique id
946 // it should be "ready"
947 EFC_GetStatus(pPrivate
, &v
);
953 // we have done this before
954 // the controller is not responding.
955 LOG_ERROR("flash controller(%d) is not ready! Error", pPrivate
->bank_number
);
959 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
960 pPrivate
->bank_number
);
961 // we do that by issuing the *STOP* command
962 EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0);
963 // above is recursive, and further recursion is blocked by
964 // if (command == AT91C_EFC_FCMD_SPUI) above
970 v
= (0x5A << 24) | (argument
<< 8) | command
;
971 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v
)));
972 r
= target_write_u32(pPrivate
->pBank
->target
,
973 pPrivate
->controller_address
+ offset_EFC_FCR
,
976 LOG_DEBUG("Error Write failed");
982 * Performs the given command and wait until its completion (or an error).
983 * @param pPrivate - info about the bank
984 * @param command - Command to perform.
985 * @param argument - Optional command argument.
986 * @param status - put command status bits here
989 EFC_PerformCommand(struct sam3_bank_private
*pPrivate
,
997 long long ms_now
, ms_end
;
1004 r
= EFC_StartCommand(pPrivate
, command
, argument
);
1005 if (r
!= ERROR_OK
) {
1009 ms_end
= 500 + timeval_ms();
1013 r
= EFC_GetStatus(pPrivate
, &v
);
1014 if (r
!= ERROR_OK
) {
1017 ms_now
= timeval_ms();
1018 if (ms_now
> ms_end
) {
1020 LOG_ERROR("Command timeout");
1024 while ((v
& 1) == 0)
1029 *status
= (v
& 0x6);
1040 * Read the unique ID.
1041 * @param pPrivate - info about the bank
1042 * The unique ID is stored in the 'pPrivate' structure.
1045 FLASHD_ReadUniqueID (struct sam3_bank_private
*pPrivate
)
1051 pPrivate
->pChip
->cfg
.unique_id
[0] = 0;
1052 pPrivate
->pChip
->cfg
.unique_id
[1] = 0;
1053 pPrivate
->pChip
->cfg
.unique_id
[2] = 0;
1054 pPrivate
->pChip
->cfg
.unique_id
[3] = 0;
1057 r
= EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_STUI
, 0);
1062 for (x
= 0 ; x
< 4 ; x
++) {
1063 r
= target_read_u32(pPrivate
->pChip
->target
,
1064 pPrivate
->pBank
->base
+ (x
* 4),
1069 pPrivate
->pChip
->cfg
.unique_id
[x
] = v
;
1072 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0, NULL
);
1073 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1075 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[0]),
1076 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[1]),
1077 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[2]),
1078 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[3]));
1084 * Erases the entire flash.
1085 * @param pPrivate - the info about the bank.
1088 FLASHD_EraseEntireBank(struct sam3_bank_private
*pPrivate
)
1091 return EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_EA
, 0, NULL
);
1097 * Gets current GPNVM state.
1098 * @param pPrivate - info about the bank.
1099 * @param gpnvm - GPNVM bit index.
1100 * @param puthere - result stored here.
1102 //------------------------------------------------------------------------------
1104 FLASHD_GetGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
, unsigned *puthere
)
1110 if (pPrivate
->bank_number
!= 0) {
1111 LOG_ERROR("GPNVM only works with Bank0");
1115 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1116 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1117 gpnvm
,pPrivate
->pChip
->details
.n_gpnvms
);
1121 // Get GPNVMs status
1122 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GFB
, 0, NULL
);
1123 if (r
!= ERROR_OK
) {
1124 LOG_ERROR("Failed");
1128 r
= EFC_GetResult(pPrivate
, &v
);
1131 // Check if GPNVM is set
1132 // get the bit and make it a 0/1
1133 *puthere
= (v
>> gpnvm
) & 1;
1143 * Clears the selected GPNVM bit.
1144 * @param pPrivate info about the bank
1145 * @param gpnvm GPNVM index.
1146 * @returns 0 if successful; otherwise returns an error code.
1149 FLASHD_ClrGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
1155 if (pPrivate
->bank_number
!= 0) {
1156 LOG_ERROR("GPNVM only works with Bank0");
1160 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1161 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1162 gpnvm
,pPrivate
->pChip
->details
.n_gpnvms
);
1166 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
1167 if (r
!= ERROR_OK
) {
1168 LOG_DEBUG("Failed: %d",r
);
1171 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CFB
, gpnvm
, NULL
);
1172 LOG_DEBUG("End: %d",r
);
1179 * Sets the selected GPNVM bit.
1180 * @param pPrivate info about the bank
1181 * @param gpnvm GPNVM index.
1184 FLASHD_SetGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
1189 if (pPrivate
->bank_number
!= 0) {
1190 LOG_ERROR("GPNVM only works with Bank0");
1194 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1195 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1196 gpnvm
,pPrivate
->pChip
->details
.n_gpnvms
);
1200 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
1201 if (r
!= ERROR_OK
) {
1209 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SFB
, gpnvm
, NULL
);
1216 * Returns a bit field (at most 64) of locked regions within a page.
1217 * @param pPrivate info about the bank
1218 * @param v where to store locked bits
1221 FLASHD_GetLockBits(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
1225 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GLB
, 0, NULL
);
1226 if (r
== ERROR_OK
) {
1227 r
= EFC_GetResult(pPrivate
, v
);
1229 LOG_DEBUG("End: %d",r
);
1235 * Unlocks all the regions in the given address range.
1236 * @param pPrivate info about the bank
1237 * @param start_sector first sector to unlock
1238 * @param end_sector last (inclusive) to unlock
1242 FLASHD_Unlock(struct sam3_bank_private
*pPrivate
,
1243 unsigned start_sector
,
1244 unsigned end_sector
)
1249 uint32_t pages_per_sector
;
1251 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
1253 /* Unlock all pages */
1254 while (start_sector
<= end_sector
) {
1255 pg
= start_sector
* pages_per_sector
;
1257 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CLB
, pg
, &status
);
1258 if (r
!= ERROR_OK
) {
1270 * @param pPrivate - info about the bank
1271 * @param start_sector - first sector to lock
1272 * @param end_sector - last sector (inclusive) to lock
1275 FLASHD_Lock(struct sam3_bank_private
*pPrivate
,
1276 unsigned start_sector
,
1277 unsigned end_sector
)
1281 uint32_t pages_per_sector
;
1284 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
1286 /* Lock all pages */
1287 while (start_sector
<= end_sector
) {
1288 pg
= start_sector
* pages_per_sector
;
1290 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SLB
, pg
, &status
);
1291 if (r
!= ERROR_OK
) {
1300 /****** END SAM3 CODE ********/
1302 /* begin helpful debug code */
1303 // print the fieldname, the field value, in dec & hex, and return field value
1305 sam3_reg_fieldname(struct sam3_chip
*pChip
,
1306 const char *regname
,
1315 // extract the field
1317 v
= v
& ((1 << width
)-1);
1327 LOG_USER_N("\t%*s: %*d [0x%0*x] ",
1328 REG_NAME_WIDTH
, regname
,
1335 static const char _unknown
[] = "unknown";
1336 static const char * const eproc_names
[] = {
1355 #define nvpsize2 nvpsize // these two tables are identical
1356 static const char * const nvpsize
[] = {
1369 "1024K bytes", // 12
1371 "2048K bytes", // 14
1376 static const char * const sramsize
[] = {
1396 static const struct archnames
{ unsigned value
; const char *name
; } archnames
[] = {
1397 { 0x19, "AT91SAM9xx Series" },
1398 { 0x29, "AT91SAM9XExx Series" },
1399 { 0x34, "AT91x34 Series" },
1400 { 0x37, "CAP7 Series" },
1401 { 0x39, "CAP9 Series" },
1402 { 0x3B, "CAP11 Series" },
1403 { 0x40, "AT91x40 Series" },
1404 { 0x42, "AT91x42 Series" },
1405 { 0x55, "AT91x55 Series" },
1406 { 0x60, "AT91SAM7Axx Series" },
1407 { 0x61, "AT91SAM7AQxx Series" },
1408 { 0x63, "AT91x63 Series" },
1409 { 0x70, "AT91SAM7Sxx Series" },
1410 { 0x71, "AT91SAM7XCxx Series" },
1411 { 0x72, "AT91SAM7SExx Series" },
1412 { 0x73, "AT91SAM7Lxx Series" },
1413 { 0x75, "AT91SAM7Xxx Series" },
1414 { 0x76, "AT91SAM7SLxx Series" },
1415 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1416 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1417 { 0x83, "ATSAM3AxC Series (100-pin version)" },
1418 { 0x84, "ATSAM3XxC Series (100-pin version)" },
1419 { 0x85, "ATSAM3XxE Series (144-pin version)" },
1420 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
1421 { 0x88, "ATSAM3SxA Series (48-pin version)" },
1422 { 0x89, "ATSAM3SxB Series (64-pin version)" },
1423 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
1424 { 0x92, "AT91x92 Series" },
1425 { 0xF0, "AT75Cxx Series" },
1430 static const char * const nvptype
[] = {
1432 "romless or onchip flash", // 1
1433 "embedded flash memory", // 2
1434 "rom(nvpsiz) + embedded flash (nvpsiz2)", //3
1435 "sram emulating flash", // 4
1442 static const char *_yes_or_no(uint32_t v
)
1451 static const char * const _rc_freq
[] = {
1452 "4 MHz", "8 MHz", "12 MHz", "reserved"
1456 sam3_explain_ckgr_mor(struct sam3_chip
*pChip
)
1461 v
= sam3_reg_fieldname(pChip
, "MOSCXTEN", pChip
->cfg
.CKGR_MOR
, 0, 1);
1462 LOG_USER("(main xtal enabled: %s)",
1464 v
= sam3_reg_fieldname(pChip
, "MOSCXTBY", pChip
->cfg
.CKGR_MOR
, 1, 1);
1465 LOG_USER("(main osc bypass: %s)",
1467 rcen
= sam3_reg_fieldname(pChip
, "MOSCRCEN", pChip
->cfg
.CKGR_MOR
, 3, 1);
1468 LOG_USER("(onchip RC-OSC enabled: %s)",
1470 v
= sam3_reg_fieldname(pChip
, "MOSCRCF", pChip
->cfg
.CKGR_MOR
, 4, 3);
1471 LOG_USER("(onchip RC-OSC freq: %s)",
1474 pChip
->cfg
.rc_freq
= 0;
1478 pChip
->cfg
.rc_freq
= 0;
1481 pChip
->cfg
.rc_freq
= 4 * 1000 * 1000;
1484 pChip
->cfg
.rc_freq
= 8 * 1000 * 1000;
1487 pChip
->cfg
.rc_freq
= 12* 1000 * 1000;
1492 v
= sam3_reg_fieldname(pChip
,"MOSCXTST", pChip
->cfg
.CKGR_MOR
, 8, 8);
1493 LOG_USER("(startup clks, time= %f uSecs)",
1494 ((float)(v
* 1000000)) / ((float)(pChip
->cfg
.slow_freq
)));
1495 v
= sam3_reg_fieldname(pChip
, "MOSCSEL", pChip
->cfg
.CKGR_MOR
, 24, 1);
1496 LOG_USER("(mainosc source: %s)",
1497 v
? "external xtal" : "internal RC");
1499 v
= sam3_reg_fieldname(pChip
,"CFDEN", pChip
->cfg
.CKGR_MOR
, 25, 1);
1500 LOG_USER("(clock failure enabled: %s)",
1507 sam3_explain_chipid_cidr(struct sam3_chip
*pChip
)
1513 sam3_reg_fieldname(pChip
, "Version", pChip
->cfg
.CHIPID_CIDR
, 0, 5);
1516 v
= sam3_reg_fieldname(pChip
, "EPROC", pChip
->cfg
.CHIPID_CIDR
, 5, 3);
1517 LOG_USER("%s", eproc_names
[v
]);
1519 v
= sam3_reg_fieldname(pChip
, "NVPSIZE", pChip
->cfg
.CHIPID_CIDR
, 8, 4);
1520 LOG_USER("%s", nvpsize
[v
]);
1522 v
= sam3_reg_fieldname(pChip
, "NVPSIZE2", pChip
->cfg
.CHIPID_CIDR
, 12, 4);
1523 LOG_USER("%s", nvpsize2
[v
]);
1525 v
= sam3_reg_fieldname(pChip
, "SRAMSIZE", pChip
->cfg
.CHIPID_CIDR
, 16,4);
1526 LOG_USER("%s", sramsize
[ v
]);
1528 v
= sam3_reg_fieldname(pChip
, "ARCH", pChip
->cfg
.CHIPID_CIDR
, 20, 8);
1530 for (x
= 0 ; archnames
[x
].name
; x
++) {
1531 if (v
== archnames
[x
].value
) {
1532 cp
= archnames
[x
].name
;
1539 v
= sam3_reg_fieldname(pChip
, "NVPTYP", pChip
->cfg
.CHIPID_CIDR
, 28, 3);
1540 LOG_USER("%s", nvptype
[ v
]);
1542 v
= sam3_reg_fieldname(pChip
, "EXTID", pChip
->cfg
.CHIPID_CIDR
, 31, 1);
1543 LOG_USER("(exists: %s)", _yes_or_no(v
));
1547 sam3_explain_ckgr_mcfr(struct sam3_chip
*pChip
)
1552 v
= sam3_reg_fieldname(pChip
, "MAINFRDY", pChip
->cfg
.CKGR_MCFR
, 16, 1);
1553 LOG_USER("(main ready: %s)", _yes_or_no(v
));
1555 v
= sam3_reg_fieldname(pChip
, "MAINF", pChip
->cfg
.CKGR_MCFR
, 0, 16);
1557 v
= (v
* pChip
->cfg
.slow_freq
) / 16;
1558 pChip
->cfg
.mainosc_freq
= v
;
1560 LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
1562 pChip
->cfg
.slow_freq
/ 1000,
1563 pChip
->cfg
.slow_freq
% 1000);
1568 sam3_explain_ckgr_plla(struct sam3_chip
*pChip
)
1572 diva
= sam3_reg_fieldname(pChip
, "DIVA", pChip
->cfg
.CKGR_PLLAR
, 0, 8);
1574 mula
= sam3_reg_fieldname(pChip
, "MULA", pChip
->cfg
.CKGR_PLLAR
, 16, 11);
1576 pChip
->cfg
.plla_freq
= 0;
1578 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
1579 } else if (diva
== 0) {
1580 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
1581 } else if (diva
== 1) {
1582 pChip
->cfg
.plla_freq
= (pChip
->cfg
.mainosc_freq
* (mula
+ 1));
1583 LOG_USER("\tPLLA Freq: %3.03f MHz",
1584 _tomhz(pChip
->cfg
.plla_freq
));
1590 sam3_explain_mckr(struct sam3_chip
*pChip
)
1592 uint32_t css
, pres
, fin
= 0;
1594 const char *cp
= NULL
;
1596 css
= sam3_reg_fieldname(pChip
, "CSS", pChip
->cfg
.PMC_MCKR
, 0, 2);
1599 fin
= pChip
->cfg
.slow_freq
;
1603 fin
= pChip
->cfg
.mainosc_freq
;
1607 fin
= pChip
->cfg
.plla_freq
;
1611 if (pChip
->cfg
.CKGR_UCKR
& (1 << 16)) {
1612 fin
= 480 * 1000 * 1000;
1616 cp
= "upll (*ERROR* UPLL is disabled)";
1624 LOG_USER("%s (%3.03f Mhz)",
1627 pres
= sam3_reg_fieldname(pChip
, "PRES", pChip
->cfg
.PMC_MCKR
, 4, 3);
1628 switch (pres
& 0x07) {
1631 cp
= "selected clock";
1665 LOG_USER("(%s)", cp
);
1667 // sam3 has a *SINGLE* clock -
1668 // other at91 series parts have divisors for these.
1669 pChip
->cfg
.cpu_freq
= fin
;
1670 pChip
->cfg
.mclk_freq
= fin
;
1671 pChip
->cfg
.fclk_freq
= fin
;
1672 LOG_USER("\t\tResult CPU Freq: %3.03f",
1677 static struct sam3_chip
*
1678 target2sam3(struct target
*pTarget
)
1680 struct sam3_chip
*pChip
;
1682 if (pTarget
== NULL
) {
1686 pChip
= all_sam3_chips
;
1688 if (pChip
->target
== pTarget
) {
1689 break; // return below
1691 pChip
= pChip
->next
;
1699 sam3_get_reg_ptr(struct sam3_cfg
*pCfg
, const struct sam3_reg_list
*pList
)
1701 // this function exists to help
1702 // keep funky offsetof() errors
1703 // and casting from causing bugs
1705 // By using prototypes - we can detect what would
1706 // be casting errors.
1708 return ((uint32_t *)(void *)(((char *)(pCfg
)) + pList
->struct_offset
));
1712 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof(struct sam3_cfg, NAME), #NAME, FUNC }
1713 static const struct sam3_reg_list sam3_all_regs
[] = {
1714 SAM3_ENTRY(CKGR_MOR
, sam3_explain_ckgr_mor
),
1715 SAM3_ENTRY(CKGR_MCFR
, sam3_explain_ckgr_mcfr
),
1716 SAM3_ENTRY(CKGR_PLLAR
, sam3_explain_ckgr_plla
),
1717 SAM3_ENTRY(CKGR_UCKR
, NULL
),
1718 SAM3_ENTRY(PMC_FSMR
, NULL
),
1719 SAM3_ENTRY(PMC_FSPR
, NULL
),
1720 SAM3_ENTRY(PMC_IMR
, NULL
),
1721 SAM3_ENTRY(PMC_MCKR
, sam3_explain_mckr
),
1722 SAM3_ENTRY(PMC_PCK0
, NULL
),
1723 SAM3_ENTRY(PMC_PCK1
, NULL
),
1724 SAM3_ENTRY(PMC_PCK2
, NULL
),
1725 SAM3_ENTRY(PMC_PCSR
, NULL
),
1726 SAM3_ENTRY(PMC_SCSR
, NULL
),
1727 SAM3_ENTRY(PMC_SR
, NULL
),
1728 SAM3_ENTRY(CHIPID_CIDR
, sam3_explain_chipid_cidr
),
1729 SAM3_ENTRY(CHIPID_EXID
, NULL
),
1730 SAM3_ENTRY(SUPC_CR
, NULL
),
1732 // TERMINATE THE LIST
1740 static struct sam3_bank_private
*
1741 get_sam3_bank_private(struct flash_bank
*bank
)
1743 return (struct sam3_bank_private
*)(bank
->driver_priv
);
1747 * Given a pointer to where it goes in the structure,
1748 * determine the register name, address from the all registers table.
1750 static const struct sam3_reg_list
*
1751 sam3_GetReg(struct sam3_chip
*pChip
, uint32_t *goes_here
)
1753 const struct sam3_reg_list
*pReg
;
1755 pReg
= &(sam3_all_regs
[0]);
1756 while (pReg
->name
) {
1757 uint32_t *pPossible
;
1759 // calculate where this one go..
1760 // it is "possibly" this register.
1762 pPossible
= ((uint32_t *)(void *)(((char *)(&(pChip
->cfg
))) + pReg
->struct_offset
));
1764 // well? Is it this register
1765 if (pPossible
== goes_here
) {
1773 // This is *TOTAL*PANIC* - we are totally screwed.
1774 LOG_ERROR("INVALID SAM3 REGISTER");
1780 sam3_ReadThisReg(struct sam3_chip
*pChip
, uint32_t *goes_here
)
1782 const struct sam3_reg_list
*pReg
;
1785 pReg
= sam3_GetReg(pChip
, goes_here
);
1790 r
= target_read_u32(pChip
->target
, pReg
->address
, goes_here
);
1791 if (r
!= ERROR_OK
) {
1792 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
1793 pReg
->name
, (unsigned)(pReg
->address
), r
);
1801 sam3_ReadAllRegs(struct sam3_chip
*pChip
)
1804 const struct sam3_reg_list
*pReg
;
1806 pReg
= &(sam3_all_regs
[0]);
1807 while (pReg
->name
) {
1808 r
= sam3_ReadThisReg(pChip
,
1809 sam3_get_reg_ptr(&(pChip
->cfg
), pReg
));
1810 if (r
!= ERROR_OK
) {
1811 LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d",
1812 pReg
->name
, ((unsigned)(pReg
->address
)), r
);
1824 sam3_GetInfo(struct sam3_chip
*pChip
)
1826 const struct sam3_reg_list
*pReg
;
1829 pReg
= &(sam3_all_regs
[0]);
1830 while (pReg
->name
) {
1832 LOG_DEBUG("Start: %s", pReg
->name
);
1833 regval
= *sam3_get_reg_ptr(&(pChip
->cfg
), pReg
);
1834 LOG_USER("%*s: [0x%08x] -> 0x%08x",
1839 if (pReg
->explain_func
) {
1840 (*(pReg
->explain_func
))(pChip
);
1842 LOG_DEBUG("End: %s", pReg
->name
);
1845 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip
->cfg
.rc_freq
));
1846 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip
->cfg
.mainosc_freq
));
1847 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip
->cfg
.plla_freq
));
1848 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip
->cfg
.cpu_freq
));
1849 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip
->cfg
.mclk_freq
));
1852 LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
1853 pChip
->cfg
.unique_id
[0],
1854 pChip
->cfg
.unique_id
[1],
1855 pChip
->cfg
.unique_id
[2],
1856 pChip
->cfg
.unique_id
[3]);
1864 sam3_erase_check(struct flash_bank
*bank
)
1869 if (bank
->target
->state
!= TARGET_HALTED
) {
1870 LOG_ERROR("Target not halted");
1871 return ERROR_TARGET_NOT_HALTED
;
1873 if (0 == bank
->num_sectors
) {
1874 LOG_ERROR("Target: not supported/not probed");
1878 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
1879 for (x
= 0 ; x
< bank
->num_sectors
; x
++) {
1880 bank
->sectors
[x
].is_erased
= 1;
1888 sam3_protect_check(struct flash_bank
*bank
)
1893 struct sam3_bank_private
*pPrivate
;
1896 if (bank
->target
->state
!= TARGET_HALTED
) {
1897 LOG_ERROR("Target not halted");
1898 return ERROR_TARGET_NOT_HALTED
;
1901 pPrivate
= get_sam3_bank_private(bank
);
1903 LOG_ERROR("no private for this bank?");
1906 if (!(pPrivate
->probed
)) {
1907 return ERROR_FLASH_BANK_NOT_PROBED
;
1910 r
= FLASHD_GetLockBits(pPrivate
, &v
);
1911 if (r
!= ERROR_OK
) {
1912 LOG_DEBUG("Failed: %d",r
);
1916 for (x
= 0 ; x
< pPrivate
->nsectors
; x
++) {
1917 bank
->sectors
[x
].is_protected
= (!!(v
& (1 << x
)));
1923 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command
)
1925 struct sam3_chip
*pChip
;
1927 pChip
= all_sam3_chips
;
1929 // is this an existing chip?
1931 if (pChip
->target
== bank
->target
) {
1934 pChip
= pChip
->next
;
1938 // this is a *NEW* chip
1939 pChip
= calloc(1, sizeof(struct sam3_chip
));
1941 LOG_ERROR("NO RAM!");
1944 pChip
->target
= bank
->target
;
1946 pChip
->next
= all_sam3_chips
;
1947 all_sam3_chips
= pChip
;
1948 pChip
->target
= bank
->target
;
1949 // assumption is this runs at 32khz
1950 pChip
->cfg
.slow_freq
= 32768;
1954 switch (bank
->base
) {
1956 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x \
1957 [at91sam3u series] or 0x%08x [at91sam3s series])",
1958 ((unsigned int)(bank
->base
)),
1959 ((unsigned int)(FLASH_BANK0_BASE_U
)),
1960 ((unsigned int)(FLASH_BANK1_BASE_U
)),
1961 ((unsigned int)(FLASH_BANK_BASE_S
)));
1966 case FLASH_BANK0_BASE_U
:
1967 bank
->driver_priv
= &(pChip
->details
.bank
[0]);
1968 bank
->bank_number
= 0;
1969 pChip
->details
.bank
[0].pChip
= pChip
;
1970 pChip
->details
.bank
[0].pBank
= bank
;
1972 case FLASH_BANK1_BASE_U
:
1973 bank
->driver_priv
= &(pChip
->details
.bank
[1]);
1974 bank
->bank_number
= 1;
1975 pChip
->details
.bank
[1].pChip
= pChip
;
1976 pChip
->details
.bank
[1].pBank
= bank
;
1980 case FLASH_BANK_BASE_S
:
1981 bank
->driver_priv
= &(pChip
->details
.bank
[0]);
1982 bank
->bank_number
= 0;
1983 pChip
->details
.bank
[0].pChip
= pChip
;
1984 pChip
->details
.bank
[0].pBank
= bank
;
1988 // we initialize after probing.
1993 sam3_GetDetails(struct sam3_bank_private
*pPrivate
)
1995 const struct sam3_chip_details
*pDetails
;
1996 struct sam3_chip
*pChip
;
1997 struct flash_bank
*saved_banks
[SAM3_MAX_FLASH_BANKS
];
2001 pDetails
= all_sam3_details
;
2002 while (pDetails
->name
) {
2003 // Compare cidr without version bits
2004 if (pDetails
->chipid_cidr
== (pPrivate
->pChip
->cfg
.CHIPID_CIDR
& 0xFFFFFFE0)) {
2010 if (pDetails
->name
== NULL
) {
2011 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
2012 (unsigned int)(pPrivate
->pChip
->cfg
.CHIPID_CIDR
));
2013 // Help the victim, print details about the chip
2014 LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
2015 pPrivate
->pChip
->cfg
.CHIPID_CIDR
);
2016 sam3_explain_chipid_cidr(pPrivate
->pChip
);
2020 // DANGER: THERE ARE DRAGONS HERE
2022 // get our pChip - it is going
2023 // to be over-written shortly
2024 pChip
= pPrivate
->pChip
;
2026 // Note that, in reality:
2028 // pPrivate = &(pChip->details.bank[0])
2029 // or pPrivate = &(pChip->details.bank[1])
2032 // save the "bank" pointers
2033 for (x
= 0 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2034 saved_banks
[ x
] = pChip
->details
.bank
[x
].pBank
;
2037 // Overwrite the "details" structure.
2038 memcpy(&(pPrivate
->pChip
->details
),
2040 sizeof(pPrivate
->pChip
->details
));
2042 // now fix the ghosted pointers
2043 for (x
= 0 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2044 pChip
->details
.bank
[x
].pChip
= pChip
;
2045 pChip
->details
.bank
[x
].pBank
= saved_banks
[x
];
2048 // update the *BANK*SIZE*
2057 _sam3_probe(struct flash_bank
*bank
, int noise
)
2061 struct sam3_bank_private
*pPrivate
;
2064 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank
->bank_number
, noise
);
2065 if (bank
->target
->state
!= TARGET_HALTED
)
2067 LOG_ERROR("Target not halted");
2068 return ERROR_TARGET_NOT_HALTED
;
2071 pPrivate
= get_sam3_bank_private(bank
);
2073 LOG_ERROR("Invalid/unknown bank number");
2077 r
= sam3_ReadAllRegs(pPrivate
->pChip
);
2078 if (r
!= ERROR_OK
) {
2084 if (pPrivate
->pChip
->probed
) {
2085 r
= sam3_GetInfo(pPrivate
->pChip
);
2087 r
= sam3_GetDetails(pPrivate
);
2089 if (r
!= ERROR_OK
) {
2093 // update the flash bank size
2094 for (x
= 0 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2095 if (bank
->base
== pPrivate
->pChip
->details
.bank
[x
].base_address
) {
2096 bank
->size
= pPrivate
->pChip
->details
.bank
[x
].size_bytes
;
2101 if (bank
->sectors
== NULL
) {
2102 bank
->sectors
= calloc(pPrivate
->nsectors
, (sizeof((bank
->sectors
)[0])));
2103 if (bank
->sectors
== NULL
) {
2104 LOG_ERROR("No memory!");
2107 bank
->num_sectors
= pPrivate
->nsectors
;
2109 for (x
= 0 ; ((int)(x
)) < bank
->num_sectors
; x
++) {
2110 bank
->sectors
[x
].size
= pPrivate
->sector_size
;
2111 bank
->sectors
[x
].offset
= x
* (pPrivate
->sector_size
);
2113 bank
->sectors
[x
].is_erased
= -1;
2114 bank
->sectors
[x
].is_protected
= -1;
2118 pPrivate
->probed
= 1;
2120 r
= sam3_protect_check(bank
);
2121 if (r
!= ERROR_OK
) {
2125 LOG_DEBUG("Bank = %d, nbanks = %d",
2126 pPrivate
->bank_number
, pPrivate
->pChip
->details
.n_banks
);
2127 if ((pPrivate
->bank_number
+ 1) == pPrivate
->pChip
->details
.n_banks
) {
2129 // it appears to be associated with the *last* flash bank.
2130 FLASHD_ReadUniqueID(pPrivate
);
2137 sam3_probe(struct flash_bank
*bank
)
2139 return _sam3_probe(bank
, 1);
2143 sam3_auto_probe(struct flash_bank
*bank
)
2145 return _sam3_probe(bank
, 0);
2151 sam3_erase(struct flash_bank
*bank
, int first
, int last
)
2153 struct sam3_bank_private
*pPrivate
;
2157 if (bank
->target
->state
!= TARGET_HALTED
) {
2158 LOG_ERROR("Target not halted");
2159 return ERROR_TARGET_NOT_HALTED
;
2162 r
= sam3_auto_probe(bank
);
2163 if (r
!= ERROR_OK
) {
2164 LOG_DEBUG("Here,r=%d",r
);
2168 pPrivate
= get_sam3_bank_private(bank
);
2169 if (!(pPrivate
->probed
)) {
2170 return ERROR_FLASH_BANK_NOT_PROBED
;
2173 if ((first
== 0) && ((last
+ 1)== ((int)(pPrivate
->nsectors
)))) {
2176 return FLASHD_EraseEntireBank(pPrivate
);
2178 LOG_INFO("sam3 auto-erases while programing (request ignored)");
2183 sam3_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
2185 struct sam3_bank_private
*pPrivate
;
2189 if (bank
->target
->state
!= TARGET_HALTED
) {
2190 LOG_ERROR("Target not halted");
2191 return ERROR_TARGET_NOT_HALTED
;
2194 pPrivate
= get_sam3_bank_private(bank
);
2195 if (!(pPrivate
->probed
)) {
2196 return ERROR_FLASH_BANK_NOT_PROBED
;
2200 r
= FLASHD_Lock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
2202 r
= FLASHD_Unlock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
2204 LOG_DEBUG("End: r=%d",r
);
2212 sam3_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
2214 if (bank
->target
->state
!= TARGET_HALTED
) {
2215 LOG_ERROR("Target not halted");
2216 return ERROR_TARGET_NOT_HALTED
;
2223 sam3_page_read(struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
2228 adr
= pagenum
* pPrivate
->page_size
;
2229 adr
+= adr
+ pPrivate
->base_address
;
2231 r
= target_read_memory(pPrivate
->pChip
->target
,
2233 4, /* THIS*MUST*BE* in 32bit values */
2234 pPrivate
->page_size
/ 4,
2236 if (r
!= ERROR_OK
) {
2237 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x", (unsigned int)(adr
));
2242 // The code below is basically this:
2244 // arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s
2246 // Only the *CPU* can write to the flash buffer.
2247 // the DAP cannot... so - we download this 28byte thing
2248 // Run the algorithm - (below)
2249 // to program the device
2251 // ========================================
2252 // #include <stdint.h>
2256 // const uint32_t *src;
2258 // volatile uint32_t *base;
2263 // uint32_t sam3_function(struct foo *p)
2265 // volatile uint32_t *v;
2267 // const uint32_t *s;
2289 // ========================================
2293 static const uint8_t
2294 sam3_page_write_opcodes
[] = {
2295 // 24 0000 0446 mov r4, r0
2297 // 25 0002 6168 ldr r1, [r4, #4]
2299 // 26 0004 0068 ldr r0, [r0, #0]
2301 // 27 0006 A268 ldr r2, [r4, #8]
2303 // 28 @ lr needed for prologue
2305 // 30 0008 51F8043B ldr r3, [r1], #4
2306 0x51,0xf8,0x04,0x3b,
2307 // 31 000c 12F1FF32 adds r2, r2, #-1
2308 0x12,0xf1,0xff,0x32,
2309 // 32 0010 40F8043B str r3, [r0], #4
2310 0x40,0xf8,0x04,0x3b,
2311 // 33 0014 F8D1 bne .L2
2313 // 34 0016 E268 ldr r2, [r4, #12]
2315 // 35 0018 2369 ldr r3, [r4, #16]
2317 // 36 001a 5360 str r3, [r2, #4]
2319 // 37 001c 0832 adds r2, r2, #8
2322 // 39 001e 1068 ldr r0, [r2, #0]
2324 // 40 0020 10F0010F tst r0, #1
2325 0x10,0xf0,0x01,0x0f,
2326 // 41 0024 FBD0 beq .L4
2328 0x00,0xBE /* bkpt #0 */
2333 sam3_page_write(struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
2339 adr
= pagenum
* pPrivate
->page_size
;
2340 adr
+= (adr
+ pPrivate
->base_address
);
2342 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum
, (unsigned int)(adr
));
2343 r
= target_write_memory(pPrivate
->pChip
->target
,
2345 4, /* THIS*MUST*BE* in 32bit values */
2346 pPrivate
->page_size
/ 4,
2348 if (r
!= ERROR_OK
) {
2349 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x", (unsigned int)(adr
));
2353 r
= EFC_PerformCommand(pPrivate
,
2354 // send Erase & Write Page
2359 if (r
!= ERROR_OK
) {
2360 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x", (unsigned int)(adr
));
2362 if (status
& (1 << 2)) {
2363 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr
));
2366 if (status
& (1 << 1)) {
2367 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr
));
2378 sam3_write(struct flash_bank
*bank
,
2387 unsigned page_offset
;
2388 struct sam3_bank_private
*pPrivate
;
2389 uint8_t *pagebuffer
;
2391 // incase we bail further below, set this to null
2394 // ignore dumb requests
2400 if (bank
->target
->state
!= TARGET_HALTED
) {
2401 LOG_ERROR("Target not halted");
2402 r
= ERROR_TARGET_NOT_HALTED
;
2406 pPrivate
= get_sam3_bank_private(bank
);
2407 if (!(pPrivate
->probed
)) {
2408 r
= ERROR_FLASH_BANK_NOT_PROBED
;
2413 if ((offset
+ count
) > pPrivate
->size_bytes
) {
2414 LOG_ERROR("Flash write error - past end of bank");
2415 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2416 (unsigned int)(offset
),
2417 (unsigned int)(count
),
2418 (unsigned int)(pPrivate
->size_bytes
));
2423 pagebuffer
= malloc(pPrivate
->page_size
);
2425 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate
->page_size
));
2430 // what page do we start & end in?
2431 page_cur
= offset
/ pPrivate
->page_size
;
2432 page_end
= (offset
+ count
- 1) / pPrivate
->page_size
;
2434 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset
), (unsigned int)(count
));
2435 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur
), (int)(page_end
));
2437 // Special case: all one page
2440 // (1) non-aligned start
2442 // (3) non-aligned end.
2444 // Handle special case - all one page.
2445 if (page_cur
== page_end
) {
2446 LOG_DEBUG("Special case, all in one page");
2447 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
2448 if (r
!= ERROR_OK
) {
2452 page_offset
= (offset
& (pPrivate
->page_size
-1));
2453 memcpy(pagebuffer
+ page_offset
,
2457 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
2458 if (r
!= ERROR_OK
) {
2465 // non-aligned start
2466 page_offset
= offset
& (pPrivate
->page_size
- 1);
2468 LOG_DEBUG("Not-Aligned start");
2470 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
2471 if (r
!= ERROR_OK
) {
2475 // over-write with new data
2476 n
= (pPrivate
->page_size
- page_offset
);
2477 memcpy(pagebuffer
+ page_offset
,
2481 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
2482 if (r
!= ERROR_OK
) {
2492 // intermediate large pages
2493 // also - the final *terminal*
2494 // if that terminal page is a full page
2495 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2496 (int)page_cur
, (int)page_end
, (unsigned int)(count
));
2498 while ((page_cur
< page_end
) &&
2499 (count
>= pPrivate
->page_size
)) {
2500 r
= sam3_page_write(pPrivate
, page_cur
, buffer
);
2501 if (r
!= ERROR_OK
) {
2504 count
-= pPrivate
->page_size
;
2505 buffer
+= pPrivate
->page_size
;
2509 // terminal partial page?
2511 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count
));
2512 // we have a partial page
2513 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
2514 if (r
!= ERROR_OK
) {
2517 // data goes at start
2518 memcpy(pagebuffer
, buffer
, count
);
2519 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
2520 if (r
!= ERROR_OK
) {
2535 COMMAND_HANDLER(sam3_handle_info_command
)
2537 struct sam3_chip
*pChip
;
2541 pChip
= get_current_sam3(CMD_CTX
);
2548 // bank0 must exist before we can do anything
2549 if (pChip
->details
.bank
[0].pBank
== NULL
) {
2552 command_print(CMD_CTX
,
2553 "Please define bank %d via command: flash bank %s ... ",
2555 at91sam3_flash
.name
);
2559 // if bank 0 is not probed, then probe it
2560 if (!(pChip
->details
.bank
[0].probed
)) {
2561 r
= sam3_auto_probe(pChip
->details
.bank
[0].pBank
);
2562 if (r
!= ERROR_OK
) {
2566 // above guarantees the "chip details" structure is valid
2567 // and thus, bank private areas are valid
2568 // and we have a SAM3 chip, what a concept!
2571 // auto-probe other banks, 0 done above
2572 for (x
= 1 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2573 // skip banks not present
2574 if (!(pChip
->details
.bank
[x
].present
)) {
2578 if (pChip
->details
.bank
[x
].pBank
== NULL
) {
2582 if (pChip
->details
.bank
[x
].probed
) {
2586 r
= sam3_auto_probe(pChip
->details
.bank
[x
].pBank
);
2587 if (r
!= ERROR_OK
) {
2593 r
= sam3_GetInfo(pChip
);
2594 if (r
!= ERROR_OK
) {
2595 LOG_DEBUG("Sam3Info, Failed %d",r
);
2602 COMMAND_HANDLER(sam3_handle_gpnvm_command
)
2606 struct sam3_chip
*pChip
;
2608 pChip
= get_current_sam3(CMD_CTX
);
2613 if (pChip
->target
->state
!= TARGET_HALTED
) {
2614 LOG_ERROR("sam3 - target not halted");
2615 return ERROR_TARGET_NOT_HALTED
;
2619 if (pChip
->details
.bank
[0].pBank
== NULL
) {
2620 command_print(CMD_CTX
, "Bank0 must be defined first via: flash bank %s ...",
2621 at91sam3_flash
.name
);
2624 if (!pChip
->details
.bank
[0].probed
) {
2625 r
= sam3_auto_probe(pChip
->details
.bank
[0].pBank
);
2626 if (r
!= ERROR_OK
) {
2634 command_print(CMD_CTX
,"Too many parameters\n");
2635 return ERROR_COMMAND_SYNTAX_ERROR
;
2645 if ((0 == strcmp(CMD_ARGV
[0], "show")) && (0 == strcmp(CMD_ARGV
[1], "all"))) {
2649 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], v32
);
2655 if (0 == strcmp("show", CMD_ARGV
[0])) {
2659 for (x
= 0 ; x
< pChip
->details
.n_gpnvms
; x
++) {
2660 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), x
, &v
);
2661 if (r
!= ERROR_OK
) {
2664 command_print(CMD_CTX
, "sam3-gpnvm%u: %u", x
, v
);
2668 if ((who
>= 0) && (((unsigned)(who
)) < pChip
->details
.n_gpnvms
)) {
2669 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), who
, &v
);
2670 command_print(CMD_CTX
, "sam3-gpnvm%u: %u", who
, v
);
2673 command_print(CMD_CTX
, "sam3-gpnvm invalid GPNVM: %u", who
);
2674 return ERROR_COMMAND_SYNTAX_ERROR
;
2679 command_print(CMD_CTX
, "Missing GPNVM number");
2680 return ERROR_COMMAND_SYNTAX_ERROR
;
2683 if (0 == strcmp("set", CMD_ARGV
[0])) {
2684 r
= FLASHD_SetGPNVM(&(pChip
->details
.bank
[0]), who
);
2685 } else if ((0 == strcmp("clr", CMD_ARGV
[0])) ||
2686 (0 == strcmp("clear", CMD_ARGV
[0]))) { // quietly accept both
2687 r
= FLASHD_ClrGPNVM(&(pChip
->details
.bank
[0]), who
);
2689 command_print(CMD_CTX
, "Unknown command: %s", CMD_ARGV
[0]);
2690 r
= ERROR_COMMAND_SYNTAX_ERROR
;
2695 COMMAND_HANDLER(sam3_handle_slowclk_command
)
2697 struct sam3_chip
*pChip
;
2699 pChip
= get_current_sam3(CMD_CTX
);
2713 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], v
);
2715 // absurd slow clock of 200Khz?
2716 command_print(CMD_CTX
,"Absurd/illegal slow clock freq: %d\n", (int)(v
));
2717 return ERROR_COMMAND_SYNTAX_ERROR
;
2719 pChip
->cfg
.slow_freq
= v
;
2724 command_print(CMD_CTX
,"Too many parameters");
2725 return ERROR_COMMAND_SYNTAX_ERROR
;
2728 command_print(CMD_CTX
, "Slowclk freq: %d.%03dkhz",
2729 (int)(pChip
->cfg
.slow_freq
/ 1000),
2730 (int)(pChip
->cfg
.slow_freq
% 1000));
2734 static const struct command_registration at91sam3_exec_command_handlers
[] = {
2737 .handler
= sam3_handle_gpnvm_command
,
2738 .mode
= COMMAND_EXEC
,
2739 .usage
= "[('clr'|'set'|'show') bitnum]",
2740 .help
= "Without arguments, shows all bits in the gpnvm "
2741 "register. Otherwise, clears, sets, or shows one "
2742 "General Purpose Non-Volatile Memory (gpnvm) bit.",
2746 .handler
= sam3_handle_info_command
,
2747 .mode
= COMMAND_EXEC
,
2748 .help
= "Print information about the current at91sam3 chip"
2749 "and its flash configuration.",
2753 .handler
= sam3_handle_slowclk_command
,
2754 .mode
= COMMAND_EXEC
,
2755 .usage
= "[clock_hz]",
2756 .help
= "Display or set the slowclock frequency "
2757 "(default 32768 Hz).",
2759 COMMAND_REGISTRATION_DONE
2761 static const struct command_registration at91sam3_command_handlers
[] = {
2764 .mode
= COMMAND_ANY
,
2765 .help
= "at91sam3 flash command group",
2766 .chain
= at91sam3_exec_command_handlers
,
2768 COMMAND_REGISTRATION_DONE
2771 struct flash_driver at91sam3_flash
= {
2773 .commands
= at91sam3_command_handlers
,
2774 .flash_bank_command
= sam3_flash_bank_command
,
2775 .erase
= sam3_erase
,
2776 .protect
= sam3_protect
,
2777 .write
= sam3_write
,
2778 .read
= default_flash_read
,
2779 .probe
= sam3_probe
,
2780 .auto_probe
= sam3_auto_probe
,
2781 .erase_check
= sam3_erase_check
,
2782 .protect_check
= sam3_protect_check
,
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