1bb549e3b56a57db47f9740fb333b146246bb734
[openocd.git] / src / flash / nor / at91sam3.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
4 * *
5 * Copyright (C) 2010 by Olaf L√ľke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
7 * *
8 * Copyright (C) 2011 by Olivier Schonken (at91sam3x* support) * *
9 * and Jim Norris *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
18 * GNU General public License for more details. *
19 * *
20 * You should have received a copy of the GNU General public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
24 ****************************************************************************/
25
26 /* Some of the the lower level code was based on code supplied by
27 * ATMEL under this copyright. */
28
29 /* BEGIN ATMEL COPYRIGHT */
30 /* ----------------------------------------------------------------------------
31 * ATMEL Microcontroller Software Support
32 * ----------------------------------------------------------------------------
33 * Copyright (c) 2009, Atmel Corporation
34 *
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions are met:
39 *
40 * - Redistributions of source code must retain the above copyright notice,
41 * this list of conditions and the disclaimer below.
42 *
43 * Atmel's name may not be used to endorse or promote products derived from
44 * this software without specific prior written permission.
45 *
46 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
48 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
49 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
51 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
52 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
53 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
54 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
55 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
56 * ----------------------------------------------------------------------------
57 */
58 /* END ATMEL COPYRIGHT */
59
60 #ifdef HAVE_CONFIG_H
61 #include "config.h"
62 #endif
63
64 #include "imp.h"
65 #include <helper/time_support.h>
66
67 #define REG_NAME_WIDTH (12)
68
69 /* at91sam3u series (has one or two flash banks) */
70 #define FLASH_BANK0_BASE_U 0x00080000
71 #define FLASH_BANK1_BASE_U 0x00100000
72
73 /* at91sam3s series (has always one flash bank) */
74 #define FLASH_BANK_BASE_S 0x00400000
75
76 /* at91sam3sd series (has always two flash banks) */
77 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
78 #define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
79
80
81 /* at91sam3n series (has always one flash bank) */
82 #define FLASH_BANK_BASE_N 0x00400000
83
84 /* at91sam3a/x series has two flash banks*/
85 #define FLASH_BANK0_BASE_AX 0x00080000
86 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
87 #define FLASH_BANK1_BASE_256K_AX 0x000A0000
88 #define FLASH_BANK1_BASE_512K_AX 0x000C0000
89
90 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
91 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
92 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
93 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
94 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
95 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
96 /* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
97 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
98 /* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
99 /* #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages? */
100 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
101 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
102 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
103 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
104 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
105 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
106 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
107 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
108
109 #define offset_EFC_FMR 0
110 #define offset_EFC_FCR 4
111 #define offset_EFC_FSR 8
112 #define offset_EFC_FRR 12
113
114 extern struct flash_driver at91sam3_flash;
115
116 static float _tomhz(uint32_t freq_hz)
117 {
118 float f;
119
120 f = ((float)(freq_hz)) / 1000000.0;
121 return f;
122 }
123
124 /* How the chip is configured. */
125 struct sam3_cfg {
126 uint32_t unique_id[4];
127
128 uint32_t slow_freq;
129 uint32_t rc_freq;
130 uint32_t mainosc_freq;
131 uint32_t plla_freq;
132 uint32_t mclk_freq;
133 uint32_t cpu_freq;
134 uint32_t fclk_freq;
135 uint32_t pclk0_freq;
136 uint32_t pclk1_freq;
137 uint32_t pclk2_freq;
138
139
140 #define SAM3_CHIPID_CIDR (0x400E0740)
141 uint32_t CHIPID_CIDR;
142 #define SAM3_CHIPID_CIDR2 (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
143 uint32_t CHIPID_CIDR2;
144 #define SAM3_CHIPID_EXID (0x400E0744)
145 uint32_t CHIPID_EXID;
146 #define SAM3_CHIPID_EXID2 (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
147 uint32_t CHIPID_EXID2;
148
149
150 #define SAM3_PMC_BASE (0x400E0400)
151 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
152 uint32_t PMC_SCSR;
153 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
154 uint32_t PMC_PCSR;
155 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
156 uint32_t CKGR_UCKR;
157 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
158 uint32_t CKGR_MOR;
159 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
160 uint32_t CKGR_MCFR;
161 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
162 uint32_t CKGR_PLLAR;
163 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
164 uint32_t PMC_MCKR;
165 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
166 uint32_t PMC_PCK0;
167 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
168 uint32_t PMC_PCK1;
169 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
170 uint32_t PMC_PCK2;
171 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
172 uint32_t PMC_SR;
173 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
174 uint32_t PMC_IMR;
175 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
176 uint32_t PMC_FSMR;
177 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
178 uint32_t PMC_FSPR;
179 };
180
181 /*
182 * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
183 * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
184 * the flash wait state (FWS) should be set to 6. It seems like that the
185 * cause of the problem is not the flash itself, but the flash write
186 * buffer. Ie the wait states have to be set before writing into the
187 * buffer.
188 * Tested and confirmed with SAM3N and SAM3U
189 */
190
191 struct sam3_bank_private {
192 int probed;
193 /* DANGER: THERE ARE DRAGONS HERE.. */
194 /* NOTE: If you add more 'ghost' pointers */
195 /* be aware that you must *manually* update */
196 /* these pointers in the function sam3_GetDetails() */
197 /* See the comment "Here there be dragons" */
198
199 /* so we can find the chip we belong to */
200 struct sam3_chip *pChip;
201 /* so we can find the original bank pointer */
202 struct flash_bank *pBank;
203 unsigned bank_number;
204 uint32_t controller_address;
205 uint32_t base_address;
206 uint32_t flash_wait_states;
207 bool present;
208 unsigned size_bytes;
209 unsigned nsectors;
210 unsigned sector_size;
211 unsigned page_size;
212 };
213
214 struct sam3_chip_details {
215 /* THERE ARE DRAGONS HERE.. */
216 /* note: If you add pointers here */
217 /* be careful about them as they */
218 /* may need to be updated inside */
219 /* the function: "sam3_GetDetails() */
220 /* which copy/overwrites the */
221 /* 'runtime' copy of this structure */
222 uint32_t chipid_cidr;
223 const char *name;
224
225 unsigned n_gpnvms;
226 #define SAM3_N_NVM_BITS 3
227 unsigned gpnvm[SAM3_N_NVM_BITS];
228 unsigned total_flash_size;
229 unsigned total_sram_size;
230 unsigned n_banks;
231 #define SAM3_MAX_FLASH_BANKS 2
232 /* these are "initialized" from the global const data */
233 struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
234 };
235
236 struct sam3_chip {
237 struct sam3_chip *next;
238 int probed;
239
240 /* this is "initialized" from the global const structure */
241 struct sam3_chip_details details;
242 struct target *target;
243 struct sam3_cfg cfg;
244 };
245
246
247 struct sam3_reg_list {
248 uint32_t address; size_t struct_offset; const char *name;
249 void (*explain_func)(struct sam3_chip *pInfo);
250 };
251
252 static struct sam3_chip *all_sam3_chips;
253
254 static struct sam3_chip *get_current_sam3(struct command_context *cmd_ctx)
255 {
256 struct target *t;
257 static struct sam3_chip *p;
258
259 t = get_current_target(cmd_ctx);
260 if (!t) {
261 command_print(cmd_ctx, "No current target?");
262 return NULL;
263 }
264
265 p = all_sam3_chips;
266 if (!p) {
267 /* this should not happen */
268 /* the command is not registered until the chip is created? */
269 command_print(cmd_ctx, "No SAM3 chips exist?");
270 return NULL;
271 }
272
273 while (p) {
274 if (p->target == t)
275 return p;
276 p = p->next;
277 }
278 command_print(cmd_ctx, "Cannot find SAM3 chip?");
279 return NULL;
280 }
281
282 /* these are used to *initialize* the "pChip->details" structure. */
283 static const struct sam3_chip_details all_sam3_details[] = {
284 /* Start at91sam3u* series */
285 {
286 .chipid_cidr = 0x28100960,
287 .name = "at91sam3u4e",
288 .total_flash_size = 256 * 1024,
289 .total_sram_size = 52 * 1024,
290 .n_gpnvms = 3,
291 .n_banks = 2,
292
293 /* System boots at address 0x0 */
294 /* gpnvm[1] = selects boot code */
295 /* if gpnvm[1] == 0 */
296 /* boot is via "SAMBA" (rom) */
297 /* else */
298 /* boot is via FLASH */
299 /* Selection is via gpnvm[2] */
300 /* endif */
301 /* */
302 /* NOTE: banks 0 & 1 switch places */
303 /* if gpnvm[2] == 0 */
304 /* Bank0 is the boot rom */
305 /* else */
306 /* Bank1 is the boot rom */
307 /* endif */
308 /* .bank[0] = { */
309 {
310 {
311 .probed = 0,
312 .pChip = NULL,
313 .pBank = NULL,
314 .bank_number = 0,
315 .base_address = FLASH_BANK0_BASE_U,
316 .controller_address = 0x400e0800,
317 .flash_wait_states = 6, /* workaround silicon bug */
318 .present = 1,
319 .size_bytes = 128 * 1024,
320 .nsectors = 16,
321 .sector_size = 8192,
322 .page_size = 256,
323 },
324
325 /* .bank[1] = { */
326 {
327 .probed = 0,
328 .pChip = NULL,
329 .pBank = NULL,
330 .bank_number = 1,
331 .base_address = FLASH_BANK1_BASE_U,
332 .controller_address = 0x400e0a00,
333 .flash_wait_states = 6, /* workaround silicon bug */
334 .present = 1,
335 .size_bytes = 128 * 1024,
336 .nsectors = 16,
337 .sector_size = 8192,
338 .page_size = 256,
339 },
340 },
341 },
342
343 {
344 .chipid_cidr = 0x281a0760,
345 .name = "at91sam3u2e",
346 .total_flash_size = 128 * 1024,
347 .total_sram_size = 36 * 1024,
348 .n_gpnvms = 2,
349 .n_banks = 1,
350
351 /* System boots at address 0x0 */
352 /* gpnvm[1] = selects boot code */
353 /* if gpnvm[1] == 0 */
354 /* boot is via "SAMBA" (rom) */
355 /* else */
356 /* boot is via FLASH */
357 /* Selection is via gpnvm[2] */
358 /* endif */
359 /* .bank[0] = { */
360 {
361 {
362 .probed = 0,
363 .pChip = NULL,
364 .pBank = NULL,
365 .bank_number = 0,
366 .base_address = FLASH_BANK0_BASE_U,
367 .controller_address = 0x400e0800,
368 .flash_wait_states = 6, /* workaround silicon bug */
369 .present = 1,
370 .size_bytes = 128 * 1024,
371 .nsectors = 16,
372 .sector_size = 8192,
373 .page_size = 256,
374 },
375 /* .bank[1] = { */
376 {
377 .present = 0,
378 .probed = 0,
379 .bank_number = 1,
380 },
381 },
382 },
383 {
384 .chipid_cidr = 0x28190560,
385 .name = "at91sam3u1e",
386 .total_flash_size = 64 * 1024,
387 .total_sram_size = 20 * 1024,
388 .n_gpnvms = 2,
389 .n_banks = 1,
390
391 /* System boots at address 0x0 */
392 /* gpnvm[1] = selects boot code */
393 /* if gpnvm[1] == 0 */
394 /* boot is via "SAMBA" (rom) */
395 /* else */
396 /* boot is via FLASH */
397 /* Selection is via gpnvm[2] */
398 /* endif */
399 /* */
400
401 /* .bank[0] = { */
402 {
403 {
404 .probed = 0,
405 .pChip = NULL,
406 .pBank = NULL,
407 .bank_number = 0,
408 .base_address = FLASH_BANK0_BASE_U,
409 .controller_address = 0x400e0800,
410 .flash_wait_states = 6, /* workaround silicon bug */
411 .present = 1,
412 .size_bytes = 64 * 1024,
413 .nsectors = 8,
414 .sector_size = 8192,
415 .page_size = 256,
416 },
417
418 /* .bank[1] = { */
419 {
420 .present = 0,
421 .probed = 0,
422 .bank_number = 1,
423 },
424 },
425 },
426
427 {
428 .chipid_cidr = 0x28000960,
429 .name = "at91sam3u4c",
430 .total_flash_size = 256 * 1024,
431 .total_sram_size = 52 * 1024,
432 .n_gpnvms = 3,
433 .n_banks = 2,
434
435 /* System boots at address 0x0 */
436 /* gpnvm[1] = selects boot code */
437 /* if gpnvm[1] == 0 */
438 /* boot is via "SAMBA" (rom) */
439 /* else */
440 /* boot is via FLASH */
441 /* Selection is via gpnvm[2] */
442 /* endif */
443 /* */
444 /* NOTE: banks 0 & 1 switch places */
445 /* if gpnvm[2] == 0 */
446 /* Bank0 is the boot rom */
447 /* else */
448 /* Bank1 is the boot rom */
449 /* endif */
450 {
451 {
452 /* .bank[0] = { */
453 .probed = 0,
454 .pChip = NULL,
455 .pBank = NULL,
456 .bank_number = 0,
457 .base_address = FLASH_BANK0_BASE_U,
458 .controller_address = 0x400e0800,
459 .flash_wait_states = 6, /* workaround silicon bug */
460 .present = 1,
461 .size_bytes = 128 * 1024,
462 .nsectors = 16,
463 .sector_size = 8192,
464 .page_size = 256,
465 },
466 /* .bank[1] = { */
467 {
468 .probed = 0,
469 .pChip = NULL,
470 .pBank = NULL,
471 .bank_number = 1,
472 .base_address = FLASH_BANK1_BASE_U,
473 .controller_address = 0x400e0a00,
474 .flash_wait_states = 6, /* workaround silicon bug */
475 .present = 1,
476 .size_bytes = 128 * 1024,
477 .nsectors = 16,
478 .sector_size = 8192,
479 .page_size = 256,
480 },
481 },
482 },
483
484 {
485 .chipid_cidr = 0x280a0760,
486 .name = "at91sam3u2c",
487 .total_flash_size = 128 * 1024,
488 .total_sram_size = 36 * 1024,
489 .n_gpnvms = 2,
490 .n_banks = 1,
491
492 /* System boots at address 0x0 */
493 /* gpnvm[1] = selects boot code */
494 /* if gpnvm[1] == 0 */
495 /* boot is via "SAMBA" (rom) */
496 /* else */
497 /* boot is via FLASH */
498 /* Selection is via gpnvm[2] */
499 /* endif */
500 {
501 /* .bank[0] = { */
502 {
503 .probed = 0,
504 .pChip = NULL,
505 .pBank = NULL,
506 .bank_number = 0,
507 .base_address = FLASH_BANK0_BASE_U,
508 .controller_address = 0x400e0800,
509 .flash_wait_states = 6, /* workaround silicon bug */
510 .present = 1,
511 .size_bytes = 128 * 1024,
512 .nsectors = 16,
513 .sector_size = 8192,
514 .page_size = 256,
515 },
516 /* .bank[1] = { */
517 {
518 .present = 0,
519 .probed = 0,
520 .bank_number = 1,
521 },
522 },
523 },
524 {
525 .chipid_cidr = 0x28090560,
526 .name = "at91sam3u1c",
527 .total_flash_size = 64 * 1024,
528 .total_sram_size = 20 * 1024,
529 .n_gpnvms = 2,
530 .n_banks = 1,
531
532 /* System boots at address 0x0 */
533 /* gpnvm[1] = selects boot code */
534 /* if gpnvm[1] == 0 */
535 /* boot is via "SAMBA" (rom) */
536 /* else */
537 /* boot is via FLASH */
538 /* Selection is via gpnvm[2] */
539 /* endif */
540 /* */
541
542 {
543 /* .bank[0] = { */
544 {
545 .probed = 0,
546 .pChip = NULL,
547 .pBank = NULL,
548 .bank_number = 0,
549 .base_address = FLASH_BANK0_BASE_U,
550 .controller_address = 0x400e0800,
551 .flash_wait_states = 6, /* workaround silicon bug */
552 .present = 1,
553 .size_bytes = 64 * 1024,
554 .nsectors = 8,
555 .sector_size = 8192,
556 .page_size = 256,
557 },
558 /* .bank[1] = { */
559 {
560 .present = 0,
561 .probed = 0,
562 .bank_number = 1,
563
564 },
565 },
566 },
567
568 /* Start at91sam3s* series */
569
570 /* Note: The preliminary at91sam3s datasheet says on page 302 */
571 /* that the flash controller is at address 0x400E0800. */
572 /* This is _not_ the case, the controller resides at address 0x400e0a00. */
573 {
574 .chipid_cidr = 0x28A00960,
575 .name = "at91sam3s4c",
576 .total_flash_size = 256 * 1024,
577 .total_sram_size = 48 * 1024,
578 .n_gpnvms = 2,
579 .n_banks = 1,
580 {
581 /* .bank[0] = { */
582 {
583 .probed = 0,
584 .pChip = NULL,
585 .pBank = NULL,
586 .bank_number = 0,
587 .base_address = FLASH_BANK_BASE_S,
588 .controller_address = 0x400e0a00,
589 .flash_wait_states = 6, /* workaround silicon bug */
590 .present = 1,
591 .size_bytes = 256 * 1024,
592 .nsectors = 16,
593 .sector_size = 16384,
594 .page_size = 256,
595 },
596 /* .bank[1] = { */
597 {
598 .present = 0,
599 .probed = 0,
600 .bank_number = 1,
601
602 },
603 },
604 },
605
606 {
607 .chipid_cidr = 0x28900960,
608 .name = "at91sam3s4b",
609 .total_flash_size = 256 * 1024,
610 .total_sram_size = 48 * 1024,
611 .n_gpnvms = 2,
612 .n_banks = 1,
613 {
614 /* .bank[0] = { */
615 {
616 .probed = 0,
617 .pChip = NULL,
618 .pBank = NULL,
619 .bank_number = 0,
620 .base_address = FLASH_BANK_BASE_S,
621 .controller_address = 0x400e0a00,
622 .flash_wait_states = 6, /* workaround silicon bug */
623 .present = 1,
624 .size_bytes = 256 * 1024,
625 .nsectors = 16,
626 .sector_size = 16384,
627 .page_size = 256,
628 },
629 /* .bank[1] = { */
630 {
631 .present = 0,
632 .probed = 0,
633 .bank_number = 1,
634
635 },
636 },
637 },
638 {
639 .chipid_cidr = 0x28800960,
640 .name = "at91sam3s4a",
641 .total_flash_size = 256 * 1024,
642 .total_sram_size = 48 * 1024,
643 .n_gpnvms = 2,
644 .n_banks = 1,
645 {
646 /* .bank[0] = { */
647 {
648 .probed = 0,
649 .pChip = NULL,
650 .pBank = NULL,
651 .bank_number = 0,
652 .base_address = FLASH_BANK_BASE_S,
653 .controller_address = 0x400e0a00,
654 .flash_wait_states = 6, /* workaround silicon bug */
655 .present = 1,
656 .size_bytes = 256 * 1024,
657 .nsectors = 16,
658 .sector_size = 16384,
659 .page_size = 256,
660 },
661 /* .bank[1] = { */
662 {
663 .present = 0,
664 .probed = 0,
665 .bank_number = 1,
666
667 },
668 },
669 },
670 {
671 .chipid_cidr = 0x28AA0760,
672 .name = "at91sam3s2c",
673 .total_flash_size = 128 * 1024,
674 .total_sram_size = 32 * 1024,
675 .n_gpnvms = 2,
676 .n_banks = 1,
677 {
678 /* .bank[0] = { */
679 {
680 .probed = 0,
681 .pChip = NULL,
682 .pBank = NULL,
683 .bank_number = 0,
684 .base_address = FLASH_BANK_BASE_S,
685 .controller_address = 0x400e0a00,
686 .flash_wait_states = 6, /* workaround silicon bug */
687 .present = 1,
688 .size_bytes = 128 * 1024,
689 .nsectors = 8,
690 .sector_size = 16384,
691 .page_size = 256,
692 },
693 /* .bank[1] = { */
694 {
695 .present = 0,
696 .probed = 0,
697 .bank_number = 1,
698
699 },
700 },
701 },
702 {
703 .chipid_cidr = 0x289A0760,
704 .name = "at91sam3s2b",
705 .total_flash_size = 128 * 1024,
706 .total_sram_size = 32 * 1024,
707 .n_gpnvms = 2,
708 .n_banks = 1,
709 {
710 /* .bank[0] = { */
711 {
712 .probed = 0,
713 .pChip = NULL,
714 .pBank = NULL,
715 .bank_number = 0,
716 .base_address = FLASH_BANK_BASE_S,
717 .controller_address = 0x400e0a00,
718 .flash_wait_states = 6, /* workaround silicon bug */
719 .present = 1,
720 .size_bytes = 128 * 1024,
721 .nsectors = 8,
722 .sector_size = 16384,
723 .page_size = 256,
724 },
725 /* .bank[1] = { */
726 {
727 .present = 0,
728 .probed = 0,
729 .bank_number = 1,
730
731 },
732 },
733 },
734 {
735 .chipid_cidr = 0x298B0A60,
736 .name = "at91sam3sd8a",
737 .total_flash_size = 512 * 1024,
738 .total_sram_size = 64 * 1024,
739 .n_gpnvms = 3,
740 .n_banks = 2,
741 {
742 /* .bank[0] = { */
743 {
744 .probed = 0,
745 .pChip = NULL,
746 .pBank = NULL,
747 .bank_number = 0,
748 .base_address = FLASH_BANK0_BASE_SD,
749 .controller_address = 0x400e0a00,
750 .flash_wait_states = 6, /* workaround silicon bug */
751 .present = 1,
752 .size_bytes = 256 * 1024,
753 .nsectors = 16,
754 .sector_size = 32768,
755 .page_size = 256,
756 },
757 /* .bank[1] = { */
758 {
759 .probed = 0,
760 .pChip = NULL,
761 .pBank = NULL,
762 .bank_number = 1,
763 .base_address = FLASH_BANK1_BASE_512K_SD,
764 .controller_address = 0x400e0a00,
765 .flash_wait_states = 6, /* workaround silicon bug */
766 .present = 1,
767 .size_bytes = 256 * 1024,
768 .nsectors = 16,
769 .sector_size = 32768,
770 .page_size = 256,
771 },
772 },
773 },
774 {
775 .chipid_cidr = 0x299B0A60,
776 .name = "at91sam3sd8b",
777 .total_flash_size = 512 * 1024,
778 .total_sram_size = 64 * 1024,
779 .n_gpnvms = 3,
780 .n_banks = 2,
781 {
782 /* .bank[0] = { */
783 {
784 .probed = 0,
785 .pChip = NULL,
786 .pBank = NULL,
787 .bank_number = 0,
788 .base_address = FLASH_BANK0_BASE_SD,
789 .controller_address = 0x400e0a00,
790 .flash_wait_states = 6, /* workaround silicon bug */
791 .present = 1,
792 .size_bytes = 256 * 1024,
793 .nsectors = 16,
794 .sector_size = 32768,
795 .page_size = 256,
796 },
797 /* .bank[1] = { */
798 {
799 .probed = 0,
800 .pChip = NULL,
801 .pBank = NULL,
802 .bank_number = 1,
803 .base_address = FLASH_BANK1_BASE_512K_SD,
804 .controller_address = 0x400e0a00,
805 .flash_wait_states = 6, /* workaround silicon bug */
806 .present = 1,
807 .size_bytes = 256 * 1024,
808 .nsectors = 16,
809 .sector_size = 32768,
810 .page_size = 256,
811 },
812 },
813 },
814 {
815 .chipid_cidr = 0x29ab0a60,
816 .name = "at91sam3sd8c",
817 .total_flash_size = 512 * 1024,
818 .total_sram_size = 64 * 1024,
819 .n_gpnvms = 3,
820 .n_banks = 2,
821 {
822 /* .bank[0] = { */
823 {
824 .probed = 0,
825 .pChip = NULL,
826 .pBank = NULL,
827 .bank_number = 0,
828 .base_address = FLASH_BANK0_BASE_SD,
829 .controller_address = 0x400e0a00,
830 .flash_wait_states = 6, /* workaround silicon bug */
831 .present = 1,
832 .size_bytes = 256 * 1024,
833 .nsectors = 16,
834 .sector_size = 32768,
835 .page_size = 256,
836 },
837 /* .bank[1] = { */
838 {
839 .probed = 0,
840 .pChip = NULL,
841 .pBank = NULL,
842 .bank_number = 1,
843 .base_address = FLASH_BANK1_BASE_512K_SD,
844 .controller_address = 0x400e0a00,
845 .flash_wait_states = 6, /* workaround silicon bug */
846 .present = 1,
847 .size_bytes = 256 * 1024,
848 .nsectors = 16,
849 .sector_size = 32768,
850 .page_size = 256,
851 },
852 },
853 },
854 {
855 .chipid_cidr = 0x288A0760,
856 .name = "at91sam3s2a",
857 .total_flash_size = 128 * 1024,
858 .total_sram_size = 32 * 1024,
859 .n_gpnvms = 2,
860 .n_banks = 1,
861 {
862 /* .bank[0] = { */
863 {
864 .probed = 0,
865 .pChip = NULL,
866 .pBank = NULL,
867 .bank_number = 0,
868 .base_address = FLASH_BANK_BASE_S,
869 .controller_address = 0x400e0a00,
870 .flash_wait_states = 6, /* workaround silicon bug */
871 .present = 1,
872 .size_bytes = 128 * 1024,
873 .nsectors = 8,
874 .sector_size = 16384,
875 .page_size = 256,
876 },
877 /* .bank[1] = { */
878 {
879 .present = 0,
880 .probed = 0,
881 .bank_number = 1,
882
883 },
884 },
885 },
886 {
887 .chipid_cidr = 0x28A90560,
888 .name = "at91sam3s1c",
889 .total_flash_size = 64 * 1024,
890 .total_sram_size = 16 * 1024,
891 .n_gpnvms = 2,
892 .n_banks = 1,
893 {
894 /* .bank[0] = { */
895 {
896 .probed = 0,
897 .pChip = NULL,
898 .pBank = NULL,
899 .bank_number = 0,
900 .base_address = FLASH_BANK_BASE_S,
901 .controller_address = 0x400e0a00,
902 .flash_wait_states = 6, /* workaround silicon bug */
903 .present = 1,
904 .size_bytes = 64 * 1024,
905 .nsectors = 4,
906 .sector_size = 16384,
907 .page_size = 256,
908 },
909 /* .bank[1] = { */
910 {
911 .present = 0,
912 .probed = 0,
913 .bank_number = 1,
914
915 },
916 },
917 },
918 {
919 .chipid_cidr = 0x28990560,
920 .name = "at91sam3s1b",
921 .total_flash_size = 64 * 1024,
922 .total_sram_size = 16 * 1024,
923 .n_gpnvms = 2,
924 .n_banks = 1,
925 {
926 /* .bank[0] = { */
927 {
928 .probed = 0,
929 .pChip = NULL,
930 .pBank = NULL,
931 .bank_number = 0,
932 .base_address = FLASH_BANK_BASE_S,
933 .controller_address = 0x400e0a00,
934 .flash_wait_states = 6, /* workaround silicon bug */
935 .present = 1,
936 .size_bytes = 64 * 1024,
937 .nsectors = 4,
938 .sector_size = 16384,
939 .page_size = 256,
940 },
941 /* .bank[1] = { */
942 {
943 .present = 0,
944 .probed = 0,
945 .bank_number = 1,
946
947 },
948 },
949 },
950 {
951 .chipid_cidr = 0x28890560,
952 .name = "at91sam3s1a",
953 .total_flash_size = 64 * 1024,
954 .total_sram_size = 16 * 1024,
955 .n_gpnvms = 2,
956 .n_banks = 1,
957 {
958 /* .bank[0] = { */
959 {
960 .probed = 0,
961 .pChip = NULL,
962 .pBank = NULL,
963 .bank_number = 0,
964 .base_address = FLASH_BANK_BASE_S,
965 .controller_address = 0x400e0a00,
966 .flash_wait_states = 6, /* workaround silicon bug */
967 .present = 1,
968 .size_bytes = 64 * 1024,
969 .nsectors = 4,
970 .sector_size = 16384,
971 .page_size = 256,
972 },
973 /* .bank[1] = { */
974 {
975 .present = 0,
976 .probed = 0,
977 .bank_number = 1,
978
979 },
980 },
981 },
982 {
983 .chipid_cidr = 0x288B0A60,
984 .name = "at91sam3s8a",
985 .total_flash_size = 256 * 2048,
986 .total_sram_size = 64 * 1024,
987 .n_gpnvms = 2,
988 .n_banks = 1,
989 {
990 /* .bank[0] = { */
991 {
992 .probed = 0,
993 .pChip = NULL,
994 .pBank = NULL,
995 .bank_number = 0,
996 .base_address = FLASH_BANK_BASE_S,
997 .controller_address = 0x400e0a00,
998 .flash_wait_states = 6, /* workaround silicon bug */
999 .present = 1,
1000 .size_bytes = 256 * 2048,
1001 .nsectors = 16,
1002 .sector_size = 32768,
1003 .page_size = 256,
1004 },
1005 /* .bank[1] = { */
1006 {
1007 .present = 0,
1008 .probed = 0,
1009 .bank_number = 1,
1010
1011 },
1012 },
1013 },
1014 {
1015 .chipid_cidr = 0x289B0A60,
1016 .name = "at91sam3s8b",
1017 .total_flash_size = 256 * 2048,
1018 .total_sram_size = 64 * 1024,
1019 .n_gpnvms = 2,
1020 .n_banks = 1,
1021 {
1022 /* .bank[0] = { */
1023 {
1024 .probed = 0,
1025 .pChip = NULL,
1026 .pBank = NULL,
1027 .bank_number = 0,
1028 .base_address = FLASH_BANK_BASE_S,
1029 .controller_address = 0x400e0a00,
1030 .flash_wait_states = 6, /* workaround silicon bug */
1031 .present = 1,
1032 .size_bytes = 256 * 2048,
1033 .nsectors = 16,
1034 .sector_size = 32768,
1035 .page_size = 256,
1036 },
1037 /* .bank[1] = { */
1038 {
1039 .present = 0,
1040 .probed = 0,
1041 .bank_number = 1,
1042
1043 },
1044 },
1045 },
1046 {
1047 .chipid_cidr = 0x28AB0A60,
1048 .name = "at91sam3s8c",
1049 .total_flash_size = 256 * 2048,
1050 .total_sram_size = 64 * 1024,
1051 .n_gpnvms = 2,
1052 .n_banks = 1,
1053 {
1054 /* .bank[0] = { */
1055 {
1056 .probed = 0,
1057 .pChip = NULL,
1058 .pBank = NULL,
1059 .bank_number = 0,
1060 .base_address = FLASH_BANK_BASE_S,
1061 .controller_address = 0x400e0a00,
1062 .flash_wait_states = 6, /* workaround silicon bug */
1063 .present = 1,
1064 .size_bytes = 256 * 2048,
1065 .nsectors = 16,
1066 .sector_size = 32768,
1067 .page_size = 256,
1068 },
1069 /* .bank[1] = { */
1070 {
1071 .present = 0,
1072 .probed = 0,
1073 .bank_number = 1,
1074
1075 },
1076 },
1077 },
1078
1079 /* Start at91sam3n* series */
1080 {
1081 .chipid_cidr = 0x29540960,
1082 .name = "at91sam3n4c",
1083 .total_flash_size = 256 * 1024,
1084 .total_sram_size = 24 * 1024,
1085 .n_gpnvms = 3,
1086 .n_banks = 1,
1087
1088 /* System boots at address 0x0 */
1089 /* gpnvm[1] = selects boot code */
1090 /* if gpnvm[1] == 0 */
1091 /* boot is via "SAMBA" (rom) */
1092 /* else */
1093 /* boot is via FLASH */
1094 /* Selection is via gpnvm[2] */
1095 /* endif */
1096 /* */
1097 /* NOTE: banks 0 & 1 switch places */
1098 /* if gpnvm[2] == 0 */
1099 /* Bank0 is the boot rom */
1100 /* else */
1101 /* Bank1 is the boot rom */
1102 /* endif */
1103 /* .bank[0] = { */
1104 {
1105 {
1106 .probed = 0,
1107 .pChip = NULL,
1108 .pBank = NULL,
1109 .bank_number = 0,
1110 .base_address = FLASH_BANK_BASE_N,
1111 .controller_address = 0x400e0A00,
1112 .flash_wait_states = 6, /* workaround silicon bug */
1113 .present = 1,
1114 .size_bytes = 256 * 1024,
1115 .nsectors = 16,
1116 .sector_size = 16384,
1117 .page_size = 256,
1118 },
1119
1120 /* .bank[1] = { */
1121 {
1122 .present = 0,
1123 .probed = 0,
1124 .bank_number = 1,
1125 },
1126 },
1127 },
1128
1129 {
1130 .chipid_cidr = 0x29440960,
1131 .name = "at91sam3n4b",
1132 .total_flash_size = 256 * 1024,
1133 .total_sram_size = 24 * 1024,
1134 .n_gpnvms = 3,
1135 .n_banks = 1,
1136
1137 /* System boots at address 0x0 */
1138 /* gpnvm[1] = selects boot code */
1139 /* if gpnvm[1] == 0 */
1140 /* boot is via "SAMBA" (rom) */
1141 /* else */
1142 /* boot is via FLASH */
1143 /* Selection is via gpnvm[2] */
1144 /* endif */
1145 /* */
1146 /* NOTE: banks 0 & 1 switch places */
1147 /* if gpnvm[2] == 0 */
1148 /* Bank0 is the boot rom */
1149 /* else */
1150 /* Bank1 is the boot rom */
1151 /* endif */
1152 /* .bank[0] = { */
1153 {
1154 {
1155 .probed = 0,
1156 .pChip = NULL,
1157 .pBank = NULL,
1158 .bank_number = 0,
1159 .base_address = FLASH_BANK_BASE_N,
1160 .controller_address = 0x400e0A00,
1161 .flash_wait_states = 6, /* workaround silicon bug */
1162 .present = 1,
1163 .size_bytes = 256 * 1024,
1164 .nsectors = 16,
1165 .sector_size = 16384,
1166 .page_size = 256,
1167 },
1168
1169 /* .bank[1] = { */
1170 {
1171 .present = 0,
1172 .probed = 0,
1173 .bank_number = 1,
1174 },
1175 },
1176 },
1177
1178 {
1179 .chipid_cidr = 0x29340960,
1180 .name = "at91sam3n4a",
1181 .total_flash_size = 256 * 1024,
1182 .total_sram_size = 24 * 1024,
1183 .n_gpnvms = 3,
1184 .n_banks = 1,
1185
1186 /* System boots at address 0x0 */
1187 /* gpnvm[1] = selects boot code */
1188 /* if gpnvm[1] == 0 */
1189 /* boot is via "SAMBA" (rom) */
1190 /* else */
1191 /* boot is via FLASH */
1192 /* Selection is via gpnvm[2] */
1193 /* endif */
1194 /* */
1195 /* NOTE: banks 0 & 1 switch places */
1196 /* if gpnvm[2] == 0 */
1197 /* Bank0 is the boot rom */
1198 /* else */
1199 /* Bank1 is the boot rom */
1200 /* endif */
1201 /* .bank[0] = { */
1202 {
1203 {
1204 .probed = 0,
1205 .pChip = NULL,
1206 .pBank = NULL,
1207 .bank_number = 0,
1208 .base_address = FLASH_BANK_BASE_N,
1209 .controller_address = 0x400e0A00,
1210 .flash_wait_states = 6, /* workaround silicon bug */
1211 .present = 1,
1212 .size_bytes = 256 * 1024,
1213 .nsectors = 16,
1214 .sector_size = 16384,
1215 .page_size = 256,
1216 },
1217
1218 /* .bank[1] = { */
1219 {
1220 .present = 0,
1221 .probed = 0,
1222 .bank_number = 1,
1223 },
1224 },
1225 },
1226
1227 {
1228 .chipid_cidr = 0x29590760,
1229 .name = "at91sam3n2c",
1230 .total_flash_size = 128 * 1024,
1231 .total_sram_size = 16 * 1024,
1232 .n_gpnvms = 3,
1233 .n_banks = 1,
1234
1235 /* System boots at address 0x0 */
1236 /* gpnvm[1] = selects boot code */
1237 /* if gpnvm[1] == 0 */
1238 /* boot is via "SAMBA" (rom) */
1239 /* else */
1240 /* boot is via FLASH */
1241 /* Selection is via gpnvm[2] */
1242 /* endif */
1243 /* */
1244 /* NOTE: banks 0 & 1 switch places */
1245 /* if gpnvm[2] == 0 */
1246 /* Bank0 is the boot rom */
1247 /* else */
1248 /* Bank1 is the boot rom */
1249 /* endif */
1250 /* .bank[0] = { */
1251 {
1252 {
1253 .probed = 0,
1254 .pChip = NULL,
1255 .pBank = NULL,
1256 .bank_number = 0,
1257 .base_address = FLASH_BANK_BASE_N,
1258 .controller_address = 0x400e0A00,
1259 .flash_wait_states = 6, /* workaround silicon bug */
1260 .present = 1,
1261 .size_bytes = 128 * 1024,
1262 .nsectors = 8,
1263 .sector_size = 16384,
1264 .page_size = 256,
1265 },
1266
1267 /* .bank[1] = { */
1268 {
1269 .present = 0,
1270 .probed = 0,
1271 .bank_number = 1,
1272 },
1273 },
1274 },
1275
1276 {
1277 .chipid_cidr = 0x29490760,
1278 .name = "at91sam3n2b",
1279 .total_flash_size = 128 * 1024,
1280 .total_sram_size = 16 * 1024,
1281 .n_gpnvms = 3,
1282 .n_banks = 1,
1283
1284 /* System boots at address 0x0 */
1285 /* gpnvm[1] = selects boot code */
1286 /* if gpnvm[1] == 0 */
1287 /* boot is via "SAMBA" (rom) */
1288 /* else */
1289 /* boot is via FLASH */
1290 /* Selection is via gpnvm[2] */
1291 /* endif */
1292 /* */
1293 /* NOTE: banks 0 & 1 switch places */
1294 /* if gpnvm[2] == 0 */
1295 /* Bank0 is the boot rom */
1296 /* else */
1297 /* Bank1 is the boot rom */
1298 /* endif */
1299 /* .bank[0] = { */
1300 {
1301 {
1302 .probed = 0,
1303 .pChip = NULL,
1304 .pBank = NULL,
1305 .bank_number = 0,
1306 .base_address = FLASH_BANK_BASE_N,
1307 .controller_address = 0x400e0A00,
1308 .flash_wait_states = 6, /* workaround silicon bug */
1309 .present = 1,
1310 .size_bytes = 128 * 1024,
1311 .nsectors = 8,
1312 .sector_size = 16384,
1313 .page_size = 256,
1314 },
1315
1316 /* .bank[1] = { */
1317 {
1318 .present = 0,
1319 .probed = 0,
1320 .bank_number = 1,
1321 },
1322 },
1323 },
1324
1325 {
1326 .chipid_cidr = 0x29390760,
1327 .name = "at91sam3n2a",
1328 .total_flash_size = 128 * 1024,
1329 .total_sram_size = 16 * 1024,
1330 .n_gpnvms = 3,
1331 .n_banks = 1,
1332
1333 /* System boots at address 0x0 */
1334 /* gpnvm[1] = selects boot code */
1335 /* if gpnvm[1] == 0 */
1336 /* boot is via "SAMBA" (rom) */
1337 /* else */
1338 /* boot is via FLASH */
1339 /* Selection is via gpnvm[2] */
1340 /* endif */
1341 /* */
1342 /* NOTE: banks 0 & 1 switch places */
1343 /* if gpnvm[2] == 0 */
1344 /* Bank0 is the boot rom */
1345 /* else */
1346 /* Bank1 is the boot rom */
1347 /* endif */
1348 /* .bank[0] = { */
1349 {
1350 {
1351 .probed = 0,
1352 .pChip = NULL,
1353 .pBank = NULL,
1354 .bank_number = 0,
1355 .base_address = FLASH_BANK_BASE_N,
1356 .controller_address = 0x400e0A00,
1357 .flash_wait_states = 6, /* workaround silicon bug */
1358 .present = 1,
1359 .size_bytes = 128 * 1024,
1360 .nsectors = 8,
1361 .sector_size = 16384,
1362 .page_size = 256,
1363 },
1364
1365 /* .bank[1] = { */
1366 {
1367 .present = 0,
1368 .probed = 0,
1369 .bank_number = 1,
1370 },
1371 },
1372 },
1373
1374 {
1375 .chipid_cidr = 0x29580560,
1376 .name = "at91sam3n1c",
1377 .total_flash_size = 64 * 1024,
1378 .total_sram_size = 8 * 1024,
1379 .n_gpnvms = 3,
1380 .n_banks = 1,
1381
1382 /* System boots at address 0x0 */
1383 /* gpnvm[1] = selects boot code */
1384 /* if gpnvm[1] == 0 */
1385 /* boot is via "SAMBA" (rom) */
1386 /* else */
1387 /* boot is via FLASH */
1388 /* Selection is via gpnvm[2] */
1389 /* endif */
1390 /* */
1391 /* NOTE: banks 0 & 1 switch places */
1392 /* if gpnvm[2] == 0 */
1393 /* Bank0 is the boot rom */
1394 /* else */
1395 /* Bank1 is the boot rom */
1396 /* endif */
1397 /* .bank[0] = { */
1398 {
1399 {
1400 .probed = 0,
1401 .pChip = NULL,
1402 .pBank = NULL,
1403 .bank_number = 0,
1404 .base_address = FLASH_BANK_BASE_N,
1405 .controller_address = 0x400e0A00,
1406 .flash_wait_states = 6, /* workaround silicon bug */
1407 .present = 1,
1408 .size_bytes = 64 * 1024,
1409 .nsectors = 4,
1410 .sector_size = 16384,
1411 .page_size = 256,
1412 },
1413
1414 /* .bank[1] = { */
1415 {
1416 .present = 0,
1417 .probed = 0,
1418 .bank_number = 1,
1419 },
1420 },
1421 },
1422
1423 {
1424 .chipid_cidr = 0x29480560,
1425 .name = "at91sam3n1b",
1426 .total_flash_size = 64 * 1024,
1427 .total_sram_size = 8 * 1024,
1428 .n_gpnvms = 3,
1429 .n_banks = 1,
1430
1431 /* System boots at address 0x0 */
1432 /* gpnvm[1] = selects boot code */
1433 /* if gpnvm[1] == 0 */
1434 /* boot is via "SAMBA" (rom) */
1435 /* else */
1436 /* boot is via FLASH */
1437 /* Selection is via gpnvm[2] */
1438 /* endif */
1439 /* */
1440 /* NOTE: banks 0 & 1 switch places */
1441 /* if gpnvm[2] == 0 */
1442 /* Bank0 is the boot rom */
1443 /* else */
1444 /* Bank1 is the boot rom */
1445 /* endif */
1446 /* .bank[0] = { */
1447 {
1448 {
1449 .probed = 0,
1450 .pChip = NULL,
1451 .pBank = NULL,
1452 .bank_number = 0,
1453 .base_address = FLASH_BANK_BASE_N,
1454 .controller_address = 0x400e0A00,
1455 .flash_wait_states = 6, /* workaround silicon bug */
1456 .present = 1,
1457 .size_bytes = 64 * 1024,
1458 .nsectors = 4,
1459 .sector_size = 16384,
1460 .page_size = 256,
1461 },
1462
1463 /* .bank[1] = { */
1464 {
1465 .present = 0,
1466 .probed = 0,
1467 .bank_number = 1,
1468 },
1469 },
1470 },
1471
1472 {
1473 .chipid_cidr = 0x29380560,
1474 .name = "at91sam3n1a",
1475 .total_flash_size = 64 * 1024,
1476 .total_sram_size = 8 * 1024,
1477 .n_gpnvms = 3,
1478 .n_banks = 1,
1479
1480 /* System boots at address 0x0 */
1481 /* gpnvm[1] = selects boot code */
1482 /* if gpnvm[1] == 0 */
1483 /* boot is via "SAMBA" (rom) */
1484 /* else */
1485 /* boot is via FLASH */
1486 /* Selection is via gpnvm[2] */
1487 /* endif */
1488 /* */
1489 /* NOTE: banks 0 & 1 switch places */
1490 /* if gpnvm[2] == 0 */
1491 /* Bank0 is the boot rom */
1492 /* else */
1493 /* Bank1 is the boot rom */
1494 /* endif */
1495 /* .bank[0] = { */
1496 {
1497 {
1498 .probed = 0,
1499 .pChip = NULL,
1500 .pBank = NULL,
1501 .bank_number = 0,
1502 .base_address = FLASH_BANK_BASE_N,
1503 .controller_address = 0x400e0A00,
1504 .flash_wait_states = 6, /* workaround silicon bug */
1505 .present = 1,
1506 .size_bytes = 64 * 1024,
1507 .nsectors = 4,
1508 .sector_size = 16384,
1509 .page_size = 256,
1510 },
1511
1512 /* .bank[1] = { */
1513 {
1514 .present = 0,
1515 .probed = 0,
1516 .bank_number = 1,
1517 },
1518 },
1519 },
1520
1521 /* Start at91sam3a series*/
1522 /* System boots at address 0x0 */
1523 /* gpnvm[1] = selects boot code */
1524 /* if gpnvm[1] == 0 */
1525 /* boot is via "SAMBA" (rom) */
1526 /* else */
1527 /* boot is via FLASH */
1528 /* Selection is via gpnvm[2] */
1529 /* endif */
1530 /* */
1531 /* NOTE: banks 0 & 1 switch places */
1532 /* if gpnvm[2] == 0 */
1533 /* Bank0 is the boot rom */
1534 /* else */
1535 /* Bank1 is the boot rom */
1536 /* endif */
1537
1538 {
1539 .chipid_cidr = 0x283E0A60,
1540 .name = "at91sam3a8c",
1541 .total_flash_size = 512 * 1024,
1542 .total_sram_size = 96 * 1024,
1543 .n_gpnvms = 3,
1544 .n_banks = 2,
1545 {
1546 /* .bank[0] = { */
1547 {
1548 .probed = 0,
1549 .pChip = NULL,
1550 .pBank = NULL,
1551 .bank_number = 0,
1552 .base_address = FLASH_BANK0_BASE_AX,
1553 .controller_address = 0x400e0a00,
1554 .flash_wait_states = 6, /* workaround silicon bug */
1555 .present = 1,
1556 .size_bytes = 256 * 1024,
1557 .nsectors = 16,
1558 .sector_size = 16384,
1559 .page_size = 256,
1560 },
1561 /* .bank[1] = { */
1562 {
1563 .probed = 0,
1564 .pChip = NULL,
1565 .pBank = NULL,
1566 .bank_number = 1,
1567 .base_address = FLASH_BANK1_BASE_512K_AX,
1568 .controller_address = 0x400e0c00,
1569 .flash_wait_states = 6, /* workaround silicon bug */
1570 .present = 1,
1571 .size_bytes = 256 * 1024,
1572 .nsectors = 16,
1573 .sector_size = 16384,
1574 .page_size = 256,
1575
1576 },
1577 },
1578 },
1579 {
1580 .chipid_cidr = 0x283B0960,
1581 .name = "at91sam3a4c",
1582 .total_flash_size = 256 * 1024,
1583 .total_sram_size = 64 * 1024,
1584 .n_gpnvms = 3,
1585 .n_banks = 2,
1586 {
1587 /* .bank[0] = { */
1588 {
1589 .probed = 0,
1590 .pChip = NULL,
1591 .pBank = NULL,
1592 .bank_number = 0,
1593 .base_address = FLASH_BANK0_BASE_AX,
1594 .controller_address = 0x400e0a00,
1595 .flash_wait_states = 6, /* workaround silicon bug */
1596 .present = 1,
1597 .size_bytes = 128 * 1024,
1598 .nsectors = 8,
1599 .sector_size = 16384,
1600 .page_size = 256,
1601 },
1602 /* .bank[1] = { */
1603 {
1604 .probed = 0,
1605 .pChip = NULL,
1606 .pBank = NULL,
1607 .bank_number = 1,
1608 .base_address = FLASH_BANK1_BASE_256K_AX,
1609 .controller_address = 0x400e0c00,
1610 .flash_wait_states = 6, /* workaround silicon bug */
1611 .present = 1,
1612 .size_bytes = 128 * 1024,
1613 .nsectors = 8,
1614 .sector_size = 16384,
1615 .page_size = 256,
1616
1617 },
1618 },
1619 },
1620
1621 /* Start at91sam3x* series */
1622 /* System boots at address 0x0 */
1623 /* gpnvm[1] = selects boot code */
1624 /* if gpnvm[1] == 0 */
1625 /* boot is via "SAMBA" (rom) */
1626 /* else */
1627 /* boot is via FLASH */
1628 /* Selection is via gpnvm[2] */
1629 /* endif */
1630 /* */
1631 /* NOTE: banks 0 & 1 switch places */
1632 /* if gpnvm[2] == 0 */
1633 /* Bank0 is the boot rom */
1634 /* else */
1635 /* Bank1 is the boot rom */
1636 /* endif */
1637 /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
1638 {
1639 .chipid_cidr = 0x286E0A20,
1640 .name = "at91sam3x8h - ES",
1641 .total_flash_size = 512 * 1024,
1642 .total_sram_size = 96 * 1024,
1643 .n_gpnvms = 3,
1644 .n_banks = 2,
1645 {
1646 /* .bank[0] = { */
1647 {
1648 .probed = 0,
1649 .pChip = NULL,
1650 .pBank = NULL,
1651 .bank_number = 0,
1652 .base_address = FLASH_BANK0_BASE_AX,
1653 .controller_address = 0x400e0a00,
1654 .flash_wait_states = 6, /* workaround silicon bug */
1655 .present = 1,
1656 .size_bytes = 256 * 1024,
1657 .nsectors = 16,
1658 .sector_size = 16384,
1659 .page_size = 256,
1660 },
1661 /* .bank[1] = { */
1662 {
1663 .probed = 0,
1664 .pChip = NULL,
1665 .pBank = NULL,
1666 .bank_number = 1,
1667 .base_address = FLASH_BANK1_BASE_512K_AX,
1668 .controller_address = 0x400e0c00,
1669 .flash_wait_states = 6, /* workaround silicon bug */
1670 .present = 1,
1671 .size_bytes = 256 * 1024,
1672 .nsectors = 16,
1673 .sector_size = 16384,
1674 .page_size = 256,
1675
1676 },
1677 },
1678 },
1679 /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
1680 {
1681 .chipid_cidr = 0x286E0A60,
1682 .name = "at91sam3x8h",
1683 .total_flash_size = 512 * 1024,
1684 .total_sram_size = 96 * 1024,
1685 .n_gpnvms = 3,
1686 .n_banks = 2,
1687 {
1688 /* .bank[0] = { */
1689 {
1690 .probed = 0,
1691 .pChip = NULL,
1692 .pBank = NULL,
1693 .bank_number = 0,
1694 .base_address = FLASH_BANK0_BASE_AX,
1695 .controller_address = 0x400e0a00,
1696 .flash_wait_states = 6, /* workaround silicon bug */
1697 .present = 1,
1698 .size_bytes = 256 * 1024,
1699 .nsectors = 16,
1700 .sector_size = 16384,
1701 .page_size = 256,
1702 },
1703 /* .bank[1] = { */
1704 {
1705 .probed = 0,
1706 .pChip = NULL,
1707 .pBank = NULL,
1708 .bank_number = 1,
1709 .base_address = FLASH_BANK1_BASE_512K_AX,
1710 .controller_address = 0x400e0c00,
1711 .flash_wait_states = 6, /* workaround silicon bug */
1712 .present = 1,
1713 .size_bytes = 256 * 1024,
1714 .nsectors = 16,
1715 .sector_size = 16384,
1716 .page_size = 256,
1717
1718 },
1719 },
1720 },
1721 {
1722 .chipid_cidr = 0x285E0A60,
1723 .name = "at91sam3x8e",
1724 .total_flash_size = 512 * 1024,
1725 .total_sram_size = 96 * 1024,
1726 .n_gpnvms = 3,
1727 .n_banks = 2,
1728 {
1729 /* .bank[0] = { */
1730 {
1731 .probed = 0,
1732 .pChip = NULL,
1733 .pBank = NULL,
1734 .bank_number = 0,
1735 .base_address = FLASH_BANK0_BASE_AX,
1736 .controller_address = 0x400e0a00,
1737 .flash_wait_states = 6, /* workaround silicon bug */
1738 .present = 1,
1739 .size_bytes = 256 * 1024,
1740 .nsectors = 16,
1741 .sector_size = 16384,
1742 .page_size = 256,
1743 },
1744 /* .bank[1] = { */
1745 {
1746 .probed = 0,
1747 .pChip = NULL,
1748 .pBank = NULL,
1749 .bank_number = 1,
1750 .base_address = FLASH_BANK1_BASE_512K_AX,
1751 .controller_address = 0x400e0c00,
1752 .flash_wait_states = 6, /* workaround silicon bug */
1753 .present = 1,
1754 .size_bytes = 256 * 1024,
1755 .nsectors = 16,
1756 .sector_size = 16384,
1757 .page_size = 256,
1758
1759 },
1760 },
1761 },
1762 {
1763 .chipid_cidr = 0x284E0A60,
1764 .name = "at91sam3x8c",
1765 .total_flash_size = 512 * 1024,
1766 .total_sram_size = 96 * 1024,
1767 .n_gpnvms = 3,
1768 .n_banks = 2,
1769 {
1770 /* .bank[0] = { */
1771 {
1772 .probed = 0,
1773 .pChip = NULL,
1774 .pBank = NULL,
1775 .bank_number = 0,
1776 .base_address = FLASH_BANK0_BASE_AX,
1777 .controller_address = 0x400e0a00,
1778 .flash_wait_states = 6, /* workaround silicon bug */
1779 .present = 1,
1780 .size_bytes = 256 * 1024,
1781 .nsectors = 16,
1782 .sector_size = 16384,
1783 .page_size = 256,
1784 },
1785 /* .bank[1] = { */
1786 {
1787 .probed = 0,
1788 .pChip = NULL,
1789 .pBank = NULL,
1790 .bank_number = 1,
1791 .base_address = FLASH_BANK1_BASE_512K_AX ,
1792 .controller_address = 0x400e0c00,
1793 .flash_wait_states = 6, /* workaround silicon bug */
1794 .present = 1,
1795 .size_bytes = 256 * 1024,
1796 .nsectors = 16,
1797 .sector_size = 16384,
1798 .page_size = 256,
1799
1800 },
1801 },
1802 },
1803 {
1804 .chipid_cidr = 0x285B0960,
1805 .name = "at91sam3x4e",
1806 .total_flash_size = 256 * 1024,
1807 .total_sram_size = 64 * 1024,
1808 .n_gpnvms = 3,
1809 .n_banks = 2,
1810 {
1811 /* .bank[0] = { */
1812 {
1813 .probed = 0,
1814 .pChip = NULL,
1815 .pBank = NULL,
1816 .bank_number = 0,
1817 .base_address = FLASH_BANK0_BASE_AX,
1818 .controller_address = 0x400e0a00,
1819 .flash_wait_states = 6, /* workaround silicon bug */
1820 .present = 1,
1821 .size_bytes = 128 * 1024,
1822 .nsectors = 8,
1823 .sector_size = 16384,
1824 .page_size = 256,
1825 },
1826 /* .bank[1] = { */
1827 {
1828 .probed = 0,
1829 .pChip = NULL,
1830 .pBank = NULL,
1831 .bank_number = 1,
1832 .base_address = FLASH_BANK1_BASE_256K_AX,
1833 .controller_address = 0x400e0c00,
1834 .flash_wait_states = 6, /* workaround silicon bug */
1835 .present = 1,
1836 .size_bytes = 128 * 1024,
1837 .nsectors = 8,
1838 .sector_size = 16384,
1839 .page_size = 256,
1840
1841 },
1842 },
1843 },
1844 {
1845 .chipid_cidr = 0x284B0960,
1846 .name = "at91sam3x4c",
1847 .total_flash_size = 256 * 1024,
1848 .total_sram_size = 64 * 1024,
1849 .n_gpnvms = 3,
1850 .n_banks = 2,
1851 {
1852 /* .bank[0] = { */
1853 {
1854 .probed = 0,
1855 .pChip = NULL,
1856 .pBank = NULL,
1857 .bank_number = 0,
1858 .base_address = FLASH_BANK0_BASE_AX,
1859 .controller_address = 0x400e0a00,
1860 .flash_wait_states = 6, /* workaround silicon bug */
1861 .present = 1,
1862 .size_bytes = 128 * 1024,
1863 .nsectors = 8,
1864 .sector_size = 16384,
1865 .page_size = 256,
1866 },
1867 /* .bank[1] = { */
1868 {
1869 .probed = 0,
1870 .pChip = NULL,
1871 .pBank = NULL,
1872 .bank_number = 1,
1873 .base_address = FLASH_BANK1_BASE_256K_AX,
1874 .controller_address = 0x400e0c00,
1875 .flash_wait_states = 6, /* workaround silicon bug */
1876 .present = 1,
1877 .size_bytes = 128 * 1024,
1878 .nsectors = 8,
1879 .sector_size = 16384,
1880 .page_size = 256,
1881
1882 },
1883 },
1884 },
1885 /* terminate */
1886 {
1887 .chipid_cidr = 0,
1888 .name = NULL,
1889 }
1890 };
1891
1892 /* Globals above */
1893 /***********************************************************************
1894 **********************************************************************
1895 **********************************************************************
1896 **********************************************************************
1897 **********************************************************************
1898 **********************************************************************/
1899 /* *ATMEL* style code - from the SAM3 driver code */
1900
1901 /**
1902 * Get the current status of the EEFC and
1903 * the value of some status bits (LOCKE, PROGE).
1904 * @param pPrivate - info about the bank
1905 * @param v - result goes here
1906 */
1907 static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
1908 {
1909 int r;
1910 r = target_read_u32(pPrivate->pChip->target,
1911 pPrivate->controller_address + offset_EFC_FSR,
1912 v);
1913 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1914 (unsigned int)(*v),
1915 ((unsigned int)((*v >> 2) & 1)),
1916 ((unsigned int)((*v >> 1) & 1)),
1917 ((unsigned int)((*v >> 0) & 1)));
1918
1919 return r;
1920 }
1921
1922 /**
1923 * Get the result of the last executed command.
1924 * @param pPrivate - info about the bank
1925 * @param v - result goes here
1926 */
1927 static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
1928 {
1929 int r;
1930 uint32_t rv;
1931 r = target_read_u32(pPrivate->pChip->target,
1932 pPrivate->controller_address + offset_EFC_FRR,
1933 &rv);
1934 if (v)
1935 *v = rv;
1936 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
1937 return r;
1938 }
1939
1940 static int EFC_StartCommand(struct sam3_bank_private *pPrivate,
1941 unsigned command, unsigned argument)
1942 {
1943 uint32_t n, v;
1944 int r;
1945 int retry;
1946
1947 retry = 0;
1948 do_retry:
1949
1950 /* Check command & argument */
1951 switch (command) {
1952
1953 case AT91C_EFC_FCMD_WP:
1954 case AT91C_EFC_FCMD_WPL:
1955 case AT91C_EFC_FCMD_EWP:
1956 case AT91C_EFC_FCMD_EWPL:
1957 /* case AT91C_EFC_FCMD_EPL: */
1958 /* case AT91C_EFC_FCMD_EPA: */
1959 case AT91C_EFC_FCMD_SLB:
1960 case AT91C_EFC_FCMD_CLB:
1961 n = (pPrivate->size_bytes / pPrivate->page_size);
1962 if (argument >= n)
1963 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
1964 break;
1965
1966 case AT91C_EFC_FCMD_SFB:
1967 case AT91C_EFC_FCMD_CFB:
1968 if (argument >= pPrivate->pChip->details.n_gpnvms) {
1969 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1970 pPrivate->pChip->details.n_gpnvms);
1971 }
1972 break;
1973
1974 case AT91C_EFC_FCMD_GETD:
1975 case AT91C_EFC_FCMD_EA:
1976 case AT91C_EFC_FCMD_GLB:
1977 case AT91C_EFC_FCMD_GFB:
1978 case AT91C_EFC_FCMD_STUI:
1979 case AT91C_EFC_FCMD_SPUI:
1980 if (argument != 0)
1981 LOG_ERROR("Argument is meaningless for cmd: %d", command);
1982 break;
1983 default:
1984 LOG_ERROR("Unknown command %d", command);
1985 break;
1986 }
1987
1988 if (command == AT91C_EFC_FCMD_SPUI) {
1989 /* this is a very special situation. */
1990 /* Situation (1) - error/retry - see below */
1991 /* And we are being called recursively */
1992 /* Situation (2) - normal, finished reading unique id */
1993 } else {
1994 /* it should be "ready" */
1995 EFC_GetStatus(pPrivate, &v);
1996 if (v & 1) {
1997 /* then it is ready */
1998 /* we go on */
1999 } else {
2000 if (retry) {
2001 /* we have done this before */
2002 /* the controller is not responding. */
2003 LOG_ERROR("flash controller(%d) is not ready! Error",
2004 pPrivate->bank_number);
2005 return ERROR_FAIL;
2006 } else {
2007 retry++;
2008 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
2009 pPrivate->bank_number);
2010 /* we do that by issuing the *STOP* command */
2011 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
2012 /* above is recursive, and further recursion is blocked by */
2013 /* if (command == AT91C_EFC_FCMD_SPUI) above */
2014 goto do_retry;
2015 }
2016 }
2017 }
2018
2019 v = (0x5A << 24) | (argument << 8) | command;
2020 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
2021 r = target_write_u32(pPrivate->pBank->target,
2022 pPrivate->controller_address + offset_EFC_FCR, v);
2023 if (r != ERROR_OK)
2024 LOG_DEBUG("Error Write failed");
2025 return r;
2026 }
2027
2028 /**
2029 * Performs the given command and wait until its completion (or an error).
2030 * @param pPrivate - info about the bank
2031 * @param command - Command to perform.
2032 * @param argument - Optional command argument.
2033 * @param status - put command status bits here
2034 */
2035 static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
2036 unsigned command,
2037 unsigned argument,
2038 uint32_t *status)
2039 {
2040
2041 int r;
2042 uint32_t v;
2043 long long ms_now, ms_end;
2044
2045 /* default */
2046 if (status)
2047 *status = 0;
2048
2049 r = EFC_StartCommand(pPrivate, command, argument);
2050 if (r != ERROR_OK)
2051 return r;
2052
2053 ms_end = 500 + timeval_ms();
2054
2055 do {
2056 r = EFC_GetStatus(pPrivate, &v);
2057 if (r != ERROR_OK)
2058 return r;
2059 ms_now = timeval_ms();
2060 if (ms_now > ms_end) {
2061 /* error */
2062 LOG_ERROR("Command timeout");
2063 return ERROR_FAIL;
2064 }
2065 } while ((v & 1) == 0);
2066
2067 /* error bits.. */
2068 if (status)
2069 *status = (v & 0x6);
2070 return ERROR_OK;
2071
2072 }
2073
2074 /**
2075 * Read the unique ID.
2076 * @param pPrivate - info about the bank
2077 * The unique ID is stored in the 'pPrivate' structure.
2078 */
2079 static int FLASHD_ReadUniqueID(struct sam3_bank_private *pPrivate)
2080 {
2081 int r;
2082 uint32_t v;
2083 int x;
2084 /* assume 0 */
2085 pPrivate->pChip->cfg.unique_id[0] = 0;
2086 pPrivate->pChip->cfg.unique_id[1] = 0;
2087 pPrivate->pChip->cfg.unique_id[2] = 0;
2088 pPrivate->pChip->cfg.unique_id[3] = 0;
2089
2090 LOG_DEBUG("Begin");
2091 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
2092 if (r < 0)
2093 return r;
2094
2095 for (x = 0; x < 4; x++) {
2096 r = target_read_u32(pPrivate->pChip->target,
2097 pPrivate->pBank->base + (x * 4),
2098 &v);
2099 if (r < 0)
2100 return r;
2101 pPrivate->pChip->cfg.unique_id[x] = v;
2102 }
2103
2104 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
2105 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
2106 r,
2107 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
2108 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
2109 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
2110 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
2111 return r;
2112
2113 }
2114
2115 /**
2116 * Erases the entire flash.
2117 * @param pPrivate - the info about the bank.
2118 */
2119 static int FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
2120 {
2121 LOG_DEBUG("Here");
2122 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
2123 }
2124
2125 /**
2126 * Gets current GPNVM state.
2127 * @param pPrivate - info about the bank.
2128 * @param gpnvm - GPNVM bit index.
2129 * @param puthere - result stored here.
2130 */
2131 /* ------------------------------------------------------------------------------ */
2132 static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
2133 {
2134 uint32_t v;
2135 int r;
2136
2137 LOG_DEBUG("Here");
2138 if (pPrivate->bank_number != 0) {
2139 LOG_ERROR("GPNVM only works with Bank0");
2140 return ERROR_FAIL;
2141 }
2142
2143 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2144 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2145 gpnvm, pPrivate->pChip->details.n_gpnvms);
2146 return ERROR_FAIL;
2147 }
2148
2149 /* Get GPNVMs status */
2150 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
2151 if (r != ERROR_OK) {
2152 LOG_ERROR("Failed");
2153 return r;
2154 }
2155
2156 r = EFC_GetResult(pPrivate, &v);
2157
2158 if (puthere) {
2159 /* Check if GPNVM is set */
2160 /* get the bit and make it a 0/1 */
2161 *puthere = (v >> gpnvm) & 1;
2162 }
2163
2164 return r;
2165 }
2166
2167 /**
2168 * Clears the selected GPNVM bit.
2169 * @param pPrivate info about the bank
2170 * @param gpnvm GPNVM index.
2171 * @returns 0 if successful; otherwise returns an error code.
2172 */
2173 static int FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
2174 {
2175 int r;
2176 unsigned v;
2177
2178 LOG_DEBUG("Here");
2179 if (pPrivate->bank_number != 0) {
2180 LOG_ERROR("GPNVM only works with Bank0");
2181 return ERROR_FAIL;
2182 }
2183
2184 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2185 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2186 gpnvm, pPrivate->pChip->details.n_gpnvms);
2187 return ERROR_FAIL;
2188 }
2189
2190 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
2191 if (r != ERROR_OK) {
2192 LOG_DEBUG("Failed: %d", r);
2193 return r;
2194 }
2195 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
2196 LOG_DEBUG("End: %d", r);
2197 return r;
2198 }
2199
2200 /**
2201 * Sets the selected GPNVM bit.
2202 * @param pPrivate info about the bank
2203 * @param gpnvm GPNVM index.
2204 */
2205 static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
2206 {
2207 int r;
2208 unsigned v;
2209
2210 if (pPrivate->bank_number != 0) {
2211 LOG_ERROR("GPNVM only works with Bank0");
2212 return ERROR_FAIL;
2213 }
2214
2215 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2216 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2217 gpnvm, pPrivate->pChip->details.n_gpnvms);
2218 return ERROR_FAIL;
2219 }
2220
2221 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
2222 if (r != ERROR_OK)
2223 return r;
2224 if (v) {
2225 /* already set */
2226 r = ERROR_OK;
2227 } else {
2228 /* set it */
2229 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
2230 }
2231 return r;
2232 }
2233
2234 /**
2235 * Returns a bit field (at most 64) of locked regions within a page.
2236 * @param pPrivate info about the bank
2237 * @param v where to store locked bits
2238 */
2239 static int FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
2240 {
2241 int r;
2242 LOG_DEBUG("Here");
2243 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
2244 if (r == ERROR_OK)
2245 r = EFC_GetResult(pPrivate, v);
2246 LOG_DEBUG("End: %d", r);
2247 return r;
2248 }
2249
2250 /**
2251 * Unlocks all the regions in the given address range.
2252 * @param pPrivate info about the bank
2253 * @param start_sector first sector to unlock
2254 * @param end_sector last (inclusive) to unlock
2255 */
2256
2257 static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
2258 unsigned start_sector,
2259 unsigned end_sector)
2260 {
2261 int r;
2262 uint32_t status;
2263 uint32_t pg;
2264 uint32_t pages_per_sector;
2265
2266 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2267
2268 /* Unlock all pages */
2269 while (start_sector <= end_sector) {
2270 pg = start_sector * pages_per_sector;
2271
2272 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
2273 if (r != ERROR_OK)
2274 return r;
2275 start_sector++;
2276 }
2277
2278 return ERROR_OK;
2279 }
2280
2281 /**
2282 * Locks regions
2283 * @param pPrivate - info about the bank
2284 * @param start_sector - first sector to lock
2285 * @param end_sector - last sector (inclusive) to lock
2286 */
2287 static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
2288 unsigned start_sector,
2289 unsigned end_sector)
2290 {
2291 uint32_t status;
2292 uint32_t pg;
2293 uint32_t pages_per_sector;
2294 int r;
2295
2296 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2297
2298 /* Lock all pages */
2299 while (start_sector <= end_sector) {
2300 pg = start_sector * pages_per_sector;
2301
2302 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
2303 if (r != ERROR_OK)
2304 return r;
2305 start_sector++;
2306 }
2307 return ERROR_OK;
2308 }
2309
2310 /****** END SAM3 CODE ********/
2311
2312 /* begin helpful debug code */
2313 /* print the fieldname, the field value, in dec & hex, and return field value */
2314 static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip,
2315 const char *regname,
2316 uint32_t value,
2317 unsigned shift,
2318 unsigned width)
2319 {
2320 uint32_t v;
2321 int hwidth, dwidth;
2322
2323
2324 /* extract the field */
2325 v = value >> shift;
2326 v = v & ((1 << width)-1);
2327 if (width <= 16) {
2328 hwidth = 4;
2329 dwidth = 5;
2330 } else {
2331 hwidth = 8;
2332 dwidth = 12;
2333 }
2334
2335 /* show the basics */
2336 LOG_USER_N("\t%*s: %*d [0x%0*x] ",
2337 REG_NAME_WIDTH, regname,
2338 dwidth, v,
2339 hwidth, v);
2340 return v;
2341 }
2342
2343 static const char _unknown[] = "unknown";
2344 static const char *const eproc_names[] = {
2345 _unknown, /* 0 */
2346 "arm946es", /* 1 */
2347 "arm7tdmi", /* 2 */
2348 "cortex-m3", /* 3 */
2349 "arm920t", /* 4 */
2350 "arm926ejs", /* 5 */
2351 _unknown, /* 6 */
2352 _unknown, /* 7 */
2353 _unknown, /* 8 */
2354 _unknown, /* 9 */
2355 _unknown, /* 10 */
2356 _unknown, /* 11 */
2357 _unknown, /* 12 */
2358 _unknown, /* 13 */
2359 _unknown, /* 14 */
2360 _unknown, /* 15 */
2361 };
2362
2363 #define nvpsize2 nvpsize /* these two tables are identical */
2364 static const char *const nvpsize[] = {
2365 "none", /* 0 */
2366 "8K bytes", /* 1 */
2367 "16K bytes", /* 2 */
2368 "32K bytes", /* 3 */
2369 _unknown, /* 4 */
2370 "64K bytes", /* 5 */
2371 _unknown, /* 6 */
2372 "128K bytes", /* 7 */
2373 _unknown, /* 8 */
2374 "256K bytes", /* 9 */
2375 "512K bytes", /* 10 */
2376 _unknown, /* 11 */
2377 "1024K bytes", /* 12 */
2378 _unknown, /* 13 */
2379 "2048K bytes", /* 14 */
2380 _unknown, /* 15 */
2381 };
2382
2383 static const char *const sramsize[] = {
2384 "48K Bytes", /* 0 */
2385 "1K Bytes", /* 1 */
2386 "2K Bytes", /* 2 */
2387 "6K Bytes", /* 3 */
2388 "112K Bytes", /* 4 */
2389 "4K Bytes", /* 5 */
2390 "80K Bytes", /* 6 */
2391 "160K Bytes", /* 7 */
2392 "8K Bytes", /* 8 */
2393 "16K Bytes", /* 9 */
2394 "32K Bytes", /* 10 */
2395 "64K Bytes", /* 11 */
2396 "128K Bytes", /* 12 */
2397 "256K Bytes", /* 13 */
2398 "96K Bytes", /* 14 */
2399 "512K Bytes", /* 15 */
2400
2401 };
2402
2403 static const struct archnames { unsigned value; const char *name; } archnames[] = {
2404 { 0x19, "AT91SAM9xx Series" },
2405 { 0x29, "AT91SAM9XExx Series" },
2406 { 0x34, "AT91x34 Series" },
2407 { 0x37, "CAP7 Series" },
2408 { 0x39, "CAP9 Series" },
2409 { 0x3B, "CAP11 Series" },
2410 { 0x40, "AT91x40 Series" },
2411 { 0x42, "AT91x42 Series" },
2412 { 0x55, "AT91x55 Series" },
2413 { 0x60, "AT91SAM7Axx Series" },
2414 { 0x61, "AT91SAM7AQxx Series" },
2415 { 0x63, "AT91x63 Series" },
2416 { 0x70, "AT91SAM7Sxx Series" },
2417 { 0x71, "AT91SAM7XCxx Series" },
2418 { 0x72, "AT91SAM7SExx Series" },
2419 { 0x73, "AT91SAM7Lxx Series" },
2420 { 0x75, "AT91SAM7Xxx Series" },
2421 { 0x76, "AT91SAM7SLxx Series" },
2422 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2423 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2424 { 0x83, "ATSAM3AxC Series (100-pin version)" },
2425 { 0x84, "ATSAM3XxC Series (100-pin version)" },
2426 { 0x85, "ATSAM3XxE Series (144-pin version)" },
2427 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
2428 { 0x88, "ATSAM3SxA Series (48-pin version)" },
2429 { 0x89, "ATSAM3SxB Series (64-pin version)" },
2430 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
2431 { 0x92, "AT91x92 Series" },
2432 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2433 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2434 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2435 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2436 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2437 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2438 { 0xA5, "ATSAM5A" },
2439 { 0xF0, "AT75Cxx Series" },
2440 { -1, NULL },
2441 };
2442
2443 static const char *const nvptype[] = {
2444 "rom", /* 0 */
2445 "romless or onchip flash", /* 1 */
2446 "embedded flash memory",/* 2 */
2447 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2448 "sram emulating flash", /* 4 */
2449 _unknown, /* 5 */
2450 _unknown, /* 6 */
2451 _unknown, /* 7 */
2452 };
2453
2454 static const char *_yes_or_no(uint32_t v)
2455 {
2456 if (v)
2457 return "YES";
2458 else
2459 return "NO";
2460 }
2461
2462 static const char *const _rc_freq[] = {
2463 "4 MHz", "8 MHz", "12 MHz", "reserved"
2464 };
2465
2466 static void sam3_explain_ckgr_mor(struct sam3_chip *pChip)
2467 {
2468 uint32_t v;
2469 uint32_t rcen;
2470
2471 v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
2472 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2473 v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
2474 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2475 rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
2476 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2477 v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
2478 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2479
2480 pChip->cfg.rc_freq = 0;
2481 if (rcen) {
2482 switch (v) {
2483 default:
2484 pChip->cfg.rc_freq = 0;
2485 break;
2486 case 0:
2487 pChip->cfg.rc_freq = 4 * 1000 * 1000;
2488 break;
2489 case 1:
2490 pChip->cfg.rc_freq = 8 * 1000 * 1000;
2491 break;
2492 case 2:
2493 pChip->cfg.rc_freq = 12 * 1000 * 1000;
2494 break;
2495 }
2496 }
2497
2498 v = sam3_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
2499 LOG_USER("(startup clks, time= %f uSecs)",
2500 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
2501 v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
2502 LOG_USER("(mainosc source: %s)",
2503 v ? "external xtal" : "internal RC");
2504
2505 v = sam3_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
2506 LOG_USER("(clock failure enabled: %s)",
2507 _yes_or_no(v));
2508 }
2509
2510 static void sam3_explain_chipid_cidr(struct sam3_chip *pChip)
2511 {
2512 int x;
2513 uint32_t v;
2514 const char *cp;
2515
2516 sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
2517 LOG_USER_N("\n");
2518
2519 v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
2520 LOG_USER("%s", eproc_names[v]);
2521
2522 v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
2523 LOG_USER("%s", nvpsize[v]);
2524
2525 v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
2526 LOG_USER("%s", nvpsize2[v]);
2527
2528 v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
2529 LOG_USER("%s", sramsize[v]);
2530
2531 v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
2532 cp = _unknown;
2533 for (x = 0; archnames[x].name; x++) {
2534 if (v == archnames[x].value) {
2535 cp = archnames[x].name;
2536 break;
2537 }
2538 }
2539
2540 LOG_USER("%s", cp);
2541
2542 v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
2543 LOG_USER("%s", nvptype[v]);
2544
2545 v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
2546 LOG_USER("(exists: %s)", _yes_or_no(v));
2547 }
2548
2549 static void sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
2550 {
2551 uint32_t v;
2552
2553 v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
2554 LOG_USER("(main ready: %s)", _yes_or_no(v));
2555
2556 v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
2557
2558 v = (v * pChip->cfg.slow_freq) / 16;
2559 pChip->cfg.mainosc_freq = v;
2560
2561 LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
2562 _tomhz(v),
2563 pChip->cfg.slow_freq / 1000,
2564 pChip->cfg.slow_freq % 1000);
2565 }
2566
2567 static void sam3_explain_ckgr_plla(struct sam3_chip *pChip)
2568 {
2569 uint32_t mula, diva;
2570
2571 diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
2572 LOG_USER_N("\n");
2573 mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
2574 LOG_USER_N("\n");
2575 pChip->cfg.plla_freq = 0;
2576 if (mula == 0)
2577 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2578 else if (diva == 0)
2579 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2580 else if (diva >= 1) {
2581 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
2582 LOG_USER("\tPLLA Freq: %3.03f MHz",
2583 _tomhz(pChip->cfg.plla_freq));
2584 }
2585 }
2586
2587 static void sam3_explain_mckr(struct sam3_chip *pChip)
2588 {
2589 uint32_t css, pres, fin = 0;
2590 int pdiv = 0;
2591 const char *cp = NULL;
2592
2593 css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
2594 switch (css & 3) {
2595 case 0:
2596 fin = pChip->cfg.slow_freq;
2597 cp = "slowclk";
2598 break;
2599 case 1:
2600 fin = pChip->cfg.mainosc_freq;
2601 cp = "mainosc";
2602 break;
2603 case 2:
2604 fin = pChip->cfg.plla_freq;
2605 cp = "plla";
2606 break;
2607 case 3:
2608 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
2609 fin = 480 * 1000 * 1000;
2610 cp = "upll";
2611 } else {
2612 fin = 0;
2613 cp = "upll (*ERROR* UPLL is disabled)";
2614 }
2615 break;
2616 default:
2617 assert(0);
2618 break;
2619 }
2620
2621 LOG_USER("%s (%3.03f Mhz)",
2622 cp,
2623 _tomhz(fin));
2624 pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
2625 switch (pres & 0x07) {
2626 case 0:
2627 pdiv = 1;
2628 cp = "selected clock";
2629 break;
2630 case 1:
2631 pdiv = 2;
2632 cp = "clock/2";
2633 break;
2634 case 2:
2635 pdiv = 4;
2636 cp = "clock/4";
2637 break;
2638 case 3:
2639 pdiv = 8;
2640 cp = "clock/8";
2641 break;
2642 case 4:
2643 pdiv = 16;
2644 cp = "clock/16";
2645 break;
2646 case 5:
2647 pdiv = 32;
2648 cp = "clock/32";
2649 break;
2650 case 6:
2651 pdiv = 64;
2652 cp = "clock/64";
2653 break;
2654 case 7:
2655 pdiv = 6;
2656 cp = "clock/6";
2657 break;
2658 default:
2659 assert(0);
2660 break;
2661 }
2662 LOG_USER("(%s)", cp);
2663 fin = fin / pdiv;
2664 /* sam3 has a *SINGLE* clock - */
2665 /* other at91 series parts have divisors for these. */
2666 pChip->cfg.cpu_freq = fin;
2667 pChip->cfg.mclk_freq = fin;
2668 pChip->cfg.fclk_freq = fin;
2669 LOG_USER("\t\tResult CPU Freq: %3.03f",
2670 _tomhz(fin));
2671 }
2672
2673 #if 0
2674 static struct sam3_chip *target2sam3(struct target *pTarget)
2675 {
2676 struct sam3_chip *pChip;
2677
2678 if (pTarget == NULL)
2679 return NULL;
2680
2681 pChip = all_sam3_chips;
2682 while (pChip) {
2683 if (pChip->target == pTarget)
2684 break; /* return below */
2685 else
2686 pChip = pChip->next;
2687 }
2688 return pChip;
2689 }
2690 #endif
2691
2692 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
2693 {
2694 /* this function exists to help */
2695 /* keep funky offsetof() errors */
2696 /* and casting from causing bugs */
2697
2698 /* By using prototypes - we can detect what would */
2699 /* be casting errors. */
2700
2701 return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
2702 }
2703
2704
2705 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2706 struct sam3_cfg, \
2707 NAME), # NAME, FUNC }
2708 static const struct sam3_reg_list sam3_all_regs[] = {
2709 SAM3_ENTRY(CKGR_MOR, sam3_explain_ckgr_mor),
2710 SAM3_ENTRY(CKGR_MCFR, sam3_explain_ckgr_mcfr),
2711 SAM3_ENTRY(CKGR_PLLAR, sam3_explain_ckgr_plla),
2712 SAM3_ENTRY(CKGR_UCKR, NULL),
2713 SAM3_ENTRY(PMC_FSMR, NULL),
2714 SAM3_ENTRY(PMC_FSPR, NULL),
2715 SAM3_ENTRY(PMC_IMR, NULL),
2716 SAM3_ENTRY(PMC_MCKR, sam3_explain_mckr),
2717 SAM3_ENTRY(PMC_PCK0, NULL),
2718 SAM3_ENTRY(PMC_PCK1, NULL),
2719 SAM3_ENTRY(PMC_PCK2, NULL),
2720 SAM3_ENTRY(PMC_PCSR, NULL),
2721 SAM3_ENTRY(PMC_SCSR, NULL),
2722 SAM3_ENTRY(PMC_SR, NULL),
2723 SAM3_ENTRY(CHIPID_CIDR, sam3_explain_chipid_cidr),
2724 SAM3_ENTRY(CHIPID_CIDR2, sam3_explain_chipid_cidr),
2725 SAM3_ENTRY(CHIPID_EXID, NULL),
2726 SAM3_ENTRY(CHIPID_EXID2, NULL),
2727 /* TERMINATE THE LIST */
2728 { .name = NULL }
2729 };
2730 #undef SAM3_ENTRY
2731
2732 static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank)
2733 {
2734 return (struct sam3_bank_private *)(bank->driver_priv);
2735 }
2736
2737 /**
2738 * Given a pointer to where it goes in the structure,
2739 * determine the register name, address from the all registers table.
2740 */
2741 static const struct sam3_reg_list *sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
2742 {
2743 const struct sam3_reg_list *pReg;
2744
2745 pReg = &(sam3_all_regs[0]);
2746 while (pReg->name) {
2747 uint32_t *pPossible;
2748
2749 /* calculate where this one go.. */
2750 /* it is "possibly" this register. */
2751
2752 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
2753
2754 /* well? Is it this register */
2755 if (pPossible == goes_here) {
2756 /* Jump for joy! */
2757 return pReg;
2758 }
2759
2760 /* next... */
2761 pReg++;
2762 }
2763 /* This is *TOTAL*PANIC* - we are totally screwed. */
2764 LOG_ERROR("INVALID SAM3 REGISTER");
2765 return NULL;
2766 }
2767
2768 static int sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
2769 {
2770 const struct sam3_reg_list *pReg;
2771 int r;
2772
2773 pReg = sam3_GetReg(pChip, goes_here);
2774 if (!pReg)
2775 return ERROR_FAIL;
2776
2777 r = target_read_u32(pChip->target, pReg->address, goes_here);
2778 if (r != ERROR_OK) {
2779 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2780 pReg->name, (unsigned)(pReg->address), r);
2781 }
2782 return r;
2783 }
2784
2785 static int sam3_ReadAllRegs(struct sam3_chip *pChip)
2786 {
2787 int r;
2788 const struct sam3_reg_list *pReg;
2789
2790 pReg = &(sam3_all_regs[0]);
2791 while (pReg->name) {
2792 r = sam3_ReadThisReg(pChip,
2793 sam3_get_reg_ptr(&(pChip->cfg), pReg));
2794 if (r != ERROR_OK) {
2795 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Error: %d",
2796 pReg->name, ((unsigned)(pReg->address)), r);
2797 return r;
2798 }
2799 pReg++;
2800 }
2801
2802 /* Chip identification register
2803 *
2804 * Unfortunately, the chip identification register is not at
2805 * a constant address across all of the SAM3 series'. As a
2806 * consequence, a simple heuristic is used to find where it's
2807 * at...
2808 *
2809 * If the contents at the first address is zero, then we know
2810 * that the second address is where the chip id register is.
2811 * We can deduce this because for those SAM's that have the
2812 * chip id @ 0x400e0940, the first address, 0x400e0740, is
2813 * located in the memory map of the Power Management Controller
2814 * (PMC). Furthermore, the address is not used by the PMC.
2815 * So when read, the memory controller returns zero.*/
2816 if (pChip->cfg.CHIPID_CIDR == 0) {
2817 /*Put the correct CIDR and EXID values in the pChip structure */
2818 pChip->cfg.CHIPID_CIDR = pChip->cfg.CHIPID_CIDR2;
2819 pChip->cfg.CHIPID_EXID = pChip->cfg.CHIPID_EXID2;
2820 }
2821 return ERROR_OK;
2822 }
2823
2824 static int sam3_GetInfo(struct sam3_chip *pChip)
2825 {
2826 const struct sam3_reg_list *pReg;
2827 uint32_t regval;
2828
2829 pReg = &(sam3_all_regs[0]);
2830 while (pReg->name) {
2831 /* display all regs */
2832 LOG_DEBUG("Start: %s", pReg->name);
2833 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
2834 LOG_USER("%*s: [0x%08x] -> 0x%08x",
2835 REG_NAME_WIDTH,
2836 pReg->name,
2837 pReg->address,
2838 regval);
2839 if (pReg->explain_func)
2840 (*(pReg->explain_func))(pChip);
2841 LOG_DEBUG("End: %s", pReg->name);
2842 pReg++;
2843 }
2844 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
2845 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
2846 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
2847 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
2848 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
2849
2850 LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
2851 pChip->cfg.unique_id[0],
2852 pChip->cfg.unique_id[1],
2853 pChip->cfg.unique_id[2],
2854 pChip->cfg.unique_id[3]);
2855
2856 return ERROR_OK;
2857 }
2858
2859 static int sam3_erase_check(struct flash_bank *bank)
2860 {
2861 int x;
2862
2863 LOG_DEBUG("Here");
2864 if (bank->target->state != TARGET_HALTED) {
2865 LOG_ERROR("Target not halted");
2866 return ERROR_TARGET_NOT_HALTED;
2867 }
2868 if (0 == bank->num_sectors) {
2869 LOG_ERROR("Target: not supported/not probed");
2870 return ERROR_FAIL;
2871 }
2872
2873 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
2874 for (x = 0; x < bank->num_sectors; x++)
2875 bank->sectors[x].is_erased = 1;
2876
2877 LOG_DEBUG("Done");
2878 return ERROR_OK;
2879 }
2880
2881 static int sam3_protect_check(struct flash_bank *bank)
2882 {
2883 int r;
2884 uint32_t v = 0;
2885 unsigned x;
2886 struct sam3_bank_private *pPrivate;
2887
2888 LOG_DEBUG("Begin");
2889 if (bank->target->state != TARGET_HALTED) {
2890 LOG_ERROR("Target not halted");
2891 return ERROR_TARGET_NOT_HALTED;
2892 }
2893
2894 pPrivate = get_sam3_bank_private(bank);
2895 if (!pPrivate) {
2896 LOG_ERROR("no private for this bank?");
2897 return ERROR_FAIL;
2898 }
2899 if (!(pPrivate->probed))
2900 return ERROR_FLASH_BANK_NOT_PROBED;
2901
2902 r = FLASHD_GetLockBits(pPrivate, &v);
2903 if (r != ERROR_OK) {
2904 LOG_DEBUG("Failed: %d", r);
2905 return r;
2906 }
2907
2908 for (x = 0; x < pPrivate->nsectors; x++)
2909 bank->sectors[x].is_protected = (!!(v & (1 << x)));
2910 LOG_DEBUG("Done");
2911 return ERROR_OK;
2912 }
2913
2914 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
2915 {
2916 struct sam3_chip *pChip;
2917
2918 pChip = all_sam3_chips;
2919
2920 /* is this an existing chip? */
2921 while (pChip) {
2922 if (pChip->target == bank->target)
2923 break;
2924 pChip = pChip->next;
2925 }
2926
2927 if (!pChip) {
2928 /* this is a *NEW* chip */
2929 pChip = calloc(1, sizeof(struct sam3_chip));
2930 if (!pChip) {
2931 LOG_ERROR("NO RAM!");
2932 return ERROR_FAIL;
2933 }
2934 pChip->target = bank->target;
2935 /* insert at head */
2936 pChip->next = all_sam3_chips;
2937 all_sam3_chips = pChip;
2938 pChip->target = bank->target;
2939 /* assumption is this runs at 32khz */
2940 pChip->cfg.slow_freq = 32768;
2941 pChip->probed = 0;
2942 }
2943
2944 switch (bank->base) {
2945 default:
2946 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
2947 "[at91sam3u series] or 0x%08x [at91sam3s series] or "
2948 "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
2949 ((unsigned int)(bank->base)),
2950 ((unsigned int)(FLASH_BANK0_BASE_U)),
2951 ((unsigned int)(FLASH_BANK1_BASE_U)),
2952 ((unsigned int)(FLASH_BANK_BASE_S)),
2953 ((unsigned int)(FLASH_BANK_BASE_N)),
2954 ((unsigned int)(FLASH_BANK0_BASE_AX)),
2955 ((unsigned int)(FLASH_BANK1_BASE_256K_AX)),
2956 ((unsigned int)(FLASH_BANK1_BASE_512K_AX)));
2957 return ERROR_FAIL;
2958 break;
2959
2960 /* at91sam3s and at91sam3n series only has bank 0*/
2961 /* at91sam3u and at91sam3ax series has the same address for bank 0*/
2962 case FLASH_BANK_BASE_S:
2963 case FLASH_BANK0_BASE_U:
2964 bank->driver_priv = &(pChip->details.bank[0]);
2965 bank->bank_number = 0;
2966 pChip->details.bank[0].pChip = pChip;
2967 pChip->details.bank[0].pBank = bank;
2968 break;
2969
2970 /* Bank 1 of at91sam3u or at91sam3ax series */
2971 case FLASH_BANK1_BASE_U:
2972 case FLASH_BANK1_BASE_256K_AX:
2973 case FLASH_BANK1_BASE_512K_AX:
2974 bank->driver_priv = &(pChip->details.bank[1]);
2975 bank->bank_number = 1;
2976 pChip->details.bank[1].pChip = pChip;
2977 pChip->details.bank[1].pBank = bank;
2978 break;
2979 }
2980
2981 /* we initialize after probing. */
2982 return ERROR_OK;
2983 }
2984
2985 static int sam3_GetDetails(struct sam3_bank_private *pPrivate)
2986 {
2987 const struct sam3_chip_details *pDetails;
2988 struct sam3_chip *pChip;
2989 struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
2990 unsigned x;
2991
2992 LOG_DEBUG("Begin");
2993 pDetails = all_sam3_details;
2994 while (pDetails->name) {
2995 /* Compare cidr without version bits */
2996 if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2997 break;
2998 else
2999 pDetails++;
3000 }
3001 if (pDetails->name == NULL) {
3002 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
3003 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
3004 /* Help the victim, print details about the chip */
3005 LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
3006 pPrivate->pChip->cfg.CHIPID_CIDR);
3007 sam3_explain_chipid_cidr(pPrivate->pChip);
3008 return ERROR_FAIL;
3009 }
3010
3011 /* DANGER: THERE ARE DRAGONS HERE */
3012
3013 /* get our pChip - it is going */
3014 /* to be over-written shortly */
3015 pChip = pPrivate->pChip;
3016
3017 /* Note that, in reality: */
3018 /* */
3019 /* pPrivate = &(pChip->details.bank[0]) */
3020 /* or pPrivate = &(pChip->details.bank[1]) */
3021 /* */
3022
3023 /* save the "bank" pointers */
3024 for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++)
3025 saved_banks[x] = pChip->details.bank[x].pBank;
3026
3027 /* Overwrite the "details" structure. */
3028 memcpy(&(pPrivate->pChip->details),
3029 pDetails,
3030 sizeof(pPrivate->pChip->details));
3031
3032 /* now fix the ghosted pointers */
3033 for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
3034 pChip->details.bank[x].pChip = pChip;
3035 pChip->details.bank[x].pBank = saved_banks[x];
3036 }
3037
3038 /* update the *BANK*SIZE* */
3039
3040 LOG_DEBUG("End");
3041 return ERROR_OK;
3042 }
3043
3044 static int _sam3_probe(struct flash_bank *bank, int noise)
3045 {
3046 unsigned x;
3047 int r;
3048 struct sam3_bank_private *pPrivate;
3049
3050
3051 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
3052 if (bank->target->state != TARGET_HALTED) {
3053 LOG_ERROR("Target not halted");
3054 return ERROR_TARGET_NOT_HALTED;
3055 }
3056
3057 pPrivate = get_sam3_bank_private(bank);
3058 if (!pPrivate) {
3059 LOG_ERROR("Invalid/unknown bank number");
3060 return ERROR_FAIL;
3061 }
3062
3063 r = sam3_ReadAllRegs(pPrivate->pChip);
3064 if (r != ERROR_OK)
3065 return r;
3066
3067 LOG_DEBUG("Here");
3068 if (pPrivate->pChip->probed)
3069 r = sam3_GetInfo(pPrivate->pChip);
3070 else
3071 r = sam3_GetDetails(pPrivate);
3072 if (r != ERROR_OK)
3073 return r;
3074
3075 /* update the flash bank size */
3076 for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
3077 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
3078 bank->size = pPrivate->pChip->details.bank[x].size_bytes;
3079 break;
3080 }
3081 }
3082
3083 if (bank->sectors == NULL) {
3084 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
3085 if (bank->sectors == NULL) {
3086 LOG_ERROR("No memory!");
3087 return ERROR_FAIL;
3088 }
3089 bank->num_sectors = pPrivate->nsectors;
3090
3091 for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
3092 bank->sectors[x].size = pPrivate->sector_size;
3093 bank->sectors[x].offset = x * (pPrivate->sector_size);
3094 /* mark as unknown */
3095 bank->sectors[x].is_erased = -1;
3096 bank->sectors[x].is_protected = -1;
3097 }
3098 }
3099
3100 pPrivate->probed = 1;
3101
3102 r = sam3_protect_check(bank);
3103 if (r != ERROR_OK)
3104 return r;
3105
3106 LOG_DEBUG("Bank = %d, nbanks = %d",
3107 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
3108 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
3109 /* read unique id, */
3110 /* it appears to be associated with the *last* flash bank. */
3111 FLASHD_ReadUniqueID(pPrivate);
3112 }
3113
3114 return r;
3115 }
3116
3117 static int sam3_probe(struct flash_bank *bank)
3118 {
3119 return _sam3_probe(bank, 1);
3120 }
3121
3122 static int sam3_auto_probe(struct flash_bank *bank)
3123 {
3124 return _sam3_probe(bank, 0);
3125 }
3126
3127 static int sam3_erase(struct flash_bank *bank, int first, int last)
3128 {
3129 struct sam3_bank_private *pPrivate;
3130 int r;
3131
3132 LOG_DEBUG("Here");
3133 if (bank->target->state != TARGET_HALTED) {
3134 LOG_ERROR("Target not halted");
3135 return ERROR_TARGET_NOT_HALTED;
3136 }
3137
3138 r = sam3_auto_probe(bank);
3139 if (r != ERROR_OK) {
3140 LOG_DEBUG("Here,r=%d", r);
3141 return r;
3142 }
3143
3144 pPrivate = get_sam3_bank_private(bank);
3145 if (!(pPrivate->probed))
3146 return ERROR_FLASH_BANK_NOT_PROBED;
3147
3148 if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
3149 /* whole chip */
3150 LOG_DEBUG("Here");
3151 return FLASHD_EraseEntireBank(pPrivate);
3152 }
3153 LOG_INFO("sam3 auto-erases while programming (request ignored)");
3154 return ERROR_OK;
3155 }
3156
3157 static int sam3_protect(struct flash_bank *bank, int set, int first, int last)
3158 {
3159 struct sam3_bank_private *pPrivate;
3160 int r;
3161
3162 LOG_DEBUG("Here");
3163 if (bank->target->state != TARGET_HALTED) {
3164 LOG_ERROR("Target not halted");
3165 return ERROR_TARGET_NOT_HALTED;
3166 }
3167
3168 pPrivate = get_sam3_bank_private(bank);
3169 if (!(pPrivate->probed))
3170 return ERROR_FLASH_BANK_NOT_PROBED;
3171
3172 if (set)
3173 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
3174 else
3175 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
3176 LOG_DEBUG("End: r=%d", r);
3177
3178 return r;
3179
3180 }
3181
3182 static int sam3_info(struct flash_bank *bank, char *buf, int buf_size)
3183 {
3184 if (bank->target->state != TARGET_HALTED) {
3185 LOG_ERROR("Target not halted");
3186 return ERROR_TARGET_NOT_HALTED;
3187 }
3188 buf[0] = 0;
3189 return ERROR_OK;
3190 }
3191
3192 static int sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
3193 {
3194 uint32_t adr;
3195 int r;
3196
3197 adr = pagenum * pPrivate->page_size;
3198 adr += pPrivate->base_address;
3199
3200 r = target_read_memory(pPrivate->pChip->target,
3201 adr,
3202 4, /* THIS*MUST*BE* in 32bit values */
3203 pPrivate->page_size / 4,
3204 buf);
3205 if (r != ERROR_OK)
3206 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
3207 (unsigned int)(adr));
3208 return r;
3209 }
3210
3211 /* The code below is basically this: */
3212 /* compiled with */
3213 /* arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s */
3214 /* */
3215 /* Only the *CPU* can write to the flash buffer. */
3216 /* the DAP cannot... so - we download this 28byte thing */
3217 /* Run the algorithm - (below) */
3218 /* to program the device */
3219 /* */
3220 /* ======================================== */
3221 /* #include <stdint.h> */
3222 /* */
3223 /* struct foo { */
3224 /* uint32_t *dst; */
3225 /* const uint32_t *src; */
3226 /* int n; */
3227 /* volatile uint32_t *base; */
3228 /* uint32_t cmd; */
3229 /* }; */
3230 /* */
3231 /* */
3232 /* uint32_t sam3_function(struct foo *p) */
3233 /* { */
3234 /* volatile uint32_t *v; */
3235 /* uint32_t *d; */
3236 /* const uint32_t *s; */
3237 /* int n; */
3238 /* uint32_t r; */
3239 /* */
3240 /* d = p->dst; */
3241 /* s = p->src; */
3242 /* n = p->n; */
3243 /* */
3244 /* do { */
3245 /* *d++ = *s++; */
3246 /* } while (--n) */
3247 /* ; */
3248 /* */
3249 /* v = p->base; */
3250 /* */
3251 /* v[ 1 ] = p->cmd; */
3252 /* do { */
3253 /* r = v[8/4]; */
3254 /* } while (!(r&1)) */
3255 /* ; */
3256 /* return r; */
3257 /* } */
3258 /* ======================================== */
3259
3260 static const uint8_t
3261 sam3_page_write_opcodes[] = {
3262 /* 24 0000 0446 mov r4, r0 */
3263 0x04, 0x46,
3264 /* 25 0002 6168 ldr r1, [r4, #4] */
3265 0x61, 0x68,
3266 /* 26 0004 0068 ldr r0, [r0, #0] */
3267 0x00, 0x68,
3268 /* 27 0006 A268 ldr r2, [r4, #8] */
3269 0xa2, 0x68,
3270 /* 28 @ lr needed for prologue */
3271 /* 29 .L2: */
3272 /* 30 0008 51F8043B ldr r3, [r1], #4 */
3273 0x51, 0xf8, 0x04, 0x3b,
3274 /* 31 000c 12F1FF32 adds r2, r2, #-1 */
3275 0x12, 0xf1, 0xff, 0x32,
3276 /* 32 0010 40F8043B str r3, [r0], #4 */
3277 0x40, 0xf8, 0x04, 0x3b,
3278 /* 33 0014 F8D1 bne .L2 */
3279 0xf8, 0xd1,
3280 /* 34 0016 E268 ldr r2, [r4, #12] */
3281 0xe2, 0x68,
3282 /* 35 0018 2369 ldr r3, [r4, #16] */
3283 0x23, 0x69,
3284 /* 36 001a 5360 str r3, [r2, #4] */
3285 0x53, 0x60,
3286 /* 37 001c 0832 adds r2, r2, #8 */
3287 0x08, 0x32,
3288 /* 38 .L4: */
3289 /* 39 001e 1068 ldr r0, [r2, #0] */
3290 0x10, 0x68,
3291 /* 40 0020 10F0010F tst r0, #1 */
3292 0x10, 0xf0, 0x01, 0x0f,
3293 /* 41 0024 FBD0 beq .L4 */
3294 0xfb, 0xd0,
3295 0x00, 0xBE /* bkpt #0 */
3296 };
3297
3298 static int sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
3299 {
3300 uint32_t adr;
3301 uint32_t status;
3302 uint32_t fmr; /* EEFC Flash Mode Register */
3303 int r;
3304
3305 adr = pagenum * pPrivate->page_size;
3306 adr += pPrivate->base_address;
3307
3308 /* Get flash mode register value */
3309 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
3310 if (r != ERROR_OK)
3311 LOG_DEBUG("Error Read failed: read flash mode register");
3312
3313 /* Clear flash wait state field */
3314 fmr &= 0xfffff0ff;
3315
3316 /* set FWS (flash wait states) field in the FMR (flash mode register) */
3317 fmr |= (pPrivate->flash_wait_states << 8);
3318
3319 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
3320 r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
3321 if (r != ERROR_OK)
3322 LOG_DEBUG("Error Write failed: set flash mode register");
3323
3324 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
3325 r = target_write_memory(pPrivate->pChip->target,
3326 adr,
3327 4, /* THIS*MUST*BE* in 32bit values */
3328 pPrivate->page_size / 4,
3329 buf);
3330 if (r != ERROR_OK) {
3331 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
3332 (unsigned int)(adr));
3333 return r;
3334 }
3335
3336 r = EFC_PerformCommand(pPrivate,
3337 /* send Erase & Write Page */
3338 AT91C_EFC_FCMD_EWP,
3339 pagenum,
3340 &status);
3341
3342 if (r != ERROR_OK)
3343 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
3344 (unsigned int)(adr));
3345 if (status & (1 << 2)) {
3346 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
3347 return ERROR_FAIL;
3348 }
3349 if (status & (1 << 1)) {
3350 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
3351 return ERROR_FAIL;
3352 }
3353 return ERROR_OK;
3354 }
3355
3356 static int sam3_write(struct flash_bank *bank,
3357 uint8_t *buffer,
3358 uint32_t offset,
3359 uint32_t count)
3360 {
3361 int n;
3362 unsigned page_cur;
3363 unsigned page_end;
3364 int r;
3365 unsigned page_offset;
3366 struct sam3_bank_private *pPrivate;
3367 uint8_t *pagebuffer;
3368
3369 /* incase we bail further below, set this to null */
3370 pagebuffer = NULL;
3371
3372 /* ignore dumb requests */
3373 if (count == 0) {
3374 r = ERROR_OK;
3375 goto done;
3376 }
3377
3378 if (bank->target->state != TARGET_HALTED) {
3379 LOG_ERROR("Target not halted");
3380 r = ERROR_TARGET_NOT_HALTED;
3381 goto done;
3382 }
3383
3384 pPrivate = get_sam3_bank_private(bank);
3385 if (!(pPrivate->probed)) {
3386 r = ERROR_FLASH_BANK_NOT_PROBED;
3387 goto done;
3388 }
3389
3390 if ((offset + count) > pPrivate->size_bytes) {
3391 LOG_ERROR("Flash write error - past end of bank");
3392 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
3393 (unsigned int)(offset),
3394 (unsigned int)(count),
3395 (unsigned int)(pPrivate->size_bytes));
3396 r = ERROR_FAIL;
3397 goto done;
3398 }
3399
3400 pagebuffer = malloc(pPrivate->page_size);
3401 if (!pagebuffer) {
3402 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
3403 r = ERROR_FAIL;
3404 goto done;
3405 }
3406
3407 /* what page do we start & end in? */
3408 page_cur = offset / pPrivate->page_size;
3409 page_end = (offset + count - 1) / pPrivate->page_size;
3410
3411 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
3412 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
3413
3414 /* Special case: all one page */
3415 /* */
3416 /* Otherwise: */
3417 /* (1) non-aligned start */
3418 /* (2) body pages */
3419 /* (3) non-aligned end. */
3420
3421 /* Handle special case - all one page. */
3422 if (page_cur == page_end) {
3423 LOG_DEBUG("Special case, all in one page");
3424 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3425 if (r != ERROR_OK)
3426 goto done;
3427
3428 page_offset = (offset & (pPrivate->page_size-1));
3429 memcpy(pagebuffer + page_offset,
3430 buffer,
3431 count);
3432
3433 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3434 if (r != ERROR_OK)
3435 goto done;
3436 r = ERROR_OK;
3437 goto done;
3438 }
3439
3440 /* non-aligned start */
3441 page_offset = offset & (pPrivate->page_size - 1);
3442 if (page_offset) {
3443 LOG_DEBUG("Not-Aligned start");
3444 /* read the partial */
3445 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3446 if (r != ERROR_OK)
3447 goto done;
3448
3449 /* over-write with new data */
3450 n = (pPrivate->page_size - page_offset);
3451 memcpy(pagebuffer + page_offset,
3452 buffer,
3453 n);
3454
3455 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3456 if (r != ERROR_OK)
3457 goto done;
3458
3459 count -= n;
3460 offset += n;
3461 buffer += n;
3462 page_cur++;
3463 }
3464
3465 /* By checking that offset is correct here, we also
3466 fix a clang warning */
3467 assert(offset % pPrivate->page_size == 0);
3468
3469 /* intermediate large pages */
3470 /* also - the final *terminal* */
3471 /* if that terminal page is a full page */
3472 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3473 (int)page_cur, (int)page_end, (unsigned int)(count));
3474
3475 while ((page_cur < page_end) &&
3476 (count >= pPrivate->page_size)) {
3477 r = sam3_page_write(pPrivate, page_cur, buffer);
3478 if (r != ERROR_OK)
3479 goto done;
3480 count -= pPrivate->page_size;
3481 buffer += pPrivate->page_size;
3482 page_cur += 1;
3483 }
3484
3485 /* terminal partial page? */
3486 if (count) {
3487 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
3488 /* we have a partial page */
3489 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3490 if (r != ERROR_OK)
3491 goto done;
3492 /* data goes at start */
3493 memcpy(pagebuffer, buffer, count);
3494 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3495 if (r != ERROR_OK)
3496 goto done;
3497 }
3498 LOG_DEBUG("Done!");
3499 r = ERROR_OK;
3500 done:
3501 if (pagebuffer)
3502 free(pagebuffer);
3503 return r;
3504 }
3505
3506 COMMAND_HANDLER(sam3_handle_info_command)
3507 {
3508 struct sam3_chip *pChip;
3509 pChip = get_current_sam3(CMD_CTX);
3510 if (!pChip)
3511 return ERROR_OK;
3512
3513 unsigned x;
3514 int r;
3515
3516 /* bank0 must exist before we can do anything */
3517 if (pChip->details.bank[0].pBank == NULL) {
3518 x = 0;
3519 need_define:
3520 command_print(CMD_CTX,
3521 "Please define bank %d via command: flash bank %s ... ",
3522 x,
3523 at91sam3_flash.name);
3524 return ERROR_FAIL;
3525 }
3526
3527 /* if bank 0 is not probed, then probe it */
3528 if (!(pChip->details.bank[0].probed)) {
3529 r = sam3_auto_probe(pChip->details.bank[0].pBank);
3530 if (r != ERROR_OK)
3531 return ERROR_FAIL;
3532 }
3533 /* above guarantees the "chip details" structure is valid */
3534 /* and thus, bank private areas are valid */
3535 /* and we have a SAM3 chip, what a concept! */
3536
3537 /* auto-probe other banks, 0 done above */
3538 for (x = 1; x < SAM3_MAX_FLASH_BANKS; x++) {
3539 /* skip banks not present */
3540 if (!(pChip->details.bank[x].present))
3541 continue;
3542
3543 if (pChip->details.bank[x].pBank == NULL)
3544 goto need_define;
3545
3546 if (pChip->details.bank[x].probed)
3547 continue;
3548
3549 r = sam3_auto_probe(pChip->details.bank[x].pBank);
3550 if (r != ERROR_OK)
3551 return r;
3552 }
3553
3554 r = sam3_GetInfo(pChip);
3555 if (r != ERROR_OK) {
3556 LOG_DEBUG("Sam3Info, Failed %d", r);
3557 return r;
3558 }
3559
3560 return ERROR_OK;
3561 }
3562
3563 COMMAND_HANDLER(sam3_handle_gpnvm_command)
3564 {
3565 unsigned x, v;
3566 int r, who;
3567 struct sam3_chip *pChip;
3568
3569 pChip = get_current_sam3(CMD_CTX);
3570 if (!pChip)
3571 return ERROR_OK;
3572
3573 if (pChip->target->state != TARGET_HALTED) {
3574 LOG_ERROR("sam3 - target not halted");
3575 return ERROR_TARGET_NOT_HALTED;
3576 }
3577
3578 if (pChip->details.bank[0].pBank == NULL) {
3579 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
3580 at91sam3_flash.name);
3581 return ERROR_FAIL;
3582 }
3583 if (!pChip->details.bank[0].probed) {
3584 r = sam3_auto_probe(pChip->details.bank[0].pBank);
3585 if (r != ERROR_OK)
3586 return r;
3587 }
3588
3589 switch (CMD_ARGC) {
3590 default:
3591 return ERROR_COMMAND_SYNTAX_ERROR;
3592 break;
3593 case 0:
3594 goto showall;
3595 break;
3596 case 1:
3597 who = -1;
3598 break;
3599 case 2:
3600 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
3601 who = -1;
3602 else {
3603 uint32_t v32;
3604 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3605 who = v32;
3606 }
3607 break;
3608 }
3609
3610 if (0 == strcmp("show", CMD_ARGV[0])) {
3611 if (who == -1) {
3612 showall:
3613 r = ERROR_OK;
3614 for (x = 0; x < pChip->details.n_gpnvms; x++) {
3615 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
3616 if (r != ERROR_OK)
3617 break;
3618 command_print(CMD_CTX, "sam3-gpnvm%u: %u", x, v);
3619 }
3620 return r;
3621 }
3622 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
3623 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
3624 command_print(CMD_CTX, "sam3-gpnvm%u: %u", who, v);
3625 return r;
3626 } else {
3627 command_print(CMD_CTX, "sam3-gpnvm invalid GPNVM: %u", who);
3628 return ERROR_COMMAND_SYNTAX_ERROR;
3629 }
3630 }
3631
3632 if (who == -1) {
3633 command_print