1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
8 * Copyright (C) 2011 by Olivier Schonken (at91sam3x* support) * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
18 * GNU General public License for more details. *
20 * You should have received a copy of the GNU General public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
24 ****************************************************************************/
26 /* Some of the the lower level code was based on code supplied by
27 * ATMEL under this copyright. */
29 /* BEGIN ATMEL COPYRIGHT */
30 /* ----------------------------------------------------------------------------
31 * ATMEL Microcontroller Software Support
32 * ----------------------------------------------------------------------------
33 * Copyright (c) 2009, Atmel Corporation
35 * All rights reserved.
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions are met:
40 * - Redistributions of source code must retain the above copyright notice,
41 * this list of conditions and the disclaimer below.
43 * Atmel's name may not be used to endorse or promote products derived from
44 * this software without specific prior written permission.
46 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
48 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
49 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
51 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
52 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
53 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
54 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
55 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
56 * ----------------------------------------------------------------------------
58 /* END ATMEL COPYRIGHT */
65 #include <helper/time_support.h>
67 #define REG_NAME_WIDTH (12)
69 /* at91sam3u series (has one or two flash banks) */
70 #define FLASH_BANK0_BASE_U 0x00080000
71 #define FLASH_BANK1_BASE_U 0x00100000
73 /* at91sam3s series (has always one flash bank) */
74 #define FLASH_BANK_BASE_S 0x00400000
76 /* at91sam3sd series (has always two flash banks) */
77 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
78 #define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
81 /* at91sam3n series (has always one flash bank) */
82 #define FLASH_BANK_BASE_N 0x00400000
84 /* at91sam3a/x series has two flash banks*/
85 #define FLASH_BANK0_BASE_AX 0x00080000
86 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
87 #define FLASH_BANK1_BASE_256K_AX 0x000A0000
88 #define FLASH_BANK1_BASE_512K_AX 0x000C0000
90 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
91 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
92 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
93 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
94 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
95 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
96 /* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
97 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
98 /* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
99 /* #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages? */
100 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
101 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
102 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
103 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
104 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
105 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
106 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
107 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
109 #define offset_EFC_FMR 0
110 #define offset_EFC_FCR 4
111 #define offset_EFC_FSR 8
112 #define offset_EFC_FRR 12
114 extern struct flash_driver at91sam3_flash
;
116 static float _tomhz(uint32_t freq_hz
)
120 f
= ((float)(freq_hz
)) / 1000000.0;
124 /* How the chip is configured. */
126 uint32_t unique_id
[4];
130 uint32_t mainosc_freq
;
140 #define SAM3_CHIPID_CIDR (0x400E0740)
141 uint32_t CHIPID_CIDR
;
142 #define SAM3_CHIPID_CIDR2 (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
143 uint32_t CHIPID_CIDR2
;
144 #define SAM3_CHIPID_EXID (0x400E0744)
145 uint32_t CHIPID_EXID
;
146 #define SAM3_CHIPID_EXID2 (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
147 uint32_t CHIPID_EXID2
;
150 #define SAM3_PMC_BASE (0x400E0400)
151 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
153 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
155 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
157 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
159 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
161 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
163 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
165 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
167 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
169 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
171 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
173 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
175 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
177 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
182 * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
183 * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
184 * the flash wait state (FWS) should be set to 6. It seems like that the
185 * cause of the problem is not the flash itself, but the flash write
186 * buffer. Ie the wait states have to be set before writing into the
188 * Tested and confirmed with SAM3N and SAM3U
191 struct sam3_bank_private
{
193 /* DANGER: THERE ARE DRAGONS HERE.. */
194 /* NOTE: If you add more 'ghost' pointers */
195 /* be aware that you must *manually* update */
196 /* these pointers in the function sam3_GetDetails() */
197 /* See the comment "Here there be dragons" */
199 /* so we can find the chip we belong to */
200 struct sam3_chip
*pChip
;
201 /* so we can find the original bank pointer */
202 struct flash_bank
*pBank
;
203 unsigned bank_number
;
204 uint32_t controller_address
;
205 uint32_t base_address
;
206 uint32_t flash_wait_states
;
210 unsigned sector_size
;
214 struct sam3_chip_details
{
215 /* THERE ARE DRAGONS HERE.. */
216 /* note: If you add pointers here */
217 /* be careful about them as they */
218 /* may need to be updated inside */
219 /* the function: "sam3_GetDetails() */
220 /* which copy/overwrites the */
221 /* 'runtime' copy of this structure */
222 uint32_t chipid_cidr
;
226 #define SAM3_N_NVM_BITS 3
227 unsigned gpnvm
[SAM3_N_NVM_BITS
];
228 unsigned total_flash_size
;
229 unsigned total_sram_size
;
231 #define SAM3_MAX_FLASH_BANKS 2
232 /* these are "initialized" from the global const data */
233 struct sam3_bank_private bank
[SAM3_MAX_FLASH_BANKS
];
237 struct sam3_chip
*next
;
240 /* this is "initialized" from the global const structure */
241 struct sam3_chip_details details
;
242 struct target
*target
;
247 struct sam3_reg_list
{
248 uint32_t address
; size_t struct_offset
; const char *name
;
249 void (*explain_func
)(struct sam3_chip
*pInfo
);
252 static struct sam3_chip
*all_sam3_chips
;
254 static struct sam3_chip
*get_current_sam3(struct command_context
*cmd_ctx
)
257 static struct sam3_chip
*p
;
259 t
= get_current_target(cmd_ctx
);
261 command_print(cmd_ctx
, "No current target?");
267 /* this should not happen */
268 /* the command is not registered until the chip is created? */
269 command_print(cmd_ctx
, "No SAM3 chips exist?");
278 command_print(cmd_ctx
, "Cannot find SAM3 chip?");
282 /* these are used to *initialize* the "pChip->details" structure. */
283 static const struct sam3_chip_details all_sam3_details
[] = {
284 /* Start at91sam3u* series */
286 .chipid_cidr
= 0x28100960,
287 .name
= "at91sam3u4e",
288 .total_flash_size
= 256 * 1024,
289 .total_sram_size
= 52 * 1024,
293 /* System boots at address 0x0 */
294 /* gpnvm[1] = selects boot code */
295 /* if gpnvm[1] == 0 */
296 /* boot is via "SAMBA" (rom) */
298 /* boot is via FLASH */
299 /* Selection is via gpnvm[2] */
302 /* NOTE: banks 0 & 1 switch places */
303 /* if gpnvm[2] == 0 */
304 /* Bank0 is the boot rom */
306 /* Bank1 is the boot rom */
315 .base_address
= FLASH_BANK0_BASE_U
,
316 .controller_address
= 0x400e0800,
317 .flash_wait_states
= 6, /* workaround silicon bug */
319 .size_bytes
= 128 * 1024,
331 .base_address
= FLASH_BANK1_BASE_U
,
332 .controller_address
= 0x400e0a00,
333 .flash_wait_states
= 6, /* workaround silicon bug */
335 .size_bytes
= 128 * 1024,
344 .chipid_cidr
= 0x281a0760,
345 .name
= "at91sam3u2e",
346 .total_flash_size
= 128 * 1024,
347 .total_sram_size
= 36 * 1024,
351 /* System boots at address 0x0 */
352 /* gpnvm[1] = selects boot code */
353 /* if gpnvm[1] == 0 */
354 /* boot is via "SAMBA" (rom) */
356 /* boot is via FLASH */
357 /* Selection is via gpnvm[2] */
366 .base_address
= FLASH_BANK0_BASE_U
,
367 .controller_address
= 0x400e0800,
368 .flash_wait_states
= 6, /* workaround silicon bug */
370 .size_bytes
= 128 * 1024,
384 .chipid_cidr
= 0x28190560,
385 .name
= "at91sam3u1e",
386 .total_flash_size
= 64 * 1024,
387 .total_sram_size
= 20 * 1024,
391 /* System boots at address 0x0 */
392 /* gpnvm[1] = selects boot code */
393 /* if gpnvm[1] == 0 */
394 /* boot is via "SAMBA" (rom) */
396 /* boot is via FLASH */
397 /* Selection is via gpnvm[2] */
408 .base_address
= FLASH_BANK0_BASE_U
,
409 .controller_address
= 0x400e0800,
410 .flash_wait_states
= 6, /* workaround silicon bug */
412 .size_bytes
= 64 * 1024,
428 .chipid_cidr
= 0x28000960,
429 .name
= "at91sam3u4c",
430 .total_flash_size
= 256 * 1024,
431 .total_sram_size
= 52 * 1024,
435 /* System boots at address 0x0 */
436 /* gpnvm[1] = selects boot code */
437 /* if gpnvm[1] == 0 */
438 /* boot is via "SAMBA" (rom) */
440 /* boot is via FLASH */
441 /* Selection is via gpnvm[2] */
444 /* NOTE: banks 0 & 1 switch places */
445 /* if gpnvm[2] == 0 */
446 /* Bank0 is the boot rom */
448 /* Bank1 is the boot rom */
457 .base_address
= FLASH_BANK0_BASE_U
,
458 .controller_address
= 0x400e0800,
459 .flash_wait_states
= 6, /* workaround silicon bug */
461 .size_bytes
= 128 * 1024,
472 .base_address
= FLASH_BANK1_BASE_U
,
473 .controller_address
= 0x400e0a00,
474 .flash_wait_states
= 6, /* workaround silicon bug */
476 .size_bytes
= 128 * 1024,
485 .chipid_cidr
= 0x280a0760,
486 .name
= "at91sam3u2c",
487 .total_flash_size
= 128 * 1024,
488 .total_sram_size
= 36 * 1024,
492 /* System boots at address 0x0 */
493 /* gpnvm[1] = selects boot code */
494 /* if gpnvm[1] == 0 */
495 /* boot is via "SAMBA" (rom) */
497 /* boot is via FLASH */
498 /* Selection is via gpnvm[2] */
507 .base_address
= FLASH_BANK0_BASE_U
,
508 .controller_address
= 0x400e0800,
509 .flash_wait_states
= 6, /* workaround silicon bug */
511 .size_bytes
= 128 * 1024,
525 .chipid_cidr
= 0x28090560,
526 .name
= "at91sam3u1c",
527 .total_flash_size
= 64 * 1024,
528 .total_sram_size
= 20 * 1024,
532 /* System boots at address 0x0 */
533 /* gpnvm[1] = selects boot code */
534 /* if gpnvm[1] == 0 */
535 /* boot is via "SAMBA" (rom) */
537 /* boot is via FLASH */
538 /* Selection is via gpnvm[2] */
549 .base_address
= FLASH_BANK0_BASE_U
,
550 .controller_address
= 0x400e0800,
551 .flash_wait_states
= 6, /* workaround silicon bug */
553 .size_bytes
= 64 * 1024,
568 /* Start at91sam3s* series */
570 /* Note: The preliminary at91sam3s datasheet says on page 302 */
571 /* that the flash controller is at address 0x400E0800. */
572 /* This is _not_ the case, the controller resides at address 0x400e0a0. */
574 .chipid_cidr
= 0x28A00960,
575 .name
= "at91sam3s4c",
576 .total_flash_size
= 256 * 1024,
577 .total_sram_size
= 48 * 1024,
587 .base_address
= FLASH_BANK_BASE_S
,
588 .controller_address
= 0x400e0a00,
589 .flash_wait_states
= 6, /* workaround silicon bug */
591 .size_bytes
= 256 * 1024,
593 .sector_size
= 16384,
607 .chipid_cidr
= 0x28900960,
608 .name
= "at91sam3s4b",
609 .total_flash_size
= 256 * 1024,
610 .total_sram_size
= 48 * 1024,
620 .base_address
= FLASH_BANK_BASE_S
,
621 .controller_address
= 0x400e0a00,
622 .flash_wait_states
= 6, /* workaround silicon bug */
624 .size_bytes
= 256 * 1024,
626 .sector_size
= 16384,
639 .chipid_cidr
= 0x28800960,
640 .name
= "at91sam3s4a",
641 .total_flash_size
= 256 * 1024,
642 .total_sram_size
= 48 * 1024,
652 .base_address
= FLASH_BANK_BASE_S
,
653 .controller_address
= 0x400e0a00,
654 .flash_wait_states
= 6, /* workaround silicon bug */
656 .size_bytes
= 256 * 1024,
658 .sector_size
= 16384,
671 .chipid_cidr
= 0x28AA0760,
672 .name
= "at91sam3s2c",
673 .total_flash_size
= 128 * 1024,
674 .total_sram_size
= 32 * 1024,
684 .base_address
= FLASH_BANK_BASE_S
,
685 .controller_address
= 0x400e0a00,
686 .flash_wait_states
= 6, /* workaround silicon bug */
688 .size_bytes
= 128 * 1024,
690 .sector_size
= 16384,
703 .chipid_cidr
= 0x289A0760,
704 .name
= "at91sam3s2b",
705 .total_flash_size
= 128 * 1024,
706 .total_sram_size
= 32 * 1024,
716 .base_address
= FLASH_BANK_BASE_S
,
717 .controller_address
= 0x400e0a00,
718 .flash_wait_states
= 6, /* workaround silicon bug */
720 .size_bytes
= 128 * 1024,
722 .sector_size
= 16384,
735 .chipid_cidr
= 0x29ab0a60,
736 .name
= "at91sam3sd8c",
737 .total_flash_size
= 512 * 1024,
738 .total_sram_size
= 64 * 1024,
748 .base_address
= FLASH_BANK0_BASE_SD
,
749 .controller_address
= 0x400e0a00,
750 .flash_wait_states
= 6, /* workaround silicon bug */
752 .size_bytes
= 256 * 1024,
754 .sector_size
= 32768,
763 .base_address
= FLASH_BANK1_BASE_512K_SD
,
764 .controller_address
= 0x400e0a00,
765 .flash_wait_states
= 6, /* workaround silicon bug */
767 .size_bytes
= 256 * 1024,
769 .sector_size
= 32768,
775 .chipid_cidr
= 0x288A0760,
776 .name
= "at91sam3s2a",
777 .total_flash_size
= 128 * 1024,
778 .total_sram_size
= 32 * 1024,
788 .base_address
= FLASH_BANK_BASE_S
,
789 .controller_address
= 0x400e0a00,
790 .flash_wait_states
= 6, /* workaround silicon bug */
792 .size_bytes
= 128 * 1024,
794 .sector_size
= 16384,
807 .chipid_cidr
= 0x28A90560,
808 .name
= "at91sam3s1c",
809 .total_flash_size
= 64 * 1024,
810 .total_sram_size
= 16 * 1024,
820 .base_address
= FLASH_BANK_BASE_S
,
821 .controller_address
= 0x400e0a00,
822 .flash_wait_states
= 6, /* workaround silicon bug */
824 .size_bytes
= 64 * 1024,
826 .sector_size
= 16384,
839 .chipid_cidr
= 0x28990560,
840 .name
= "at91sam3s1b",
841 .total_flash_size
= 64 * 1024,
842 .total_sram_size
= 16 * 1024,
852 .base_address
= FLASH_BANK_BASE_S
,
853 .controller_address
= 0x400e0a00,
854 .flash_wait_states
= 6, /* workaround silicon bug */
856 .size_bytes
= 64 * 1024,
858 .sector_size
= 16384,
871 .chipid_cidr
= 0x28890560,
872 .name
= "at91sam3s1a",
873 .total_flash_size
= 64 * 1024,
874 .total_sram_size
= 16 * 1024,
884 .base_address
= FLASH_BANK_BASE_S
,
885 .controller_address
= 0x400e0a00,
886 .flash_wait_states
= 6, /* workaround silicon bug */
888 .size_bytes
= 64 * 1024,
890 .sector_size
= 16384,
903 /* Start at91sam3n* series */
905 .chipid_cidr
= 0x29540960,
906 .name
= "at91sam3n4c",
907 .total_flash_size
= 256 * 1024,
908 .total_sram_size
= 24 * 1024,
912 /* System boots at address 0x0 */
913 /* gpnvm[1] = selects boot code */
914 /* if gpnvm[1] == 0 */
915 /* boot is via "SAMBA" (rom) */
917 /* boot is via FLASH */
918 /* Selection is via gpnvm[2] */
921 /* NOTE: banks 0 & 1 switch places */
922 /* if gpnvm[2] == 0 */
923 /* Bank0 is the boot rom */
925 /* Bank1 is the boot rom */
934 .base_address
= FLASH_BANK_BASE_N
,
935 .controller_address
= 0x400e0A00,
936 .flash_wait_states
= 6, /* workaround silicon bug */
938 .size_bytes
= 256 * 1024,
940 .sector_size
= 16384,
954 .chipid_cidr
= 0x29440960,
955 .name
= "at91sam3n4b",
956 .total_flash_size
= 256 * 1024,
957 .total_sram_size
= 24 * 1024,
961 /* System boots at address 0x0 */
962 /* gpnvm[1] = selects boot code */
963 /* if gpnvm[1] == 0 */
964 /* boot is via "SAMBA" (rom) */
966 /* boot is via FLASH */
967 /* Selection is via gpnvm[2] */
970 /* NOTE: banks 0 & 1 switch places */
971 /* if gpnvm[2] == 0 */
972 /* Bank0 is the boot rom */
974 /* Bank1 is the boot rom */
983 .base_address
= FLASH_BANK_BASE_N
,
984 .controller_address
= 0x400e0A00,
985 .flash_wait_states
= 6, /* workaround silicon bug */
987 .size_bytes
= 256 * 1024,
989 .sector_size
= 16384,
1003 .chipid_cidr
= 0x29340960,
1004 .name
= "at91sam3n4a",
1005 .total_flash_size
= 256 * 1024,
1006 .total_sram_size
= 24 * 1024,
1010 /* System boots at address 0x0 */
1011 /* gpnvm[1] = selects boot code */
1012 /* if gpnvm[1] == 0 */
1013 /* boot is via "SAMBA" (rom) */
1015 /* boot is via FLASH */
1016 /* Selection is via gpnvm[2] */
1019 /* NOTE: banks 0 & 1 switch places */
1020 /* if gpnvm[2] == 0 */
1021 /* Bank0 is the boot rom */
1023 /* Bank1 is the boot rom */
1032 .base_address
= FLASH_BANK_BASE_N
,
1033 .controller_address
= 0x400e0A00,
1034 .flash_wait_states
= 6, /* workaround silicon bug */
1036 .size_bytes
= 256 * 1024,
1038 .sector_size
= 16384,
1052 .chipid_cidr
= 0x29590760,
1053 .name
= "at91sam3n2c",
1054 .total_flash_size
= 128 * 1024,
1055 .total_sram_size
= 16 * 1024,
1059 /* System boots at address 0x0 */
1060 /* gpnvm[1] = selects boot code */
1061 /* if gpnvm[1] == 0 */
1062 /* boot is via "SAMBA" (rom) */
1064 /* boot is via FLASH */
1065 /* Selection is via gpnvm[2] */
1068 /* NOTE: banks 0 & 1 switch places */
1069 /* if gpnvm[2] == 0 */
1070 /* Bank0 is the boot rom */
1072 /* Bank1 is the boot rom */
1081 .base_address
= FLASH_BANK_BASE_N
,
1082 .controller_address
= 0x400e0A00,
1083 .flash_wait_states
= 6, /* workaround silicon bug */
1085 .size_bytes
= 128 * 1024,
1087 .sector_size
= 16384,
1101 .chipid_cidr
= 0x29490760,
1102 .name
= "at91sam3n2b",
1103 .total_flash_size
= 128 * 1024,
1104 .total_sram_size
= 16 * 1024,
1108 /* System boots at address 0x0 */
1109 /* gpnvm[1] = selects boot code */
1110 /* if gpnvm[1] == 0 */
1111 /* boot is via "SAMBA" (rom) */
1113 /* boot is via FLASH */
1114 /* Selection is via gpnvm[2] */
1117 /* NOTE: banks 0 & 1 switch places */
1118 /* if gpnvm[2] == 0 */
1119 /* Bank0 is the boot rom */
1121 /* Bank1 is the boot rom */
1130 .base_address
= FLASH_BANK_BASE_N
,
1131 .controller_address
= 0x400e0A00,
1132 .flash_wait_states
= 6, /* workaround silicon bug */
1134 .size_bytes
= 128 * 1024,
1136 .sector_size
= 16384,
1150 .chipid_cidr
= 0x29390760,
1151 .name
= "at91sam3n2a",
1152 .total_flash_size
= 128 * 1024,
1153 .total_sram_size
= 16 * 1024,
1157 /* System boots at address 0x0 */
1158 /* gpnvm[1] = selects boot code */
1159 /* if gpnvm[1] == 0 */
1160 /* boot is via "SAMBA" (rom) */
1162 /* boot is via FLASH */
1163 /* Selection is via gpnvm[2] */
1166 /* NOTE: banks 0 & 1 switch places */
1167 /* if gpnvm[2] == 0 */
1168 /* Bank0 is the boot rom */
1170 /* Bank1 is the boot rom */
1179 .base_address
= FLASH_BANK_BASE_N
,
1180 .controller_address
= 0x400e0A00,
1181 .flash_wait_states
= 6, /* workaround silicon bug */
1183 .size_bytes
= 128 * 1024,
1185 .sector_size
= 16384,
1199 .chipid_cidr
= 0x29580560,
1200 .name
= "at91sam3n1c",
1201 .total_flash_size
= 64 * 1024,
1202 .total_sram_size
= 8 * 1024,
1206 /* System boots at address 0x0 */
1207 /* gpnvm[1] = selects boot code */
1208 /* if gpnvm[1] == 0 */
1209 /* boot is via "SAMBA" (rom) */
1211 /* boot is via FLASH */
1212 /* Selection is via gpnvm[2] */
1215 /* NOTE: banks 0 & 1 switch places */
1216 /* if gpnvm[2] == 0 */
1217 /* Bank0 is the boot rom */
1219 /* Bank1 is the boot rom */
1228 .base_address
= FLASH_BANK_BASE_N
,
1229 .controller_address
= 0x400e0A00,
1230 .flash_wait_states
= 6, /* workaround silicon bug */
1232 .size_bytes
= 64 * 1024,
1234 .sector_size
= 16384,
1248 .chipid_cidr
= 0x29480560,
1249 .name
= "at91sam3n1b",
1250 .total_flash_size
= 64 * 1024,
1251 .total_sram_size
= 8 * 1024,
1255 /* System boots at address 0x0 */
1256 /* gpnvm[1] = selects boot code */
1257 /* if gpnvm[1] == 0 */
1258 /* boot is via "SAMBA" (rom) */
1260 /* boot is via FLASH */
1261 /* Selection is via gpnvm[2] */
1264 /* NOTE: banks 0 & 1 switch places */
1265 /* if gpnvm[2] == 0 */
1266 /* Bank0 is the boot rom */
1268 /* Bank1 is the boot rom */
1277 .base_address
= FLASH_BANK_BASE_N
,
1278 .controller_address
= 0x400e0A00,
1279 .flash_wait_states
= 6, /* workaround silicon bug */
1281 .size_bytes
= 64 * 1024,
1283 .sector_size
= 16384,
1297 .chipid_cidr
= 0x29380560,
1298 .name
= "at91sam3n1a",
1299 .total_flash_size
= 64 * 1024,
1300 .total_sram_size
= 8 * 1024,
1304 /* System boots at address 0x0 */
1305 /* gpnvm[1] = selects boot code */
1306 /* if gpnvm[1] == 0 */
1307 /* boot is via "SAMBA" (rom) */
1309 /* boot is via FLASH */
1310 /* Selection is via gpnvm[2] */
1313 /* NOTE: banks 0 & 1 switch places */
1314 /* if gpnvm[2] == 0 */
1315 /* Bank0 is the boot rom */
1317 /* Bank1 is the boot rom */
1326 .base_address
= FLASH_BANK_BASE_N
,
1327 .controller_address
= 0x400e0A00,
1328 .flash_wait_states
= 6, /* workaround silicon bug */
1330 .size_bytes
= 64 * 1024,
1332 .sector_size
= 16384,
1345 /* Start at91sam3a series*/
1346 /* System boots at address 0x0 */
1347 /* gpnvm[1] = selects boot code */
1348 /* if gpnvm[1] == 0 */
1349 /* boot is via "SAMBA" (rom) */
1351 /* boot is via FLASH */
1352 /* Selection is via gpnvm[2] */
1355 /* NOTE: banks 0 & 1 switch places */
1356 /* if gpnvm[2] == 0 */
1357 /* Bank0 is the boot rom */
1359 /* Bank1 is the boot rom */
1363 .chipid_cidr
= 0x283E0A60,
1364 .name
= "at91sam3a8c",
1365 .total_flash_size
= 512 * 1024,
1366 .total_sram_size
= 96 * 1024,
1376 .base_address
= FLASH_BANK0_BASE_AX
,
1377 .controller_address
= 0x400e0a00,
1378 .flash_wait_states
= 6, /* workaround silicon bug */
1380 .size_bytes
= 256 * 1024,
1382 .sector_size
= 16384,
1391 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1392 .controller_address
= 0x400e0c00,
1393 .flash_wait_states
= 6, /* workaround silicon bug */
1395 .size_bytes
= 256 * 1024,
1397 .sector_size
= 16384,
1404 .chipid_cidr
= 0x283B0960,
1405 .name
= "at91sam3a4c",
1406 .total_flash_size
= 256 * 1024,
1407 .total_sram_size
= 64 * 1024,
1417 .base_address
= FLASH_BANK0_BASE_AX
,
1418 .controller_address
= 0x400e0a00,
1419 .flash_wait_states
= 6, /* workaround silicon bug */
1421 .size_bytes
= 128 * 1024,
1423 .sector_size
= 16384,
1432 .base_address
= FLASH_BANK1_BASE_256K_AX
,
1433 .controller_address
= 0x400e0c00,
1434 .flash_wait_states
= 6, /* workaround silicon bug */
1436 .size_bytes
= 128 * 1024,
1438 .sector_size
= 16384,
1445 /* Start at91sam3x* series */
1446 /* System boots at address 0x0 */
1447 /* gpnvm[1] = selects boot code */
1448 /* if gpnvm[1] == 0 */
1449 /* boot is via "SAMBA" (rom) */
1451 /* boot is via FLASH */
1452 /* Selection is via gpnvm[2] */
1455 /* NOTE: banks 0 & 1 switch places */
1456 /* if gpnvm[2] == 0 */
1457 /* Bank0 is the boot rom */
1459 /* Bank1 is the boot rom */
1461 /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
1463 .chipid_cidr
= 0x286E0A20,
1464 .name
= "at91sam3x8h - ES",
1465 .total_flash_size
= 512 * 1024,
1466 .total_sram_size
= 96 * 1024,
1476 .base_address
= FLASH_BANK0_BASE_AX
,
1477 .controller_address
= 0x400e0a00,
1478 .flash_wait_states
= 6, /* workaround silicon bug */
1480 .size_bytes
= 256 * 1024,
1482 .sector_size
= 16384,
1491 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1492 .controller_address
= 0x400e0c00,
1493 .flash_wait_states
= 6, /* workaround silicon bug */
1495 .size_bytes
= 256 * 1024,
1497 .sector_size
= 16384,
1503 /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
1505 .chipid_cidr
= 0x286E0A60,
1506 .name
= "at91sam3x8h",
1507 .total_flash_size
= 512 * 1024,
1508 .total_sram_size
= 96 * 1024,
1518 .base_address
= FLASH_BANK0_BASE_AX
,
1519 .controller_address
= 0x400e0a00,
1520 .flash_wait_states
= 6, /* workaround silicon bug */
1522 .size_bytes
= 256 * 1024,
1524 .sector_size
= 16384,
1533 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1534 .controller_address
= 0x400e0c00,
1535 .flash_wait_states
= 6, /* workaround silicon bug */
1537 .size_bytes
= 256 * 1024,
1539 .sector_size
= 16384,
1546 .chipid_cidr
= 0x285E0A60,
1547 .name
= "at91sam3x8e",
1548 .total_flash_size
= 512 * 1024,
1549 .total_sram_size
= 96 * 1024,
1559 .base_address
= FLASH_BANK0_BASE_AX
,
1560 .controller_address
= 0x400e0a00,
1561 .flash_wait_states
= 6, /* workaround silicon bug */
1563 .size_bytes
= 256 * 1024,
1565 .sector_size
= 16384,
1574 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1575 .controller_address
= 0x400e0c00,
1576 .flash_wait_states
= 6, /* workaround silicon bug */
1578 .size_bytes
= 256 * 1024,
1580 .sector_size
= 16384,
1587 .chipid_cidr
= 0x284E0A60,
1588 .name
= "at91sam3x8c",
1589 .total_flash_size
= 512 * 1024,
1590 .total_sram_size
= 96 * 1024,
1600 .base_address
= FLASH_BANK0_BASE_AX
,
1601 .controller_address
= 0x400e0a00,
1602 .flash_wait_states
= 6, /* workaround silicon bug */
1604 .size_bytes
= 256 * 1024,
1606 .sector_size
= 16384,
1615 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1616 .controller_address
= 0x400e0c00,
1617 .flash_wait_states
= 6, /* workaround silicon bug */
1619 .size_bytes
= 256 * 1024,
1621 .sector_size
= 16384,
1628 .chipid_cidr
= 0x285B0960,
1629 .name
= "at91sam3x4e",
1630 .total_flash_size
= 256 * 1024,
1631 .total_sram_size
= 64 * 1024,
1641 .base_address
= FLASH_BANK0_BASE_AX
,
1642 .controller_address
= 0x400e0a00,
1643 .flash_wait_states
= 6, /* workaround silicon bug */
1645 .size_bytes
= 128 * 1024,
1647 .sector_size
= 16384,
1656 .base_address
= FLASH_BANK1_BASE_256K_AX
,
1657 .controller_address
= 0x400e0c00,
1658 .flash_wait_states
= 6, /* workaround silicon bug */
1660 .size_bytes
= 128 * 1024,
1662 .sector_size
= 16384,
1669 .chipid_cidr
= 0x284B0960,
1670 .name
= "at91sam3x4c",
1671 .total_flash_size
= 256 * 1024,
1672 .total_sram_size
= 64 * 1024,
1682 .base_address
= FLASH_BANK0_BASE_AX
,
1683 .controller_address
= 0x400e0a00,
1684 .flash_wait_states
= 6, /* workaround silicon bug */
1686 .size_bytes
= 128 * 1024,
1688 .sector_size
= 16384,
1697 .base_address
= FLASH_BANK1_BASE_256K_AX
,
1698 .controller_address
= 0x400e0c00,
1699 .flash_wait_states
= 6, /* workaround silicon bug */
1701 .size_bytes
= 128 * 1024,
1703 .sector_size
= 16384,
1717 /***********************************************************************
1718 **********************************************************************
1719 **********************************************************************
1720 **********************************************************************
1721 **********************************************************************
1722 **********************************************************************/
1723 /* *ATMEL* style code - from the SAM3 driver code */
1726 * Get the current status of the EEFC and
1727 * the value of some status bits (LOCKE, PROGE).
1728 * @param pPrivate - info about the bank
1729 * @param v - result goes here
1731 static int EFC_GetStatus(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
1734 r
= target_read_u32(pPrivate
->pChip
->target
,
1735 pPrivate
->controller_address
+ offset_EFC_FSR
,
1737 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1739 ((unsigned int)((*v
>> 2) & 1)),
1740 ((unsigned int)((*v
>> 1) & 1)),
1741 ((unsigned int)((*v
>> 0) & 1)));
1747 * Get the result of the last executed command.
1748 * @param pPrivate - info about the bank
1749 * @param v - result goes here
1751 static int EFC_GetResult(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
1755 r
= target_read_u32(pPrivate
->pChip
->target
,
1756 pPrivate
->controller_address
+ offset_EFC_FRR
,
1760 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv
)));
1764 static int EFC_StartCommand(struct sam3_bank_private
*pPrivate
,
1765 unsigned command
, unsigned argument
)
1774 /* Check command & argument */
1777 case AT91C_EFC_FCMD_WP
:
1778 case AT91C_EFC_FCMD_WPL
:
1779 case AT91C_EFC_FCMD_EWP
:
1780 case AT91C_EFC_FCMD_EWPL
:
1781 /* case AT91C_EFC_FCMD_EPL: */
1782 /* case AT91C_EFC_FCMD_EPA: */
1783 case AT91C_EFC_FCMD_SLB
:
1784 case AT91C_EFC_FCMD_CLB
:
1785 n
= (pPrivate
->size_bytes
/ pPrivate
->page_size
);
1787 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n
));
1790 case AT91C_EFC_FCMD_SFB
:
1791 case AT91C_EFC_FCMD_CFB
:
1792 if (argument
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1793 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1794 pPrivate
->pChip
->details
.n_gpnvms
);
1798 case AT91C_EFC_FCMD_GETD
:
1799 case AT91C_EFC_FCMD_EA
:
1800 case AT91C_EFC_FCMD_GLB
:
1801 case AT91C_EFC_FCMD_GFB
:
1802 case AT91C_EFC_FCMD_STUI
:
1803 case AT91C_EFC_FCMD_SPUI
:
1805 LOG_ERROR("Argument is meaningless for cmd: %d", command
);
1808 LOG_ERROR("Unknown command %d", command
);
1812 if (command
== AT91C_EFC_FCMD_SPUI
) {
1813 /* this is a very special situation. */
1814 /* Situation (1) - error/retry - see below */
1815 /* And we are being called recursively */
1816 /* Situation (2) - normal, finished reading unique id */
1818 /* it should be "ready" */
1819 EFC_GetStatus(pPrivate
, &v
);
1821 /* then it is ready */
1825 /* we have done this before */
1826 /* the controller is not responding. */
1827 LOG_ERROR("flash controller(%d) is not ready! Error",
1828 pPrivate
->bank_number
);
1832 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1833 pPrivate
->bank_number
);
1834 /* we do that by issuing the *STOP* command */
1835 EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0);
1836 /* above is recursive, and further recursion is blocked by */
1837 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1843 v
= (0x5A << 24) | (argument
<< 8) | command
;
1844 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v
)));
1845 r
= target_write_u32(pPrivate
->pBank
->target
,
1846 pPrivate
->controller_address
+ offset_EFC_FCR
, v
);
1848 LOG_DEBUG("Error Write failed");
1853 * Performs the given command and wait until its completion (or an error).
1854 * @param pPrivate - info about the bank
1855 * @param command - Command to perform.
1856 * @param argument - Optional command argument.
1857 * @param status - put command status bits here
1859 static int EFC_PerformCommand(struct sam3_bank_private
*pPrivate
,
1867 long long ms_now
, ms_end
;
1873 r
= EFC_StartCommand(pPrivate
, command
, argument
);
1877 ms_end
= 500 + timeval_ms();
1880 r
= EFC_GetStatus(pPrivate
, &v
);
1883 ms_now
= timeval_ms();
1884 if (ms_now
> ms_end
) {
1886 LOG_ERROR("Command timeout");
1889 } while ((v
& 1) == 0);
1893 *status
= (v
& 0x6);
1899 * Read the unique ID.
1900 * @param pPrivate - info about the bank
1901 * The unique ID is stored in the 'pPrivate' structure.
1903 static int FLASHD_ReadUniqueID(struct sam3_bank_private
*pPrivate
)
1909 pPrivate
->pChip
->cfg
.unique_id
[0] = 0;
1910 pPrivate
->pChip
->cfg
.unique_id
[1] = 0;
1911 pPrivate
->pChip
->cfg
.unique_id
[2] = 0;
1912 pPrivate
->pChip
->cfg
.unique_id
[3] = 0;
1915 r
= EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_STUI
, 0);
1919 for (x
= 0; x
< 4; x
++) {
1920 r
= target_read_u32(pPrivate
->pChip
->target
,
1921 pPrivate
->pBank
->base
+ (x
* 4),
1925 pPrivate
->pChip
->cfg
.unique_id
[x
] = v
;
1928 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0, NULL
);
1929 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1931 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[0]),
1932 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[1]),
1933 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[2]),
1934 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[3]));
1940 * Erases the entire flash.
1941 * @param pPrivate - the info about the bank.
1943 static int FLASHD_EraseEntireBank(struct sam3_bank_private
*pPrivate
)
1946 return EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_EA
, 0, NULL
);
1950 * Gets current GPNVM state.
1951 * @param pPrivate - info about the bank.
1952 * @param gpnvm - GPNVM bit index.
1953 * @param puthere - result stored here.
1955 /* ------------------------------------------------------------------------------ */
1956 static int FLASHD_GetGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
, unsigned *puthere
)
1962 if (pPrivate
->bank_number
!= 0) {
1963 LOG_ERROR("GPNVM only works with Bank0");
1967 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1968 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1969 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
1973 /* Get GPNVMs status */
1974 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GFB
, 0, NULL
);
1975 if (r
!= ERROR_OK
) {
1976 LOG_ERROR("Failed");
1980 r
= EFC_GetResult(pPrivate
, &v
);
1983 /* Check if GPNVM is set */
1984 /* get the bit and make it a 0/1 */
1985 *puthere
= (v
>> gpnvm
) & 1;
1992 * Clears the selected GPNVM bit.
1993 * @param pPrivate info about the bank
1994 * @param gpnvm GPNVM index.
1995 * @returns 0 if successful; otherwise returns an error code.
1997 static int FLASHD_ClrGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
2003 if (pPrivate
->bank_number
!= 0) {
2004 LOG_ERROR("GPNVM only works with Bank0");
2008 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
2009 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2010 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
2014 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
2015 if (r
!= ERROR_OK
) {
2016 LOG_DEBUG("Failed: %d", r
);
2019 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CFB
, gpnvm
, NULL
);
2020 LOG_DEBUG("End: %d", r
);
2025 * Sets the selected GPNVM bit.
2026 * @param pPrivate info about the bank
2027 * @param gpnvm GPNVM index.
2029 static int FLASHD_SetGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
2034 if (pPrivate
->bank_number
!= 0) {
2035 LOG_ERROR("GPNVM only works with Bank0");
2039 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
2040 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2041 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
2045 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
2053 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SFB
, gpnvm
, NULL
);
2059 * Returns a bit field (at most 64) of locked regions within a page.
2060 * @param pPrivate info about the bank
2061 * @param v where to store locked bits
2063 static int FLASHD_GetLockBits(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
2067 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GLB
, 0, NULL
);
2069 r
= EFC_GetResult(pPrivate
, v
);
2070 LOG_DEBUG("End: %d", r
);
2075 * Unlocks all the regions in the given address range.
2076 * @param pPrivate info about the bank
2077 * @param start_sector first sector to unlock
2078 * @param end_sector last (inclusive) to unlock
2081 static int FLASHD_Unlock(struct sam3_bank_private
*pPrivate
,
2082 unsigned start_sector
,
2083 unsigned end_sector
)
2088 uint32_t pages_per_sector
;
2090 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
2092 /* Unlock all pages */
2093 while (start_sector
<= end_sector
) {
2094 pg
= start_sector
* pages_per_sector
;
2096 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CLB
, pg
, &status
);
2107 * @param pPrivate - info about the bank
2108 * @param start_sector - first sector to lock
2109 * @param end_sector - last sector (inclusive) to lock
2111 static int FLASHD_Lock(struct sam3_bank_private
*pPrivate
,
2112 unsigned start_sector
,
2113 unsigned end_sector
)
2117 uint32_t pages_per_sector
;
2120 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
2122 /* Lock all pages */
2123 while (start_sector
<= end_sector
) {
2124 pg
= start_sector
* pages_per_sector
;
2126 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SLB
, pg
, &status
);
2134 /****** END SAM3 CODE ********/
2136 /* begin helpful debug code */
2137 /* print the fieldname, the field value, in dec & hex, and return field value */
2138 static uint32_t sam3_reg_fieldname(struct sam3_chip
*pChip
,
2139 const char *regname
,
2148 /* extract the field */
2150 v
= v
& ((1 << width
)-1);
2159 /* show the basics */
2160 LOG_USER_N("\t%*s: %*d [0x%0*x] ",
2161 REG_NAME_WIDTH
, regname
,
2167 static const char _unknown
[] = "unknown";
2168 static const char *const eproc_names
[] = {
2172 "cortex-m3", /* 3 */
2174 "arm926ejs", /* 5 */
2187 #define nvpsize2 nvpsize /* these two tables are identical */
2188 static const char *const nvpsize
[] = {
2191 "16K bytes", /* 2 */
2192 "32K bytes", /* 3 */
2194 "64K bytes", /* 5 */
2196 "128K bytes", /* 7 */
2198 "256K bytes", /* 9 */
2199 "512K bytes", /* 10 */
2201 "1024K bytes", /* 12 */
2203 "2048K bytes", /* 14 */
2207 static const char *const sramsize
[] = {
2208 "48K Bytes", /* 0 */
2212 "112K Bytes", /* 4 */
2214 "80K Bytes", /* 6 */
2215 "160K Bytes", /* 7 */
2217 "16K Bytes", /* 9 */
2218 "32K Bytes", /* 10 */
2219 "64K Bytes", /* 11 */
2220 "128K Bytes", /* 12 */
2221 "256K Bytes", /* 13 */
2222 "96K Bytes", /* 14 */
2223 "512K Bytes", /* 15 */
2227 static const struct archnames
{ unsigned value
; const char *name
; } archnames
[] = {
2228 { 0x19, "AT91SAM9xx Series" },
2229 { 0x29, "AT91SAM9XExx Series" },
2230 { 0x34, "AT91x34 Series" },
2231 { 0x37, "CAP7 Series" },
2232 { 0x39, "CAP9 Series" },
2233 { 0x3B, "CAP11 Series" },
2234 { 0x40, "AT91x40 Series" },
2235 { 0x42, "AT91x42 Series" },
2236 { 0x55, "AT91x55 Series" },
2237 { 0x60, "AT91SAM7Axx Series" },
2238 { 0x61, "AT91SAM7AQxx Series" },
2239 { 0x63, "AT91x63 Series" },
2240 { 0x70, "AT91SAM7Sxx Series" },
2241 { 0x71, "AT91SAM7XCxx Series" },
2242 { 0x72, "AT91SAM7SExx Series" },
2243 { 0x73, "AT91SAM7Lxx Series" },
2244 { 0x75, "AT91SAM7Xxx Series" },
2245 { 0x76, "AT91SAM7SLxx Series" },
2246 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2247 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2248 { 0x83, "ATSAM3AxC Series (100-pin version)" },
2249 { 0x84, "ATSAM3XxC Series (100-pin version)" },
2250 { 0x85, "ATSAM3XxE Series (144-pin version)" },
2251 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
2252 { 0x88, "ATSAM3SxA Series (48-pin version)" },
2253 { 0x89, "ATSAM3SxB Series (64-pin version)" },
2254 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
2255 { 0x92, "AT91x92 Series" },
2256 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2257 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2258 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2259 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2260 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2261 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2262 { 0xA5, "ATSAM5A" },
2263 { 0xF0, "AT75Cxx Series" },
2267 static const char *const nvptype
[] = {
2269 "romless or onchip flash", /* 1 */
2270 "embedded flash memory",/* 2 */
2271 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2272 "sram emulating flash", /* 4 */
2278 static const char *_yes_or_no(uint32_t v
)
2286 static const char *const _rc_freq
[] = {
2287 "4 MHz", "8 MHz", "12 MHz", "reserved"
2290 static void sam3_explain_ckgr_mor(struct sam3_chip
*pChip
)
2295 v
= sam3_reg_fieldname(pChip
, "MOSCXTEN", pChip
->cfg
.CKGR_MOR
, 0, 1);
2296 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v
));
2297 v
= sam3_reg_fieldname(pChip
, "MOSCXTBY", pChip
->cfg
.CKGR_MOR
, 1, 1);
2298 LOG_USER("(main osc bypass: %s)", _yes_or_no(v
));
2299 rcen
= sam3_reg_fieldname(pChip
, "MOSCRCEN", pChip
->cfg
.CKGR_MOR
, 3, 1);
2300 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen
));
2301 v
= sam3_reg_fieldname(pChip
, "MOSCRCF", pChip
->cfg
.CKGR_MOR
, 4, 3);
2302 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq
[v
]);
2304 pChip
->cfg
.rc_freq
= 0;
2308 pChip
->cfg
.rc_freq
= 0;
2311 pChip
->cfg
.rc_freq
= 4 * 1000 * 1000;
2314 pChip
->cfg
.rc_freq
= 8 * 1000 * 1000;
2317 pChip
->cfg
.rc_freq
= 12 * 1000 * 1000;
2322 v
= sam3_reg_fieldname(pChip
, "MOSCXTST", pChip
->cfg
.CKGR_MOR
, 8, 8);
2323 LOG_USER("(startup clks, time= %f uSecs)",
2324 ((float)(v
* 1000000)) / ((float)(pChip
->cfg
.slow_freq
)));
2325 v
= sam3_reg_fieldname(pChip
, "MOSCSEL", pChip
->cfg
.CKGR_MOR
, 24, 1);
2326 LOG_USER("(mainosc source: %s)",
2327 v
? "external xtal" : "internal RC");
2329 v
= sam3_reg_fieldname(pChip
, "CFDEN", pChip
->cfg
.CKGR_MOR
, 25, 1);
2330 LOG_USER("(clock failure enabled: %s)",
2334 static void sam3_explain_chipid_cidr(struct sam3_chip
*pChip
)
2340 sam3_reg_fieldname(pChip
, "Version", pChip
->cfg
.CHIPID_CIDR
, 0, 5);
2343 v
= sam3_reg_fieldname(pChip
, "EPROC", pChip
->cfg
.CHIPID_CIDR
, 5, 3);
2344 LOG_USER("%s", eproc_names
[v
]);
2346 v
= sam3_reg_fieldname(pChip
, "NVPSIZE", pChip
->cfg
.CHIPID_CIDR
, 8, 4);
2347 LOG_USER("%s", nvpsize
[v
]);
2349 v
= sam3_reg_fieldname(pChip
, "NVPSIZE2", pChip
->cfg
.CHIPID_CIDR
, 12, 4);
2350 LOG_USER("%s", nvpsize2
[v
]);
2352 v
= sam3_reg_fieldname(pChip
, "SRAMSIZE", pChip
->cfg
.CHIPID_CIDR
, 16, 4);
2353 LOG_USER("%s", sramsize
[v
]);
2355 v
= sam3_reg_fieldname(pChip
, "ARCH", pChip
->cfg
.CHIPID_CIDR
, 20, 8);
2357 for (x
= 0; archnames
[x
].name
; x
++) {
2358 if (v
== archnames
[x
].value
) {
2359 cp
= archnames
[x
].name
;
2366 v
= sam3_reg_fieldname(pChip
, "NVPTYP", pChip
->cfg
.CHIPID_CIDR
, 28, 3);
2367 LOG_USER("%s", nvptype
[v
]);
2369 v
= sam3_reg_fieldname(pChip
, "EXTID", pChip
->cfg
.CHIPID_CIDR
, 31, 1);
2370 LOG_USER("(exists: %s)", _yes_or_no(v
));
2373 static void sam3_explain_ckgr_mcfr(struct sam3_chip
*pChip
)
2377 v
= sam3_reg_fieldname(pChip
, "MAINFRDY", pChip
->cfg
.CKGR_MCFR
, 16, 1);
2378 LOG_USER("(main ready: %s)", _yes_or_no(v
));
2380 v
= sam3_reg_fieldname(pChip
, "MAINF", pChip
->cfg
.CKGR_MCFR
, 0, 16);
2382 v
= (v
* pChip
->cfg
.slow_freq
) / 16;
2383 pChip
->cfg
.mainosc_freq
= v
;
2385 LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
2387 pChip
->cfg
.slow_freq
/ 1000,
2388 pChip
->cfg
.slow_freq
% 1000);
2391 static void sam3_explain_ckgr_plla(struct sam3_chip
*pChip
)
2393 uint32_t mula
, diva
;
2395 diva
= sam3_reg_fieldname(pChip
, "DIVA", pChip
->cfg
.CKGR_PLLAR
, 0, 8);
2397 mula
= sam3_reg_fieldname(pChip
, "MULA", pChip
->cfg
.CKGR_PLLAR
, 16, 11);
2399 pChip
->cfg
.plla_freq
= 0;
2401 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2403 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2404 else if (diva
>= 1) {
2405 pChip
->cfg
.plla_freq
= (pChip
->cfg
.mainosc_freq
* (mula
+ 1) / diva
);
2406 LOG_USER("\tPLLA Freq: %3.03f MHz",
2407 _tomhz(pChip
->cfg
.plla_freq
));
2411 static void sam3_explain_mckr(struct sam3_chip
*pChip
)
2413 uint32_t css
, pres
, fin
= 0;
2415 const char *cp
= NULL
;
2417 css
= sam3_reg_fieldname(pChip
, "CSS", pChip
->cfg
.PMC_MCKR
, 0, 2);
2420 fin
= pChip
->cfg
.slow_freq
;
2424 fin
= pChip
->cfg
.mainosc_freq
;
2428 fin
= pChip
->cfg
.plla_freq
;
2432 if (pChip
->cfg
.CKGR_UCKR
& (1 << 16)) {
2433 fin
= 480 * 1000 * 1000;
2437 cp
= "upll (*ERROR* UPLL is disabled)";
2445 LOG_USER("%s (%3.03f Mhz)",
2448 pres
= sam3_reg_fieldname(pChip
, "PRES", pChip
->cfg
.PMC_MCKR
, 4, 3);
2449 switch (pres
& 0x07) {
2452 cp
= "selected clock";
2486 LOG_USER("(%s)", cp
);
2488 /* sam3 has a *SINGLE* clock - */
2489 /* other at91 series parts have divisors for these. */
2490 pChip
->cfg
.cpu_freq
= fin
;
2491 pChip
->cfg
.mclk_freq
= fin
;
2492 pChip
->cfg
.fclk_freq
= fin
;
2493 LOG_USER("\t\tResult CPU Freq: %3.03f",
2498 static struct sam3_chip
*target2sam3(struct target
*pTarget
)
2500 struct sam3_chip
*pChip
;
2502 if (pTarget
== NULL
)
2505 pChip
= all_sam3_chips
;
2507 if (pChip
->target
== pTarget
)
2508 break; /* return below */
2510 pChip
= pChip
->next
;
2516 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg
*pCfg
, const struct sam3_reg_list
*pList
)
2518 /* this function exists to help */
2519 /* keep funky offsetof() errors */
2520 /* and casting from causing bugs */
2522 /* By using prototypes - we can detect what would */
2523 /* be casting errors. */
2525 return (uint32_t *)(void *)(((char *)(pCfg
)) + pList
->struct_offset
);
2529 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2531 NAME), # NAME, FUNC }
2532 static const struct sam3_reg_list sam3_all_regs
[] = {
2533 SAM3_ENTRY(CKGR_MOR
, sam3_explain_ckgr_mor
),
2534 SAM3_ENTRY(CKGR_MCFR
, sam3_explain_ckgr_mcfr
),
2535 SAM3_ENTRY(CKGR_PLLAR
, sam3_explain_ckgr_plla
),
2536 SAM3_ENTRY(CKGR_UCKR
, NULL
),
2537 SAM3_ENTRY(PMC_FSMR
, NULL
),
2538 SAM3_ENTRY(PMC_FSPR
, NULL
),
2539 SAM3_ENTRY(PMC_IMR
, NULL
),
2540 SAM3_ENTRY(PMC_MCKR
, sam3_explain_mckr
),
2541 SAM3_ENTRY(PMC_PCK0
, NULL
),
2542 SAM3_ENTRY(PMC_PCK1
, NULL
),
2543 SAM3_ENTRY(PMC_PCK2
, NULL
),
2544 SAM3_ENTRY(PMC_PCSR
, NULL
),
2545 SAM3_ENTRY(PMC_SCSR
, NULL
),
2546 SAM3_ENTRY(PMC_SR
, NULL
),
2547 SAM3_ENTRY(CHIPID_CIDR
, sam3_explain_chipid_cidr
),
2548 SAM3_ENTRY(CHIPID_CIDR2
, sam3_explain_chipid_cidr
),
2549 SAM3_ENTRY(CHIPID_EXID
, NULL
),
2550 SAM3_ENTRY(CHIPID_EXID2
, NULL
),
2551 /* TERMINATE THE LIST */
2556 static struct sam3_bank_private
*get_sam3_bank_private(struct flash_bank
*bank
)
2558 return (struct sam3_bank_private
*)(bank
->driver_priv
);
2562 * Given a pointer to where it goes in the structure,
2563 * determine the register name, address from the all registers table.
2565 static const struct sam3_reg_list
*sam3_GetReg(struct sam3_chip
*pChip
, uint32_t *goes_here
)
2567 const struct sam3_reg_list
*pReg
;
2569 pReg
= &(sam3_all_regs
[0]);
2570 while (pReg
->name
) {
2571 uint32_t *pPossible
;
2573 /* calculate where this one go.. */
2574 /* it is "possibly" this register. */
2576 pPossible
= ((uint32_t *)(void *)(((char *)(&(pChip
->cfg
))) + pReg
->struct_offset
));
2578 /* well? Is it this register */
2579 if (pPossible
== goes_here
) {
2587 /* This is *TOTAL*PANIC* - we are totally screwed. */
2588 LOG_ERROR("INVALID SAM3 REGISTER");
2592 static int sam3_ReadThisReg(struct sam3_chip
*pChip
, uint32_t *goes_here
)
2594 const struct sam3_reg_list
*pReg
;
2597 pReg
= sam3_GetReg(pChip
, goes_here
);
2601 r
= target_read_u32(pChip
->target
, pReg
->address
, goes_here
);
2602 if (r
!= ERROR_OK
) {
2603 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2604 pReg
->name
, (unsigned)(pReg
->address
), r
);
2609 static int sam3_ReadAllRegs(struct sam3_chip
*pChip
)
2612 const struct sam3_reg_list
*pReg
;
2614 pReg
= &(sam3_all_regs
[0]);
2615 while (pReg
->name
) {
2616 r
= sam3_ReadThisReg(pChip
,
2617 sam3_get_reg_ptr(&(pChip
->cfg
), pReg
));
2618 if (r
!= ERROR_OK
) {
2619 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Error: %d",
2620 pReg
->name
, ((unsigned)(pReg
->address
)), r
);
2626 /* Chip identification register
2628 * Unfortunately, the chip identification register is not at
2629 * a constant address across all of the SAM3 series'. As a
2630 * consequence, a simple heuristic is used to find where it's
2633 * If the contents at the first address is zero, then we know
2634 * that the second address is where the chip id register is.
2635 * We can deduce this because for those SAM's that have the
2636 * chip id @ 0x400e0940, the first address, 0x400e0740, is
2637 * located in the memory map of the Power Management Controller
2638 * (PMC). Furthermore, the address is not used by the PMC.
2639 * So when read, the memory controller returns zero.*/
2640 if (pChip
->cfg
.CHIPID_CIDR
== 0) {
2641 /*Put the correct CIDR and EXID values in the pChip structure */
2642 pChip
->cfg
.CHIPID_CIDR
= pChip
->cfg
.CHIPID_CIDR2
;
2643 pChip
->cfg
.CHIPID_EXID
= pChip
->cfg
.CHIPID_EXID2
;
2648 static int sam3_GetInfo(struct sam3_chip
*pChip
)
2650 const struct sam3_reg_list
*pReg
;
2653 pReg
= &(sam3_all_regs
[0]);
2654 while (pReg
->name
) {
2655 /* display all regs */
2656 LOG_DEBUG("Start: %s", pReg
->name
);
2657 regval
= *sam3_get_reg_ptr(&(pChip
->cfg
), pReg
);
2658 LOG_USER("%*s: [0x%08x] -> 0x%08x",
2663 if (pReg
->explain_func
)
2664 (*(pReg
->explain_func
))(pChip
);
2665 LOG_DEBUG("End: %s", pReg
->name
);
2668 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip
->cfg
.rc_freq
));
2669 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip
->cfg
.mainosc_freq
));
2670 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip
->cfg
.plla_freq
));
2671 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip
->cfg
.cpu_freq
));
2672 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip
->cfg
.mclk_freq
));
2674 LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
2675 pChip
->cfg
.unique_id
[0],
2676 pChip
->cfg
.unique_id
[1],
2677 pChip
->cfg
.unique_id
[2],
2678 pChip
->cfg
.unique_id
[3]);
2683 static int sam3_erase_check(struct flash_bank
*bank
)
2688 if (bank
->target
->state
!= TARGET_HALTED
) {
2689 LOG_ERROR("Target not halted");
2690 return ERROR_TARGET_NOT_HALTED
;
2692 if (0 == bank
->num_sectors
) {
2693 LOG_ERROR("Target: not supported/not probed");
2697 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
2698 for (x
= 0; x
< bank
->num_sectors
; x
++)
2699 bank
->sectors
[x
].is_erased
= 1;
2705 static int sam3_protect_check(struct flash_bank
*bank
)
2710 struct sam3_bank_private
*pPrivate
;
2713 if (bank
->target
->state
!= TARGET_HALTED
) {
2714 LOG_ERROR("Target not halted");
2715 return ERROR_TARGET_NOT_HALTED
;
2718 pPrivate
= get_sam3_bank_private(bank
);
2720 LOG_ERROR("no private for this bank?");
2723 if (!(pPrivate
->probed
))
2724 return ERROR_FLASH_BANK_NOT_PROBED
;
2726 r
= FLASHD_GetLockBits(pPrivate
, &v
);
2727 if (r
!= ERROR_OK
) {
2728 LOG_DEBUG("Failed: %d", r
);
2732 for (x
= 0; x
< pPrivate
->nsectors
; x
++)
2733 bank
->sectors
[x
].is_protected
= (!!(v
& (1 << x
)));
2738 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command
)
2740 struct sam3_chip
*pChip
;
2742 pChip
= all_sam3_chips
;
2744 /* is this an existing chip? */
2746 if (pChip
->target
== bank
->target
)
2748 pChip
= pChip
->next
;
2752 /* this is a *NEW* chip */
2753 pChip
= calloc(1, sizeof(struct sam3_chip
));
2755 LOG_ERROR("NO RAM!");
2758 pChip
->target
= bank
->target
;
2759 /* insert at head */
2760 pChip
->next
= all_sam3_chips
;
2761 all_sam3_chips
= pChip
;
2762 pChip
->target
= bank
->target
;
2763 /* assumption is this runs at 32khz */
2764 pChip
->cfg
.slow_freq
= 32768;
2768 switch (bank
->base
) {
2770 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
2771 "[at91sam3u series] or 0x%08x [at91sam3s series] or "
2772 "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
2773 ((unsigned int)(bank
->base
)),
2774 ((unsigned int)(FLASH_BANK0_BASE_U
)),
2775 ((unsigned int)(FLASH_BANK1_BASE_U
)),
2776 ((unsigned int)(FLASH_BANK_BASE_S
)),
2777 ((unsigned int)(FLASH_BANK_BASE_N
)),
2778 ((unsigned int)(FLASH_BANK0_BASE_AX
)),
2779 ((unsigned int)(FLASH_BANK1_BASE_256K_AX
)),
2780 ((unsigned int)(FLASH_BANK1_BASE_512K_AX
)));
2784 /* at91sam3s and at91sam3n series only has bank 0*/
2785 /* at91sam3u and at91sam3ax series has the same address for bank 0*/
2786 case FLASH_BANK_BASE_S
:
2787 case FLASH_BANK0_BASE_U
:
2788 bank
->driver_priv
= &(pChip
->details
.bank
[0]);
2789 bank
->bank_number
= 0;
2790 pChip
->details
.bank
[0].pChip
= pChip
;
2791 pChip
->details
.bank
[0].pBank
= bank
;
2794 /* Bank 1 of at91sam3u or at91sam3ax series */
2795 case FLASH_BANK1_BASE_U
:
2796 case FLASH_BANK1_BASE_256K_AX
:
2797 case FLASH_BANK1_BASE_512K_AX
:
2798 bank
->driver_priv
= &(pChip
->details
.bank
[1]);
2799 bank
->bank_number
= 1;
2800 pChip
->details
.bank
[1].pChip
= pChip
;
2801 pChip
->details
.bank
[1].pBank
= bank
;
2805 /* we initialize after probing. */
2809 static int sam3_GetDetails(struct sam3_bank_private
*pPrivate
)
2811 const struct sam3_chip_details
*pDetails
;
2812 struct sam3_chip
*pChip
;
2813 struct flash_bank
*saved_banks
[SAM3_MAX_FLASH_BANKS
];
2817 pDetails
= all_sam3_details
;
2818 while (pDetails
->name
) {
2819 /* Compare cidr without version bits */
2820 if (pDetails
->chipid_cidr
== (pPrivate
->pChip
->cfg
.CHIPID_CIDR
& 0xFFFFFFE0))
2825 if (pDetails
->name
== NULL
) {
2826 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2827 (unsigned int)(pPrivate
->pChip
->cfg
.CHIPID_CIDR
));
2828 /* Help the victim, print details about the chip */
2829 LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
2830 pPrivate
->pChip
->cfg
.CHIPID_CIDR
);
2831 sam3_explain_chipid_cidr(pPrivate
->pChip
);
2835 /* DANGER: THERE ARE DRAGONS HERE */
2837 /* get our pChip - it is going */
2838 /* to be over-written shortly */
2839 pChip
= pPrivate
->pChip
;
2841 /* Note that, in reality: */
2843 /* pPrivate = &(pChip->details.bank[0]) */
2844 /* or pPrivate = &(pChip->details.bank[1]) */
2847 /* save the "bank" pointers */
2848 for (x
= 0; x
< SAM3_MAX_FLASH_BANKS
; x
++)
2849 saved_banks
[x
] = pChip
->details
.bank
[x
].pBank
;
2851 /* Overwrite the "details" structure. */
2852 memcpy(&(pPrivate
->pChip
->details
),
2854 sizeof(pPrivate
->pChip
->details
));
2856 /* now fix the ghosted pointers */
2857 for (x
= 0; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2858 pChip
->details
.bank
[x
].pChip
= pChip
;
2859 pChip
->details
.bank
[x
].pBank
= saved_banks
[x
];
2862 /* update the *BANK*SIZE* */
2868 static int _sam3_probe(struct flash_bank
*bank
, int noise
)
2872 struct sam3_bank_private
*pPrivate
;
2875 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank
->bank_number
, noise
);
2876 if (bank
->target
->state
!= TARGET_HALTED
) {
2877 LOG_ERROR("Target not halted");
2878 return ERROR_TARGET_NOT_HALTED
;
2881 pPrivate
= get_sam3_bank_private(bank
);
2883 LOG_ERROR("Invalid/unknown bank number");
2887 r
= sam3_ReadAllRegs(pPrivate
->pChip
);
2892 if (pPrivate
->pChip
->probed
)
2893 r
= sam3_GetInfo(pPrivate
->pChip
);
2895 r
= sam3_GetDetails(pPrivate
);
2899 /* update the flash bank size */
2900 for (x
= 0; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2901 if (bank
->base
== pPrivate
->pChip
->details
.bank
[x
].base_address
) {
2902 bank
->size
= pPrivate
->pChip
->details
.bank
[x
].size_bytes
;
2907 if (bank
->sectors
== NULL
) {
2908 bank
->sectors
= calloc(pPrivate
->nsectors
, (sizeof((bank
->sectors
)[0])));
2909 if (bank
->sectors
== NULL
) {
2910 LOG_ERROR("No memory!");
2913 bank
->num_sectors
= pPrivate
->nsectors
;
2915 for (x
= 0; ((int)(x
)) < bank
->num_sectors
; x
++) {
2916 bank
->sectors
[x
].size
= pPrivate
->sector_size
;
2917 bank
->sectors
[x
].offset
= x
* (pPrivate
->sector_size
);
2918 /* mark as unknown */
2919 bank
->sectors
[x
].is_erased
= -1;
2920 bank
->sectors
[x
].is_protected
= -1;
2924 pPrivate
->probed
= 1;
2926 r
= sam3_protect_check(bank
);
2930 LOG_DEBUG("Bank = %d, nbanks = %d",
2931 pPrivate
->bank_number
, pPrivate
->pChip
->details
.n_banks
);
2932 if ((pPrivate
->bank_number
+ 1) == pPrivate
->pChip
->details
.n_banks
) {
2933 /* read unique id, */
2934 /* it appears to be associated with the *last* flash bank. */
2935 FLASHD_ReadUniqueID(pPrivate
);
2941 static int sam3_probe(struct flash_bank
*bank
)
2943 return _sam3_probe(bank
, 1);
2946 static int sam3_auto_probe(struct flash_bank
*bank
)
2948 return _sam3_probe(bank
, 0);
2951 static int sam3_erase(struct flash_bank
*bank
, int first
, int last
)
2953 struct sam3_bank_private
*pPrivate
;
2957 if (bank
->target
->state
!= TARGET_HALTED
) {
2958 LOG_ERROR("Target not halted");
2959 return ERROR_TARGET_NOT_HALTED
;
2962 r
= sam3_auto_probe(bank
);
2963 if (r
!= ERROR_OK
) {
2964 LOG_DEBUG("Here,r=%d", r
);
2968 pPrivate
= get_sam3_bank_private(bank
);
2969 if (!(pPrivate
->probed
))
2970 return ERROR_FLASH_BANK_NOT_PROBED
;
2972 if ((first
== 0) && ((last
+ 1) == ((int)(pPrivate
->nsectors
)))) {
2975 return FLASHD_EraseEntireBank(pPrivate
);
2977 LOG_INFO("sam3 auto-erases while programming (request ignored)");
2981 static int sam3_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
2983 struct sam3_bank_private
*pPrivate
;
2987 if (bank
->target
->state
!= TARGET_HALTED
) {
2988 LOG_ERROR("Target not halted");
2989 return ERROR_TARGET_NOT_HALTED
;
2992 pPrivate
= get_sam3_bank_private(bank
);
2993 if (!(pPrivate
->probed
))
2994 return ERROR_FLASH_BANK_NOT_PROBED
;
2997 r
= FLASHD_Lock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
2999 r
= FLASHD_Unlock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
3000 LOG_DEBUG("End: r=%d", r
);
3006 static int sam3_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
3008 if (bank
->target
->state
!= TARGET_HALTED
) {
3009 LOG_ERROR("Target not halted");
3010 return ERROR_TARGET_NOT_HALTED
;
3016 static int sam3_page_read(struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
3021 adr
= pagenum
* pPrivate
->page_size
;
3022 adr
+= pPrivate
->base_address
;
3024 r
= target_read_memory(pPrivate
->pChip
->target
,
3026 4, /* THIS*MUST*BE* in 32bit values */
3027 pPrivate
->page_size
/ 4,
3030 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
3031 (unsigned int)(adr
));
3035 /* The code below is basically this: */
3037 /* arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s */
3039 /* Only the *CPU* can write to the flash buffer. */
3040 /* the DAP cannot... so - we download this 28byte thing */
3041 /* Run the algorithm - (below) */
3042 /* to program the device */
3044 /* ======================================== */
3045 /* #include <stdint.h> */
3048 /* uint32_t *dst; */
3049 /* const uint32_t *src; */
3051 /* volatile uint32_t *base; */
3056 /* uint32_t sam3_function(struct foo *p) */
3058 /* volatile uint32_t *v; */
3060 /* const uint32_t *s; */
3075 /* v[ 1 ] = p->cmd; */
3078 /* } while (!(r&1)) */
3082 /* ======================================== */
3084 static const uint8_t
3085 sam3_page_write_opcodes
[] = {
3086 /* 24 0000 0446 mov r4, r0 */
3088 /* 25 0002 6168 ldr r1, [r4, #4] */
3090 /* 26 0004 0068 ldr r0, [r0, #0] */
3092 /* 27 0006 A268 ldr r2, [r4, #8] */
3094 /* 28 @ lr needed for prologue */
3096 /* 30 0008 51F8043B ldr r3, [r1], #4 */
3097 0x51, 0xf8, 0x04, 0x3b,
3098 /* 31 000c 12F1FF32 adds r2, r2, #-1 */
3099 0x12, 0xf1, 0xff, 0x32,
3100 /* 32 0010 40F8043B str r3, [r0], #4 */
3101 0x40, 0xf8, 0x04, 0x3b,
3102 /* 33 0014 F8D1 bne .L2 */
3104 /* 34 0016 E268 ldr r2, [r4, #12] */
3106 /* 35 0018 2369 ldr r3, [r4, #16] */
3108 /* 36 001a 5360 str r3, [r2, #4] */
3110 /* 37 001c 0832 adds r2, r2, #8 */
3113 /* 39 001e 1068 ldr r0, [r2, #0] */
3115 /* 40 0020 10F0010F tst r0, #1 */
3116 0x10, 0xf0, 0x01, 0x0f,
3117 /* 41 0024 FBD0 beq .L4 */
3119 0x00, 0xBE /* bkpt #0 */
3122 static int sam3_page_write(struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
3126 uint32_t fmr
; /* EEFC Flash Mode Register */
3129 adr
= pagenum
* pPrivate
->page_size
;
3130 adr
+= pPrivate
->base_address
;
3132 /* Get flash mode register value */
3133 r
= target_read_u32(pPrivate
->pChip
->target
, pPrivate
->controller_address
, &fmr
);
3135 LOG_DEBUG("Error Read failed: read flash mode register");
3137 /* Clear flash wait state field */
3140 /* set FWS (flash wait states) field in the FMR (flash mode register) */
3141 fmr
|= (pPrivate
->flash_wait_states
<< 8);
3143 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr
)));
3144 r
= target_write_u32(pPrivate
->pBank
->target
, pPrivate
->controller_address
, fmr
);
3146 LOG_DEBUG("Error Write failed: set flash mode register");
3148 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum
, (unsigned int)(adr
));
3149 r
= target_write_memory(pPrivate
->pChip
->target
,
3151 4, /* THIS*MUST*BE* in 32bit values */
3152 pPrivate
->page_size
/ 4,
3154 if (r
!= ERROR_OK
) {
3155 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
3156 (unsigned int)(adr
));
3160 r
= EFC_PerformCommand(pPrivate
,
3161 /* send Erase & Write Page */
3167 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
3168 (unsigned int)(adr
));
3169 if (status
& (1 << 2)) {
3170 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr
));
3173 if (status
& (1 << 1)) {
3174 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr
));
3180 static int sam3_write(struct flash_bank
*bank
,
3189 unsigned page_offset
;
3190 struct sam3_bank_private
*pPrivate
;
3191 uint8_t *pagebuffer
;
3193 /* incase we bail further below, set this to null */
3196 /* ignore dumb requests */
3202 if (bank
->target
->state
!= TARGET_HALTED
) {
3203 LOG_ERROR("Target not halted");
3204 r
= ERROR_TARGET_NOT_HALTED
;
3208 pPrivate
= get_sam3_bank_private(bank
);
3209 if (!(pPrivate
->probed
)) {
3210 r
= ERROR_FLASH_BANK_NOT_PROBED
;
3214 if ((offset
+ count
) > pPrivate
->size_bytes
) {
3215 LOG_ERROR("Flash write error - past end of bank");
3216 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
3217 (unsigned int)(offset
),
3218 (unsigned int)(count
),
3219 (unsigned int)(pPrivate
->size_bytes
));
3224 pagebuffer
= malloc(pPrivate
->page_size
);
3226 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate
->page_size
));
3231 /* what page do we start & end in? */
3232 page_cur
= offset
/ pPrivate
->page_size
;
3233 page_end
= (offset
+ count
- 1) / pPrivate
->page_size
;
3235 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset
), (unsigned int)(count
));
3236 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur
), (int)(page_end
));
3238 /* Special case: all one page */
3241 /* (1) non-aligned start */
3242 /* (2) body pages */
3243 /* (3) non-aligned end. */
3245 /* Handle special case - all one page. */
3246 if (page_cur
== page_end
) {
3247 LOG_DEBUG("Special case, all in one page");
3248 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
3252 page_offset
= (offset
& (pPrivate
->page_size
-1));
3253 memcpy(pagebuffer
+ page_offset
,
3257 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
3264 /* non-aligned start */
3265 page_offset
= offset
& (pPrivate
->page_size
- 1);
3267 LOG_DEBUG("Not-Aligned start");
3268 /* read the partial */
3269 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
3273 /* over-write with new data */
3274 n
= (pPrivate
->page_size
- page_offset
);
3275 memcpy(pagebuffer
+ page_offset
,
3279 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
3289 /* By checking that offset is correct here, we also
3290 fix a clang warning */
3291 assert(offset
% pPrivate
->page_size
== 0);
3293 /* intermediate large pages */
3294 /* also - the final *terminal* */
3295 /* if that terminal page is a full page */
3296 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3297 (int)page_cur
, (int)page_end
, (unsigned int)(count
));
3299 while ((page_cur
< page_end
) &&
3300 (count
>= pPrivate
->page_size
)) {
3301 r
= sam3_page_write(pPrivate
, page_cur
, buffer
);
3304 count
-= pPrivate
->page_size
;
3305 buffer
+= pPrivate
->page_size
;
3309 /* terminal partial page? */
3311 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count
));
3312 /* we have a partial page */
3313 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
3316 /* data goes at start */
3317 memcpy(pagebuffer
, buffer
, count
);
3318 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
3330 COMMAND_HANDLER(sam3_handle_info_command
)
3332 struct sam3_chip
*pChip
;
3333 pChip
= get_current_sam3(CMD_CTX
);
3340 /* bank0 must exist before we can do anything */
3341 if (pChip
->details
.bank
[0].pBank
== NULL
) {
3344 command_print(CMD_CTX
,
3345 "Please define bank %d via command: flash bank %s ... ",
3347 at91sam3_flash
.name
);
3351 /* if bank 0 is not probed, then probe it */
3352 if (!(pChip
->details
.bank
[0].probed
)) {
3353 r
= sam3_auto_probe(pChip
->details
.bank
[0].pBank
);
3357 /* above guarantees the "chip details" structure is valid */
3358 /* and thus, bank private areas are valid */
3359 /* and we have a SAM3 chip, what a concept! */
3361 /* auto-probe other banks, 0 done above */
3362 for (x
= 1; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
3363 /* skip banks not present */
3364 if (!(pChip
->details
.bank
[x
].present
))
3367 if (pChip
->details
.bank
[x
].pBank
== NULL
)
3370 if (pChip
->details
.bank
[x
].probed
)
3373 r
= sam3_auto_probe(pChip
->details
.bank
[x
].pBank
);
3378 r
= sam3_GetInfo(pChip
);
3379 if (r
!= ERROR_OK
) {
3380 LOG_DEBUG("Sam3Info, Failed %d", r
);
3387 COMMAND_HANDLER(sam3_handle_gpnvm_command
)
3391 struct sam3_chip
*pChip
;
3393 pChip
= get_current_sam3(CMD_CTX
);
3397 if (pChip
->target
->state
!= TARGET_HALTED
) {
3398 LOG_ERROR("sam3 - target not halted");
3399 return ERROR_TARGET_NOT_HALTED
;
3402 if (pChip
->details
.bank
[0].pBank
== NULL
) {
3403 command_print(CMD_CTX
, "Bank0 must be defined first via: flash bank %s ...",
3404 at91sam3_flash
.name
);
3407 if (!pChip
->details
.bank
[0].probed
) {
3408 r
= sam3_auto_probe(pChip
->details
.bank
[0].pBank
);
3415 return ERROR_COMMAND_SYNTAX_ERROR
;
3424 if ((0 == strcmp(CMD_ARGV
[0], "show")) && (0 == strcmp(CMD_ARGV
[1], "all")))
3428 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], v32
);
3434 if (0 == strcmp("show", CMD_ARGV
[0])) {
3438 for (x
= 0; x
< pChip
->details
.n_gpnvms
; x
++) {
3439 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), x
, &v
);
3442 command_print(CMD_CTX
, "sam3-gpnvm%u: %u", x
, v
);
3446 if ((who
>= 0) && (((unsigned)(who
)) < pChip
->details
.n_gpnvms
)) {
3447 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), who
, &v
);
3448 command_print(CMD_CTX
, "sam3-gpnvm%u: %u", who
, v
);
3451 command_print(CMD_CTX
, "sam3-gpnvm invalid GPNVM: %u", who
);
3452 return ERROR_COMMAND_SYNTAX_ERROR
;
3457 command_print(CMD_CTX
, "Missing GPNVM number");
3458 return ERROR_COMMAND_SYNTAX_ERROR
;
3461 if (0 == strcmp("set", CMD_ARGV
[0]))
3462 r
= FLASHD_SetGPNVM(&(pChip
->details
.bank
[0]), who
);
3463 else if ((0 == strcmp("clr", CMD_ARGV
[0])) ||
3464 (0 == strcmp("clear", CMD_ARGV
[0]))) /* quietly accept both */
3465 r
= FLASHD_ClrGPNVM(&(pChip
->details
.bank
[0]), who
);
3467 command_print(CMD_CTX
, "Unknown command: %s", CMD_ARGV
[0]);
3468 r
= ERROR_COMMAND_SYNTAX_ERROR
;
3473 COMMAND_HANDLER(sam3_handle_slowclk_command
)
3475 struct sam3_chip
*pChip
;
3477 pChip
= get_current_sam3(CMD_CTX
);
3489 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], v
);
3491 /* absurd slow clock of 200Khz? */
3492 command_print(CMD_CTX
, "Absurd/illegal slow clock freq: %d\n", (int)(v
));
3493 return ERROR_COMMAND_SYNTAX_ERROR
;
3495 pChip
->cfg
.slow_freq
= v
;
3500 command_print(CMD_CTX
, "Too many parameters");
3501 return ERROR_COMMAND_SYNTAX_ERROR
;
3504 command_print(CMD_CTX
, "Slowclk freq: %d.%03dkhz",
3505 (int)(pChip
->cfg
.slow_freq
/ 1000),
3506 (int)(pChip
->cfg
.slow_freq
% 1000));
3510 static const struct command_registration at91sam3_exec_command_handlers
[] = {
3513 .handler
= sam3_handle_gpnvm_command
,
3514 .mode
= COMMAND_EXEC
,
3515 .usage
= "[('clr'|'set'|'show') bitnum]",
3516 .help
= "Without arguments, shows all bits in the gpnvm "
3517 "register. Otherwise, clears, sets, or shows one "
3518 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3522 .handler
= sam3_handle_info_command
,
3523 .mode
= COMMAND_EXEC
,
3524 .help
= "Print information about the current at91sam3 chip"
3525 "and its flash configuration.",
3529 .handler
= sam3_handle_slowclk_command
,
3530 .mode
= COMMAND_EXEC
,
3531 .usage
= "[clock_hz]",
3532 .help
= "Display or set the slowclock frequency "
3533 "(default 32768 Hz).",
3535 COMMAND_REGISTRATION_DONE
3537 static const struct command_registration at91sam3_command_handlers
[] = {
3540 .mode
= COMMAND_ANY
,
3541 .help
= "at91sam3 flash command group",
3543 .chain
= at91sam3_exec_command_handlers
,
3545 COMMAND_REGISTRATION_DONE
3548 struct flash_driver at91sam3_flash
= {
3550 .commands
= at91sam3_command_handlers
,
3551 .flash_bank_command
= sam3_flash_bank_command
,
3552 .erase
= sam3_erase
,
3553 .protect
= sam3_protect
,
3554 .write
= sam3_write
,
3555 .read
= default_flash_read
,
3556 .probe
= sam3_probe
,
3557 .auto_probe
= sam3_auto_probe
,
3558 .erase_check
= sam3_erase_check
,
3559 .protect_check
= sam3_protect_check
,
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