139599006c376c399d5ea9dbad1832cad35301e3
[openocd.git] / src / flash / nor / at91sam3.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
4 * *
5 * Copyright (C) 2010 by Olaf L√ľke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
7 * *
8 * Copyright (C) 2011 by Olivier Schonken (at91sam3x* support) * *
9 * and Jim Norris *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
18 * GNU General public License for more details. *
19 * *
20 * You should have received a copy of the GNU General public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
24 ****************************************************************************/
25
26 /* Some of the the lower level code was based on code supplied by
27 * ATMEL under this copyright. */
28
29 /* BEGIN ATMEL COPYRIGHT */
30 /* ----------------------------------------------------------------------------
31 * ATMEL Microcontroller Software Support
32 * ----------------------------------------------------------------------------
33 * Copyright (c) 2009, Atmel Corporation
34 *
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions are met:
39 *
40 * - Redistributions of source code must retain the above copyright notice,
41 * this list of conditions and the disclaimer below.
42 *
43 * Atmel's name may not be used to endorse or promote products derived from
44 * this software without specific prior written permission.
45 *
46 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
48 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
49 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
51 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
52 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
53 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
54 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
55 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
56 * ----------------------------------------------------------------------------
57 */
58 /* END ATMEL COPYRIGHT */
59
60 #ifdef HAVE_CONFIG_H
61 #include "config.h"
62 #endif
63
64 #include "imp.h"
65 #include <helper/time_support.h>
66
67 #define REG_NAME_WIDTH (12)
68
69 /* at91sam3u series (has one or two flash banks) */
70 #define FLASH_BANK0_BASE_U 0x00080000
71 #define FLASH_BANK1_BASE_U 0x00100000
72
73 /* at91sam3s series (has always one flash bank) */
74 #define FLASH_BANK_BASE_S 0x00400000
75
76 /* at91sam3sd series (has always two flash banks) */
77 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
78 #define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
79
80
81 /* at91sam3n series (has always one flash bank) */
82 #define FLASH_BANK_BASE_N 0x00400000
83
84 /* at91sam3a/x series has two flash banks*/
85 #define FLASH_BANK0_BASE_AX 0x00080000
86 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
87 #define FLASH_BANK1_BASE_256K_AX 0x000A0000
88 #define FLASH_BANK1_BASE_512K_AX 0x000C0000
89
90 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
91 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
92 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
93 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
94 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
95 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
96 /* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
97 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
98 /* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
99 /* #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages? */
100 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
101 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
102 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
103 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
104 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
105 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
106 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
107 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
108
109 #define offset_EFC_FMR 0
110 #define offset_EFC_FCR 4
111 #define offset_EFC_FSR 8
112 #define offset_EFC_FRR 12
113
114 extern struct flash_driver at91sam3_flash;
115
116 static float _tomhz(uint32_t freq_hz)
117 {
118 float f;
119
120 f = ((float)(freq_hz)) / 1000000.0;
121 return f;
122 }
123
124 /* How the chip is configured. */
125 struct sam3_cfg {
126 uint32_t unique_id[4];
127
128 uint32_t slow_freq;
129 uint32_t rc_freq;
130 uint32_t mainosc_freq;
131 uint32_t plla_freq;
132 uint32_t mclk_freq;
133 uint32_t cpu_freq;
134 uint32_t fclk_freq;
135 uint32_t pclk0_freq;
136 uint32_t pclk1_freq;
137 uint32_t pclk2_freq;
138
139
140 #define SAM3_CHIPID_CIDR (0x400E0740)
141 uint32_t CHIPID_CIDR;
142 #define SAM3_CHIPID_CIDR2 (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
143 uint32_t CHIPID_CIDR2;
144 #define SAM3_CHIPID_EXID (0x400E0744)
145 uint32_t CHIPID_EXID;
146 #define SAM3_CHIPID_EXID2 (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
147 uint32_t CHIPID_EXID2;
148
149
150 #define SAM3_PMC_BASE (0x400E0400)
151 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
152 uint32_t PMC_SCSR;
153 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
154 uint32_t PMC_PCSR;
155 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
156 uint32_t CKGR_UCKR;
157 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
158 uint32_t CKGR_MOR;
159 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
160 uint32_t CKGR_MCFR;
161 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
162 uint32_t CKGR_PLLAR;
163 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
164 uint32_t PMC_MCKR;
165 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
166 uint32_t PMC_PCK0;
167 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
168 uint32_t PMC_PCK1;
169 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
170 uint32_t PMC_PCK2;
171 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
172 uint32_t PMC_SR;
173 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
174 uint32_t PMC_IMR;
175 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
176 uint32_t PMC_FSMR;
177 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
178 uint32_t PMC_FSPR;
179 };
180
181 /*
182 * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
183 * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
184 * the flash wait state (FWS) should be set to 6. It seems like that the
185 * cause of the problem is not the flash itself, but the flash write
186 * buffer. Ie the wait states have to be set before writing into the
187 * buffer.
188 * Tested and confirmed with SAM3N and SAM3U
189 */
190
191 struct sam3_bank_private {
192 int probed;
193 /* DANGER: THERE ARE DRAGONS HERE.. */
194 /* NOTE: If you add more 'ghost' pointers */
195 /* be aware that you must *manually* update */
196 /* these pointers in the function sam3_GetDetails() */
197 /* See the comment "Here there be dragons" */
198
199 /* so we can find the chip we belong to */
200 struct sam3_chip *pChip;
201 /* so we can find the original bank pointer */
202 struct flash_bank *pBank;
203 unsigned bank_number;
204 uint32_t controller_address;
205 uint32_t base_address;
206 uint32_t flash_wait_states;
207 bool present;
208 unsigned size_bytes;
209 unsigned nsectors;
210 unsigned sector_size;
211 unsigned page_size;
212 };
213
214 struct sam3_chip_details {
215 /* THERE ARE DRAGONS HERE.. */
216 /* note: If you add pointers here */
217 /* be careful about them as they */
218 /* may need to be updated inside */
219 /* the function: "sam3_GetDetails() */
220 /* which copy/overwrites the */
221 /* 'runtime' copy of this structure */
222 uint32_t chipid_cidr;
223 const char *name;
224
225 unsigned n_gpnvms;
226 #define SAM3_N_NVM_BITS 3
227 unsigned gpnvm[SAM3_N_NVM_BITS];
228 unsigned total_flash_size;
229 unsigned total_sram_size;
230 unsigned n_banks;
231 #define SAM3_MAX_FLASH_BANKS 2
232 /* these are "initialized" from the global const data */
233 struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
234 };
235
236 struct sam3_chip {
237 struct sam3_chip *next;
238 int probed;
239
240 /* this is "initialized" from the global const structure */
241 struct sam3_chip_details details;
242 struct target *target;
243 struct sam3_cfg cfg;
244 };
245
246
247 struct sam3_reg_list {
248 uint32_t address; size_t struct_offset; const char *name;
249 void (*explain_func)(struct sam3_chip *pInfo);
250 };
251
252 static struct sam3_chip *all_sam3_chips;
253
254 static struct sam3_chip *get_current_sam3(struct command_context *cmd_ctx)
255 {
256 struct target *t;
257 static struct sam3_chip *p;
258
259 t = get_current_target(cmd_ctx);
260 if (!t) {
261 command_print(cmd_ctx, "No current target?");
262 return NULL;
263 }
264
265 p = all_sam3_chips;
266 if (!p) {
267 /* this should not happen */
268 /* the command is not registered until the chip is created? */
269 command_print(cmd_ctx, "No SAM3 chips exist?");
270 return NULL;
271 }
272
273 while (p) {
274 if (p->target == t)
275 return p;
276 p = p->next;
277 }
278 command_print(cmd_ctx, "Cannot find SAM3 chip?");
279 return NULL;
280 }
281
282 /* these are used to *initialize* the "pChip->details" structure. */
283 static const struct sam3_chip_details all_sam3_details[] = {
284 /* Start at91sam3u* series */
285 {
286 .chipid_cidr = 0x28100960,
287 .name = "at91sam3u4e",
288 .total_flash_size = 256 * 1024,
289 .total_sram_size = 52 * 1024,
290 .n_gpnvms = 3,
291 .n_banks = 2,
292
293 /* System boots at address 0x0 */
294 /* gpnvm[1] = selects boot code */
295 /* if gpnvm[1] == 0 */
296 /* boot is via "SAMBA" (rom) */
297 /* else */
298 /* boot is via FLASH */
299 /* Selection is via gpnvm[2] */
300 /* endif */
301 /* */
302 /* NOTE: banks 0 & 1 switch places */
303 /* if gpnvm[2] == 0 */
304 /* Bank0 is the boot rom */
305 /* else */
306 /* Bank1 is the boot rom */
307 /* endif */
308 /* .bank[0] = { */
309 {
310 {
311 .probed = 0,
312 .pChip = NULL,
313 .pBank = NULL,
314 .bank_number = 0,
315 .base_address = FLASH_BANK0_BASE_U,
316 .controller_address = 0x400e0800,
317 .flash_wait_states = 6, /* workaround silicon bug */
318 .present = 1,
319 .size_bytes = 128 * 1024,
320 .nsectors = 16,
321 .sector_size = 8192,
322 .page_size = 256,
323 },
324
325 /* .bank[1] = { */
326 {
327 .probed = 0,
328 .pChip = NULL,
329 .pBank = NULL,
330 .bank_number = 1,
331 .base_address = FLASH_BANK1_BASE_U,
332 .controller_address = 0x400e0a00,
333 .flash_wait_states = 6, /* workaround silicon bug */
334 .present = 1,
335 .size_bytes = 128 * 1024,
336 .nsectors = 16,
337 .sector_size = 8192,
338 .page_size = 256,
339 },
340 },
341 },
342
343 {
344 .chipid_cidr = 0x281a0760,
345 .name = "at91sam3u2e",
346 .total_flash_size = 128 * 1024,
347 .total_sram_size = 36 * 1024,
348 .n_gpnvms = 2,
349 .n_banks = 1,
350
351 /* System boots at address 0x0 */
352 /* gpnvm[1] = selects boot code */
353 /* if gpnvm[1] == 0 */
354 /* boot is via "SAMBA" (rom) */
355 /* else */
356 /* boot is via FLASH */
357 /* Selection is via gpnvm[2] */
358 /* endif */
359 /* .bank[0] = { */
360 {
361 {
362 .probed = 0,
363 .pChip = NULL,
364 .pBank = NULL,
365 .bank_number = 0,
366 .base_address = FLASH_BANK0_BASE_U,
367 .controller_address = 0x400e0800,
368 .flash_wait_states = 6, /* workaround silicon bug */
369 .present = 1,
370 .size_bytes = 128 * 1024,
371 .nsectors = 16,
372 .sector_size = 8192,
373 .page_size = 256,
374 },
375 /* .bank[1] = { */
376 {
377 .present = 0,
378 .probed = 0,
379 .bank_number = 1,
380 },
381 },
382 },
383 {
384 .chipid_cidr = 0x28190560,
385 .name = "at91sam3u1e",
386 .total_flash_size = 64 * 1024,
387 .total_sram_size = 20 * 1024,
388 .n_gpnvms = 2,
389 .n_banks = 1,
390
391 /* System boots at address 0x0 */
392 /* gpnvm[1] = selects boot code */
393 /* if gpnvm[1] == 0 */
394 /* boot is via "SAMBA" (rom) */
395 /* else */
396 /* boot is via FLASH */
397 /* Selection is via gpnvm[2] */
398 /* endif */
399 /* */
400
401 /* .bank[0] = { */
402 {
403 {
404 .probed = 0,
405 .pChip = NULL,
406 .pBank = NULL,
407 .bank_number = 0,
408 .base_address = FLASH_BANK0_BASE_U,
409 .controller_address = 0x400e0800,
410 .flash_wait_states = 6, /* workaround silicon bug */
411 .present = 1,
412 .size_bytes = 64 * 1024,
413 .nsectors = 8,
414 .sector_size = 8192,
415 .page_size = 256,
416 },
417
418 /* .bank[1] = { */
419 {
420 .present = 0,
421 .probed = 0,
422 .bank_number = 1,
423 },
424 },
425 },
426
427 {
428 .chipid_cidr = 0x28000960,
429 .name = "at91sam3u4c",
430 .total_flash_size = 256 * 1024,
431 .total_sram_size = 52 * 1024,
432 .n_gpnvms = 3,
433 .n_banks = 2,
434
435 /* System boots at address 0x0 */
436 /* gpnvm[1] = selects boot code */
437 /* if gpnvm[1] == 0 */
438 /* boot is via "SAMBA" (rom) */
439 /* else */
440 /* boot is via FLASH */
441 /* Selection is via gpnvm[2] */
442 /* endif */
443 /* */
444 /* NOTE: banks 0 & 1 switch places */
445 /* if gpnvm[2] == 0 */
446 /* Bank0 is the boot rom */
447 /* else */
448 /* Bank1 is the boot rom */
449 /* endif */
450 {
451 {
452 /* .bank[0] = { */
453 .probed = 0,
454 .pChip = NULL,
455 .pBank = NULL,
456 .bank_number = 0,
457 .base_address = FLASH_BANK0_BASE_U,
458 .controller_address = 0x400e0800,
459 .flash_wait_states = 6, /* workaround silicon bug */
460 .present = 1,
461 .size_bytes = 128 * 1024,
462 .nsectors = 16,
463 .sector_size = 8192,
464 .page_size = 256,
465 },
466 /* .bank[1] = { */
467 {
468 .probed = 0,
469 .pChip = NULL,
470 .pBank = NULL,
471 .bank_number = 1,
472 .base_address = FLASH_BANK1_BASE_U,
473 .controller_address = 0x400e0a00,
474 .flash_wait_states = 6, /* workaround silicon bug */
475 .present = 1,
476 .size_bytes = 128 * 1024,
477 .nsectors = 16,
478 .sector_size = 8192,
479 .page_size = 256,
480 },
481 },
482 },
483
484 {
485 .chipid_cidr = 0x280a0760,
486 .name = "at91sam3u2c",
487 .total_flash_size = 128 * 1024,
488 .total_sram_size = 36 * 1024,
489 .n_gpnvms = 2,
490 .n_banks = 1,
491
492 /* System boots at address 0x0 */
493 /* gpnvm[1] = selects boot code */
494 /* if gpnvm[1] == 0 */
495 /* boot is via "SAMBA" (rom) */
496 /* else */
497 /* boot is via FLASH */
498 /* Selection is via gpnvm[2] */
499 /* endif */
500 {
501 /* .bank[0] = { */
502 {
503 .probed = 0,
504 .pChip = NULL,
505 .pBank = NULL,
506 .bank_number = 0,
507 .base_address = FLASH_BANK0_BASE_U,
508 .controller_address = 0x400e0800,
509 .flash_wait_states = 6, /* workaround silicon bug */
510 .present = 1,
511 .size_bytes = 128 * 1024,
512 .nsectors = 16,
513 .sector_size = 8192,
514 .page_size = 256,
515 },
516 /* .bank[1] = { */
517 {
518 .present = 0,
519 .probed = 0,
520 .bank_number = 1,
521 },
522 },
523 },
524 {
525 .chipid_cidr = 0x28090560,
526 .name = "at91sam3u1c",
527 .total_flash_size = 64 * 1024,
528 .total_sram_size = 20 * 1024,
529 .n_gpnvms = 2,
530 .n_banks = 1,
531
532 /* System boots at address 0x0 */
533 /* gpnvm[1] = selects boot code */
534 /* if gpnvm[1] == 0 */
535 /* boot is via "SAMBA" (rom) */
536 /* else */
537 /* boot is via FLASH */
538 /* Selection is via gpnvm[2] */
539 /* endif */
540 /* */
541
542 {
543 /* .bank[0] = { */
544 {
545 .probed = 0,
546 .pChip = NULL,
547 .pBank = NULL,
548 .bank_number = 0,
549 .base_address = FLASH_BANK0_BASE_U,
550 .controller_address = 0x400e0800,
551 .flash_wait_states = 6, /* workaround silicon bug */
552 .present = 1,
553 .size_bytes = 64 * 1024,
554 .nsectors = 8,
555 .sector_size = 8192,
556 .page_size = 256,
557 },
558 /* .bank[1] = { */
559 {
560 .present = 0,
561 .probed = 0,
562 .bank_number = 1,
563
564 },
565 },
566 },
567
568 /* Start at91sam3s* series */
569
570 /* Note: The preliminary at91sam3s datasheet says on page 302 */
571 /* that the flash controller is at address 0x400E0800. */
572 /* This is _not_ the case, the controller resides at address 0x400e0a0. */
573 {
574 .chipid_cidr = 0x28A00960,
575 .name = "at91sam3s4c",
576 .total_flash_size = 256 * 1024,
577 .total_sram_size = 48 * 1024,
578 .n_gpnvms = 2,
579 .n_banks = 1,
580 {
581 /* .bank[0] = { */
582 {
583 .probed = 0,
584 .pChip = NULL,
585 .pBank = NULL,
586 .bank_number = 0,
587 .base_address = FLASH_BANK_BASE_S,
588 .controller_address = 0x400e0a00,
589 .flash_wait_states = 6, /* workaround silicon bug */
590 .present = 1,
591 .size_bytes = 256 * 1024,
592 .nsectors = 16,
593 .sector_size = 16384,
594 .page_size = 256,
595 },
596 /* .bank[1] = { */
597 {
598 .present = 0,
599 .probed = 0,
600 .bank_number = 1,
601
602 },
603 },
604 },
605
606 {
607 .chipid_cidr = 0x28900960,
608 .name = "at91sam3s4b",
609 .total_flash_size = 256 * 1024,
610 .total_sram_size = 48 * 1024,
611 .n_gpnvms = 2,
612 .n_banks = 1,
613 {
614 /* .bank[0] = { */
615 {
616 .probed = 0,
617 .pChip = NULL,
618 .pBank = NULL,
619 .bank_number = 0,
620 .base_address = FLASH_BANK_BASE_S,
621 .controller_address = 0x400e0a00,
622 .flash_wait_states = 6, /* workaround silicon bug */
623 .present = 1,
624 .size_bytes = 256 * 1024,
625 .nsectors = 16,
626 .sector_size = 16384,
627 .page_size = 256,
628 },
629 /* .bank[1] = { */
630 {
631 .present = 0,
632 .probed = 0,
633 .bank_number = 1,
634
635 },
636 },
637 },
638 {
639 .chipid_cidr = 0x28800960,
640 .name = "at91sam3s4a",
641 .total_flash_size = 256 * 1024,
642 .total_sram_size = 48 * 1024,
643 .n_gpnvms = 2,
644 .n_banks = 1,
645 {
646 /* .bank[0] = { */
647 {
648 .probed = 0,
649 .pChip = NULL,
650 .pBank = NULL,
651 .bank_number = 0,
652 .base_address = FLASH_BANK_BASE_S,
653 .controller_address = 0x400e0a00,
654 .flash_wait_states = 6, /* workaround silicon bug */
655 .present = 1,
656 .size_bytes = 256 * 1024,
657 .nsectors = 16,
658 .sector_size = 16384,
659 .page_size = 256,
660 },
661 /* .bank[1] = { */
662 {
663 .present = 0,
664 .probed = 0,
665 .bank_number = 1,
666
667 },
668 },
669 },
670 {
671 .chipid_cidr = 0x28AA0760,
672 .name = "at91sam3s2c",
673 .total_flash_size = 128 * 1024,
674 .total_sram_size = 32 * 1024,
675 .n_gpnvms = 2,
676 .n_banks = 1,
677 {
678 /* .bank[0] = { */
679 {
680 .probed = 0,
681 .pChip = NULL,
682 .pBank = NULL,
683 .bank_number = 0,
684 .base_address = FLASH_BANK_BASE_S,
685 .controller_address = 0x400e0a00,
686 .flash_wait_states = 6, /* workaround silicon bug */
687 .present = 1,
688 .size_bytes = 128 * 1024,
689 .nsectors = 8,
690 .sector_size = 16384,
691 .page_size = 256,
692 },
693 /* .bank[1] = { */
694 {
695 .present = 0,
696 .probed = 0,
697 .bank_number = 1,
698
699 },
700 },
701 },
702 {
703 .chipid_cidr = 0x289A0760,
704 .name = "at91sam3s2b",
705 .total_flash_size = 128 * 1024,
706 .total_sram_size = 32 * 1024,
707 .n_gpnvms = 2,
708 .n_banks = 1,
709 {
710 /* .bank[0] = { */
711 {
712 .probed = 0,
713 .pChip = NULL,
714 .pBank = NULL,
715 .bank_number = 0,
716 .base_address = FLASH_BANK_BASE_S,
717 .controller_address = 0x400e0a00,
718 .flash_wait_states = 6, /* workaround silicon bug */
719 .present = 1,
720 .size_bytes = 128 * 1024,
721 .nsectors = 8,
722 .sector_size = 16384,
723 .page_size = 256,
724 },
725 /* .bank[1] = { */
726 {
727 .present = 0,
728 .probed = 0,
729 .bank_number = 1,
730
731 },
732 },
733 },
734 {
735 .chipid_cidr = 0x29ab0a60,
736 .name = "at91sam3sd8c",
737 .total_flash_size = 512 * 1024,
738 .total_sram_size = 64 * 1024,
739 .n_gpnvms = 3,
740 .n_banks = 2,
741 {
742 /* .bank[0] = { */
743 {
744 .probed = 0,
745 .pChip = NULL,
746 .pBank = NULL,
747 .bank_number = 0,
748 .base_address = FLASH_BANK0_BASE_SD,
749 .controller_address = 0x400e0a00,
750 .flash_wait_states = 6, /* workaround silicon bug */
751 .present = 1,
752 .size_bytes = 256 * 1024,
753 .nsectors = 16,
754 .sector_size = 32768,
755 .page_size = 256,
756 },
757 /* .bank[1] = { */
758 {
759 .probed = 0,
760 .pChip = NULL,
761 .pBank = NULL,
762 .bank_number = 1,
763 .base_address = FLASH_BANK1_BASE_512K_SD,
764 .controller_address = 0x400e0a00,
765 .flash_wait_states = 6, /* workaround silicon bug */
766 .present = 1,
767 .size_bytes = 256 * 1024,
768 .nsectors = 16,
769 .sector_size = 32768,
770 .page_size = 256,
771 },
772 },
773 },
774 {
775 .chipid_cidr = 0x288A0760,
776 .name = "at91sam3s2a",
777 .total_flash_size = 128 * 1024,
778 .total_sram_size = 32 * 1024,
779 .n_gpnvms = 2,
780 .n_banks = 1,
781 {
782 /* .bank[0] = { */
783 {
784 .probed = 0,
785 .pChip = NULL,
786 .pBank = NULL,
787 .bank_number = 0,
788 .base_address = FLASH_BANK_BASE_S,
789 .controller_address = 0x400e0a00,
790 .flash_wait_states = 6, /* workaround silicon bug */
791 .present = 1,
792 .size_bytes = 128 * 1024,
793 .nsectors = 8,
794 .sector_size = 16384,
795 .page_size = 256,
796 },
797 /* .bank[1] = { */
798 {
799 .present = 0,
800 .probed = 0,
801 .bank_number = 1,
802
803 },
804 },
805 },
806 {
807 .chipid_cidr = 0x28A90560,
808 .name = "at91sam3s1c",
809 .total_flash_size = 64 * 1024,
810 .total_sram_size = 16 * 1024,
811 .n_gpnvms = 2,
812 .n_banks = 1,
813 {
814 /* .bank[0] = { */
815 {
816 .probed = 0,
817 .pChip = NULL,
818 .pBank = NULL,
819 .bank_number = 0,
820 .base_address = FLASH_BANK_BASE_S,
821 .controller_address = 0x400e0a00,
822 .flash_wait_states = 6, /* workaround silicon bug */
823 .present = 1,
824 .size_bytes = 64 * 1024,
825 .nsectors = 4,
826 .sector_size = 16384,
827 .page_size = 256,
828 },
829 /* .bank[1] = { */
830 {
831 .present = 0,
832 .probed = 0,
833 .bank_number = 1,
834
835 },
836 },
837 },
838 {
839 .chipid_cidr = 0x28990560,
840 .name = "at91sam3s1b",
841 .total_flash_size = 64 * 1024,
842 .total_sram_size = 16 * 1024,
843 .n_gpnvms = 2,
844 .n_banks = 1,
845 {
846 /* .bank[0] = { */
847 {
848 .probed = 0,
849 .pChip = NULL,
850 .pBank = NULL,
851 .bank_number = 0,
852 .base_address = FLASH_BANK_BASE_S,
853 .controller_address = 0x400e0a00,
854 .flash_wait_states = 6, /* workaround silicon bug */
855 .present = 1,
856 .size_bytes = 64 * 1024,
857 .nsectors = 4,
858 .sector_size = 16384,
859 .page_size = 256,
860 },
861 /* .bank[1] = { */
862 {
863 .present = 0,
864 .probed = 0,
865 .bank_number = 1,
866
867 },
868 },
869 },
870 {
871 .chipid_cidr = 0x28890560,
872 .name = "at91sam3s1a",
873 .total_flash_size = 64 * 1024,
874 .total_sram_size = 16 * 1024,
875 .n_gpnvms = 2,
876 .n_banks = 1,
877 {
878 /* .bank[0] = { */
879 {
880 .probed = 0,
881 .pChip = NULL,
882 .pBank = NULL,
883 .bank_number = 0,
884 .base_address = FLASH_BANK_BASE_S,
885 .controller_address = 0x400e0a00,
886 .flash_wait_states = 6, /* workaround silicon bug */
887 .present = 1,
888 .size_bytes = 64 * 1024,
889 .nsectors = 4,
890 .sector_size = 16384,
891 .page_size = 256,
892 },
893 /* .bank[1] = { */
894 {
895 .present = 0,
896 .probed = 0,
897 .bank_number = 1,
898
899 },
900 },
901 },
902
903 /* Start at91sam3n* series */
904 {
905 .chipid_cidr = 0x29540960,
906 .name = "at91sam3n4c",
907 .total_flash_size = 256 * 1024,
908 .total_sram_size = 24 * 1024,
909 .n_gpnvms = 3,
910 .n_banks = 1,
911
912 /* System boots at address 0x0 */
913 /* gpnvm[1] = selects boot code */
914 /* if gpnvm[1] == 0 */
915 /* boot is via "SAMBA" (rom) */
916 /* else */
917 /* boot is via FLASH */
918 /* Selection is via gpnvm[2] */
919 /* endif */
920 /* */
921 /* NOTE: banks 0 & 1 switch places */
922 /* if gpnvm[2] == 0 */
923 /* Bank0 is the boot rom */
924 /* else */
925 /* Bank1 is the boot rom */
926 /* endif */
927 /* .bank[0] = { */
928 {
929 {
930 .probed = 0,
931 .pChip = NULL,
932 .pBank = NULL,
933 .bank_number = 0,
934 .base_address = FLASH_BANK_BASE_N,
935 .controller_address = 0x400e0A00,
936 .flash_wait_states = 6, /* workaround silicon bug */
937 .present = 1,
938 .size_bytes = 256 * 1024,
939 .nsectors = 16,
940 .sector_size = 16384,
941 .page_size = 256,
942 },
943
944 /* .bank[1] = { */
945 {
946 .present = 0,
947 .probed = 0,
948 .bank_number = 1,
949 },
950 },
951 },
952
953 {
954 .chipid_cidr = 0x29440960,
955 .name = "at91sam3n4b",
956 .total_flash_size = 256 * 1024,
957 .total_sram_size = 24 * 1024,
958 .n_gpnvms = 3,
959 .n_banks = 1,
960
961 /* System boots at address 0x0 */
962 /* gpnvm[1] = selects boot code */
963 /* if gpnvm[1] == 0 */
964 /* boot is via "SAMBA" (rom) */
965 /* else */
966 /* boot is via FLASH */
967 /* Selection is via gpnvm[2] */
968 /* endif */
969 /* */
970 /* NOTE: banks 0 & 1 switch places */
971 /* if gpnvm[2] == 0 */
972 /* Bank0 is the boot rom */
973 /* else */
974 /* Bank1 is the boot rom */
975 /* endif */
976 /* .bank[0] = { */
977 {
978 {
979 .probed = 0,
980 .pChip = NULL,
981 .pBank = NULL,
982 .bank_number = 0,
983 .base_address = FLASH_BANK_BASE_N,
984 .controller_address = 0x400e0A00,
985 .flash_wait_states = 6, /* workaround silicon bug */
986 .present = 1,
987 .size_bytes = 256 * 1024,
988 .nsectors = 16,
989 .sector_size = 16384,
990 .page_size = 256,
991 },
992
993 /* .bank[1] = { */
994 {
995 .present = 0,
996 .probed = 0,
997 .bank_number = 1,
998 },
999 },
1000 },
1001
1002 {
1003 .chipid_cidr = 0x29340960,
1004 .name = "at91sam3n4a",
1005 .total_flash_size = 256 * 1024,
1006 .total_sram_size = 24 * 1024,
1007 .n_gpnvms = 3,
1008 .n_banks = 1,
1009
1010 /* System boots at address 0x0 */
1011 /* gpnvm[1] = selects boot code */
1012 /* if gpnvm[1] == 0 */
1013 /* boot is via "SAMBA" (rom) */
1014 /* else */
1015 /* boot is via FLASH */
1016 /* Selection is via gpnvm[2] */
1017 /* endif */
1018 /* */
1019 /* NOTE: banks 0 & 1 switch places */
1020 /* if gpnvm[2] == 0 */
1021 /* Bank0 is the boot rom */
1022 /* else */
1023 /* Bank1 is the boot rom */
1024 /* endif */
1025 /* .bank[0] = { */
1026 {
1027 {
1028 .probed = 0,
1029 .pChip = NULL,
1030 .pBank = NULL,
1031 .bank_number = 0,
1032 .base_address = FLASH_BANK_BASE_N,
1033 .controller_address = 0x400e0A00,
1034 .flash_wait_states = 6, /* workaround silicon bug */
1035 .present = 1,
1036 .size_bytes = 256 * 1024,
1037 .nsectors = 16,
1038 .sector_size = 16384,
1039 .page_size = 256,
1040 },
1041
1042 /* .bank[1] = { */
1043 {
1044 .present = 0,
1045 .probed = 0,
1046 .bank_number = 1,
1047 },
1048 },
1049 },
1050
1051 {
1052 .chipid_cidr = 0x29590760,
1053 .name = "at91sam3n2c",
1054 .total_flash_size = 128 * 1024,
1055 .total_sram_size = 16 * 1024,
1056 .n_gpnvms = 3,
1057 .n_banks = 1,
1058
1059 /* System boots at address 0x0 */
1060 /* gpnvm[1] = selects boot code */
1061 /* if gpnvm[1] == 0 */
1062 /* boot is via "SAMBA" (rom) */
1063 /* else */
1064 /* boot is via FLASH */
1065 /* Selection is via gpnvm[2] */
1066 /* endif */
1067 /* */
1068 /* NOTE: banks 0 & 1 switch places */
1069 /* if gpnvm[2] == 0 */
1070 /* Bank0 is the boot rom */
1071 /* else */
1072 /* Bank1 is the boot rom */
1073 /* endif */
1074 /* .bank[0] = { */
1075 {
1076 {
1077 .probed = 0,
1078 .pChip = NULL,
1079 .pBank = NULL,
1080 .bank_number = 0,
1081 .base_address = FLASH_BANK_BASE_N,
1082 .controller_address = 0x400e0A00,
1083 .flash_wait_states = 6, /* workaround silicon bug */
1084 .present = 1,
1085 .size_bytes = 128 * 1024,
1086 .nsectors = 8,
1087 .sector_size = 16384,
1088 .page_size = 256,
1089 },
1090
1091 /* .bank[1] = { */
1092 {
1093 .present = 0,
1094 .probed = 0,
1095 .bank_number = 1,
1096 },
1097 },
1098 },
1099
1100 {
1101 .chipid_cidr = 0x29490760,
1102 .name = "at91sam3n2b",
1103 .total_flash_size = 128 * 1024,
1104 .total_sram_size = 16 * 1024,
1105 .n_gpnvms = 3,
1106 .n_banks = 1,
1107
1108 /* System boots at address 0x0 */
1109 /* gpnvm[1] = selects boot code */
1110 /* if gpnvm[1] == 0 */
1111 /* boot is via "SAMBA" (rom) */
1112 /* else */
1113 /* boot is via FLASH */
1114 /* Selection is via gpnvm[2] */
1115 /* endif */
1116 /* */
1117 /* NOTE: banks 0 & 1 switch places */
1118 /* if gpnvm[2] == 0 */
1119 /* Bank0 is the boot rom */
1120 /* else */
1121 /* Bank1 is the boot rom */
1122 /* endif */
1123 /* .bank[0] = { */
1124 {
1125 {
1126 .probed = 0,
1127 .pChip = NULL,
1128 .pBank = NULL,
1129 .bank_number = 0,
1130 .base_address = FLASH_BANK_BASE_N,
1131 .controller_address = 0x400e0A00,
1132 .flash_wait_states = 6, /* workaround silicon bug */
1133 .present = 1,
1134 .size_bytes = 128 * 1024,
1135 .nsectors = 8,
1136 .sector_size = 16384,
1137 .page_size = 256,
1138 },
1139
1140 /* .bank[1] = { */
1141 {
1142 .present = 0,
1143 .probed = 0,
1144 .bank_number = 1,
1145 },
1146 },
1147 },
1148
1149 {
1150 .chipid_cidr = 0x29390760,
1151 .name = "at91sam3n2a",
1152 .total_flash_size = 128 * 1024,
1153 .total_sram_size = 16 * 1024,
1154 .n_gpnvms = 3,
1155 .n_banks = 1,
1156
1157 /* System boots at address 0x0 */
1158 /* gpnvm[1] = selects boot code */
1159 /* if gpnvm[1] == 0 */
1160 /* boot is via "SAMBA" (rom) */
1161 /* else */
1162 /* boot is via FLASH */
1163 /* Selection is via gpnvm[2] */
1164 /* endif */
1165 /* */
1166 /* NOTE: banks 0 & 1 switch places */
1167 /* if gpnvm[2] == 0 */
1168 /* Bank0 is the boot rom */
1169 /* else */
1170 /* Bank1 is the boot rom */
1171 /* endif */
1172 /* .bank[0] = { */
1173 {
1174 {
1175 .probed = 0,
1176 .pChip = NULL,
1177 .pBank = NULL,
1178 .bank_number = 0,
1179 .base_address = FLASH_BANK_BASE_N,
1180 .controller_address = 0x400e0A00,
1181 .flash_wait_states = 6, /* workaround silicon bug */
1182 .present = 1,
1183 .size_bytes = 128 * 1024,
1184 .nsectors = 8,
1185 .sector_size = 16384,
1186 .page_size = 256,
1187 },
1188
1189 /* .bank[1] = { */
1190 {
1191 .present = 0,
1192 .probed = 0,
1193 .bank_number = 1,
1194 },
1195 },
1196 },
1197
1198 {
1199 .chipid_cidr = 0x29580560,
1200 .name = "at91sam3n1c",
1201 .total_flash_size = 64 * 1024,
1202 .total_sram_size = 8 * 1024,
1203 .n_gpnvms = 3,
1204 .n_banks = 1,
1205
1206 /* System boots at address 0x0 */
1207 /* gpnvm[1] = selects boot code */
1208 /* if gpnvm[1] == 0 */
1209 /* boot is via "SAMBA" (rom) */
1210 /* else */
1211 /* boot is via FLASH */
1212 /* Selection is via gpnvm[2] */
1213 /* endif */
1214 /* */
1215 /* NOTE: banks 0 & 1 switch places */
1216 /* if gpnvm[2] == 0 */
1217 /* Bank0 is the boot rom */
1218 /* else */
1219 /* Bank1 is the boot rom */
1220 /* endif */
1221 /* .bank[0] = { */
1222 {
1223 {
1224 .probed = 0,
1225 .pChip = NULL,
1226 .pBank = NULL,
1227 .bank_number = 0,
1228 .base_address = FLASH_BANK_BASE_N,
1229 .controller_address = 0x400e0A00,
1230 .flash_wait_states = 6, /* workaround silicon bug */
1231 .present = 1,
1232 .size_bytes = 64 * 1024,
1233 .nsectors = 4,
1234 .sector_size = 16384,
1235 .page_size = 256,
1236 },
1237
1238 /* .bank[1] = { */
1239 {
1240 .present = 0,
1241 .probed = 0,
1242 .bank_number = 1,
1243 },
1244 },
1245 },
1246
1247 {
1248 .chipid_cidr = 0x29480560,
1249 .name = "at91sam3n1b",
1250 .total_flash_size = 64 * 1024,
1251 .total_sram_size = 8 * 1024,
1252 .n_gpnvms = 3,
1253 .n_banks = 1,
1254
1255 /* System boots at address 0x0 */
1256 /* gpnvm[1] = selects boot code */
1257 /* if gpnvm[1] == 0 */
1258 /* boot is via "SAMBA" (rom) */
1259 /* else */
1260 /* boot is via FLASH */
1261 /* Selection is via gpnvm[2] */
1262 /* endif */
1263 /* */
1264 /* NOTE: banks 0 & 1 switch places */
1265 /* if gpnvm[2] == 0 */
1266 /* Bank0 is the boot rom */
1267 /* else */
1268 /* Bank1 is the boot rom */
1269 /* endif */
1270 /* .bank[0] = { */
1271 {
1272 {
1273 .probed = 0,
1274 .pChip = NULL,
1275 .pBank = NULL,
1276 .bank_number = 0,
1277 .base_address = FLASH_BANK_BASE_N,
1278 .controller_address = 0x400e0A00,
1279 .flash_wait_states = 6, /* workaround silicon bug */
1280 .present = 1,
1281 .size_bytes = 64 * 1024,
1282 .nsectors = 4,
1283 .sector_size = 16384,
1284 .page_size = 256,
1285 },
1286
1287 /* .bank[1] = { */
1288 {
1289 .present = 0,
1290 .probed = 0,
1291 .bank_number = 1,
1292 },
1293 },
1294 },
1295
1296 {
1297 .chipid_cidr = 0x29380560,
1298 .name = "at91sam3n1a",
1299 .total_flash_size = 64 * 1024,
1300 .total_sram_size = 8 * 1024,
1301 .n_gpnvms = 3,
1302 .n_banks = 1,
1303
1304 /* System boots at address 0x0 */
1305 /* gpnvm[1] = selects boot code */
1306 /* if gpnvm[1] == 0 */
1307 /* boot is via "SAMBA" (rom) */
1308 /* else */
1309 /* boot is via FLASH */
1310 /* Selection is via gpnvm[2] */
1311 /* endif */
1312 /* */
1313 /* NOTE: banks 0 & 1 switch places */
1314 /* if gpnvm[2] == 0 */
1315 /* Bank0 is the boot rom */
1316 /* else */
1317 /* Bank1 is the boot rom */
1318 /* endif */
1319 /* .bank[0] = { */
1320 {
1321 {
1322 .probed = 0,
1323 .pChip = NULL,
1324 .pBank = NULL,
1325 .bank_number = 0,
1326 .base_address = FLASH_BANK_BASE_N,
1327 .controller_address = 0x400e0A00,
1328 .flash_wait_states = 6, /* workaround silicon bug */
1329 .present = 1,
1330 .size_bytes = 64 * 1024,
1331 .nsectors = 4,
1332 .sector_size = 16384,
1333 .page_size = 256,
1334 },
1335
1336 /* .bank[1] = { */
1337 {
1338 .present = 0,
1339 .probed = 0,
1340 .bank_number = 1,
1341 },
1342 },
1343 },
1344
1345 /* Start at91sam3a series*/
1346 /* System boots at address 0x0 */
1347 /* gpnvm[1] = selects boot code */
1348 /* if gpnvm[1] == 0 */
1349 /* boot is via "SAMBA" (rom) */
1350 /* else */
1351 /* boot is via FLASH */
1352 /* Selection is via gpnvm[2] */
1353 /* endif */
1354 /* */
1355 /* NOTE: banks 0 & 1 switch places */
1356 /* if gpnvm[2] == 0 */
1357 /* Bank0 is the boot rom */
1358 /* else */
1359 /* Bank1 is the boot rom */
1360 /* endif */
1361
1362 {
1363 .chipid_cidr = 0x283E0A60,
1364 .name = "at91sam3a8c",
1365 .total_flash_size = 512 * 1024,
1366 .total_sram_size = 96 * 1024,
1367 .n_gpnvms = 3,
1368 .n_banks = 2,
1369 {
1370 /* .bank[0] = { */
1371 {
1372 .probed = 0,
1373 .pChip = NULL,
1374 .pBank = NULL,
1375 .bank_number = 0,
1376 .base_address = FLASH_BANK0_BASE_AX,
1377 .controller_address = 0x400e0a00,
1378 .flash_wait_states = 6, /* workaround silicon bug */
1379 .present = 1,
1380 .size_bytes = 256 * 1024,
1381 .nsectors = 16,
1382 .sector_size = 16384,
1383 .page_size = 256,
1384 },
1385 /* .bank[1] = { */
1386 {
1387 .probed = 0,
1388 .pChip = NULL,
1389 .pBank = NULL,
1390 .bank_number = 1,
1391 .base_address = FLASH_BANK1_BASE_512K_AX,
1392 .controller_address = 0x400e0c00,
1393 .flash_wait_states = 6, /* workaround silicon bug */
1394 .present = 1,
1395 .size_bytes = 256 * 1024,
1396 .nsectors = 16,
1397 .sector_size = 16384,
1398 .page_size = 256,
1399
1400 },
1401 },
1402 },
1403 {
1404 .chipid_cidr = 0x283B0960,
1405 .name = "at91sam3a4c",
1406 .total_flash_size = 256 * 1024,
1407 .total_sram_size = 64 * 1024,
1408 .n_gpnvms = 3,
1409 .n_banks = 2,
1410 {
1411 /* .bank[0] = { */
1412 {
1413 .probed = 0,
1414 .pChip = NULL,
1415 .pBank = NULL,
1416 .bank_number = 0,
1417 .base_address = FLASH_BANK0_BASE_AX,
1418 .controller_address = 0x400e0a00,
1419 .flash_wait_states = 6, /* workaround silicon bug */
1420 .present = 1,
1421 .size_bytes = 128 * 1024,
1422 .nsectors = 8,
1423 .sector_size = 16384,
1424 .page_size = 256,
1425 },
1426 /* .bank[1] = { */
1427 {
1428 .probed = 0,
1429 .pChip = NULL,
1430 .pBank = NULL,
1431 .bank_number = 1,
1432 .base_address = FLASH_BANK1_BASE_256K_AX,
1433 .controller_address = 0x400e0c00,
1434 .flash_wait_states = 6, /* workaround silicon bug */
1435 .present = 1,
1436 .size_bytes = 128 * 1024,
1437 .nsectors = 8,
1438 .sector_size = 16384,
1439 .page_size = 256,
1440
1441 },
1442 },
1443 },
1444
1445 /* Start at91sam3x* series */
1446 /* System boots at address 0x0 */
1447 /* gpnvm[1] = selects boot code */
1448 /* if gpnvm[1] == 0 */
1449 /* boot is via "SAMBA" (rom) */
1450 /* else */
1451 /* boot is via FLASH */
1452 /* Selection is via gpnvm[2] */
1453 /* endif */
1454 /* */
1455 /* NOTE: banks 0 & 1 switch places */
1456 /* if gpnvm[2] == 0 */
1457 /* Bank0 is the boot rom */
1458 /* else */
1459 /* Bank1 is the boot rom */
1460 /* endif */
1461 /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
1462 {
1463 .chipid_cidr = 0x286E0A20,
1464 .name = "at91sam3x8h - ES",
1465 .total_flash_size = 512 * 1024,
1466 .total_sram_size = 96 * 1024,
1467 .n_gpnvms = 3,
1468 .n_banks = 2,
1469 {
1470 /* .bank[0] = { */
1471 {
1472 .probed = 0,
1473 .pChip = NULL,
1474 .pBank = NULL,
1475 .bank_number = 0,
1476 .base_address = FLASH_BANK0_BASE_AX,
1477 .controller_address = 0x400e0a00,
1478 .flash_wait_states = 6, /* workaround silicon bug */
1479 .present = 1,
1480 .size_bytes = 256 * 1024,
1481 .nsectors = 16,
1482 .sector_size = 16384,
1483 .page_size = 256,
1484 },
1485 /* .bank[1] = { */
1486 {
1487 .probed = 0,
1488 .pChip = NULL,
1489 .pBank = NULL,
1490 .bank_number = 1,
1491 .base_address = FLASH_BANK1_BASE_512K_AX,
1492 .controller_address = 0x400e0c00,
1493 .flash_wait_states = 6, /* workaround silicon bug */
1494 .present = 1,
1495 .size_bytes = 256 * 1024,
1496 .nsectors = 16,
1497 .sector_size = 16384,
1498 .page_size = 256,
1499
1500 },
1501 },
1502 },
1503 /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
1504 {
1505 .chipid_cidr = 0x286E0A60,
1506 .name = "at91sam3x8h",
1507 .total_flash_size = 512 * 1024,
1508 .total_sram_size = 96 * 1024,
1509 .n_gpnvms = 3,
1510 .n_banks = 2,
1511 {
1512 /* .bank[0] = { */
1513 {
1514 .probed = 0,
1515 .pChip = NULL,
1516 .pBank = NULL,
1517 .bank_number = 0,
1518 .base_address = FLASH_BANK0_BASE_AX,
1519 .controller_address = 0x400e0a00,
1520 .flash_wait_states = 6, /* workaround silicon bug */
1521 .present = 1,
1522 .size_bytes = 256 * 1024,
1523 .nsectors = 16,
1524 .sector_size = 16384,
1525 .page_size = 256,
1526 },
1527 /* .bank[1] = { */
1528 {
1529 .probed = 0,
1530 .pChip = NULL,
1531 .pBank = NULL,
1532 .bank_number = 1,
1533 .base_address = FLASH_BANK1_BASE_512K_AX,
1534 .controller_address = 0x400e0c00,
1535 .flash_wait_states = 6, /* workaround silicon bug */
1536 .present = 1,
1537 .size_bytes = 256 * 1024,
1538 .nsectors = 16,
1539 .sector_size = 16384,
1540 .page_size = 256,
1541
1542 },
1543 },
1544 },
1545 {
1546 .chipid_cidr = 0x285E0A60,
1547 .name = "at91sam3x8e",
1548 .total_flash_size = 512 * 1024,
1549 .total_sram_size = 96 * 1024,
1550 .n_gpnvms = 3,
1551 .n_banks = 2,
1552 {
1553 /* .bank[0] = { */
1554 {
1555 .probed = 0,
1556 .pChip = NULL,
1557 .pBank = NULL,
1558 .bank_number = 0,
1559 .base_address = FLASH_BANK0_BASE_AX,
1560 .controller_address = 0x400e0a00,
1561 .flash_wait_states = 6, /* workaround silicon bug */
1562 .present = 1,
1563 .size_bytes = 256 * 1024,
1564 .nsectors = 16,
1565 .sector_size = 16384,
1566 .page_size = 256,
1567 },
1568 /* .bank[1] = { */
1569 {
1570 .probed = 0,
1571 .pChip = NULL,
1572 .pBank = NULL,
1573 .bank_number = 1,
1574 .base_address = FLASH_BANK1_BASE_512K_AX,
1575 .controller_address = 0x400e0c00,
1576 .flash_wait_states = 6, /* workaround silicon bug */
1577 .present = 1,
1578 .size_bytes = 256 * 1024,
1579 .nsectors = 16,
1580 .sector_size = 16384,
1581 .page_size = 256,
1582
1583 },
1584 },
1585 },
1586 {
1587 .chipid_cidr = 0x284E0A60,
1588 .name = "at91sam3x8c",
1589 .total_flash_size = 512 * 1024,
1590 .total_sram_size = 96 * 1024,
1591 .n_gpnvms = 3,
1592 .n_banks = 2,
1593 {
1594 /* .bank[0] = { */
1595 {
1596 .probed = 0,
1597 .pChip = NULL,
1598 .pBank = NULL,
1599 .bank_number = 0,
1600 .base_address = FLASH_BANK0_BASE_AX,
1601 .controller_address = 0x400e0a00,
1602 .flash_wait_states = 6, /* workaround silicon bug */
1603 .present = 1,
1604 .size_bytes = 256 * 1024,
1605 .nsectors = 16,
1606 .sector_size = 16384,
1607 .page_size = 256,
1608 },
1609 /* .bank[1] = { */
1610 {
1611 .probed = 0,
1612 .pChip = NULL,
1613 .pBank = NULL,
1614 .bank_number = 1,
1615 .base_address = FLASH_BANK1_BASE_512K_AX ,
1616 .controller_address = 0x400e0c00,
1617 .flash_wait_states = 6, /* workaround silicon bug */
1618 .present = 1,
1619 .size_bytes = 256 * 1024,
1620 .nsectors = 16,
1621 .sector_size = 16384,
1622 .page_size = 256,
1623
1624 },
1625 },
1626 },
1627 {
1628 .chipid_cidr = 0x285B0960,
1629 .name = "at91sam3x4e",
1630 .total_flash_size = 256 * 1024,
1631 .total_sram_size = 64 * 1024,
1632 .n_gpnvms = 3,
1633 .n_banks = 2,
1634 {
1635 /* .bank[0] = { */
1636 {
1637 .probed = 0,
1638 .pChip = NULL,
1639 .pBank = NULL,
1640 .bank_number = 0,
1641 .base_address = FLASH_BANK0_BASE_AX,
1642 .controller_address = 0x400e0a00,
1643 .flash_wait_states = 6, /* workaround silicon bug */
1644 .present = 1,
1645 .size_bytes = 128 * 1024,
1646 .nsectors = 8,
1647 .sector_size = 16384,
1648 .page_size = 256,
1649 },
1650 /* .bank[1] = { */
1651 {
1652 .probed = 0,
1653 .pChip = NULL,
1654 .pBank = NULL,
1655 .bank_number = 1,
1656 .base_address = FLASH_BANK1_BASE_256K_AX,
1657 .controller_address = 0x400e0c00,
1658 .flash_wait_states = 6, /* workaround silicon bug */
1659 .present = 1,
1660 .size_bytes = 128 * 1024,
1661 .nsectors = 8,
1662 .sector_size = 16384,
1663 .page_size = 256,
1664
1665 },
1666 },
1667 },
1668 {
1669 .chipid_cidr = 0x284B0960,
1670 .name = "at91sam3x4c",
1671 .total_flash_size = 256 * 1024,
1672 .total_sram_size = 64 * 1024,
1673 .n_gpnvms = 3,
1674 .n_banks = 2,
1675 {
1676 /* .bank[0] = { */
1677 {
1678 .probed = 0,
1679 .pChip = NULL,
1680 .pBank = NULL,
1681 .bank_number = 0,
1682 .base_address = FLASH_BANK0_BASE_AX,
1683 .controller_address = 0x400e0a00,
1684 .flash_wait_states = 6, /* workaround silicon bug */
1685 .present = 1,
1686 .size_bytes = 128 * 1024,
1687 .nsectors = 8,
1688 .sector_size = 16384,
1689 .page_size = 256,
1690 },
1691 /* .bank[1] = { */
1692 {
1693 .probed = 0,
1694 .pChip = NULL,
1695 .pBank = NULL,
1696 .bank_number = 1,
1697 .base_address = FLASH_BANK1_BASE_256K_AX,
1698 .controller_address = 0x400e0c00,
1699 .flash_wait_states = 6, /* workaround silicon bug */
1700 .present = 1,
1701 .size_bytes = 128 * 1024,
1702 .nsectors = 8,
1703 .sector_size = 16384,
1704 .page_size = 256,
1705
1706 },
1707 },
1708 },
1709 /* terminate */
1710 {
1711 .chipid_cidr = 0,
1712 .name = NULL,
1713 }
1714 };
1715
1716 /* Globals above */
1717 /***********************************************************************
1718 **********************************************************************
1719 **********************************************************************
1720 **********************************************************************
1721 **********************************************************************
1722 **********************************************************************/
1723 /* *ATMEL* style code - from the SAM3 driver code */
1724
1725 /**
1726 * Get the current status of the EEFC and
1727 * the value of some status bits (LOCKE, PROGE).
1728 * @param pPrivate - info about the bank
1729 * @param v - result goes here
1730 */
1731 static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
1732 {
1733 int r;
1734 r = target_read_u32(pPrivate->pChip->target,
1735 pPrivate->controller_address + offset_EFC_FSR,
1736 v);
1737 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1738 (unsigned int)(*v),
1739 ((unsigned int)((*v >> 2) & 1)),
1740 ((unsigned int)((*v >> 1) & 1)),
1741 ((unsigned int)((*v >> 0) & 1)));
1742
1743 return r;
1744 }
1745
1746 /**
1747 * Get the result of the last executed command.
1748 * @param pPrivate - info about the bank
1749 * @param v - result goes here
1750 */
1751 static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
1752 {
1753 int r;
1754 uint32_t rv;
1755 r = target_read_u32(pPrivate->pChip->target,
1756 pPrivate->controller_address + offset_EFC_FRR,
1757 &rv);
1758 if (v)
1759 *v = rv;
1760 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
1761 return r;
1762 }
1763
1764 static int EFC_StartCommand(struct sam3_bank_private *pPrivate,
1765 unsigned command, unsigned argument)
1766 {
1767 uint32_t n, v;
1768 int r;
1769 int retry;
1770
1771 retry = 0;
1772 do_retry:
1773
1774 /* Check command & argument */
1775 switch (command) {
1776
1777 case AT91C_EFC_FCMD_WP:
1778 case AT91C_EFC_FCMD_WPL:
1779 case AT91C_EFC_FCMD_EWP:
1780 case AT91C_EFC_FCMD_EWPL:
1781 /* case AT91C_EFC_FCMD_EPL: */
1782 /* case AT91C_EFC_FCMD_EPA: */
1783 case AT91C_EFC_FCMD_SLB:
1784 case AT91C_EFC_FCMD_CLB:
1785 n = (pPrivate->size_bytes / pPrivate->page_size);
1786 if (argument >= n)
1787 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
1788 break;
1789
1790 case AT91C_EFC_FCMD_SFB:
1791 case AT91C_EFC_FCMD_CFB:
1792 if (argument >= pPrivate->pChip->details.n_gpnvms) {
1793 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1794 pPrivate->pChip->details.n_gpnvms);
1795 }
1796 break;
1797
1798 case AT91C_EFC_FCMD_GETD:
1799 case AT91C_EFC_FCMD_EA:
1800 case AT91C_EFC_FCMD_GLB:
1801 case AT91C_EFC_FCMD_GFB:
1802 case AT91C_EFC_FCMD_STUI:
1803 case AT91C_EFC_FCMD_SPUI:
1804 if (argument != 0)
1805 LOG_ERROR("Argument is meaningless for cmd: %d", command);
1806 break;
1807 default:
1808 LOG_ERROR("Unknown command %d", command);
1809 break;
1810 }
1811
1812 if (command == AT91C_EFC_FCMD_SPUI) {
1813 /* this is a very special situation. */
1814 /* Situation (1) - error/retry - see below */
1815 /* And we are being called recursively */
1816 /* Situation (2) - normal, finished reading unique id */
1817 } else {
1818 /* it should be "ready" */
1819 EFC_GetStatus(pPrivate, &v);
1820 if (v & 1) {
1821 /* then it is ready */
1822 /* we go on */
1823 } else {
1824 if (retry) {
1825 /* we have done this before */
1826 /* the controller is not responding. */
1827 LOG_ERROR("flash controller(%d) is not ready! Error",
1828 pPrivate->bank_number);
1829 return ERROR_FAIL;
1830 } else {
1831 retry++;
1832 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1833 pPrivate->bank_number);
1834 /* we do that by issuing the *STOP* command */
1835 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
1836 /* above is recursive, and further recursion is blocked by */
1837 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1838 goto do_retry;
1839 }
1840 }
1841 }
1842
1843 v = (0x5A << 24) | (argument << 8) | command;
1844 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
1845 r = target_write_u32(pPrivate->pBank->target,
1846 pPrivate->controller_address + offset_EFC_FCR, v);
1847 if (r != ERROR_OK)
1848 LOG_DEBUG("Error Write failed");
1849 return r;
1850 }
1851
1852 /**
1853 * Performs the given command and wait until its completion (or an error).
1854 * @param pPrivate - info about the bank
1855 * @param command - Command to perform.
1856 * @param argument - Optional command argument.
1857 * @param status - put command status bits here
1858 */
1859 static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
1860 unsigned command,
1861 unsigned argument,
1862 uint32_t *status)
1863 {
1864
1865 int r;
1866 uint32_t v;
1867 long long ms_now, ms_end;
1868
1869 /* default */
1870 if (status)
1871 *status = 0;
1872
1873 r = EFC_StartCommand(pPrivate, command, argument);
1874 if (r != ERROR_OK)
1875 return r;
1876
1877 ms_end = 500 + timeval_ms();
1878
1879 do {
1880 r = EFC_GetStatus(pPrivate, &v);
1881 if (r != ERROR_OK)
1882 return r;
1883 ms_now = timeval_ms();
1884 if (ms_now > ms_end) {
1885 /* error */
1886 LOG_ERROR("Command timeout");
1887 return ERROR_FAIL;
1888 }
1889 } while ((v & 1) == 0);
1890
1891 /* error bits.. */
1892 if (status)
1893 *status = (v & 0x6);
1894 return ERROR_OK;
1895
1896 }
1897
1898 /**
1899 * Read the unique ID.
1900 * @param pPrivate - info about the bank
1901 * The unique ID is stored in the 'pPrivate' structure.
1902 */
1903 static int FLASHD_ReadUniqueID(struct sam3_bank_private *pPrivate)
1904 {
1905 int r;
1906 uint32_t v;
1907 int x;
1908 /* assume 0 */
1909 pPrivate->pChip->cfg.unique_id[0] = 0;
1910 pPrivate->pChip->cfg.unique_id[1] = 0;
1911 pPrivate->pChip->cfg.unique_id[2] = 0;
1912 pPrivate->pChip->cfg.unique_id[3] = 0;
1913
1914 LOG_DEBUG("Begin");
1915 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
1916 if (r < 0)
1917 return r;
1918
1919 for (x = 0; x < 4; x++) {
1920 r = target_read_u32(pPrivate->pChip->target,
1921 pPrivate->pBank->base + (x * 4),
1922 &v);
1923 if (r < 0)
1924 return r;
1925 pPrivate->pChip->cfg.unique_id[x] = v;
1926 }
1927
1928 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
1929 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1930 r,
1931 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
1932 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
1933 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
1934 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
1935 return r;
1936
1937 }
1938
1939 /**
1940 * Erases the entire flash.
1941 * @param pPrivate - the info about the bank.
1942 */
1943 static int FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
1944 {
1945 LOG_DEBUG("Here");
1946 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
1947 }
1948
1949 /**
1950 * Gets current GPNVM state.
1951 * @param pPrivate - info about the bank.
1952 * @param gpnvm - GPNVM bit index.
1953 * @param puthere - result stored here.
1954 */
1955 /* ------------------------------------------------------------------------------ */
1956 static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
1957 {
1958 uint32_t v;
1959 int r;
1960
1961 LOG_DEBUG("Here");
1962 if (pPrivate->bank_number != 0) {
1963 LOG_ERROR("GPNVM only works with Bank0");
1964 return ERROR_FAIL;
1965 }
1966
1967 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1968 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1969 gpnvm, pPrivate->pChip->details.n_gpnvms);
1970 return ERROR_FAIL;
1971 }
1972
1973 /* Get GPNVMs status */
1974 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
1975 if (r != ERROR_OK) {
1976 LOG_ERROR("Failed");
1977 return r;
1978 }
1979
1980 r = EFC_GetResult(pPrivate, &v);
1981
1982 if (puthere) {
1983 /* Check if GPNVM is set */
1984 /* get the bit and make it a 0/1 */
1985 *puthere = (v >> gpnvm) & 1;
1986 }
1987
1988 return r;
1989 }
1990
1991 /**
1992 * Clears the selected GPNVM bit.
1993 * @param pPrivate info about the bank
1994 * @param gpnvm GPNVM index.
1995 * @returns 0 if successful; otherwise returns an error code.
1996 */
1997 static int FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
1998 {
1999 int r;
2000 unsigned v;
2001
2002 LOG_DEBUG("Here");
2003 if (pPrivate->bank_number != 0) {
2004 LOG_ERROR("GPNVM only works with Bank0");
2005 return ERROR_FAIL;
2006 }
2007
2008 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2009 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2010 gpnvm, pPrivate->pChip->details.n_gpnvms);
2011 return ERROR_FAIL;
2012 }
2013
2014 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
2015 if (r != ERROR_OK) {
2016 LOG_DEBUG("Failed: %d", r);
2017 return r;
2018 }
2019 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
2020 LOG_DEBUG("End: %d", r);
2021 return r;
2022 }
2023
2024 /**
2025 * Sets the selected GPNVM bit.
2026 * @param pPrivate info about the bank
2027 * @param gpnvm GPNVM index.
2028 */
2029 static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
2030 {
2031 int r;
2032 unsigned v;
2033
2034 if (pPrivate->bank_number != 0) {
2035 LOG_ERROR("GPNVM only works with Bank0");
2036 return ERROR_FAIL;
2037 }
2038
2039 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2040 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2041 gpnvm, pPrivate->pChip->details.n_gpnvms);
2042 return ERROR_FAIL;
2043 }
2044
2045 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
2046 if (r != ERROR_OK)
2047 return r;
2048 if (v) {
2049 /* already set */
2050 r = ERROR_OK;
2051 } else {
2052 /* set it */
2053 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
2054 }
2055 return r;
2056 }
2057
2058 /**
2059 * Returns a bit field (at most 64) of locked regions within a page.
2060 * @param pPrivate info about the bank
2061 * @param v where to store locked bits
2062 */
2063 static int FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
2064 {
2065 int r;
2066 LOG_DEBUG("Here");
2067 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
2068 if (r == ERROR_OK)
2069 r = EFC_GetResult(pPrivate, v);
2070 LOG_DEBUG("End: %d", r);
2071 return r;
2072 }
2073
2074 /**
2075 * Unlocks all the regions in the given address range.
2076 * @param pPrivate info about the bank
2077 * @param start_sector first sector to unlock
2078 * @param end_sector last (inclusive) to unlock
2079 */
2080
2081 static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
2082 unsigned start_sector,
2083 unsigned end_sector)
2084 {
2085 int r;
2086 uint32_t status;
2087 uint32_t pg;
2088 uint32_t pages_per_sector;
2089
2090 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2091
2092 /* Unlock all pages */
2093 while (start_sector <= end_sector) {
2094 pg = start_sector * pages_per_sector;
2095
2096 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
2097 if (r != ERROR_OK)
2098 return r;
2099 start_sector++;
2100 }
2101
2102 return ERROR_OK;
2103 }
2104
2105 /**
2106 * Locks regions
2107 * @param pPrivate - info about the bank
2108 * @param start_sector - first sector to lock
2109 * @param end_sector - last sector (inclusive) to lock
2110 */
2111 static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
2112 unsigned start_sector,
2113 unsigned end_sector)
2114 {
2115 uint32_t status;
2116 uint32_t pg;
2117 uint32_t pages_per_sector;
2118 int r;
2119
2120 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2121
2122 /* Lock all pages */
2123 while (start_sector <= end_sector) {
2124 pg = start_sector * pages_per_sector;
2125
2126 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
2127 if (r != ERROR_OK)
2128 return r;
2129 start_sector++;
2130 }
2131 return ERROR_OK;
2132 }
2133
2134 /****** END SAM3 CODE ********/
2135
2136 /* begin helpful debug code */
2137 /* print the fieldname, the field value, in dec & hex, and return field value */
2138 static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip,
2139 const char *regname,
2140 uint32_t value,
2141 unsigned shift,
2142 unsigned width)
2143 {
2144 uint32_t v;
2145 int hwidth, dwidth;
2146
2147
2148 /* extract the field */
2149 v = value >> shift;
2150 v = v & ((1 << width)-1);
2151 if (width <= 16) {
2152 hwidth = 4;
2153 dwidth = 5;
2154 } else {
2155 hwidth = 8;
2156 dwidth = 12;
2157 }
2158
2159 /* show the basics */
2160 LOG_USER_N("\t%*s: %*d [0x%0*x] ",
2161 REG_NAME_WIDTH, regname,
2162 dwidth, v,
2163 hwidth, v);
2164 return v;
2165 }
2166
2167 static const char _unknown[] = "unknown";
2168 static const char *const eproc_names[] = {
2169 _unknown, /* 0 */
2170 "arm946es", /* 1 */
2171 "arm7tdmi", /* 2 */
2172 "cortex-m3", /* 3 */
2173 "arm920t", /* 4 */
2174 "arm926ejs", /* 5 */
2175 _unknown, /* 6 */
2176 _unknown, /* 7 */
2177 _unknown, /* 8 */
2178 _unknown, /* 9 */
2179 _unknown, /* 10 */
2180 _unknown, /* 11 */
2181 _unknown, /* 12 */
2182 _unknown, /* 13 */
2183 _unknown, /* 14 */
2184 _unknown, /* 15 */
2185 };
2186
2187 #define nvpsize2 nvpsize /* these two tables are identical */
2188 static const char *const nvpsize[] = {
2189 "none", /* 0 */
2190 "8K bytes", /* 1 */
2191 "16K bytes", /* 2 */
2192 "32K bytes", /* 3 */
2193 _unknown, /* 4 */
2194 "64K bytes", /* 5 */
2195 _unknown, /* 6 */
2196 "128K bytes", /* 7 */
2197 _unknown, /* 8 */
2198 "256K bytes", /* 9 */
2199 "512K bytes", /* 10 */
2200 _unknown, /* 11 */
2201 "1024K bytes", /* 12 */
2202 _unknown, /* 13 */
2203 "2048K bytes", /* 14 */
2204 _unknown, /* 15 */
2205 };
2206
2207 static const char *const sramsize[] = {
2208 "48K Bytes", /* 0 */
2209 "1K Bytes", /* 1 */
2210 "2K Bytes", /* 2 */
2211 "6K Bytes", /* 3 */
2212 "112K Bytes", /* 4 */
2213 "4K Bytes", /* 5 */
2214 "80K Bytes", /* 6 */
2215 "160K Bytes", /* 7 */
2216 "8K Bytes", /* 8 */
2217 "16K Bytes", /* 9 */
2218 "32K Bytes", /* 10 */
2219 "64K Bytes", /* 11 */
2220 "128K Bytes", /* 12 */
2221 "256K Bytes", /* 13 */
2222 "96K Bytes", /* 14 */
2223 "512K Bytes", /* 15 */
2224
2225 };
2226
2227 static const struct archnames { unsigned value; const char *name; } archnames[] = {
2228 { 0x19, "AT91SAM9xx Series" },
2229 { 0x29, "AT91SAM9XExx Series" },
2230 { 0x34, "AT91x34 Series" },
2231 { 0x37, "CAP7 Series" },
2232 { 0x39, "CAP9 Series" },
2233 { 0x3B, "CAP11 Series" },
2234 { 0x40, "AT91x40 Series" },
2235 { 0x42, "AT91x42 Series" },
2236 { 0x55, "AT91x55 Series" },
2237 { 0x60, "AT91SAM7Axx Series" },
2238 { 0x61, "AT91SAM7AQxx Series" },
2239 { 0x63, "AT91x63 Series" },
2240 { 0x70, "AT91SAM7Sxx Series" },
2241 { 0x71, "AT91SAM7XCxx Series" },
2242 { 0x72, "AT91SAM7SExx Series" },
2243 { 0x73, "AT91SAM7Lxx Series" },
2244 { 0x75, "AT91SAM7Xxx Series" },
2245 { 0x76, "AT91SAM7SLxx Series" },
2246 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2247 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2248 { 0x83, "ATSAM3AxC Series (100-pin version)" },
2249 { 0x84, "ATSAM3XxC Series (100-pin version)" },
2250 { 0x85, "ATSAM3XxE Series (144-pin version)" },
2251 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
2252 { 0x88, "ATSAM3SxA Series (48-pin version)" },
2253 { 0x89, "ATSAM3SxB Series (64-pin version)" },
2254 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
2255 { 0x92, "AT91x92 Series" },
2256 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2257 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2258 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2259 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2260 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2261 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2262 { 0xA5, "ATSAM5A" },
2263 { 0xF0, "AT75Cxx Series" },
2264 { -1, NULL },
2265 };
2266
2267 static const char *const nvptype[] = {
2268 "rom", /* 0 */
2269 "romless or onchip flash", /* 1 */
2270 "embedded flash memory",/* 2 */
2271 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2272 "sram emulating flash", /* 4 */
2273 _unknown, /* 5 */
2274 _unknown, /* 6 */
2275 _unknown, /* 7 */
2276 };
2277
2278 static const char *_yes_or_no(uint32_t v)
2279 {
2280 if (v)
2281 return "YES";
2282 else
2283 return "NO";
2284 }
2285
2286 static const char *const _rc_freq[] = {
2287 "4 MHz", "8 MHz", "12 MHz", "reserved"
2288 };
2289
2290 static void sam3_explain_ckgr_mor(struct sam3_chip *pChip)
2291 {
2292 uint32_t v;
2293 uint32_t rcen;
2294
2295 v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
2296 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2297 v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
2298 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2299 rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
2300 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2301 v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
2302 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2303
2304 pChip->cfg.rc_freq = 0;
2305 if (rcen) {
2306 switch (v) {
2307 default:
2308 pChip->cfg.rc_freq = 0;
2309 break;
2310 case 0:
2311 pChip->cfg.rc_freq = 4 * 1000 * 1000;
2312 break;
2313 case 1:
2314 pChip->cfg.rc_freq = 8 * 1000 * 1000;
2315 break;
2316 case 2:
2317 pChip->cfg.rc_freq = 12 * 1000 * 1000;
2318 break;
2319 }
2320 }
2321
2322 v = sam3_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
2323 LOG_USER("(startup clks, time= %f uSecs)",
2324 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
2325 v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
2326 LOG_USER("(mainosc source: %s)",
2327 v ? "external xtal" : "internal RC");
2328
2329 v = sam3_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
2330 LOG_USER("(clock failure enabled: %s)",
2331 _yes_or_no(v));
2332 }
2333
2334 static void sam3_explain_chipid_cidr(struct sam3_chip *pChip)
2335 {
2336 int x;
2337 uint32_t v;
2338 const char *cp;
2339
2340 sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
2341 LOG_USER_N("\n");
2342
2343 v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
2344 LOG_USER("%s", eproc_names[v]);
2345
2346 v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
2347 LOG_USER("%s", nvpsize[v]);
2348
2349 v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
2350 LOG_USER("%s", nvpsize2[v]);
2351
2352 v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
2353 LOG_USER("%s", sramsize[v]);
2354
2355 v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
2356 cp = _unknown;
2357 for (x = 0; archnames[x].name; x++) {
2358 if (v == archnames[x].value) {
2359 cp = archnames[x].name;
2360 break;
2361 }
2362 }
2363
2364 LOG_USER("%s", cp);
2365
2366 v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
2367 LOG_USER("%s", nvptype[v]);
2368
2369 v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
2370 LOG_USER("(exists: %s)", _yes_or_no(v));
2371 }
2372
2373 static void sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
2374 {
2375 uint32_t v;
2376
2377 v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
2378 LOG_USER("(main ready: %s)", _yes_or_no(v));
2379
2380 v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
2381
2382 v = (v * pChip->cfg.slow_freq) / 16;
2383 pChip->cfg.mainosc_freq = v;
2384
2385 LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
2386 _tomhz(v),
2387 pChip->cfg.slow_freq / 1000,
2388 pChip->cfg.slow_freq % 1000);
2389 }
2390
2391 static void sam3_explain_ckgr_plla(struct sam3_chip *pChip)
2392 {
2393 uint32_t mula, diva;
2394
2395 diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
2396 LOG_USER_N("\n");
2397 mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
2398 LOG_USER_N("\n");
2399 pChip->cfg.plla_freq = 0;
2400 if (mula == 0)
2401 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2402 else if (diva == 0)
2403 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2404 else if (diva >= 1) {
2405 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
2406 LOG_USER("\tPLLA Freq: %3.03f MHz",
2407 _tomhz(pChip->cfg.plla_freq));
2408 }
2409 }
2410
2411 static void sam3_explain_mckr(struct sam3_chip *pChip)
2412 {
2413 uint32_t css, pres, fin = 0;
2414 int pdiv = 0;
2415 const char *cp = NULL;
2416
2417 css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
2418 switch (css & 3) {
2419 case 0:
2420 fin = pChip->cfg.slow_freq;
2421 cp = "slowclk";
2422 break;
2423 case 1:
2424 fin = pChip->cfg.mainosc_freq;
2425 cp = "mainosc";
2426 break;
2427 case 2:
2428 fin = pChip->cfg.plla_freq;
2429 cp = "plla";
2430 break;
2431 case 3:
2432 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
2433 fin = 480 * 1000 * 1000;
2434 cp = "upll";
2435 } else {
2436 fin = 0;
2437 cp = "upll (*ERROR* UPLL is disabled)";
2438 }
2439 break;
2440 default:
2441 assert(0);
2442 break;
2443 }
2444
2445 LOG_USER("%s (%3.03f Mhz)",
2446 cp,
2447 _tomhz(fin));
2448 pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
2449 switch (pres & 0x07) {
2450 case 0:
2451 pdiv = 1;
2452 cp = "selected clock";
2453 break;
2454 case 1:
2455 pdiv = 2;
2456 cp = "clock/2";
2457 break;
2458 case 2:
2459 pdiv = 4;
2460 cp = "clock/4";
2461 break;
2462 case 3:
2463 pdiv = 8;
2464 cp = "clock/8";
2465 break;
2466 case 4:
2467 pdiv = 16;
2468 cp = "clock/16";
2469 break;
2470 case 5:
2471 pdiv = 32;
2472 cp = "clock/32";
2473 break;
2474 case 6:
2475 pdiv = 64;
2476 cp = "clock/64";
2477 break;
2478 case 7:
2479 pdiv = 6;
2480 cp = "clock/6";
2481 break;
2482 default:
2483 assert(0);
2484 break;
2485 }
2486 LOG_USER("(%s)", cp);
2487 fin = fin / pdiv;
2488 /* sam3 has a *SINGLE* clock - */
2489 /* other at91 series parts have divisors for these. */
2490 pChip->cfg.cpu_freq = fin;
2491 pChip->cfg.mclk_freq = fin;
2492 pChip->cfg.fclk_freq = fin;
2493 LOG_USER("\t\tResult CPU Freq: %3.03f",
2494 _tomhz(fin));
2495 }
2496
2497 #if 0
2498 static struct sam3_chip *target2sam3(struct target *pTarget)
2499 {
2500 struct sam3_chip *pChip;
2501
2502 if (pTarget == NULL)
2503 return NULL;
2504
2505 pChip = all_sam3_chips;
2506 while (pChip) {
2507 if (pChip->target == pTarget)
2508 break; /* return below */
2509 else
2510 pChip = pChip->next;
2511 }
2512 return pChip;
2513 }
2514 #endif
2515
2516 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
2517 {
2518 /* this function exists to help */
2519 /* keep funky offsetof() errors */
2520 /* and casting from causing bugs */
2521
2522 /* By using prototypes - we can detect what would */
2523 /* be casting errors. */
2524
2525 return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
2526 }
2527
2528
2529 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2530 struct sam3_cfg, \
2531 NAME), # NAME, FUNC }
2532 static const struct sam3_reg_list sam3_all_regs[] = {
2533 SAM3_ENTRY(CKGR_MOR, sam3_explain_ckgr_mor),
2534 SAM3_ENTRY(CKGR_MCFR, sam3_explain_ckgr_mcfr),
2535 SAM3_ENTRY(CKGR_PLLAR, sam3_explain_ckgr_plla),
2536 SAM3_ENTRY(CKGR_UCKR, NULL),
2537 SAM3_ENTRY(PMC_FSMR, NULL),
2538 SAM3_ENTRY(PMC_FSPR, NULL),
2539 SAM3_ENTRY(PMC_IMR, NULL),
2540 SAM3_ENTRY(PMC_MCKR, sam3_explain_mckr),
2541 SAM3_ENTRY(PMC_PCK0, NULL),
2542 SAM3_ENTRY(PMC_PCK1, NULL),
2543 SAM3_ENTRY(PMC_PCK2, NULL),
2544 SAM3_ENTRY(PMC_PCSR, NULL),
2545 SAM3_ENTRY(PMC_SCSR, NULL),
2546 SAM3_ENTRY(PMC_SR, NULL),
2547 SAM3_ENTRY(CHIPID_CIDR, sam3_explain_chipid_cidr),
2548 SAM3_ENTRY(CHIPID_CIDR2, sam3_explain_chipid_cidr),
2549 SAM3_ENTRY(CHIPID_EXID, NULL),
2550 SAM3_ENTRY(CHIPID_EXID2, NULL),
2551 /* TERMINATE THE LIST */
2552 { .name = NULL }
2553 };
2554 #undef SAM3_ENTRY
2555
2556 static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank)
2557 {
2558 return (struct sam3_bank_private *)(bank->driver_priv);
2559 }
2560
2561 /**
2562 * Given a pointer to where it goes in the structure,
2563 * determine the register name, address from the all registers table.
2564 */
2565 static const struct sam3_reg_list *sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
2566 {
2567 const struct sam3_reg_list *pReg;
2568
2569 pReg = &(sam3_all_regs[0]);
2570 while (pReg->name) {
2571 uint32_t *pPossible;
2572
2573 /* calculate where this one go.. */
2574 /* it is "possibly" this register. */
2575
2576 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
2577
2578 /* well? Is it this register */
2579 if (pPossible == goes_here) {
2580 /* Jump for joy! */
2581 return pReg;
2582 }
2583
2584 /* next... */
2585 pReg++;
2586 }
2587 /* This is *TOTAL*PANIC* - we are totally screwed. */
2588 LOG_ERROR("INVALID SAM3 REGISTER");
2589 return NULL;
2590 }
2591
2592 static int sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
2593 {
2594 const struct sam3_reg_list *pReg;
2595 int r;
2596
2597 pReg = sam3_GetReg(pChip, goes_here);
2598 if (!pReg)
2599 return ERROR_FAIL;
2600
2601 r = target_read_u32(pChip->target, pReg->address, goes_here);
2602 if (r != ERROR_OK) {
2603 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2604 pReg->name, (unsigned)(pReg->address), r);
2605 }
2606 return r;
2607 }
2608
2609 static int sam3_ReadAllRegs(struct sam3_chip *pChip)
2610 {
2611 int r;
2612 const struct sam3_reg_list *pReg;
2613
2614 pReg = &(sam3_all_regs[0]);
2615 while (pReg->name) {
2616 r = sam3_ReadThisReg(pChip,
2617 sam3_get_reg_ptr(&(pChip->cfg), pReg));
2618 if (r != ERROR_OK) {
2619 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Error: %d",
2620 pReg->name, ((unsigned)(pReg->address)), r);
2621 return r;
2622 }
2623 pReg++;
2624 }
2625
2626 /* Chip identification register
2627 *
2628 * Unfortunately, the chip identification register is not at
2629 * a constant address across all of the SAM3 series'. As a
2630 * consequence, a simple heuristic is used to find where it's
2631 * at...
2632 *
2633 * If the contents at the first address is zero, then we know
2634 * that the second address is where the chip id register is.
2635 * We can deduce this because for those SAM's that have the
2636 * chip id @ 0x400e0940, the first address, 0x400e0740, is
2637 * located in the memory map of the Power Management Controller
2638 * (PMC). Furthermore, the address is not used by the PMC.
2639 * So when read, the memory controller returns zero.*/
2640 if (pChip->cfg.CHIPID_CIDR == 0) {
2641 /*Put the correct CIDR and EXID values in the pChip structure */
2642 pChip->cfg.CHIPID_CIDR = pChip->cfg.CHIPID_CIDR2;
2643 pChip->cfg.CHIPID_EXID = pChip->cfg.CHIPID_EXID2;
2644 }
2645 return ERROR_OK;
2646 }
2647
2648 static int sam3_GetInfo(struct sam3_chip *pChip)
2649 {
2650 const struct sam3_reg_list *pReg;
2651 uint32_t regval;
2652
2653 pReg = &(sam3_all_regs[0]);
2654 while (pReg->name) {
2655 /* display all regs */
2656 LOG_DEBUG("Start: %s", pReg->name);
2657 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
2658 LOG_USER("%*s: [0x%08x] -> 0x%08x",
2659 REG_NAME_WIDTH,
2660 pReg->name,
2661 pReg->address,
2662 regval);
2663 if (pReg->explain_func)
2664 (*(pReg->explain_func))(pChip);
2665 LOG_DEBUG("End: %s", pReg->name);
2666 pReg++;
2667 }
2668 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
2669 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
2670 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
2671 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
2672 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
2673
2674 LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
2675 pChip->cfg.unique_id[0],
2676 pChip->cfg.unique_id[1],
2677 pChip->cfg.unique_id[2],
2678 pChip->cfg.unique_id[3]);
2679
2680 return ERROR_OK;
2681 }
2682
2683 static int sam3_erase_check(struct flash_bank *bank)
2684 {
2685 int x;
2686
2687 LOG_DEBUG("Here");
2688 if (bank->target->state != TARGET_HALTED) {
2689 LOG_ERROR("Target not halted");
2690 return ERROR_TARGET_NOT_HALTED;
2691 }
2692 if (0 == bank->num_sectors) {
2693 LOG_ERROR("Target: not supported/not probed");
2694 return ERROR_FAIL;
2695 }
2696
2697 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
2698 for (x = 0; x < bank->num_sectors; x++)
2699 bank->sectors[x].is_erased = 1;
2700
2701 LOG_DEBUG("Done");
2702 return ERROR_OK;
2703 }
2704
2705 static int sam3_protect_check(struct flash_bank *bank)
2706 {
2707 int r;
2708 uint32_t v = 0;
2709 unsigned x;
2710 struct sam3_bank_private *pPrivate;
2711
2712 LOG_DEBUG("Begin");
2713 if (bank->target->state != TARGET_HALTED) {
2714 LOG_ERROR("Target not halted");
2715 return ERROR_TARGET_NOT_HALTED;
2716 }
2717
2718 pPrivate = get_sam3_bank_private(bank);
2719 if (!pPrivate) {
2720 LOG_ERROR("no private for this bank?");
2721 return ERROR_FAIL;
2722 }
2723 if (!(pPrivate->probed))
2724 return ERROR_FLASH_BANK_NOT_PROBED;
2725
2726 r = FLASHD_GetLockBits(pPrivate, &v);
2727 if (r != ERROR_OK) {
2728 LOG_DEBUG("Failed: %d", r);
2729 return r;
2730 }
2731
2732 for (x = 0; x < pPrivate->nsectors; x++)
2733 bank->sectors[x].is_protected = (!!(v & (1 << x)));
2734 LOG_DEBUG("Done");
2735 return ERROR_OK;
2736 }
2737
2738 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
2739 {
2740 struct sam3_chip *pChip;
2741
2742 pChip = all_sam3_chips;
2743
2744 /* is this an existing chip? */
2745 while (pChip) {
2746 if (pChip->target == bank->target)
2747 break;
2748 pChip = pChip->next;
2749 }
2750
2751 if (!pChip) {
2752 /* this is a *NEW* chip */
2753 pChip = calloc(1, sizeof(struct sam3_chip));
2754 if (!pChip) {
2755 LOG_ERROR("NO RAM!");
2756 return ERROR_FAIL;
2757 }
2758 pChip->target = bank->target;
2759 /* insert at head */
2760 pChip->next = all_sam3_chips;
2761 all_sam3_chips = pChip;
2762 pChip->target = bank->target;
2763 /* assumption is this runs at 32khz */
2764 pChip->cfg.slow_freq = 32768;
2765 pChip->probed = 0;
2766 }
2767
2768 switch (bank->base) {
2769 default:
2770 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
2771 "[at91sam3u series] or 0x%08x [at91sam3s series] or "
2772 "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
2773 ((unsigned int)(bank->base)),
2774 ((unsigned int)(FLASH_BANK0_BASE_U)),
2775 ((unsigned int)(FLASH_BANK1_BASE_U)),
2776 ((unsigned int)(FLASH_BANK_BASE_S)),
2777 ((unsigned int)(FLASH_BANK_BASE_N)),
2778 ((unsigned int)(FLASH_BANK0_BASE_AX)),
2779 ((unsigned int)(FLASH_BANK1_BASE_256K_AX)),
2780 ((unsigned int)(FLASH_BANK1_BASE_512K_AX)));
2781 return ERROR_FAIL;
2782 break;
2783
2784 /* at91sam3s and at91sam3n series only has bank 0*/
2785 /* at91sam3u and at91sam3ax series has the same address for bank 0*/
2786 case FLASH_BANK_BASE_S:
2787 case FLASH_BANK0_BASE_U:
2788 bank->driver_priv = &(pChip->details.bank[0]);
2789 bank->bank_number = 0;
2790 pChip->details.bank[0].pChip = pChip;
2791 pChip->details.bank[0].pBank = bank;
2792 break;
2793
2794 /* Bank 1 of at91sam3u or at91sam3ax series */
2795 case FLASH_BANK1_BASE_U:
2796 case FLASH_BANK1_BASE_256K_AX:
2797 case FLASH_BANK1_BASE_512K_AX:
2798 bank->driver_priv = &(pChip->details.bank[1]);
2799 bank->bank_number = 1;
2800 pChip->details.bank[1].pChip = pChip;
2801 pChip->details.bank[1].pBank = bank;
2802 break;
2803 }
2804
2805 /* we initialize after probing. */
2806 return ERROR_OK;
2807 }
2808
2809 static int sam3_GetDetails(struct sam3_bank_private *pPrivate)
2810 {
2811 const struct sam3_chip_details *pDetails;
2812 struct sam3_chip *pChip;
2813 struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
2814 unsigned x;
2815
2816 LOG_DEBUG("Begin");
2817 pDetails = all_sam3_details;
2818 while (pDetails->name) {
2819 /* Compare cidr without version bits */
2820 if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2821 break;
2822 else
2823 pDetails++;
2824 }
2825 if (pDetails->name == NULL) {
2826 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2827 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
2828 /* Help the victim, print details about the chip */
2829 LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
2830 pPrivate->pChip->cfg.CHIPID_CIDR);
2831 sam3_explain_chipid_cidr(pPrivate->pChip);
2832 return ERROR_FAIL;
2833 }
2834
2835 /* DANGER: THERE ARE DRAGONS HERE */
2836
2837 /* get our pChip - it is going */
2838 /* to be over-written shortly */
2839 pChip = pPrivate->pChip;
2840
2841 /* Note that, in reality: */
2842 /* */
2843 /* pPrivate = &(pChip->details.bank[0]) */
2844 /* or pPrivate = &(pChip->details.bank[1]) */
2845 /* */
2846
2847 /* save the "bank" pointers */
2848 for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++)
2849 saved_banks[x] = pChip->details.bank[x].pBank;
2850
2851 /* Overwrite the "details" structure. */
2852 memcpy(&(pPrivate->pChip->details),
2853 pDetails,
2854 sizeof(pPrivate->pChip->details));
2855
2856 /* now fix the ghosted pointers */
2857 for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
2858 pChip->details.bank[x].pChip = pChip;
2859 pChip->details.bank[x].pBank = saved_banks[x];
2860 }
2861
2862 /* update the *BANK*SIZE* */
2863
2864 LOG_DEBUG("End");
2865 return ERROR_OK;
2866 }
2867
2868 static int _sam3_probe(struct flash_bank *bank, int noise)
2869 {
2870 unsigned x;
2871 int r;
2872 struct sam3_bank_private *pPrivate;
2873
2874
2875 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
2876 if (bank->target->state != TARGET_HALTED) {
2877 LOG_ERROR("Target not halted");
2878 return ERROR_TARGET_NOT_HALTED;
2879 }
2880
2881 pPrivate = get_sam3_bank_private(bank);
2882 if (!pPrivate) {
2883 LOG_ERROR("Invalid/unknown bank number");
2884 return ERROR_FAIL;
2885 }
2886
2887 r = sam3_ReadAllRegs(pPrivate->pChip);
2888 if (r != ERROR_OK)
2889 return r;
2890
2891 LOG_DEBUG("Here");
2892 if (pPrivate->pChip->probed)
2893 r = sam3_GetInfo(pPrivate->pChip);
2894 else
2895 r = sam3_GetDetails(pPrivate);
2896 if (r != ERROR_OK)
2897 return r;
2898
2899 /* update the flash bank size */
2900 for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
2901 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
2902 bank->size = pPrivate->pChip->details.bank[x].size_bytes;
2903 break;
2904 }
2905 }
2906
2907 if (bank->sectors == NULL) {
2908 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
2909 if (bank->sectors == NULL) {
2910 LOG_ERROR("No memory!");
2911 return ERROR_FAIL;
2912 }
2913 bank->num_sectors = pPrivate->nsectors;
2914
2915 for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
2916 bank->sectors[x].size = pPrivate->sector_size;
2917 bank->sectors[x].offset = x * (pPrivate->sector_size);
2918 /* mark as unknown */
2919 bank->sectors[x].is_erased = -1;
2920 bank->sectors[x].is_protected = -1;
2921 }
2922 }
2923
2924 pPrivate->probed = 1;
2925
2926 r = sam3_protect_check(bank);
2927 if (r != ERROR_OK)
2928 return r;
2929
2930 LOG_DEBUG("Bank = %d, nbanks = %d",
2931 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
2932 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
2933 /* read unique id, */
2934 /* it appears to be associated with the *last* flash bank. */
2935 FLASHD_ReadUniqueID(pPrivate);
2936 }
2937
2938 return r;
2939 }
2940
2941 static int sam3_probe(struct flash_bank *bank)
2942 {
2943 return _sam3_probe(bank, 1);
2944 }
2945
2946 static int sam3_auto_probe(struct flash_bank *bank)
2947 {
2948 return _sam3_probe(bank, 0);
2949 }
2950
2951 static int sam3_erase(struct flash_bank *bank, int first, int last)
2952 {
2953 struct sam3_bank_private *pPrivate;
2954 int r;
2955
2956 LOG_DEBUG("Here");
2957 if (bank->target->state != TARGET_HALTED) {
2958 LOG_ERROR("Target not halted");
2959 return ERROR_TARGET_NOT_HALTED;
2960 }
2961
2962 r = sam3_auto_probe(bank);
2963 if (r != ERROR_OK) {
2964 LOG_DEBUG("Here,r=%d", r);
2965 return r;
2966 }
2967
2968 pPrivate = get_sam3_bank_private(bank);
2969 if (!(pPrivate->probed))
2970 return ERROR_FLASH_BANK_NOT_PROBED;
2971
2972 if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
2973 /* whole chip */
2974 LOG_DEBUG("Here");
2975 return FLASHD_EraseEntireBank(pPrivate);
2976 }
2977 LOG_INFO("sam3 auto-erases while programming (request ignored)");
2978 return ERROR_OK;
2979 }
2980
2981 static int sam3_protect(struct flash_bank *bank, int set, int first, int last)
2982 {
2983 struct sam3_bank_private *pPrivate;
2984 int r;
2985
2986 LOG_DEBUG("Here");
2987 if (bank->target->state != TARGET_HALTED) {
2988 LOG_ERROR("Target not halted");
2989 return ERROR_TARGET_NOT_HALTED;
2990 }
2991
2992 pPrivate = get_sam3_bank_private(bank);
2993 if (!(pPrivate->probed))
2994 return ERROR_FLASH_BANK_NOT_PROBED;
2995
2996 if (set)
2997 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
2998 else
2999 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
3000 LOG_DEBUG("End: r=%d", r);
3001
3002 return r;
3003
3004 }
3005
3006 static int sam3_info(struct flash_bank *bank, char *buf, int buf_size)
3007 {
3008 if (bank->target->state != TARGET_HALTED) {
3009 LOG_ERROR("Target not halted");
3010 return ERROR_TARGET_NOT_HALTED;
3011 }
3012 buf[0] = 0;
3013 return ERROR_OK;
3014 }
3015
3016 static int sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
3017 {
3018 uint32_t adr;
3019 int r;
3020
3021 adr = pagenum * pPrivate->page_size;
3022 adr += pPrivate->base_address;
3023
3024 r = target_read_memory(pPrivate->pChip->target,
3025 adr,
3026 4, /* THIS*MUST*BE* in 32bit values */
3027 pPrivate->page_size / 4,
3028 buf);
3029 if (r != ERROR_OK)
3030 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
3031 (unsigned int)(adr));
3032 return r;
3033 }
3034
3035 /* The code below is basically this: */
3036 /* compiled with */
3037 /* arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s */
3038 /* */
3039 /* Only the *CPU* can write to the flash buffer. */
3040 /* the DAP cannot... so - we download this 28byte thing */
3041 /* Run the algorithm - (below) */
3042 /* to program the device */
3043 /* */
3044 /* ======================================== */
3045 /* #include <stdint.h> */
3046 /* */
3047 /* struct foo { */
3048 /* uint32_t *dst; */
3049 /* const uint32_t *src; */
3050 /* int n; */
3051 /* volatile uint32_t *base; */
3052 /* uint32_t cmd; */
3053 /* }; */
3054 /* */
3055 /* */
3056 /* uint32_t sam3_function(struct foo *p) */
3057 /* { */
3058 /* volatile uint32_t *v; */
3059 /* uint32_t *d; */
3060 /* const uint32_t *s; */
3061 /* int n; */
3062 /* uint32_t r; */
3063 /* */
3064 /* d = p->dst; */
3065 /* s = p->src; */
3066 /* n = p->n; */
3067 /* */
3068 /* do { */
3069 /* *d++ = *s++; */
3070 /* } while (--n) */
3071 /* ; */
3072 /* */
3073 /* v = p->base; */
3074 /* */
3075 /* v[ 1 ] = p->cmd; */
3076 /* do { */
3077 /* r = v[8/4]; */
3078 /* } while (!(r&1)) */
3079 /* ; */
3080 /* return r; */
3081 /* } */
3082 /* ======================================== */
3083
3084 static const uint8_t
3085 sam3_page_write_opcodes[] = {
3086 /* 24 0000 0446 mov r4, r0 */
3087 0x04, 0x46,
3088 /* 25 0002 6168 ldr r1, [r4, #4] */
3089 0x61, 0x68,
3090 /* 26 0004 0068 ldr r0, [r0, #0] */
3091 0x00, 0x68,
3092 /* 27 0006 A268 ldr r2, [r4, #8] */
3093 0xa2, 0x68,
3094 /* 28 @ lr needed for prologue */
3095 /* 29 .L2: */
3096 /* 30 0008 51F8043B ldr r3, [r1], #4 */
3097 0x51, 0xf8, 0x04, 0x3b,
3098 /* 31 000c 12F1FF32 adds r2, r2, #-1 */
3099 0x12, 0xf1, 0xff, 0x32,
3100 /* 32 0010 40F8043B str r3, [r0], #4 */
3101 0x40, 0xf8, 0x04, 0x3b,
3102 /* 33 0014 F8D1 bne .L2 */
3103 0xf8, 0xd1,
3104 /* 34 0016 E268 ldr r2, [r4, #12] */
3105 0xe2, 0x68,
3106 /* 35 0018 2369 ldr r3, [r4, #16] */
3107 0x23, 0x69,
3108 /* 36 001a 5360 str r3, [r2, #4] */
3109 0x53, 0x60,
3110 /* 37 001c 0832 adds r2, r2, #8 */
3111 0x08, 0x32,
3112 /* 38 .L4: */
3113 /* 39 001e 1068 ldr r0, [r2, #0] */
3114 0x10, 0x68,
3115 /* 40 0020 10F0010F tst r0, #1 */
3116 0x10, 0xf0, 0x01, 0x0f,
3117 /* 41 0024 FBD0 beq .L4 */
3118 0xfb, 0xd0,
3119 0x00, 0xBE /* bkpt #0 */
3120 };
3121
3122 static int sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
3123 {
3124 uint32_t adr;
3125 uint32_t status;
3126 uint32_t fmr; /* EEFC Flash Mode Register */
3127 int r;
3128
3129 adr = pagenum * pPrivate->page_size;
3130 adr += pPrivate->base_address;
3131
3132 /* Get flash mode register value */
3133 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
3134 if (r != ERROR_OK)
3135 LOG_DEBUG("Error Read failed: read flash mode register");
3136
3137 /* Clear flash wait state field */
3138 fmr &= 0xfffff0ff;
3139
3140 /* set FWS (flash wait states) field in the FMR (flash mode register) */
3141 fmr |= (pPrivate->flash_wait_states << 8);
3142
3143 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
3144 r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
3145 if (r != ERROR_OK)
3146 LOG_DEBUG("Error Write failed: set flash mode register");
3147
3148 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
3149 r = target_write_memory(pPrivate->pChip->target,
3150 adr,
3151 4, /* THIS*MUST*BE* in 32bit values */
3152 pPrivate->page_size / 4,
3153 buf);
3154 if (r != ERROR_OK) {
3155 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
3156 (unsigned int)(adr));
3157 return r;
3158 }
3159
3160 r = EFC_PerformCommand(pPrivate,
3161 /* send Erase & Write Page */
3162 AT91C_EFC_FCMD_EWP,
3163 pagenum,
3164 &status);
3165
3166 if (r != ERROR_OK)
3167 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
3168 (unsigned int)(adr));
3169 if (status & (1 << 2)) {
3170 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
3171 return ERROR_FAIL;
3172 }
3173 if (status & (1 << 1)) {
3174 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
3175 return ERROR_FAIL;
3176 }
3177 return ERROR_OK;
3178 }
3179
3180 static int sam3_write(struct flash_bank *bank,
3181 uint8_t *buffer,
3182 uint32_t offset,
3183 uint32_t count)
3184 {
3185 int n;
3186 unsigned page_cur;
3187 unsigned page_end;
3188 int r;
3189 unsigned page_offset;
3190 struct sam3_bank_private *pPrivate;
3191 uint8_t *pagebuffer;
3192
3193 /* incase we bail further below, set this to null */
3194 pagebuffer = NULL;
3195
3196 /* ignore dumb requests */
3197 if (count == 0) {
3198 r = ERROR_OK;
3199 goto done;
3200 }
3201
3202 if (bank->target->state != TARGET_HALTED) {
3203 LOG_ERROR("Target not halted");
3204 r = ERROR_TARGET_NOT_HALTED;
3205 goto done;
3206 }
3207
3208 pPrivate = get_sam3_bank_private(bank);
3209 if (!(pPrivate->probed)) {
3210 r = ERROR_FLASH_BANK_NOT_PROBED;
3211 goto done;
3212 }
3213
3214 if ((offset + count) > pPrivate->size_bytes) {
3215 LOG_ERROR("Flash write error - past end of bank");
3216 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
3217 (unsigned int)(offset),
3218 (unsigned int)(count),
3219 (unsigned int)(pPrivate->size_bytes));
3220 r = ERROR_FAIL;
3221 goto done;
3222 }
3223
3224 pagebuffer = malloc(pPrivate->page_size);
3225 if (!pagebuffer) {
3226 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
3227 r = ERROR_FAIL;
3228 goto done;
3229 }
3230
3231 /* what page do we start & end in? */
3232 page_cur = offset / pPrivate->page_size;
3233 page_end = (offset + count - 1) / pPrivate->page_size;
3234
3235 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
3236 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
3237
3238 /* Special case: all one page */
3239 /* */
3240 /* Otherwise: */
3241 /* (1) non-aligned start */
3242 /* (2) body pages */
3243 /* (3) non-aligned end. */
3244
3245 /* Handle special case - all one page. */
3246 if (page_cur == page_end) {
3247 LOG_DEBUG("Special case, all in one page");
3248 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3249 if (r != ERROR_OK)
3250 goto done;
3251
3252 page_offset = (offset & (pPrivate->page_size-1));
3253 memcpy(pagebuffer + page_offset,
3254 buffer,
3255 count);
3256
3257 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3258 if (r != ERROR_OK)
3259 goto done;
3260 r = ERROR_OK;
3261 goto done;
3262 }
3263
3264 /* non-aligned start */
3265 page_offset = offset & (pPrivate->page_size - 1);
3266 if (page_offset) {
3267 LOG_DEBUG("Not-Aligned start");
3268 /* read the partial */
3269 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3270 if (r != ERROR_OK)
3271 goto done;
3272
3273 /* over-write with new data */
3274 n = (pPrivate->page_size - page_offset);
3275 memcpy(pagebuffer + page_offset,
3276 buffer,
3277 n);
3278
3279 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3280 if (r != ERROR_OK)
3281 goto done;
3282
3283 count -= n;
3284 offset += n;
3285 buffer += n;
3286 page_cur++;
3287 }
3288
3289 /* By checking that offset is correct here, we also
3290 fix a clang warning */
3291 assert(offset % pPrivate->page_size == 0);
3292
3293 /* intermediate large pages */
3294 /* also - the final *terminal* */
3295 /* if that terminal page is a full page */
3296 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3297 (int)page_cur, (int)page_end, (unsigned int)(count));
3298
3299 while ((page_cur < page_end) &&
3300 (count >= pPrivate->page_size)) {
3301 r = sam3_page_write(pPrivate, page_cur, buffer);
3302 if (r != ERROR_OK)
3303 goto done;
3304 count -= pPrivate->page_size;
3305 buffer += pPrivate->page_size;
3306 page_cur += 1;
3307 }
3308
3309 /* terminal partial page? */
3310 if (count) {
3311 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
3312 /* we have a partial page */
3313 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3314 if (r != ERROR_OK)
3315 goto done;
3316 /* data goes at start */
3317 memcpy(pagebuffer, buffer, count);
3318 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3319 if (r != ERROR_OK)
3320 goto done;
3321 }
3322 LOG_DEBUG("Done!");
3323 r = ERROR_OK;
3324 done:
3325 if (pagebuffer)
3326 free(pagebuffer);
3327 return r;
3328 }
3329
3330 COMMAND_HANDLER(sam3_handle_info_command)
3331 {
3332 struct sam3_chip *pChip;
3333 pChip = get_current_sam3(CMD_CTX);
3334 if (!pChip)
3335 return ERROR_OK;
3336
3337 unsigned x;
3338 int r;
3339
3340 /* bank0 must exist before we can do anything */
3341 if (pChip->details.bank[0].pBank == NULL) {
3342 x = 0;
3343 need_define:
3344 command_print(CMD_CTX,
3345 "Please define bank %d via command: flash bank %s ... ",
3346 x,
3347 at91sam3_flash.name);
3348 return ERROR_FAIL;
3349 }
3350
3351 /* if bank 0 is not probed, then probe it */
3352 if (!(pChip->details.bank[0].probed)) {
3353 r = sam3_auto_probe(pChip->details.bank[0].pBank);
3354 if (r != ERROR_OK)
3355 return ERROR_FAIL;
3356 }
3357 /* above guarantees the "chip details" structure is valid */
3358 /* and thus, bank private areas are valid */
3359 /* and we have a SAM3 chip, what a concept! */
3360
3361 /* auto-probe other banks, 0 done above */
3362 for (x = 1; x < SAM3_MAX_FLASH_BANKS; x++) {
3363 /* skip banks not present */
3364 if (!(pChip->details.bank[x].present))
3365 continue;
3366
3367 if (pChip->details.bank[x].pBank == NULL)
3368 goto need_define;
3369
3370 if (pChip->details.bank[x].probed)
3371 continue;
3372
3373 r = sam3_auto_probe(pChip->details.bank[x].pBank);
3374 if (r != ERROR_OK)
3375 return r;
3376 }
3377
3378 r = sam3_GetInfo(pChip);
3379 if (r != ERROR_OK) {
3380 LOG_DEBUG("Sam3Info, Failed %d", r);
3381 return r;
3382 }
3383
3384 return ERROR_OK;
3385 }
3386
3387 COMMAND_HANDLER(sam3_handle_gpnvm_command)
3388 {
3389 unsigned x, v;
3390 int r, who;
3391 struct sam3_chip *pChip;
3392
3393 pChip = get_current_sam3(CMD_CTX);
3394 if (!pChip)
3395 return ERROR_OK;
3396
3397 if (pChip->target->state != TARGET_HALTED) {
3398 LOG_ERROR("sam3 - target not halted");
3399 return ERROR_TARGET_NOT_HALTED;
3400 }
3401
3402 if (pChip->details.bank[0].pBank == NULL) {
3403 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
3404 at91sam3_flash.name);
3405 return ERROR_FAIL;
3406 }
3407 if (!pChip->details.bank[0].probed) {
3408 r = sam3_auto_probe(pChip->details.bank[0].pBank);
3409 if (r != ERROR_OK)
3410 return r;
3411 }
3412
3413 switch (CMD_ARGC) {
3414 default:
3415 return ERROR_COMMAND_SYNTAX_ERROR;
3416 break;
3417 case 0:
3418 goto showall;
3419 break;
3420 case 1:
3421 who = -1;
3422 break;
3423 case 2:
3424 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
3425 who = -1;
3426 else {
3427 uint32_t v32;
3428 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3429 who = v32;
3430 }
3431 break;
3432 }
3433
3434 if (0 == strcmp("show", CMD_ARGV[0])) {
3435 if (who == -1) {
3436 showall:
3437 r = ERROR_OK;
3438 for (x = 0; x < pChip->details.n_gpnvms; x++) {
3439 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
3440 if (r != ERROR_OK)
3441 break;
3442 command_print(CMD_CTX, "sam3-gpnvm%u: %u", x, v);
3443 }
3444 return r;
3445 }
3446 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
3447 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
3448 command_print(CMD_CTX, "sam3-gpnvm%u: %u", who, v);
3449 return r;
3450 } else {
3451 command_print(CMD_CTX, "sam3-gpnvm invalid GPNVM: %u", who);
3452 return ERROR_COMMAND_SYNTAX_ERROR;
3453 }
3454 }
3455
3456 if (who == -1) {
3457 command_print(CMD_CTX, "Missing GPNVM number");
3458 return ERROR_COMMAND_SYNTAX_ERROR;
3459 }
3460
3461 if (0 == strcmp("set", CMD_ARGV[0]))
3462 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
3463 else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
3464 (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
3465 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
3466 else {
3467 command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
3468 r = ERROR_COMMAND_SYNTAX_ERROR;
3469 }
3470 return r;
3471 }
3472
3473 COMMAND_HANDLER(sam3_handle_slowclk_command)
3474 {
3475 struct sam3_chip *pChip;
3476
3477 pChip = get_current_sam3(CMD_CTX);
3478 if (!pChip)
3479 return ERROR_OK;
3480
3481 switch (CMD_ARGC) {
3482 case 0:
3483 /* show */
3484 break;
3485 case 1:
3486 {
3487 /* set */
3488 uint32_t v;
3489 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3490 if (v > 200000) {
3491 /* absurd slow clock of 200Khz? */
3492 command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3493 return ERROR_COMMAND_SYNTAX_ERROR;
3494 }
3495 pChip->cfg.slow_freq = v;
3496 break;
3497 }
3498 default:
3499 /* error */
3500 command_print(CMD_CTX, "Too many parameters");
3501 return ERROR_COMMAND_SYNTAX_ERROR;
3502 break;
3503 }
3504 command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
3505 (int)(pChip->cfg.slow_freq / 1000),
3506 (int)(pChip->cfg.slow_freq % 1000));
3507 return ERROR_OK;
3508 }
3509
3510 static const struct command_registration at91sam3_exec_command_handlers[] = {
3511 {
3512 .name = "gpnvm",
3513 .handler = sam3_handle_gpnvm_command,
3514 .mode = COMMAND_EXEC,
3515 .usage = "[('clr'|'set'|'show') bitnum]",
3516 .help = "Without arguments, shows all bits in the gpnvm "
3517 "register. Otherwise, clears, sets, or shows one "
3518 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3519 },
3520 {
3521 .name = "info",
3522 .handler = sam3_handle_info_command,
3523 .mode = COMMAND_EXEC,
3524 .help = "Print information about the current at91sam3 chip"
3525 "and its flash configuration.",
3526 },
3527 {
3528 .name = "slowclk",
3529 .handler = sam3_handle_slowclk_command,
3530 .mode = COMMAND_EXEC,
3531 .usage = "[clock_hz]",
3532 .help = "Display or set the slowclock frequency "
3533 "(default 32768 Hz).",
3534 },
3535 COMMAND_REGISTRATION_DONE
3536 };
3537 static const struct command_registration at91sam3_command_handlers[] = {
3538 {
3539 .name = "at91sam3",
3540 .mode = COMMAND_ANY,
3541 .help = "at91sam3 flash command group",
3542 .usage = "",
3543 .chain = at91sam3_exec_command_handlers,
3544 },
3545 COMMAND_REGISTRATION_DONE
3546 };
3547
3548 struct flash_driver at91sam3_flash = {
3549 .name = "at91sam3",
3550 .commands = at91sam3_command_handlers,
3551 .flash_bank_command = sam3_flash_bank_command,
3552 .erase = sam3_erase,
3553 .protect = sam3_protect,
3554 .write = sam3_write,
3555 .read = default_flash_read,
3556 .probe = sam3_probe,
3557 .auto_probe = sam3_auto_probe,
3558 .erase_check = sam3_erase_check,
3559 .protect_check = sam3_protect_check,
3560 .info = sam3_info,
3561 };