flash/nor: consolidate flash protect/protect_check
[openocd.git] / src / flash / nor / aduc702x.c
1 /***************************************************************************
2 * Copyright (C) 2008 by Kevin McGuire *
3 * Copyright (C) 2008 by Marcel Wijlaars *
4 * Copyright (C) 2009 by Michael Ashton *
5 * *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
10 * *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
15 * *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
18 ***************************************************************************/
19
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "imp.h"
25 #include <helper/binarybuffer.h>
26 #include <helper/time_support.h>
27 #include <target/algorithm.h>
28 #include <target/arm.h>
29
30 static int aduc702x_build_sector_list(struct flash_bank *bank);
31 static int aduc702x_check_flash_completion(struct target *target, unsigned int timeout_ms);
32 static int aduc702x_set_write_enable(struct target *target, int enable);
33
34 #define ADUC702x_FLASH 0xfffff800
35 #define ADUC702x_FLASH_FEESTA (0*4)
36 #define ADUC702x_FLASH_FEEMOD (1*4)
37 #define ADUC702x_FLASH_FEECON (2*4)
38 #define ADUC702x_FLASH_FEEDAT (3*4)
39 #define ADUC702x_FLASH_FEEADR (4*4)
40 #define ADUC702x_FLASH_FEESIGN (5*4)
41 #define ADUC702x_FLASH_FEEPRO (6*4)
42 #define ADUC702x_FLASH_FEEHIDE (7*4)
43
44 /* flash bank aduc702x 0 0 0 0 <target#>
45 * The ADC7019-28 devices all have the same flash layout */
46 FLASH_BANK_COMMAND_HANDLER(aduc702x_flash_bank_command)
47 {
48 bank->base = 0x80000;
49 bank->size = 0xF800; /* top 4k not accessible */
50
51 aduc702x_build_sector_list(bank);
52
53 return ERROR_OK;
54 }
55
56 static int aduc702x_build_sector_list(struct flash_bank *bank)
57 {
58 /* aduc7026_struct flash_bank *aduc7026_info = bank->driver_priv; */
59
60 int i = 0;
61 uint32_t offset = 0;
62
63 /* sector size is 512 */
64 bank->num_sectors = bank->size / 512;
65 bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
66 for (i = 0; i < bank->num_sectors; ++i) {
67 bank->sectors[i].offset = offset;
68 bank->sectors[i].size = 512;
69 offset += bank->sectors[i].size;
70 bank->sectors[i].is_erased = -1;
71 bank->sectors[i].is_protected = 0;
72 }
73
74 return ERROR_OK;
75 }
76
77 static int aduc702x_erase(struct flash_bank *bank, int first, int last)
78 {
79 /* int res; */
80 int x;
81 int count;
82 /* uint32_t v; */
83 struct target *target = bank->target;
84
85 aduc702x_set_write_enable(target, 1);
86
87 /* mass erase */
88 if (((first | last) == 0) || ((first == 0) && (last >= bank->num_sectors))) {
89 LOG_DEBUG("performing mass erase.");
90 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEDAT, 0x3cff);
91 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, 0xffc3);
92 target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x06);
93
94 if (aduc702x_check_flash_completion(target, 3500) != ERROR_OK) {
95 LOG_ERROR("mass erase failed");
96 aduc702x_set_write_enable(target, 0);
97 return ERROR_FLASH_OPERATION_FAILED;
98 }
99
100 LOG_DEBUG("mass erase successful.");
101 return ERROR_OK;
102 } else {
103 unsigned long adr;
104
105 count = last - first + 1;
106 for (x = 0; x < count; ++x) {
107 adr = bank->base + ((first + x) * 512);
108
109 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, adr);
110 target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x05);
111
112 if (aduc702x_check_flash_completion(target, 50) != ERROR_OK) {
113 LOG_ERROR("failed to erase sector at address 0x%08lX", adr);
114 aduc702x_set_write_enable(target, 0);
115 return ERROR_FLASH_SECTOR_NOT_ERASED;
116 }
117
118 LOG_DEBUG("erased sector at address 0x%08lX", adr);
119 }
120 }
121
122 aduc702x_set_write_enable(target, 0);
123
124 return ERROR_OK;
125 }
126
127 /* If this fn returns ERROR_TARGET_RESOURCE_NOT_AVAILABLE, then the caller can fall
128 * back to another mechanism that does not require onboard RAM
129 *
130 * Caller should not check for other return values specifically
131 */
132 static int aduc702x_write_block(struct flash_bank *bank,
133 const uint8_t *buffer,
134 uint32_t offset,
135 uint32_t count)
136 {
137 struct target *target = bank->target;
138 uint32_t buffer_size = 7000;
139 struct working_area *write_algorithm;
140 struct working_area *source;
141 uint32_t address = bank->base + offset;
142 struct reg_param reg_params[6];
143 struct arm_algorithm arm_algo;
144 int retval = ERROR_OK;
145
146 if (((count%2) != 0) || ((offset%2) != 0)) {
147 LOG_ERROR("write block must be multiple of two bytes in offset & length");
148 return ERROR_FAIL;
149 }
150
151 /* parameters:
152
153 r0 - address of source data (absolute)
154 r1 - number of halfwords to be copied
155 r2 - start address in flash (offset from beginning of flash memory)
156 r3 - exit code
157 r4 - base address of flash controller (0xFFFFF800)
158
159 registers:
160
161 r5 - scratch
162 r6 - set to 2, used to write flash command
163
164 */
165 static const uint32_t aduc702x_flash_write_code[] = {
166 /* <_start>: */
167 0xe3a05008, /* mov r5, #8 ; 0x8 */
168 0xe5845004, /* str r5, [r4, #4] */
169 0xe3a06002, /* mov r6, #2 ; 0x2 */
170 /* <next>: */
171 0xe1c421b0, /* strh r2, [r4, #16] */
172 0xe0d050b2, /* ldrh r5, [r0], #2 */
173 0xe1c450bc, /* strh r5, [r4, #12] */
174 0xe5c46008, /* strb r6, [r4, #8] */
175 /* <wait_complete>: */
176 0xe1d430b0, /* ldrh r3, [r4] */
177 0xe3130004, /* tst r3, #4 ; 0x4 */
178 0x1afffffc, /* bne 1001c <wait_complete> */
179 0xe2822002, /* add r2, r2, #2 ; 0x2 */
180 0xe2511001, /* subs r1, r1, #1 ; 0x1 */
181 0x0a000001, /* beq 1003c <done> */
182 0xe3130001, /* tst r3, #1 ; 0x1 */
183 0x1afffff3, /* bne 1000c <next> */
184 /* <done>: */
185 0xeafffffe /* b 1003c <done> */
186 };
187
188 /* flash write code */
189 if (target_alloc_working_area(target, sizeof(aduc702x_flash_write_code),
190 &write_algorithm) != ERROR_OK) {
191 LOG_WARNING("no working area available, can't do block memory writes");
192 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
193 }
194
195 uint8_t code[sizeof(aduc702x_flash_write_code)];
196 target_buffer_set_u32_array(target, code, ARRAY_SIZE(aduc702x_flash_write_code),
197 aduc702x_flash_write_code);
198 retval = target_write_buffer(target, write_algorithm->address, sizeof(code), code);
199 if (retval != ERROR_OK)
200 return retval;
201
202 /* memory buffer */
203 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
204 buffer_size /= 2;
205 if (buffer_size <= 256) {
206 /* we already allocated the writing code, but failed to get a buffer,
207 *free the algorithm */
208 target_free_working_area(target, write_algorithm);
209
210 LOG_WARNING("no large enough working area available, can't do block memory writes");
211 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
212 }
213 }
214
215 arm_algo.common_magic = ARM_COMMON_MAGIC;
216 arm_algo.core_mode = ARM_MODE_SVC;
217 arm_algo.core_state = ARM_STATE_ARM;
218
219 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
220 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
221 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
222 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
223 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
224
225 while (count > 0) {
226 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
227
228 retval = target_write_buffer(target, source->address, thisrun_count, buffer);
229 if (retval != ERROR_OK)
230 break;
231
232 buf_set_u32(reg_params[0].value, 0, 32, source->address);
233 buf_set_u32(reg_params[1].value, 0, 32, thisrun_count/2);
234 buf_set_u32(reg_params[2].value, 0, 32, address);
235 buf_set_u32(reg_params[4].value, 0, 32, 0xFFFFF800);
236
237 retval = target_run_algorithm(target, 0, NULL, 5,
238 reg_params, write_algorithm->address,
239 write_algorithm->address +
240 sizeof(aduc702x_flash_write_code) - 4,
241 10000, &arm_algo);
242 if (retval != ERROR_OK) {
243 LOG_ERROR("error executing aduc702x flash write algorithm");
244 break;
245 }
246
247 if ((buf_get_u32(reg_params[3].value, 0, 32) & 1) != 1) {
248 /* FIX!!!! what does this mean??? replace w/sensible error message */
249 LOG_ERROR("aduc702x detected error writing flash");
250 retval = ERROR_FAIL;
251 break;
252 }
253
254 buffer += thisrun_count;
255 address += thisrun_count;
256 count -= thisrun_count;
257 }
258
259 target_free_working_area(target, source);
260 target_free_working_area(target, write_algorithm);
261
262 destroy_reg_param(&reg_params[0]);
263 destroy_reg_param(&reg_params[1]);
264 destroy_reg_param(&reg_params[2]);
265 destroy_reg_param(&reg_params[3]);
266 destroy_reg_param(&reg_params[4]);
267
268 return retval;
269 }
270
271 /* All-JTAG, single-access method. Very slow. Used only if there is no
272 * working area available. */
273 static int aduc702x_write_single(struct flash_bank *bank,
274 const uint8_t *buffer,
275 uint32_t offset,
276 uint32_t count)
277 {
278 uint32_t x;
279 uint8_t b;
280 struct target *target = bank->target;
281
282 aduc702x_set_write_enable(target, 1);
283
284 for (x = 0; x < count; x += 2) {
285 /* FEEADR = address */
286 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, offset + x);
287
288 /* set up data */
289 if ((x + 1) == count) {
290 /* last byte */
291 target_read_u8(target, offset + x + 1, &b);
292 } else
293 b = buffer[x + 1];
294
295 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEDAT, buffer[x] | (b << 8));
296
297 /* do single-write command */
298 target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x02);
299
300 if (aduc702x_check_flash_completion(target, 1) != ERROR_OK) {
301 LOG_ERROR("single write failed for address 0x%08lX",
302 (unsigned long)(offset + x));
303 aduc702x_set_write_enable(target, 0);
304 return ERROR_FLASH_OPERATION_FAILED;
305 }
306
307 }
308 LOG_DEBUG("wrote %d bytes at address 0x%08lX", (int)count, (unsigned long)(offset + x));
309
310 aduc702x_set_write_enable(target, 0);
311
312 return ERROR_OK;
313 }
314
315 static int aduc702x_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
316 {
317 int retval;
318
319 /* try using a block write */
320 retval = aduc702x_write_block(bank, buffer, offset, count);
321 if (retval != ERROR_OK) {
322 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
323 /* if block write failed (no sufficient working area),
324 * use normal (slow) JTAG method */
325 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
326
327 retval = aduc702x_write_single(bank, buffer, offset, count);
328 if (retval != ERROR_OK) {
329 LOG_ERROR("slow write failed");
330 return ERROR_FLASH_OPERATION_FAILED;
331 }
332 }
333 }
334
335 return retval;
336 }
337
338 static int aduc702x_probe(struct flash_bank *bank)
339 {
340 return ERROR_OK;
341 }
342
343 /* sets FEEMOD bit 3
344 * enable = 1 enables writes & erases, 0 disables them */
345 static int aduc702x_set_write_enable(struct target *target, int enable)
346 {
347 /* don't bother to preserve int enable bit here */
348 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEMOD, enable ? 8 : 0);
349
350 return ERROR_OK;
351 }
352
353 /* wait up to timeout_ms for controller to not be busy,
354 * then check whether the command passed or failed.
355 *
356 * this function sleeps 1ms between checks (after the first one),
357 * so in some cases may slow things down without a usleep after the first read */
358 static int aduc702x_check_flash_completion(struct target *target, unsigned int timeout_ms)
359 {
360 uint8_t v = 4;
361
362 int64_t endtime = timeval_ms() + timeout_ms;
363 while (1) {
364 target_read_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEESTA, &v);
365 if ((v & 4) == 0)
366 break;
367 alive_sleep(1);
368 if (timeval_ms() >= endtime)
369 break;
370 }
371
372 if (v & 2)
373 return ERROR_FAIL;
374 /* if a command is ignored, both the success and fail bits may be 0 */
375 else if ((v & 3) == 0)
376 return ERROR_FAIL;
377 else
378 return ERROR_OK;
379 }
380
381 struct flash_driver aduc702x_flash = {
382 .name = "aduc702x",
383 .flash_bank_command = aduc702x_flash_bank_command,
384 .erase = aduc702x_erase,
385 .write = aduc702x_write,
386 .read = default_flash_read,
387 .probe = aduc702x_probe,
388 .auto_probe = aduc702x_probe,
389 .erase_check = default_flash_blank_check,
390 };