move remaining nand helper files
[openocd.git] / src / flash / nand / orion.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Marvell Semiconductors, Inc. *
3 * Written by Nicolas Pitre <nico at marvell.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20
21 /*
22 * NAND controller interface for Marvell Orion/Kirkwood SoCs.
23 */
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "arm_io.h"
30 #include <target/armv4_5.h>
31
32
33 struct orion_nand_controller
34 {
35 struct target *target;
36
37 struct arm_nand_data io;
38
39 uint32_t cmd;
40 uint32_t addr;
41 uint32_t data;
42 };
43
44 #define CHECK_HALTED \
45 do { \
46 if (target->state != TARGET_HALTED) { \
47 LOG_ERROR("NAND flash access requires halted target"); \
48 return ERROR_NAND_OPERATION_FAILED; \
49 } \
50 } while (0)
51
52 static int orion_nand_command(struct nand_device *nand, uint8_t command)
53 {
54 struct orion_nand_controller *hw = nand->controller_priv;
55 struct target *target = hw->target;
56
57 CHECK_HALTED;
58 target_write_u8(target, hw->cmd, command);
59 return ERROR_OK;
60 }
61
62 static int orion_nand_address(struct nand_device *nand, uint8_t address)
63 {
64 struct orion_nand_controller *hw = nand->controller_priv;
65 struct target *target = hw->target;
66
67 CHECK_HALTED;
68 target_write_u8(target, hw->addr, address);
69 return ERROR_OK;
70 }
71
72 static int orion_nand_read(struct nand_device *nand, void *data)
73 {
74 struct orion_nand_controller *hw = nand->controller_priv;
75 struct target *target = hw->target;
76
77 CHECK_HALTED;
78 target_read_u8(target, hw->data, data);
79 return ERROR_OK;
80 }
81
82 static int orion_nand_write(struct nand_device *nand, uint16_t data)
83 {
84 struct orion_nand_controller *hw = nand->controller_priv;
85 struct target *target = hw->target;
86
87 CHECK_HALTED;
88 target_write_u8(target, hw->data, data);
89 return ERROR_OK;
90 }
91
92 static int orion_nand_slow_block_write(struct nand_device *nand, uint8_t *data, int size)
93 {
94 while (size--)
95 orion_nand_write(nand, *data++);
96 return ERROR_OK;
97 }
98
99 static int orion_nand_fast_block_write(struct nand_device *nand, uint8_t *data, int size)
100 {
101 struct orion_nand_controller *hw = nand->controller_priv;
102 int retval;
103
104 hw->io.chunk_size = nand->page_size;
105
106 retval = arm_nandwrite(&hw->io, data, size);
107 if (retval == ERROR_NAND_NO_BUFFER)
108 retval = orion_nand_slow_block_write(nand, data, size);
109
110 return retval;
111 }
112
113 static int orion_nand_reset(struct nand_device *nand)
114 {
115 return orion_nand_command(nand, NAND_CMD_RESET);
116 }
117
118 static int orion_nand_controller_ready(struct nand_device *nand, int timeout)
119 {
120 return 1;
121 }
122
123 NAND_DEVICE_COMMAND_HANDLER(orion_nand_device_command)
124 {
125 struct orion_nand_controller *hw;
126 uint32_t base;
127 uint8_t ale, cle;
128
129 if (CMD_ARGC != 3) {
130 LOG_ERROR("arguments must be: <target_id> <NAND_address>\n");
131 return ERROR_NAND_DEVICE_INVALID;
132 }
133
134 hw = calloc(1, sizeof(*hw));
135 if (!hw) {
136 LOG_ERROR("no memory for nand controller\n");
137 return ERROR_NAND_DEVICE_INVALID;
138 }
139
140 nand->controller_priv = hw;
141 hw->target = get_target(CMD_ARGV[1]);
142 if (!hw->target) {
143 LOG_ERROR("target '%s' not defined", CMD_ARGV[1]);
144 free(hw);
145 return ERROR_NAND_DEVICE_INVALID;
146 }
147
148 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], base);
149 cle = 0;
150 ale = 1;
151
152 hw->data = base;
153 hw->cmd = base + (1 << cle);
154 hw->addr = base + (1 << ale);
155
156 hw->io.target = hw->target;
157 hw->io.data = hw->data;
158 hw->io.op = ARM_NAND_NONE;
159
160 return ERROR_OK;
161 }
162
163 static int orion_nand_init(struct nand_device *nand)
164 {
165 return ERROR_OK;
166 }
167
168 struct nand_flash_controller orion_nand_controller =
169 {
170 .name = "orion",
171 .command = orion_nand_command,
172 .address = orion_nand_address,
173 .read_data = orion_nand_read,
174 .write_data = orion_nand_write,
175 .write_block_data = orion_nand_fast_block_write,
176 .reset = orion_nand_reset,
177 .controller_ready = orion_nand_controller_ready,
178 .nand_device_command = orion_nand_device_command,
179 .init = orion_nand_init,
180 };
181