Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
Convert to non-recursive make
[openocd.git] / src / flash / nand / mxc.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Alexei Babich *
3 * Rezonans plc., Chelyabinsk, Russia *
4 * impatt@mail.ru *
5 * *
6 * Copyright (C) 2010 by Gaetan CARLIER *
7 * Trump s.a., Belgium *
8 * *
9 * Copyright (C) 2011 by Erik Ahlen *
10 * Avalon Innovation, Sweden *
11 * *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
16 * *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
21 * *
22 * You should have received a copy of the GNU General Public License *
23 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
24 ***************************************************************************/
25
26 /*
27 * Freescale iMX OpenOCD NAND Flash controller support.
28 * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
29 */
30
31 /*
32 * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
33 * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
34 * "nand write # file 0", "nand verify"
35 *
36 * get_next_halfword_from_sram_buffer() not tested
37 * !! all function only tested with 2k page nand device; mxc_write_page
38 * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
39 * !! oob must be be used due to NFS bug
40 * !! oob must be 64 bytes per 2KiB page
41 */
42 #ifdef HAVE_CONFIG_H
43 #include "config.h"
44 #endif
45
46 #include "imp.h"
47 #include "mxc.h"
48 #include <target/target.h>
49
50 #define OOB_SIZE 64
51
52 #define nfc_is_v1() (mxc_nf_info->mxc_version == MXC_VERSION_MX27 || \
53 mxc_nf_info->mxc_version == MXC_VERSION_MX31)
54 #define nfc_is_v2() (mxc_nf_info->mxc_version == MXC_VERSION_MX25 || \
55 mxc_nf_info->mxc_version == MXC_VERSION_MX35)
56
57 /* This permits to print (in LOG_INFO) how much bytes
58 * has been written after a page read or write.
59 * This is useful when OpenOCD is used with a graphical
60 * front-end to estimate progression of the global read/write
61 */
62 #undef _MXC_PRINT_STAT
63 /* #define _MXC_PRINT_STAT */
64
65 static const char target_not_halted_err_msg[] =
66 "target must be halted to use mxc NAND flash controller";
67 static const char data_block_size_err_msg[] =
68 "minimal granularity is one half-word, %" PRId32 " is incorrect";
69 static const char sram_buffer_bounds_err_msg[] =
70 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
71 static const char get_status_register_err_msg[] = "can't get NAND status";
72 static uint32_t in_sram_address;
73 static unsigned char sign_of_sequental_byte_read;
74
75 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr);
76 static int initialize_nf_controller(struct nand_device *nand);
77 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value);
78 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value);
79 static int poll_for_complete_op(struct nand_device *nand, const char *text);
80 static int validate_target_state(struct nand_device *nand);
81 static int do_data_output(struct nand_device *nand);
82
83 static int mxc_command(struct nand_device *nand, uint8_t command);
84 static int mxc_address(struct nand_device *nand, uint8_t address);
85
86 NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
87 {
88 struct mxc_nf_controller *mxc_nf_info;
89 int hwecc_needed;
90
91 mxc_nf_info = malloc(sizeof(struct mxc_nf_controller));
92 if (mxc_nf_info == NULL) {
93 LOG_ERROR("no memory for nand controller");
94 return ERROR_FAIL;
95 }
96 nand->controller_priv = mxc_nf_info;
97
98 if (CMD_ARGC < 4) {
99 LOG_ERROR("use \"nand device mxc target mx25|mx27|mx31|mx35 noecc|hwecc [biswap]\"");
100 return ERROR_FAIL;
101 }
102
103 /*
104 * check board type
105 */
106 if (strcmp(CMD_ARGV[2], "mx25") == 0) {
107 mxc_nf_info->mxc_version = MXC_VERSION_MX25;
108 mxc_nf_info->mxc_base_addr = 0xBB000000;
109 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
110 } else if (strcmp(CMD_ARGV[2], "mx27") == 0) {
111 mxc_nf_info->mxc_version = MXC_VERSION_MX27;
112 mxc_nf_info->mxc_base_addr = 0xD8000000;
113 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
114 } else if (strcmp(CMD_ARGV[2], "mx31") == 0) {
115 mxc_nf_info->mxc_version = MXC_VERSION_MX31;
116 mxc_nf_info->mxc_base_addr = 0xB8000000;
117 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
118 } else if (strcmp(CMD_ARGV[2], "mx35") == 0) {
119 mxc_nf_info->mxc_version = MXC_VERSION_MX35;
120 mxc_nf_info->mxc_base_addr = 0xBB000000;
121 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
122 }
123
124 /*
125 * check hwecc requirements
126 */
127 hwecc_needed = strcmp(CMD_ARGV[3], "hwecc");
128 if (hwecc_needed == 0)
129 mxc_nf_info->flags.hw_ecc_enabled = 1;
130 else
131 mxc_nf_info->flags.hw_ecc_enabled = 0;
132
133 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
134 mxc_nf_info->fin = MXC_NF_FIN_NONE;
135 mxc_nf_info->flags.target_little_endian =
136 (nand->target->endianness == TARGET_LITTLE_ENDIAN);
137
138 /*
139 * should factory bad block indicator be swaped
140 * as a workaround for how the nfc handles pages.
141 */
142 if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
143 LOG_DEBUG("BI-swap enabled");
144 mxc_nf_info->flags.biswap_enabled = 1;
145 }
146
147 return ERROR_OK;
148 }
149
150 COMMAND_HANDLER(handle_mxc_biswap_command)
151 {
152 struct nand_device *nand = NULL;
153 struct mxc_nf_controller *mxc_nf_info = NULL;
154
155 if (CMD_ARGC < 1 || CMD_ARGC > 2)
156 return ERROR_COMMAND_SYNTAX_ERROR;
157
158 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
159 if (retval != ERROR_OK) {
160 command_print(CMD_CTX, "invalid nand device number or name: %s", CMD_ARGV[0]);
161 return ERROR_COMMAND_ARGUMENT_INVALID;
162 }
163
164 mxc_nf_info = nand->controller_priv;
165 if (CMD_ARGC == 2) {
166 if (strcmp(CMD_ARGV[1], "enable") == 0)
167 mxc_nf_info->flags.biswap_enabled = true;
168 else
169 mxc_nf_info->flags.biswap_enabled = false;
170 }
171 if (mxc_nf_info->flags.biswap_enabled)
172 command_print(CMD_CTX, "BI-swapping enabled on %s", nand->name);
173 else
174 command_print(CMD_CTX, "BI-swapping disabled on %s", nand->name);
175
176 return ERROR_OK;
177 }
178
179 static const struct command_registration mxc_sub_command_handlers[] = {
180 {
181 .name = "biswap",
182 .handler = handle_mxc_biswap_command,
183 .help = "Turns on/off bad block information swaping from main area, "
184 "without parameter query status.",
185 .usage = "bank_id ['enable'|'disable']",
186 },
187 COMMAND_REGISTRATION_DONE
188 };
189
190 static const struct command_registration mxc_nand_command_handler[] = {
191 {
192 .name = "mxc",
193 .mode = COMMAND_ANY,
194 .help = "MXC NAND flash controller commands",
195 .chain = mxc_sub_command_handlers
196 },
197 COMMAND_REGISTRATION_DONE
198 };
199
200 static int mxc_init(struct nand_device *nand)
201 {
202 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
203 struct target *target = nand->target;
204
205 int validate_target_result;
206 uint16_t buffsize_register_content;
207 uint32_t sreg_content;
208 uint32_t SREG = MX2_FMCR;
209 uint32_t SEL_16BIT = MX2_FMCR_NF_16BIT_SEL;
210 uint32_t SEL_FMS = MX2_FMCR_NF_FMS;
211 int retval;
212 uint16_t nand_status_content;
213 /*
214 * validate target state
215 */
216 validate_target_result = validate_target_state(nand);
217 if (validate_target_result != ERROR_OK)
218 return validate_target_result;
219
220 if (nfc_is_v1()) {
221 target_read_u16(target, MXC_NF_BUFSIZ, &buffsize_register_content);
222 mxc_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
223 } else
224 mxc_nf_info->flags.one_kb_sram = 0;
225
226 if (mxc_nf_info->mxc_version == MXC_VERSION_MX31) {
227 SREG = MX3_PCSR;
228 SEL_16BIT = MX3_PCSR_NF_16BIT_SEL;
229 SEL_FMS = MX3_PCSR_NF_FMS;
230 } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX25) {
231 SREG = MX25_RCSR;
232 SEL_16BIT = MX25_RCSR_NF_16BIT_SEL;
233 SEL_FMS = MX25_RCSR_NF_FMS;
234 } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX35) {
235 SREG = MX35_RCSR;
236 SEL_16BIT = MX35_RCSR_NF_16BIT_SEL;
237 SEL_FMS = MX35_RCSR_NF_FMS;
238 }
239
240 target_read_u32(target, SREG, &sreg_content);
241 if (!nand->bus_width) {
242 /* bus_width not yet defined. Read it from MXC_FMCR */
243 nand->bus_width = (sreg_content & SEL_16BIT) ? 16 : 8;
244 } else {
245 /* bus_width forced in soft. Sync it to MXC_FMCR */
246 sreg_content |= ((nand->bus_width == 16) ? SEL_16BIT : 0x00000000);
247 target_write_u32(target, SREG, sreg_content);
248 }
249 if (nand->bus_width == 16)
250 LOG_DEBUG("MXC_NF : bus is 16-bit width");
251 else
252 LOG_DEBUG("MXC_NF : bus is 8-bit width");
253
254 if (!nand->page_size)
255 nand->page_size = (sreg_content & SEL_FMS) ? 2048 : 512;
256 else {
257 sreg_content |= ((nand->page_size == 2048) ? SEL_FMS : 0x00000000);
258 target_write_u32(target, SREG, sreg_content);
259 }
260 if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
261 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
262 "pagesize 2048 is incompatible with it");
263 } else
264 LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
265
266 if (nfc_is_v2() && sreg_content & MX35_RCSR_NF_4K)
267 LOG_ERROR("MXC driver does not have support for 4k pagesize.");
268
269 initialize_nf_controller(nand);
270
271 retval = ERROR_OK;
272 retval |= mxc_command(nand, NAND_CMD_STATUS);
273 retval |= mxc_address(nand, 0x00);
274 retval |= do_data_output(nand);
275 if (retval != ERROR_OK) {
276 LOG_ERROR(get_status_register_err_msg);
277 return ERROR_FAIL;
278 }
279 target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
280 if (!(nand_status_content & 0x0080)) {
281 LOG_INFO("NAND read-only");
282 mxc_nf_info->flags.nand_readonly = 1;
283 } else
284 mxc_nf_info->flags.nand_readonly = 0;
285 return ERROR_OK;
286 }
287
288 static int mxc_read_data(struct nand_device *nand, void *data)
289 {
290 int validate_target_result;
291 int try_data_output_from_nand_chip;
292 /*
293 * validate target state
294 */
295 validate_target_result = validate_target_state(nand);
296 if (validate_target_result != ERROR_OK)
297 return validate_target_result;
298
299 /*
300 * get data from nand chip
301 */
302 try_data_output_from_nand_chip = do_data_output(nand);
303 if (try_data_output_from_nand_chip != ERROR_OK) {
304 LOG_ERROR("mxc_read_data : read data failed : '%x'",
305 try_data_output_from_nand_chip);
306 return try_data_output_from_nand_chip;
307 }
308
309 if (nand->bus_width == 16)
310 get_next_halfword_from_sram_buffer(nand, data);
311 else
312 get_next_byte_from_sram_buffer(nand, data);
313
314 return ERROR_OK;
315 }
316
317 static int mxc_write_data(struct nand_device *nand, uint16_t data)
318 {
319 LOG_ERROR("write_data() not implemented");
320 return ERROR_NAND_OPERATION_FAILED;
321 }
322
323 static int mxc_reset(struct nand_device *nand)
324 {
325 /*
326 * validate target state
327 */
328 int validate_target_result;
329 validate_target_result = validate_target_state(nand);
330 if (validate_target_result != ERROR_OK)
331 return validate_target_result;
332 initialize_nf_controller(nand);
333 return ERROR_OK;
334 }
335
336 static int mxc_command(struct nand_device *nand, uint8_t command)
337 {
338 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
339 struct target *target = nand->target;
340 int validate_target_result;
341 int poll_result;
342 /*
343 * validate target state
344 */
345 validate_target_result = validate_target_state(nand);
346 if (validate_target_result != ERROR_OK)
347 return validate_target_result;
348
349 switch (command) {
350 case NAND_CMD_READOOB:
351 command = NAND_CMD_READ0;
352 /* set read point for data_read() and read_block_data() to
353 * spare area in SRAM buffer
354 */
355 if (nfc_is_v1())
356 in_sram_address = MXC_NF_V1_SPARE_BUFFER0;
357 else
358 in_sram_address = MXC_NF_V2_SPARE_BUFFER0;
359 break;
360 case NAND_CMD_READ1:
361 command = NAND_CMD_READ0;
362 /*
363 * offset == one half of page size
364 */
365 in_sram_address = MXC_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
366 break;
367 default:
368 in_sram_address = MXC_NF_MAIN_BUFFER0;
369 break;
370 }
371
372 target_write_u16(target, MXC_NF_FCMD, command);
373 /*
374 * start command input operation (set MXC_NF_BIT_OP_DONE==0)
375 */
376 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FCI);
377 poll_result = poll_for_complete_op(nand, "command");
378 if (poll_result != ERROR_OK)
379 return poll_result;
380 /*
381 * reset cursor to begin of the buffer
382 */
383 sign_of_sequental_byte_read = 0;
384 /* Handle special read command and adjust NF_CFG2(FDO) */
385 switch (command) {
386 case NAND_CMD_READID:
387 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDID;
388 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
389 break;
390 case NAND_CMD_STATUS:
391 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
392 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
393 target_write_u16 (target, MXC_NF_BUFADDR, 0);
394 in_sram_address = 0;
395 break;
396 case NAND_CMD_READ0:
397 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
398 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
399 break;
400 default:
401 /* Ohter command use the default 'One page data out' FDO */
402 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
403 break;
404 }
405 return ERROR_OK;
406 }
407
408 static int mxc_address(struct nand_device *nand, uint8_t address)
409 {
410 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
411 struct target *target = nand->target;
412 int validate_target_result;
413 int poll_result;
414 /*
415 * validate target state
416 */
417 validate_target_result = validate_target_state(nand);
418 if (validate_target_result != ERROR_OK)
419 return validate_target_result;
420
421 target_write_u16(target, MXC_NF_FADDR, address);
422 /*
423 * start address input operation (set MXC_NF_BIT_OP_DONE==0)
424 */
425 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FAI);
426 poll_result = poll_for_complete_op(nand, "address");
427 if (poll_result != ERROR_OK)
428 return poll_result;
429
430 return ERROR_OK;
431 }
432
433 static int mxc_nand_ready(struct nand_device *nand, int tout)
434 {
435 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
436 struct target *target = nand->target;
437 uint16_t poll_complete_status;
438 int validate_target_result;
439
440 /*
441 * validate target state
442 */
443 validate_target_result = validate_target_state(nand);
444 if (validate_target_result != ERROR_OK)
445 return validate_target_result;
446
447 do {
448 target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
449 if (poll_complete_status & MXC_NF_BIT_OP_DONE)
450 return tout;
451
452 alive_sleep(1);
453 } while (tout-- > 0);
454 return tout;
455 }
456
457 static int mxc_write_page(struct nand_device *nand, uint32_t page,
458 uint8_t *data, uint32_t data_size,
459 uint8_t *oob, uint32_t oob_size)
460 {
461 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
462 struct target *target = nand->target;
463 int retval;
464 uint16_t nand_status_content;
465 uint16_t swap1, swap2, new_swap1;
466 uint8_t bufs;
467 int poll_result;
468
469 if (data_size % 2) {
470 LOG_ERROR(data_block_size_err_msg, data_size);
471 return ERROR_NAND_OPERATION_FAILED;
472 }
473 if (oob_size % 2) {
474 LOG_ERROR(data_block_size_err_msg, oob_size);
475 return ERROR_NAND_OPERATION_FAILED;
476 }
477 if (!data) {
478 LOG_ERROR("nothing to program");
479 return ERROR_NAND_OPERATION_FAILED;
480 }
481
482 /*
483 * validate target state
484 */
485 retval = validate_target_state(nand);
486 if (retval != ERROR_OK)
487 return retval;
488
489 in_sram_address = MXC_NF_MAIN_BUFFER0;
490 sign_of_sequental_byte_read = 0;
491 retval = ERROR_OK;
492 retval |= mxc_command(nand, NAND_CMD_SEQIN);
493 retval |= mxc_address(nand, 0); /* col */
494 retval |= mxc_address(nand, 0); /* col */
495 retval |= mxc_address(nand, page & 0xff); /* page address */
496 retval |= mxc_address(nand, (page >> 8) & 0xff);/* page address */
497 retval |= mxc_address(nand, (page >> 16) & 0xff); /* page address */
498
499 target_write_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
500 if (oob) {
501 if (mxc_nf_info->flags.hw_ecc_enabled) {
502 /*
503 * part of spare block will be overrided by hardware
504 * ECC generator
505 */
506 LOG_DEBUG("part of spare block will be overrided "
507 "by hardware ECC generator");
508 }
509 if (nfc_is_v1())
510 target_write_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
511 else {
512 uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
513 while (oob_size > 0) {
514 uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
515 target_write_buffer(target, addr, len, oob);
516 addr = align_address_v2(nand, addr + len);
517 oob += len;
518 oob_size -= len;
519 }
520 }
521 }
522
523 if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
524 /* BI-swap - work-around of i.MX NFC for NAND device with page == 2kb*/
525 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
526 if (oob) {
527 LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
528 return ERROR_NAND_OPERATION_FAILED;
529 }
530 swap2 = 0xffff; /* Spare buffer unused forced to 0xffff */
531 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
532 swap2 = (swap1 << 8) | (swap2 & 0xFF);
533 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
534 if (nfc_is_v1())
535 target_write_u16(target, MXC_NF_V1_SPARE_BUFFER3 + 4, swap2);
536 else
537 target_write_u16(target, MXC_NF_V2_SPARE_BUFFER3, swap2);
538 }
539
540 /*
541 * start data input operation (set MXC_NF_BIT_OP_DONE==0)
542 */
543 if (nfc_is_v1() && nand->page_size > 512)
544 bufs = 4;
545 else
546 bufs = 1;
547
548 for (uint8_t i = 0; i < bufs; ++i) {
549 target_write_u16(target, MXC_NF_BUFADDR, i);
550 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
551 poll_result = poll_for_complete_op(nand, "data input");
552 if (poll_result != ERROR_OK)
553 return poll_result;
554 }
555
556 retval |= mxc_command(nand, NAND_CMD_PAGEPROG);
557 if (retval != ERROR_OK)
558 return retval;
559
560 /*
561 * check status register
562 */
563 retval = ERROR_OK;
564 retval |= mxc_command(nand, NAND_CMD_STATUS);
565 target_write_u16 (target, MXC_NF_BUFADDR, 0);
566 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
567 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
568 retval |= do_data_output(nand);
569 if (retval != ERROR_OK) {
570 LOG_ERROR(get_status_register_err_msg);
571 return retval;
572 }
573 target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
574 if (nand_status_content & 0x0001) {
575 /*
576 * page not correctly written
577 */
578 return ERROR_NAND_OPERATION_FAILED;
579 }
580 #ifdef _MXC_PRINT_STAT
581 LOG_INFO("%d bytes newly written", data_size);
582 #endif
583 return ERROR_OK;
584 }
585
586 static int mxc_read_page(struct nand_device *nand, uint32_t page,
587 uint8_t *data, uint32_t data_size,
588 uint8_t *oob, uint32_t oob_size)
589 {
590 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
591 struct target *target = nand->target;
592 int retval;
593 uint8_t bufs;
594 uint16_t swap1, swap2, new_swap1;
595
596 if (data_size % 2) {
597 LOG_ERROR(data_block_size_err_msg, data_size);
598 return ERROR_NAND_OPERATION_FAILED;
599 }
600 if (oob_size % 2) {
601 LOG_ERROR(data_block_size_err_msg, oob_size);
602 return ERROR_NAND_OPERATION_FAILED;
603 }
604
605 /*
606 * validate target state
607 */
608 retval = validate_target_state(nand);
609 if (retval != ERROR_OK)
610 return retval;
611 /* Reset address_cycles before mxc_command ?? */
612 retval = mxc_command(nand, NAND_CMD_READ0);
613 if (retval != ERROR_OK)
614 return retval;
615 retval = mxc_address(nand, 0); /* col */
616 if (retval != ERROR_OK)
617 return retval;
618 retval = mxc_address(nand, 0); /* col */
619 if (retval != ERROR_OK)
620 return retval;
621 retval = mxc_address(nand, page & 0xff);/* page address */
622 if (retval != ERROR_OK)
623 return retval;
624 retval = mxc_address(nand, (page >> 8) & 0xff); /* page address */
625 if (retval != ERROR_OK)
626 return retval;
627 retval = mxc_address(nand, (page >> 16) & 0xff);/* page address */
628 if (retval != ERROR_OK)
629 return retval;
630 retval = mxc_command(nand, NAND_CMD_READSTART);
631 if (retval != ERROR_OK)
632 return retval;
633
634 if (nfc_is_v1() && nand->page_size > 512)
635 bufs = 4;
636 else
637 bufs = 1;
638
639 for (uint8_t i = 0; i < bufs; ++i) {
640 target_write_u16(target, MXC_NF_BUFADDR, i);
641 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
642 retval = do_data_output(nand);
643 if (retval != ERROR_OK) {
644 LOG_ERROR("MXC_NF : Error reading page %d", i);
645 return retval;
646 }
647 }
648
649 if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
650 uint32_t SPARE_BUFFER3;
651 /* BI-swap - work-around of mxc NFC for NAND device with page == 2k */
652 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
653 if (nfc_is_v1())
654 SPARE_BUFFER3 = MXC_NF_V1_SPARE_BUFFER3 + 4;
655 else
656 SPARE_BUFFER3 = MXC_NF_V2_SPARE_BUFFER3;
657 target_read_u16(target, SPARE_BUFFER3, &swap2);
658 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
659 swap2 = (swap1 << 8) | (swap2 & 0xFF);
660 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
661 target_write_u16(target, SPARE_BUFFER3, swap2);
662 }
663
664 if (data)
665 target_read_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
666 if (oob) {
667 if (nfc_is_v1())
668 target_read_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
669 else {
670 uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
671 while (oob_size > 0) {
672 uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
673 target_read_buffer(target, addr, len, oob);
674 addr = align_address_v2(nand, addr + len);
675 oob += len;
676 oob_size -= len;
677 }
678 }
679 }
680
681 #ifdef _MXC_PRINT_STAT
682 if (data_size > 0) {
683 /* When Operation Status is read (when page is erased),
684 * this function is used but data_size is null.
685 */
686 LOG_INFO("%d bytes newly read", data_size);
687 }
688 #endif
689 return ERROR_OK;
690 }
691
692 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr)
693 {
694 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
695 uint32_t ret = addr;
696 if (addr > MXC_NF_V2_SPARE_BUFFER0 &&
697 (addr & 0x1F) == MXC_NF_SPARE_BUFFER_LEN)
698 ret += MXC_NF_SPARE_BUFFER_MAX - MXC_NF_SPARE_BUFFER_LEN;
699 else if (addr >= (mxc_nf_info->mxc_base_addr + (uint32_t)nand->page_size))
700 ret = MXC_NF_V2_SPARE_BUFFER0;
701 return ret;
702 }
703
704 static int initialize_nf_controller(struct nand_device *nand)
705 {
706 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
707 struct target *target = nand->target;
708 uint16_t work_mode = 0;
709 uint16_t temp;
710 /*
711 * resets NAND flash controller in zero time ? I dont know.
712 */
713 target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
714 if (mxc_nf_info->mxc_version == MXC_VERSION_MX27)
715 work_mode = MXC_NF_BIT_INT_DIS; /* disable interrupt */
716
717 if (target->endianness == TARGET_BIG_ENDIAN) {
718 LOG_DEBUG("MXC_NF : work in Big Endian mode");
719 work_mode |= MXC_NF_BIT_BE_EN;
720 } else
721 LOG_DEBUG("MXC_NF : work in Little Endian mode");
722 if (mxc_nf_info->flags.hw_ecc_enabled) {
723 LOG_DEBUG("MXC_NF : work with ECC mode");
724 work_mode |= MXC_NF_BIT_ECC_EN;
725 } else
726 LOG_DEBUG("MXC_NF : work without ECC mode");
727 if (nfc_is_v2()) {
728 target_write_u16(target, MXC_NF_V2_SPAS, OOB_SIZE / 2);
729 if (nand->page_size) {
730 uint16_t pages_per_block = nand->erase_size / nand->page_size;
731 work_mode |= MXC_NF_V2_CFG1_PPB(ffs(pages_per_block) - 6);
732 }
733 work_mode |= MXC_NF_BIT_ECC_4BIT;
734 }
735 target_write_u16(target, MXC_NF_CFG1, work_mode);
736
737 /*
738 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
739 */
740 target_write_u16(target, MXC_NF_BUFCFG, 2);
741 target_read_u16(target, MXC_NF_FWP, &temp);
742 if ((temp & 0x0007) == 1) {
743 LOG_ERROR("NAND flash is tight-locked, reset needed");
744 return ERROR_FAIL;
745 }
746
747 /*
748 * unlock NAND flash for write
749 */
750 if (nfc_is_v1()) {
751 target_write_u16(target, MXC_NF_V1_UNLOCKSTART, 0x0000);
752 target_write_u16(target, MXC_NF_V1_UNLOCKEND, 0xFFFF);
753 } else {
754 target_write_u16(target, MXC_NF_V2_UNLOCKSTART0, 0x0000);
755 target_write_u16(target, MXC_NF_V2_UNLOCKSTART1, 0x0000);
756 target_write_u16(target, MXC_NF_V2_UNLOCKSTART2, 0x0000);
757 target_write_u16(target, MXC_NF_V2_UNLOCKSTART3, 0x0000);
758 target_write_u16(target, MXC_NF_V2_UNLOCKEND0, 0xFFFF);
759 target_write_u16(target, MXC_NF_V2_UNLOCKEND1, 0xFFFF);
760 target_write_u16(target, MXC_NF_V2_UNLOCKEND2, 0xFFFF);
761 target_write_u16(target, MXC_NF_V2_UNLOCKEND3, 0xFFFF);
762 }
763 target_write_u16(target, MXC_NF_FWP, 4);
764
765 /*
766 * 0x0000 means that first SRAM buffer @base_addr will be used
767 */
768 target_write_u16(target, MXC_NF_BUFADDR, 0x0000);
769 /*
770 * address of SRAM buffer
771 */
772 in_sram_address = MXC_NF_MAIN_BUFFER0;
773 sign_of_sequental_byte_read = 0;
774 return ERROR_OK;
775 }
776
777 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value)
778 {
779 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
780 struct target *target = nand->target;
781 static uint8_t even_byte;
782 uint16_t temp;
783 /*
784 * host-big_endian ??
785 */
786 if (sign_of_sequental_byte_read == 0)
787 even_byte = 0;
788
789 if (in_sram_address > (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
790 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
791 *value = 0;
792 sign_of_sequental_byte_read = 0;
793 even_byte = 0;
794 return ERROR_NAND_OPERATION_FAILED;
795 } else {
796 if (nfc_is_v2())
797 in_sram_address = align_address_v2(nand, in_sram_address);
798
799 target_read_u16(target, in_sram_address, &temp);
800 if (even_byte) {
801 *value = temp >> 8;
802 even_byte = 0;
803 in_sram_address += 2;
804 } else {
805 *value = temp & 0xff;
806 even_byte = 1;
807 }
808 }
809 sign_of_sequental_byte_read = 1;
810 return ERROR_OK;
811 }
812
813 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value)
814 {
815 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
816 struct target *target = nand->target;
817
818 if (in_sram_address > (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
819 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
820 *value = 0;
821 return ERROR_NAND_OPERATION_FAILED;
822 } else {
823 if (nfc_is_v2())
824 in_sram_address = align_address_v2(nand, in_sram_address);
825
826 target_read_u16(target, in_sram_address, value);
827 in_sram_address += 2;
828 }
829 return ERROR_OK;
830 }
831
832 static int poll_for_complete_op(struct nand_device *nand, const char *text)
833 {
834 if (mxc_nand_ready(nand, 1000) == -1) {
835 LOG_ERROR("%s sending timeout", text);
836 return ERROR_NAND_OPERATION_FAILED;
837 }
838 return ERROR_OK;
839 }
840
841 static int validate_target_state(struct nand_device *nand)
842 {
843 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
844 struct target *target = nand->target;
845
846 if (target->state != TARGET_HALTED) {
847 LOG_ERROR(target_not_halted_err_msg);
848 return ERROR_NAND_OPERATION_FAILED;
849 }
850
851 if (mxc_nf_info->flags.target_little_endian !=
852 (target->endianness == TARGET_LITTLE_ENDIAN)) {
853 /*
854 * endianness changed after NAND controller probed
855 */
856 return ERROR_NAND_OPERATION_FAILED;
857 }
858 return ERROR_OK;
859 }
860
861 int ecc_status_v1(struct nand_device *nand)
862 {
863 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
864 struct target *target = nand->target;
865 uint16_t ecc_status;
866
867 target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
868 switch (ecc_status & 0x000c) {
869 case 1 << 2:
870 LOG_INFO("main area read with 1 (correctable) error");
871 break;
872 case 2 << 2:
873 LOG_INFO("main area read with more than 1 (incorrectable) error");
874 return ERROR_NAND_OPERATION_FAILED;
875 break;
876 }
877 switch (ecc_status & 0x0003) {
878 case 1:
879 LOG_INFO("spare area read with 1 (correctable) error");
880 break;
881 case 2:
882 LOG_INFO("main area read with more than 1 (incorrectable) error");
883 return ERROR_NAND_OPERATION_FAILED;
884 break;
885 }
886 return ERROR_OK;
887 }
888
889 int ecc_status_v2(struct nand_device *nand)
890 {
891 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
892 struct target *target = nand->target;
893 uint16_t ecc_status;
894 uint8_t no_subpages;
895 uint8_t err;
896
897 no_subpages = nand->page_size >> 9;
898
899 target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
900 do {
901 err = ecc_status & 0xF;
902 if (err > 4) {
903 LOG_INFO("UnCorrectable RS-ECC Error");
904 return ERROR_NAND_OPERATION_FAILED;
905 } else if (err > 0)
906 LOG_INFO("%d Symbol Correctable RS-ECC Error", err);
907 ecc_status >>= 4;
908 } while (--no_subpages);
909 return ERROR_OK;
910 }
911
912 static int do_data_output(struct nand_device *nand)
913 {
914 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
915 struct target *target = nand->target;
916 int poll_result;
917 switch (mxc_nf_info->fin) {
918 case MXC_NF_FIN_DATAOUT:
919 /*
920 * start data output operation (set MXC_NF_BIT_OP_DONE==0)
921 */
922 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info->optype));
923 poll_result = poll_for_complete_op(nand, "data output");
924 if (poll_result != ERROR_OK)
925 return poll_result;
926
927 mxc_nf_info->fin = MXC_NF_FIN_NONE;
928 /*
929 * ECC stuff
930 */
931 if (mxc_nf_info->optype == MXC_NF_DATAOUT_PAGE && mxc_nf_info->flags.hw_ecc_enabled) {
932 int ecc_status;
933 if (nfc_is_v1())
934 ecc_status = ecc_status_v1(nand);
935 else
936 ecc_status = ecc_status_v2(nand);
937 if (ecc_status != ERROR_OK)
938 return ecc_status;
939 }
940 break;
941 case MXC_NF_FIN_NONE:
942 break;
943 }
944 return ERROR_OK;
945 }
946
947 struct nand_flash_controller mxc_nand_flash_controller = {
948 .name = "mxc",
949 .nand_device_command = &mxc_nand_device_command,
950 .commands = mxc_nand_command_handler,
951 .init = &mxc_init,
952 .reset = &mxc_reset,
953 .command = &mxc_command,
954 .address = &mxc_address,
955 .write_data = &mxc_write_data,
956 .read_data = &mxc_read_data,
957 .write_page = &mxc_write_page,
958 .read_page = &mxc_read_page,
959 .nand_ready = &mxc_nand_ready,
960 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)