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Renamed mx2.{c,h} to mxc.{c,h} and added copyright notice
[openocd.git] / src / flash / nand / mxc.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Alexei Babich *
3 * Rezonans plc., Chelyabinsk, Russia *
4 * impatt@mail.ru *
5 * *
6 * Copyright (C) 2010 by Gaetan CARLIER *
7 * Trump s.a., Belgium *
8 * *
9 * Copyright (C) 2011 by Erik Ahlen *
10 * Avalon Innovation, Sweden *
11 * *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
16 * *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
21 * *
22 * You should have received a copy of the GNU General Public License *
23 * along with this program; if not, write to the *
24 * Free Software Foundation, Inc., *
25 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
26 ***************************************************************************/
27
28 /*
29 * Freescale iMX OpenOCD NAND Flash controller support.
30 * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
31 */
32
33 /*
34 * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
35 * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
36 * "nand write # file 0", "nand verify"
37 *
38 * get_next_halfword_from_sram_buffer() not tested
39 * !! all function only tested with 2k page nand device; mxc_write_page
40 * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
41 * !! oob must be be used due to NFS bug
42 */
43 #ifdef HAVE_CONFIG_H
44 #include "config.h"
45 #endif
46
47 #include "imp.h"
48 #include "mxc.h"
49 #include <target/target.h>
50
51 #define nfc_is_v1() (mxc_nf_info->mxc_version == MXC_VERSION_MX27 || \
52 mxc_nf_info->mxc_version == MXC_VERSION_MX31)
53 #define nfc_is_v2() (mxc_nf_info->mxc_version == MXC_VERSION_MX35)
54
55 /* This permits to print (in LOG_INFO) how much bytes
56 * has been written after a page read or write.
57 * This is useful when OpenOCD is used with a graphical
58 * front-end to estimate progression of the global read/write
59 */
60 #undef _MXC_PRINT_STAT
61 /* #define _MXC_PRINT_STAT */
62
63 static const char target_not_halted_err_msg[] =
64 "target must be halted to use mxc NAND flash controller";
65 static const char data_block_size_err_msg[] =
66 "minimal granularity is one half-word, %" PRId32 " is incorrect";
67 static const char sram_buffer_bounds_err_msg[] =
68 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
69 static const char get_status_register_err_msg[] = "can't get NAND status";
70 static uint32_t in_sram_address;
71 static unsigned char sign_of_sequental_byte_read;
72
73 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr);
74 static int initialize_nf_controller(struct nand_device *nand);
75 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value);
76 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value);
77 static int poll_for_complete_op(struct nand_device *nand, const char *text);
78 static int validate_target_state(struct nand_device *nand);
79 static int do_data_output(struct nand_device *nand);
80
81 static int mxc_command(struct nand_device *nand, uint8_t command);
82 static int mxc_address(struct nand_device *nand, uint8_t address);
83
84 NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
85 {
86 struct mxc_nf_controller *mxc_nf_info;
87 int hwecc_needed;
88 int x;
89
90 mxc_nf_info = malloc(sizeof(struct mxc_nf_controller));
91 if (mxc_nf_info == NULL) {
92 LOG_ERROR("no memory for nand controller");
93 return ERROR_FAIL;
94 }
95 nand->controller_priv = mxc_nf_info;
96
97 if (CMD_ARGC < 4) {
98 LOG_ERROR("use \"nand device mxc target mx27|mx31|mx35 noecc|hwecc [biswap]\"");
99 return ERROR_FAIL;
100 }
101
102 /*
103 * check board type
104 */
105 if (strcmp(CMD_ARGV[2], "mx27") == 0) {
106 mxc_nf_info->mxc_version = MXC_VERSION_MX27;
107 mxc_nf_info->mxc_base_addr = 0xD8000000;
108 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
109 } else if (strcmp(CMD_ARGV[2], "mx31") == 0) {
110 mxc_nf_info->mxc_version = MXC_VERSION_MX31;
111 mxc_nf_info->mxc_base_addr = 0xB8000000;
112 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
113 } else if (strcmp(CMD_ARGV[2], "mx35") == 0) {
114 mxc_nf_info->mxc_version = MXC_VERSION_MX35;
115 mxc_nf_info->mxc_base_addr = 0xBB000000;
116 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
117 }
118
119 /*
120 * check hwecc requirements
121 */
122 hwecc_needed = strcmp(CMD_ARGV[3], "hwecc");
123 if (hwecc_needed == 0)
124 mxc_nf_info->flags.hw_ecc_enabled = 1;
125 else
126 mxc_nf_info->flags.hw_ecc_enabled = 0;
127
128 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
129 mxc_nf_info->fin = MXC_NF_FIN_NONE;
130 mxc_nf_info->flags.target_little_endian =
131 (nand->target->endianness == TARGET_LITTLE_ENDIAN);
132
133 /*
134 * should factory bad block indicator be swaped
135 * as a workaround for how the nfc handles pages.
136 */
137 if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
138 LOG_DEBUG("BI-swap enabled");
139 mxc_nf_info->flags.biswap_enabled = 1;
140 }
141
142 /*
143 * testing host endianness
144 */
145 x = 1;
146 if (*(char *) &x == 1)
147 mxc_nf_info->flags.host_little_endian = 1;
148 else
149 mxc_nf_info->flags.host_little_endian = 0;
150 return ERROR_OK;
151 }
152
153 COMMAND_HANDLER(handle_mxc_biswap_command)
154 {
155 struct nand_device *nand = NULL;
156 struct mxc_nf_controller *mxc_nf_info = NULL;
157
158 if (CMD_ARGC < 1 || CMD_ARGC > 2)
159 return ERROR_COMMAND_SYNTAX_ERROR;
160
161 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
162 if (retval != ERROR_OK) {
163 command_print(CMD_CTX, "invalid nand device number or name: %s", CMD_ARGV[0]);
164 return ERROR_COMMAND_ARGUMENT_INVALID;
165 }
166
167 mxc_nf_info = nand->controller_priv;
168 if (CMD_ARGC == 2) {
169 if (strcmp(CMD_ARGV[1], "enable") == 0)
170 mxc_nf_info->flags.biswap_enabled = true;
171 else
172 mxc_nf_info->flags.biswap_enabled = false;
173 }
174 if (mxc_nf_info->flags.biswap_enabled)
175 command_print(CMD_CTX, "BI-swapping enabled on %s", nand->name);
176 else
177 command_print(CMD_CTX, "BI-swapping disabled on %s", nand->name);
178
179 return ERROR_OK;
180 }
181
182 static const struct command_registration mxc_sub_command_handlers[] = {
183 {
184 .name = "biswap",
185 .handler = handle_mxc_biswap_command ,
186 .help = "Turns on/off bad block information swaping from main area, "
187 "without parameter query status.",
188 .usage = "bank_id ['enable'|'disable']",
189 },
190 COMMAND_REGISTRATION_DONE
191 };
192
193 static const struct command_registration mxc_nand_command_handler[] = {
194 {
195 .name = "mxc",
196 .mode = COMMAND_ANY,
197 .help = "MXC NAND flash controller commands",
198 .chain = mxc_sub_command_handlers
199 },
200 COMMAND_REGISTRATION_DONE
201 };
202
203 static int mxc_init(struct nand_device *nand)
204 {
205 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
206 struct target *target = nand->target;
207
208 int validate_target_result;
209 uint16_t buffsize_register_content;
210 uint32_t sreg_content;
211 uint32_t SREG = MX2_FMCR;
212 uint32_t SEL_16BIT = MX2_FMCR_NF_16BIT_SEL;
213 uint32_t SEL_FMS = MX2_FMCR_NF_FMS;
214 int retval;
215 uint16_t nand_status_content;
216 /*
217 * validate target state
218 */
219 validate_target_result = validate_target_state(nand);
220 if (validate_target_result != ERROR_OK)
221 return validate_target_result;
222
223 if (nfc_is_v1()) {
224 target_read_u16(target, MXC_NF_BUFSIZ, &buffsize_register_content);
225 mxc_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
226 } else
227 mxc_nf_info->flags.one_kb_sram = 0;
228
229 if (mxc_nf_info->mxc_version == MXC_VERSION_MX31) {
230 SREG = MX3_PCSR;
231 SEL_16BIT = MX3_PCSR_NF_16BIT_SEL;
232 SEL_FMS = MX3_PCSR_NF_FMS;
233 } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX35) {
234 SREG = MX35_RCSR;
235 SEL_16BIT = MX35_RCSR_NF_16BIT_SEL;
236 SEL_FMS = MX35_RCSR_NF_FMS;
237 }
238
239 target_read_u32(target, SREG, &sreg_content);
240 if (!nand->bus_width) {
241 /* bus_width not yet defined. Read it from MXC_FMCR */
242 nand->bus_width = (sreg_content & SEL_16BIT) ? 16 : 8;
243 } else {
244 /* bus_width forced in soft. Sync it to MXC_FMCR */
245 sreg_content |= ((nand->bus_width == 16) ? SEL_16BIT : 0x00000000);
246 target_write_u32(target, SREG, sreg_content);
247 }
248 if (nand->bus_width == 16)
249 LOG_DEBUG("MXC_NF : bus is 16-bit width");
250 else
251 LOG_DEBUG("MXC_NF : bus is 8-bit width");
252
253 if (!nand->page_size) {
254 nand->page_size = (sreg_content & SEL_FMS) ? 2048 : 512;
255 } else {
256 sreg_content |= ((nand->page_size == 2048) ? SEL_FMS : 0x00000000);
257 target_write_u32(target, SREG, sreg_content);
258 }
259 if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
260 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
261 "pagesize 2048 is incompatible with it");
262 } else {
263 LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
264 }
265
266 if (nfc_is_v2() && sreg_content & MX35_RCSR_NF_4K)
267 LOG_ERROR("MXC driver does not have support for 4k pagesize.");
268
269 initialize_nf_controller(nand);
270
271 retval = ERROR_OK;
272 retval |= mxc_command(nand, NAND_CMD_STATUS);
273 retval |= mxc_address(nand, 0x00);
274 retval |= do_data_output(nand);
275 if (retval != ERROR_OK) {
276 LOG_ERROR(get_status_register_err_msg);
277 return ERROR_FAIL;
278 }
279 target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
280 if (!(nand_status_content & 0x0080)) {
281 LOG_INFO("NAND read-only");
282 mxc_nf_info->flags.nand_readonly = 1;
283 } else {
284 mxc_nf_info->flags.nand_readonly = 0;
285 }
286 return ERROR_OK;
287 }
288
289 static int mxc_read_data(struct nand_device *nand, void *data)
290 {
291 int validate_target_result;
292 int try_data_output_from_nand_chip;
293 /*
294 * validate target state
295 */
296 validate_target_result = validate_target_state(nand);
297 if (validate_target_result != ERROR_OK)
298 return validate_target_result;
299
300 /*
301 * get data from nand chip
302 */
303 try_data_output_from_nand_chip = do_data_output(nand);
304 if (try_data_output_from_nand_chip != ERROR_OK) {
305 LOG_ERROR("mxc_read_data : read data failed : '%x'",
306 try_data_output_from_nand_chip);
307 return try_data_output_from_nand_chip;
308 }
309
310 if (nand->bus_width == 16)
311 get_next_halfword_from_sram_buffer(nand, data);
312 else
313 get_next_byte_from_sram_buffer(nand, data);
314
315 return ERROR_OK;
316 }
317
318 static int mxc_write_data(struct nand_device *nand, uint16_t data)
319 {
320 LOG_ERROR("write_data() not implemented");
321 return ERROR_NAND_OPERATION_FAILED;
322 }
323
324 static int mxc_reset(struct nand_device *nand)
325 {
326 /*
327 * validate target state
328 */
329 int validate_target_result;
330 validate_target_result = validate_target_state(nand);
331 if (validate_target_result != ERROR_OK)
332 return validate_target_result;
333 initialize_nf_controller(nand);
334 return ERROR_OK;
335 }
336
337 static int mxc_command(struct nand_device *nand, uint8_t command)
338 {
339 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
340 struct target *target = nand->target;
341 int validate_target_result;
342 int poll_result;
343 /*
344 * validate target state
345 */
346 validate_target_result = validate_target_state(nand);
347 if (validate_target_result != ERROR_OK)
348 return validate_target_result;
349
350 switch (command) {
351 case NAND_CMD_READOOB:
352 command = NAND_CMD_READ0;
353 /* set read point for data_read() and read_block_data() to
354 * spare area in SRAM buffer
355 */
356 if (nfc_is_v1())
357 in_sram_address = MXC_NF_V1_SPARE_BUFFER0;
358 else
359 in_sram_address = MXC_NF_V2_SPARE_BUFFER0;
360 break;
361 case NAND_CMD_READ1:
362 command = NAND_CMD_READ0;
363 /*
364 * offset == one half of page size
365 */
366 in_sram_address = MXC_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
367 break;
368 default:
369 in_sram_address = MXC_NF_MAIN_BUFFER0;
370 break;
371 }
372
373 target_write_u16(target, MXC_NF_FCMD, command);
374 /*
375 * start command input operation (set MXC_NF_BIT_OP_DONE==0)
376 */
377 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FCI);
378 poll_result = poll_for_complete_op(nand, "command");
379 if (poll_result != ERROR_OK)
380 return poll_result;
381 /*
382 * reset cursor to begin of the buffer
383 */
384 sign_of_sequental_byte_read = 0;
385 /* Handle special read command and adjust NF_CFG2(FDO) */
386 switch (command) {
387 case NAND_CMD_READID:
388 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDID;
389 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
390 break;
391 case NAND_CMD_STATUS:
392 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
393 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
394 target_write_u16 (target, MXC_NF_BUFADDR, 0);
395 in_sram_address = 0;
396 break;
397 case NAND_CMD_READ0:
398 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
399 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
400 break;
401 default:
402 /* Ohter command use the default 'One page data out' FDO */
403 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
404 break;
405 }
406 return ERROR_OK;
407 }
408
409 static int mxc_address(struct nand_device *nand, uint8_t address)
410 {
411 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
412 struct target *target = nand->target;
413 int validate_target_result;
414 int poll_result;
415 /*
416 * validate target state
417 */
418 validate_target_result = validate_target_state(nand);
419 if (validate_target_result != ERROR_OK)
420 return validate_target_result;
421
422 target_write_u16(target, MXC_NF_FADDR, address);
423 /*
424 * start address input operation (set MXC_NF_BIT_OP_DONE==0)
425 */
426 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FAI);
427 poll_result = poll_for_complete_op(nand, "address");
428 if (poll_result != ERROR_OK)
429 return poll_result;
430
431 return ERROR_OK;
432 }
433
434 static int mxc_nand_ready(struct nand_device *nand, int tout)
435 {
436 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
437 struct target *target = nand->target;
438 uint16_t poll_complete_status;
439 int validate_target_result;
440
441 /*
442 * validate target state
443 */
444 validate_target_result = validate_target_state(nand);
445 if (validate_target_result != ERROR_OK)
446 return validate_target_result;
447
448 do {
449 target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
450 if (poll_complete_status & MXC_NF_BIT_OP_DONE)
451 return tout;
452
453 alive_sleep(1);
454 }
455 while (tout-- > 0);
456 return tout;
457 }
458
459 static int mxc_write_page(struct nand_device *nand, uint32_t page,
460 uint8_t *data, uint32_t data_size,
461 uint8_t *oob, uint32_t oob_size)
462 {
463 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
464 struct target *target = nand->target;
465 int retval;
466 uint16_t nand_status_content;
467 uint16_t swap1, swap2, new_swap1;
468 uint8_t bufs;
469 int poll_result;
470
471 if (data_size % 2) {
472 LOG_ERROR(data_block_size_err_msg, data_size);
473 return ERROR_NAND_OPERATION_FAILED;
474 }
475 if (oob_size % 2) {
476 LOG_ERROR(data_block_size_err_msg, oob_size);
477 return ERROR_NAND_OPERATION_FAILED;
478 }
479 if (!data) {
480 LOG_ERROR("nothing to program");
481 return ERROR_NAND_OPERATION_FAILED;
482 }
483
484 /*
485 * validate target state
486 */
487 retval = validate_target_state(nand);
488 if (retval != ERROR_OK)
489 return retval;
490
491 in_sram_address = MXC_NF_MAIN_BUFFER0;
492 sign_of_sequental_byte_read = 0;
493 retval = ERROR_OK;
494 retval |= mxc_command(nand, NAND_CMD_SEQIN);
495 retval |= mxc_address(nand, 0); /* col */
496 retval |= mxc_address(nand, 0); /* col */
497 retval |= mxc_address(nand, page & 0xff); /* page address */
498 retval |= mxc_address(nand, (page >> 8) & 0xff); /* page address */
499 retval |= mxc_address(nand, (page >> 16) & 0xff); /* page address */
500
501 target_write_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
502 if (oob) {
503 if (mxc_nf_info->flags.hw_ecc_enabled) {
504 /*
505 * part of spare block will be overrided by hardware
506 * ECC generator
507 */
508 LOG_DEBUG("part of spare block will be overrided "
509 "by hardware ECC generator");
510 }
511 if (nfc_is_v1())
512 target_write_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
513 else {
514 uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
515 while (oob_size > 0) {
516 uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
517 target_write_buffer(target, addr, len, oob);
518 addr = align_address_v2(nand, addr + len);
519 oob += len;
520 oob_size -= len;
521 }
522 }
523 }
524
525 if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
526 /* BI-swap - work-around of i.MX NFC for NAND device with page == 2kb*/
527 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
528 if (oob) {
529 LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
530 return ERROR_NAND_OPERATION_FAILED;
531 }
532 swap2 = 0xffff; /* Spare buffer unused forced to 0xffff */
533 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
534 swap2 = (swap1 << 8) | (swap2 & 0xFF);
535 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
536 if (nfc_is_v1())
537 target_write_u16(target, MXC_NF_V1_SPARE_BUFFER3, swap2);
538 else
539 target_write_u16(target, MXC_NF_V2_SPARE_BUFFER3, swap2);
540 }
541
542 /*
543 * start data input operation (set MXC_NF_BIT_OP_DONE==0)
544 */
545 if (nfc_is_v1() && nand->page_size > 512)
546 bufs = 4;
547 else
548 bufs = 1;
549
550 for (uint8_t i = 0 ; i < bufs ; ++i) {
551 target_write_u16(target, MXC_NF_BUFADDR, i);
552 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
553 poll_result = poll_for_complete_op(nand, "data input");
554 if (poll_result != ERROR_OK)
555 return poll_result;
556 }
557
558 retval |= mxc_command(nand, NAND_CMD_PAGEPROG);
559 if (retval != ERROR_OK)
560 return retval;
561
562 /*
563 * check status register
564 */
565 retval = ERROR_OK;
566 retval |= mxc_command(nand, NAND_CMD_STATUS);
567 target_write_u16 (target, MXC_NF_BUFADDR, 0);
568 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
569 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
570 retval |= do_data_output(nand);
571 if (retval != ERROR_OK) {
572 LOG_ERROR(get_status_register_err_msg);
573 return retval;
574 }
575 target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
576 if (nand_status_content & 0x0001) {
577 /*
578 * page not correctly written
579 */
580 return ERROR_NAND_OPERATION_FAILED;
581 }
582 #ifdef _MXC_PRINT_STAT
583 LOG_INFO("%d bytes newly written", data_size);
584 #endif
585 return ERROR_OK;
586 }
587
588 static int mxc_read_page(struct nand_device *nand, uint32_t page,
589 uint8_t *data, uint32_t data_size,
590 uint8_t *oob, uint32_t oob_size)
591 {
592 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
593 struct target *target = nand->target;
594 int retval;
595 uint8_t bufs;
596 uint16_t swap1, swap2, new_swap1;
597
598 if (data_size % 2) {
599 LOG_ERROR(data_block_size_err_msg, data_size);
600 return ERROR_NAND_OPERATION_FAILED;
601 }
602 if (oob_size % 2) {
603 LOG_ERROR(data_block_size_err_msg, oob_size);
604 return ERROR_NAND_OPERATION_FAILED;
605 }
606
607 /*
608 * validate target state
609 */
610 retval = validate_target_state(nand);
611 if (retval != ERROR_OK) {
612 return retval;
613 }
614 /* Reset address_cycles before mxc_command ?? */
615 retval = mxc_command(nand, NAND_CMD_READ0);
616 if (retval != ERROR_OK) return retval;
617 retval = mxc_address(nand, 0); /* col */
618 if (retval != ERROR_OK) return retval;
619 retval = mxc_address(nand, 0); /* col */
620 if (retval != ERROR_OK) return retval;
621 retval = mxc_address(nand, page & 0xff); /* page address */
622 if (retval != ERROR_OK) return retval;
623 retval = mxc_address(nand, (page >> 8) & 0xff); /* page address */
624 if (retval != ERROR_OK) return retval;
625 retval = mxc_address(nand, (page >> 16) & 0xff); /* page address */
626 if (retval != ERROR_OK) return retval;
627 retval = mxc_command(nand, NAND_CMD_READSTART);
628 if (retval != ERROR_OK) return retval;
629
630 if (nfc_is_v1() && nand->page_size > 512)
631 bufs = 4;
632 else
633 bufs = 1;
634
635 for (uint8_t i = 0 ; i < bufs ; ++i) {
636 target_write_u16(target, MXC_NF_BUFADDR, i);
637 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
638 retval = do_data_output(nand);
639 if (retval != ERROR_OK) {
640 LOG_ERROR("MXC_NF : Error reading page %d", i);
641 return retval;
642 }
643 }
644
645 if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
646 uint32_t SPARE_BUFFER3;
647 /* BI-swap - work-around of mxc NFC for NAND device with page == 2k */
648 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
649 if (nfc_is_v1())
650 SPARE_BUFFER3 = MXC_NF_V1_SPARE_BUFFER3;
651 else
652 SPARE_BUFFER3 = MXC_NF_V2_SPARE_BUFFER3;
653 target_read_u16(target, SPARE_BUFFER3, &swap2);
654 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
655 swap2 = (swap1 << 8) | (swap2 & 0xFF);
656 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
657 target_write_u16(target, SPARE_BUFFER3, swap2);
658 }
659
660 if (data)
661 target_read_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
662 if (oob) {
663 if (nfc_is_v1())
664 target_read_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
665 else {
666 uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
667 while (oob_size > 0) {
668 uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
669 target_read_buffer(target, addr, len, oob);
670 addr = align_address_v2(nand, addr + len);
671 oob += len;
672 oob_size -= len;
673 }
674 }
675 }
676
677 #ifdef _MXC_PRINT_STAT
678 if (data_size > 0) {
679 /* When Operation Status is read (when page is erased),
680 * this function is used but data_size is null.
681 */
682 LOG_INFO("%d bytes newly read", data_size);
683 }
684 #endif
685 return ERROR_OK;
686 }
687
688 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr)
689 {
690 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
691 uint32_t ret = addr;
692 if (addr > MXC_NF_V2_SPARE_BUFFER0 &&
693 (addr & 0x1F) == MXC_NF_SPARE_BUFFER_LEN) {
694 ret += MXC_NF_SPARE_BUFFER_MAX - MXC_NF_SPARE_BUFFER_LEN;
695 } else if (addr >= (mxc_nf_info->mxc_base_addr + (uint32_t)nand->page_size))
696 ret = MXC_NF_V2_SPARE_BUFFER0;
697 return ret;
698 }
699
700 static int initialize_nf_controller(struct nand_device *nand)
701 {
702 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
703 struct target *target = nand->target;
704 uint16_t work_mode = 0;
705 uint16_t temp;
706 /*
707 * resets NAND flash controller in zero time ? I dont know.
708 */
709 target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
710 if (mxc_nf_info->mxc_version == MXC_VERSION_MX27)
711 work_mode = MXC_NF_BIT_INT_DIS; /* disable interrupt */
712
713 if (target->endianness == TARGET_BIG_ENDIAN) {
714 LOG_DEBUG("MXC_NF : work in Big Endian mode");
715 work_mode |= MXC_NF_BIT_BE_EN;
716 } else {
717 LOG_DEBUG("MXC_NF : work in Little Endian mode");
718 }
719 if (mxc_nf_info->flags.hw_ecc_enabled) {
720 LOG_DEBUG("MXC_NF : work with ECC mode");
721 work_mode |= MXC_NF_BIT_ECC_EN;
722 } else {
723 LOG_DEBUG("MXC_NF : work without ECC mode");
724 }
725 if (nfc_is_v2()) {
726 if (nand->page_size) {
727 uint16_t pages_per_block = nand->erase_size / nand->page_size;
728 work_mode |= MXC_NF_V2_CFG1_PPB(ffs(pages_per_block) - 6);
729 }
730 work_mode |= MXC_NF_BIT_ECC_4BIT;
731 }
732 target_write_u16(target, MXC_NF_CFG1, work_mode);
733
734 /*
735 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
736 */
737 target_write_u16(target, MXC_NF_BUFCFG, 2);
738 target_read_u16(target, MXC_NF_FWP, &temp);
739 if ((temp & 0x0007) == 1) {
740 LOG_ERROR("NAND flash is tight-locked, reset needed");
741 return ERROR_FAIL;
742 }
743
744 /*
745 * unlock NAND flash for write
746 */
747 if (nfc_is_v1()) {
748 target_write_u16(target, MXC_NF_V1_UNLOCKSTART, 0x0000);
749 target_write_u16(target, MXC_NF_V1_UNLOCKEND, 0xFFFF);
750 } else {
751 target_write_u16(target, MXC_NF_V2_UNLOCKSTART0, 0x0000);
752 target_write_u16(target, MXC_NF_V2_UNLOCKSTART1, 0x0000);
753 target_write_u16(target, MXC_NF_V2_UNLOCKSTART2, 0x0000);
754 target_write_u16(target, MXC_NF_V2_UNLOCKSTART3, 0x0000);
755 target_write_u16(target, MXC_NF_V2_UNLOCKEND0, 0xFFFF);
756 target_write_u16(target, MXC_NF_V2_UNLOCKEND1, 0xFFFF);
757 target_write_u16(target, MXC_NF_V2_UNLOCKEND2, 0xFFFF);
758 target_write_u16(target, MXC_NF_V2_UNLOCKEND3, 0xFFFF);
759 }
760 target_write_u16(target, MXC_NF_FWP, 4);
761
762 /*
763 * 0x0000 means that first SRAM buffer @base_addr will be used
764 */
765 target_write_u16(target, MXC_NF_BUFADDR, 0x0000);
766 /*
767 * address of SRAM buffer
768 */
769 in_sram_address = MXC_NF_MAIN_BUFFER0;
770 sign_of_sequental_byte_read = 0;
771 return ERROR_OK;
772 }
773
774 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value)
775 {
776 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
777 struct target *target = nand->target;
778 static uint8_t even_byte = 0;
779 uint16_t temp;
780 /*
781 * host-big_endian ??
782 */
783 if (sign_of_sequental_byte_read == 0)
784 even_byte = 0;
785
786 if (in_sram_address >
787 (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
788 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
789 *value = 0;
790 sign_of_sequental_byte_read = 0;
791 even_byte = 0;
792 return ERROR_NAND_OPERATION_FAILED;
793 } else {
794 if (nfc_is_v2())
795 in_sram_address = align_address_v2(nand, in_sram_address);
796
797 target_read_u16(target, in_sram_address, &temp);
798 if (even_byte) {
799 *value = temp >> 8;
800 even_byte = 0;
801 in_sram_address += 2;
802 } else {
803 *value = temp & 0xff;
804 even_byte = 1;
805 }
806 }
807 sign_of_sequental_byte_read = 1;
808 return ERROR_OK;
809 }
810
811 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value)
812 {
813 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
814 struct target *target = nand->target;
815
816 if (in_sram_address >
817 (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
818 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
819 *value = 0;
820 return ERROR_NAND_OPERATION_FAILED;
821 } else {
822 if (nfc_is_v2())
823 in_sram_address = align_address_v2(nand, in_sram_address);
824
825 target_read_u16(target, in_sram_address, value);
826 in_sram_address += 2;
827 }
828 return ERROR_OK;
829 }
830
831 static int poll_for_complete_op(struct nand_device *nand, const char *text)
832 {
833 if (mxc_nand_ready(nand, 1000) == -1) {
834 LOG_ERROR("%s sending timeout", text);
835 return ERROR_NAND_OPERATION_FAILED;
836 }
837 return ERROR_OK;
838 }
839
840 static int validate_target_state(struct nand_device *nand)
841 {
842 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
843 struct target *target = nand->target;
844
845 if (target->state != TARGET_HALTED) {
846 LOG_ERROR(target_not_halted_err_msg);
847 return ERROR_NAND_OPERATION_FAILED;
848 }
849
850 if (mxc_nf_info->flags.target_little_endian !=
851 (target->endianness == TARGET_LITTLE_ENDIAN)) {
852 /*
853 * endianness changed after NAND controller probed
854 */
855 return ERROR_NAND_OPERATION_FAILED;
856 }
857 return ERROR_OK;
858 }
859
860 int ecc_status_v1(struct nand_device *nand)
861 {
862 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
863 struct target *target = nand->target;
864 uint16_t ecc_status;
865
866 target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
867 switch (ecc_status & 0x000c) {
868 case 1 << 2:
869 LOG_INFO("main area read with 1 (correctable) error");
870 break;
871 case 2 << 2:
872 LOG_INFO("main area read with more than 1 (incorrectable) error");
873 return ERROR_NAND_OPERATION_FAILED;
874 break;
875 }
876 switch (ecc_status & 0x0003) {
877 case 1:
878 LOG_INFO("spare area read with 1 (correctable) error");
879 break;
880 case 2:
881 LOG_INFO("main area read with more than 1 (incorrectable) error");
882 return ERROR_NAND_OPERATION_FAILED;
883 break;
884 }
885 return ERROR_OK;
886 }
887
888 int ecc_status_v2(struct nand_device *nand)
889 {
890 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
891 struct target *target = nand->target;
892 uint16_t ecc_status;
893 uint8_t no_subpages;
894 uint8_t err;
895
896 no_subpages = nand->page_size >> 9;
897
898 target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
899 do {
900 err = ecc_status & 0xF;
901 if (err > 4) {
902 LOG_INFO("UnCorrectable RS-ECC Error");
903 return ERROR_NAND_OPERATION_FAILED;
904 } else if (err > 0)
905 LOG_INFO("%d Symbol Correctable RS-ECC Error", err);
906 ecc_status >>= 4;
907 } while (--no_subpages);
908 return ERROR_OK;
909 }
910
911 static int do_data_output(struct nand_device *nand)
912 {
913 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
914 struct target *target = nand->target;
915 int poll_result;
916 switch (mxc_nf_info->fin) {
917 case MXC_NF_FIN_DATAOUT:
918 /*
919 * start data output operation (set MXC_NF_BIT_OP_DONE==0)
920 */
921 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info->optype));
922 poll_result = poll_for_complete_op(nand, "data output");
923 if (poll_result != ERROR_OK)
924 return poll_result;
925
926 mxc_nf_info->fin = MXC_NF_FIN_NONE;
927 /*
928 * ECC stuff
929 */
930 if (mxc_nf_info->optype == MXC_NF_DATAOUT_PAGE &&
931 mxc_nf_info->flags.hw_ecc_enabled) {
932 int ecc_status;
933 if (nfc_is_v1())
934 ecc_status = ecc_status_v1(nand);
935 else
936 ecc_status = ecc_status_v2(nand);
937 if (ecc_status != ERROR_OK)
938 return ecc_status;
939 }
940 break;
941 case MXC_NF_FIN_NONE:
942 break;
943 }
944 return ERROR_OK;
945 }
946
947 struct nand_flash_controller mxc_nand_flash_controller = {
948 .name = "mxc",
949 .nand_device_command = &mxc_nand_device_command,
950 .commands = mxc_nand_command_handler,
951 .init = &mxc_init,
952 .reset = &mxc_reset,
953 .command = &mxc_command,
954 .address = &mxc_address,
955 .write_data = &mxc_write_data,
956 .read_data = &mxc_read_data,
957 .write_page = &mxc_write_page,
958 .read_page = &mxc_read_page,
959 .nand_ready = &mxc_nand_ready,
960 };
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