src/flash/nand/mx3.h

   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Alexei Babich                                   *
   3  *   Rezonans plc., Chelyabinsk, Russia                                    *
   4  *   impatt@mail.ru                                                        *
   5  *                                                                         *
   6  *   This program is free software; you can redistribute it and/or modify  *
   7  *   it under the terms of the GNU General Public License as published by  *
   8  *   the Free Software Foundation; either version 2 of the License, or     *
   9  *   (at your option) any later version.                                   *
  10  *                                                                         *
  11  *   This program is distributed in the hope that it will be useful,       *
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  14  *   GNU General Public License for more details.                          *
  15  *                                                                         *
  16  *   You should have received a copy of the GNU General Public License     *
  17  *   along with this program; if not, write to the                         *
  18  *   Free Software Foundation, Inc.,                                       *
  19  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  20  ***************************************************************************/
  21
  22 /*
  23  * Freescale iMX3* OpenOCD NAND Flash controller support.
  24  *
  25  * Many thanks to Ben Dooks for writing s3c24xx driver.
  26  */
  27
  28 #define MX3_NF_BASE_ADDR                                0xb8000000
  29 #define MX3_NF_BUFSIZ                                   (MX3_NF_BASE_ADDR + 0xe00)
  30 #define MX3_NF_BUFADDR                                  (MX3_NF_BASE_ADDR + 0xe04)
  31 #define MX3_NF_FADDR                                    (MX3_NF_BASE_ADDR + 0xe06)
  32 #define MX3_NF_FCMD                                             (MX3_NF_BASE_ADDR + 0xe08)
  33 #define MX3_NF_BUFCFG                                   (MX3_NF_BASE_ADDR + 0xe0a)
  34 #define MX3_NF_ECCSTATUS                                (MX3_NF_BASE_ADDR + 0xe0c)
  35 #define MX3_NF_ECCMAINPOS                               (MX3_NF_BASE_ADDR + 0xe0e)
  36 #define MX3_NF_ECCSPAREPOS                              (MX3_NF_BASE_ADDR + 0xe10)
  37 #define MX3_NF_FWP                                              (MX3_NF_BASE_ADDR + 0xe12)
  38 #define MX3_NF_LOCKSTART                                (MX3_NF_BASE_ADDR + 0xe14)
  39 #define MX3_NF_LOCKEND                                  (MX3_NF_BASE_ADDR + 0xe16)
  40 #define MX3_NF_FWPSTATUS                                (MX3_NF_BASE_ADDR + 0xe18)
  41 /*
  42  * all bits not marked as self-clearing bit
  43  */
  44 #define MX3_NF_CFG1                                             (MX3_NF_BASE_ADDR + 0xe1a)
  45 #define MX3_NF_CFG2                                             (MX3_NF_BASE_ADDR + 0xe1c)
  46
  47 #define MX3_NF_MAIN_BUFFER0                             (MX3_NF_BASE_ADDR + 0x0000)
  48 #define MX3_NF_MAIN_BUFFER1                             (MX3_NF_BASE_ADDR + 0x0200)
  49 #define MX3_NF_MAIN_BUFFER2                             (MX3_NF_BASE_ADDR + 0x0400)
  50 #define MX3_NF_MAIN_BUFFER3                             (MX3_NF_BASE_ADDR + 0x0600)
  51 #define MX3_NF_SPARE_BUFFER0                    (MX3_NF_BASE_ADDR + 0x0800)
  52 #define MX3_NF_SPARE_BUFFER1                    (MX3_NF_BASE_ADDR + 0x0810)
  53 #define MX3_NF_SPARE_BUFFER2                    (MX3_NF_BASE_ADDR + 0x0820)
  54 #define MX3_NF_SPARE_BUFFER3                    (MX3_NF_BASE_ADDR + 0x0830)
  55 #define MX3_NF_MAIN_BUFFER_LEN                  512
  56 #define MX3_NF_SPARE_BUFFER_LEN                 16
  57 #define MX3_NF_LAST_BUFFER_ADDR                 ((MX3_NF_SPARE_BUFFER3) + MX3_NF_SPARE_BUFFER_LEN - 2)
  58
  59 /* bits in MX3_NF_CFG1 register */
  60 #define MX3_NF_BIT_SPARE_ONLY_EN                (1<<2)
  61 #define MX3_NF_BIT_ECC_EN                               (1<<3)
  62 #define MX3_NF_BIT_INT_DIS                              (1<<4)
  63 #define MX3_NF_BIT_BE_EN                                (1<<5)
  64 #define MX3_NF_BIT_RESET_EN                             (1<<6)
  65 #define MX3_NF_BIT_FORCE_CE                             (1<<7)
  66
  67 /* bits in MX3_NF_CFG2 register */
  68
  69 /*Flash Command Input*/
  70 #define MX3_NF_BIT_OP_FCI                               (1<<0)
  71 /*
  72  * Flash Address Input
  73  */
  74 #define MX3_NF_BIT_OP_FAI                               (1<<1)
  75 /*
  76  * Flash Data Input
  77  */
  78 #define MX3_NF_BIT_OP_FDI                               (1<<2)
  79
  80 /* see "enum mx_dataout_type" below */
  81 #define MX3_NF_BIT_DATAOUT_TYPE(x)              ((x)<<3)
  82 #define MX3_NF_BIT_OP_DONE                              (1<<15)
  83
  84 #define MX3_CCM_CGR2                                    0x53f80028
  85 #define MX3_GPR                                                 0x43fac008
  86 #define MX3_PCSR                                                0x53f8000c
  87
  88 enum mx_dataout_type {
  89         MX3_NF_DATAOUT_PAGE = 1,
  90         MX3_NF_DATAOUT_NANDID = 2,
  91         MX3_NF_DATAOUT_NANDSTATUS = 4,
  92 };
  93 enum mx_nf_finalize_action {
  94         MX3_NF_FIN_NONE,
  95         MX3_NF_FIN_DATAOUT,
  96 };
  97
  98 struct mx3_nf_flags {
  99         unsigned host_little_endian:1;
 100         unsigned target_little_endian:1;
 101         unsigned nand_readonly:1;
 102         unsigned one_kb_sram:1;
 103         unsigned hw_ecc_enabled:1;
 104 };
 105
 106 struct mx3_nf_controller {
 107         enum mx_dataout_type optype;
 108         enum mx_nf_finalize_action fin;
 109         struct mx3_nf_flags flags;
 110 };