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NAND/DAVINCI: remove private "target" copy
[openocd.git] / src / flash / nand / mx3.c
1
2 /***************************************************************************
3 * Copyright (C) 2009 by Alexei Babich *
4 * Rezonans plc., Chelyabinsk, Russia *
5 * impatt@mail.ru *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22
23 /*
24 * Freescale iMX3* OpenOCD NAND Flash controller support.
25 *
26 * Many thanks to Ben Dooks for writing s3c24xx driver.
27 */
28
29 /*
30 driver tested with STMicro NAND512W3A @imx31
31 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
32 get_next_halfword_from_sram_buffer() not tested
33 */
34 #ifdef HAVE_CONFIG_H
35 #include "config.h"
36 #endif
37
38 #include "imp.h"
39 #include "mx3.h"
40 #include <target/target.h>
41
42 static const char target_not_halted_err_msg[] =
43 "target must be halted to use mx3 NAND flash controller";
44 static const char data_block_size_err_msg[] =
45 "minimal granularity is one half-word, %" PRId32 " is incorrect";
46 static const char sram_buffer_bounds_err_msg[] =
47 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
48 static const char get_status_register_err_msg[] = "can't get NAND status";
49 static uint32_t in_sram_address;
50 static unsigned char sign_of_sequental_byte_read;
51
52 static int test_iomux_settings (struct target * target, uint32_t value,
53 uint32_t mask, const char *text);
54 static int initialize_nf_controller (struct nand_device *nand);
55 static int get_next_byte_from_sram_buffer (struct target * target, uint8_t * value);
56 static int get_next_halfword_from_sram_buffer (struct target * target,
57 uint16_t * value);
58 static int poll_for_complete_op (struct target * target, const char *text);
59 static int validate_target_state (struct nand_device *nand);
60 static int do_data_output (struct nand_device *nand);
61
62 static int imx31_command (struct nand_device *nand, uint8_t command);
63 static int imx31_address (struct nand_device *nand, uint8_t address);
64
65 NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command)
66 {
67 struct mx3_nf_controller *mx3_nf_info;
68 mx3_nf_info = malloc (sizeof (struct mx3_nf_controller));
69 if (mx3_nf_info == NULL)
70 {
71 LOG_ERROR ("no memory for nand controller");
72 return ERROR_FAIL;
73 }
74
75 nand->controller_priv = mx3_nf_info;
76
77 mx3_nf_info->target = get_target (CMD_ARGV[1]);
78 if (mx3_nf_info->target == NULL)
79 {
80 LOG_ERROR ("target '%s' not defined", CMD_ARGV[1]);
81 return ERROR_FAIL;
82 }
83 if (CMD_ARGC < 3)
84 {
85 LOG_ERROR ("use \"nand device imx31 target noecc|hwecc\"");
86 return ERROR_FAIL;
87 }
88 /*
89 * check hwecc requirements
90 */
91 {
92 int hwecc_needed;
93 hwecc_needed = strcmp (CMD_ARGV[2], "hwecc");
94 if (hwecc_needed == 0)
95 {
96 mx3_nf_info->flags.hw_ecc_enabled = 1;
97 }
98 else
99 {
100 mx3_nf_info->flags.hw_ecc_enabled = 0;
101 }
102 }
103
104 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
105 mx3_nf_info->fin = MX3_NF_FIN_NONE;
106 mx3_nf_info->flags.target_little_endian =
107 (mx3_nf_info->target->endianness == TARGET_LITTLE_ENDIAN);
108 /*
109 * testing host endianess
110 */
111 {
112 int x = 1;
113 if (*(char *) &x == 1)
114 {
115 mx3_nf_info->flags.host_little_endian = 1;
116 }
117 else
118 {
119 mx3_nf_info->flags.host_little_endian = 0;
120 }
121 }
122 return ERROR_OK;
123 }
124
125 static int imx31_init (struct nand_device *nand)
126 {
127 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
128 struct target *target = mx3_nf_info->target;
129
130 {
131 /*
132 * validate target state
133 */
134 int validate_target_result;
135 validate_target_result = validate_target_state(nand);
136 if (validate_target_result != ERROR_OK)
137 {
138 return validate_target_result;
139 }
140 }
141
142 {
143 uint16_t buffsize_register_content;
144 target_read_u16 (target, MX3_NF_BUFSIZ, &buffsize_register_content);
145 mx3_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
146 }
147
148 {
149 uint32_t pcsr_register_content;
150 target_read_u32 (target, MX3_PCSR, &pcsr_register_content);
151 if (!nand->bus_width)
152 {
153 nand->bus_width =
154 (pcsr_register_content & 0x80000000) ? 16 : 8;
155 }
156 else
157 {
158 pcsr_register_content |=
159 ((nand->bus_width == 16) ? 0x80000000 : 0x00000000);
160 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
161 }
162
163 if (!nand->page_size)
164 {
165 nand->page_size =
166 (pcsr_register_content & 0x40000000) ? 2048 : 512;
167 }
168 else
169 {
170 pcsr_register_content |=
171 ((nand->page_size == 2048) ? 0x40000000 : 0x00000000);
172 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
173 }
174 if (mx3_nf_info->flags.one_kb_sram && (nand->page_size == 2048))
175 {
176 LOG_ERROR
177 ("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it");
178 }
179 }
180
181 {
182 uint32_t cgr_register_content;
183 target_read_u32 (target, MX3_CCM_CGR2, &cgr_register_content);
184 if (!(cgr_register_content & 0x00000300))
185 {
186 LOG_ERROR ("clock gating to EMI disabled");
187 return ERROR_FAIL;
188 }
189 }
190
191 {
192 uint32_t gpr_register_content;
193 target_read_u32 (target, MX3_GPR, &gpr_register_content);
194 if (gpr_register_content & 0x00000060)
195 {
196 LOG_ERROR ("pins mode overrided by GPR");
197 return ERROR_FAIL;
198 }
199 }
200
201 {
202 /*
203 * testing IOMUX settings; must be in "functional-mode output and
204 * functional-mode input" mode
205 */
206 int test_iomux;
207 test_iomux = ERROR_OK;
208 test_iomux |=
209 test_iomux_settings (target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
210 test_iomux |=
211 test_iomux_settings (target, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
212 test_iomux |=
213 test_iomux_settings (target, 0x43fac0c8, 0x0000007f, "d7");
214 if (nand->bus_width == 16)
215 {
216 test_iomux |=
217 test_iomux_settings (target, 0x43fac0c8, 0x7f7f7f00,
218 "d8,d9,d10");
219 test_iomux |=
220 test_iomux_settings (target, 0x43fac0cc, 0x7f7f7f7f,
221 "d11,d12,d13,d14");
222 test_iomux |=
223 test_iomux_settings (target, 0x43fac0d0, 0x0000007f, "d15");
224 }
225 test_iomux |=
226 test_iomux_settings (target, 0x43fac0d0, 0x7f7f7f00,
227 "nfwp,nfce,nfrb");
228 test_iomux |=
229 test_iomux_settings (target, 0x43fac0d4, 0x7f7f7f7f,
230 "nfwe,nfre,nfale,nfcle");
231 if (test_iomux != ERROR_OK)
232 {
233 return ERROR_FAIL;
234 }
235 }
236
237 initialize_nf_controller (nand);
238
239 {
240 int retval;
241 uint16_t nand_status_content;
242 retval = ERROR_OK;
243 retval |= imx31_command (nand, NAND_CMD_STATUS);
244 retval |= imx31_address (nand, 0x00);
245 retval |= do_data_output (nand);
246 if (retval != ERROR_OK)
247 {
248 LOG_ERROR (get_status_register_err_msg);
249 return ERROR_FAIL;
250 }
251 target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
252 if (!(nand_status_content & 0x0080))
253 {
254 /*
255 * is host-big-endian correctly ??
256 */
257 LOG_INFO ("NAND read-only");
258 mx3_nf_info->flags.nand_readonly = 1;
259 }
260 else
261 {
262 mx3_nf_info->flags.nand_readonly = 0;
263 }
264 }
265 return ERROR_OK;
266 }
267
268 static int imx31_read_data (struct nand_device *nand, void *data)
269 {
270 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
271 struct target *target = mx3_nf_info->target;
272 {
273 /*
274 * validate target state
275 */
276 int validate_target_result;
277 validate_target_result = validate_target_state (nand);
278 if (validate_target_result != ERROR_OK)
279 {
280 return validate_target_result;
281 }
282 }
283
284 {
285 /*
286 * get data from nand chip
287 */
288 int try_data_output_from_nand_chip;
289 try_data_output_from_nand_chip = do_data_output (nand);
290 if (try_data_output_from_nand_chip != ERROR_OK)
291 {
292 return try_data_output_from_nand_chip;
293 }
294 }
295
296 if (nand->bus_width == 16)
297 {
298 get_next_halfword_from_sram_buffer (target, data);
299 }
300 else
301 {
302 get_next_byte_from_sram_buffer (target, data);
303 }
304
305 return ERROR_OK;
306 }
307
308 static int imx31_write_data (struct nand_device *nand, uint16_t data)
309 {
310 LOG_ERROR ("write_data() not implemented");
311 return ERROR_NAND_OPERATION_FAILED;
312 }
313
314 static int imx31_reset (struct nand_device *nand)
315 {
316 /*
317 * validate target state
318 */
319 int validate_target_result;
320 validate_target_result = validate_target_state (nand);
321 if (validate_target_result != ERROR_OK)
322 {
323 return validate_target_result;
324 }
325 initialize_nf_controller (nand);
326 return ERROR_OK;
327 }
328
329 static int imx31_command (struct nand_device *nand, uint8_t command)
330 {
331 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
332 struct target *target = mx3_nf_info->target;
333 {
334 /*
335 * validate target state
336 */
337 int validate_target_result;
338 validate_target_result = validate_target_state (nand);
339 if (validate_target_result != ERROR_OK)
340 {
341 return validate_target_result;
342 }
343 }
344
345 switch (command)
346 {
347 case NAND_CMD_READOOB:
348 command = NAND_CMD_READ0;
349 in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
350 * data_read() and
351 * read_block_data() to
352 * spare area in SRAM
353 * buffer */
354 break;
355 case NAND_CMD_READ1:
356 command = NAND_CMD_READ0;
357 /*
358 * offset == one half of page size
359 */
360 in_sram_address =
361 MX3_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
362 default:
363 in_sram_address = MX3_NF_MAIN_BUFFER0;
364 }
365
366 target_write_u16 (target, MX3_NF_FCMD, command);
367 /*
368 * start command input operation (set MX3_NF_BIT_OP_DONE==0)
369 */
370 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FCI);
371 {
372 int poll_result;
373 poll_result = poll_for_complete_op (target, "command");
374 if (poll_result != ERROR_OK)
375 {
376 return poll_result;
377 }
378 }
379 /*
380 * reset cursor to begin of the buffer
381 */
382 sign_of_sequental_byte_read = 0;
383 switch (command)
384 {
385 case NAND_CMD_READID:
386 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
387 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
388 break;
389 case NAND_CMD_STATUS:
390 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
391 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
392 break;
393 case NAND_CMD_READ0:
394 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
395 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
396 break;
397 default:
398 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
399 }
400 return ERROR_OK;
401 }
402
403 static int imx31_address (struct nand_device *nand, uint8_t address)
404 {
405 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
406 struct target *target = mx3_nf_info->target;
407 {
408 /*
409 * validate target state
410 */
411 int validate_target_result;
412 validate_target_result = validate_target_state (nand);
413 if (validate_target_result != ERROR_OK)
414 {
415 return validate_target_result;
416 }
417 }
418
419 target_write_u16 (target, MX3_NF_FADDR, address);
420 /*
421 * start address input operation (set MX3_NF_BIT_OP_DONE==0)
422 */
423 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FAI);
424 {
425 int poll_result;
426 poll_result = poll_for_complete_op (target, "address");
427 if (poll_result != ERROR_OK)
428 {
429 return poll_result;
430 }
431 }
432 return ERROR_OK;
433 }
434
435 static int imx31_nand_ready (struct nand_device *nand, int tout)
436 {
437 uint16_t poll_complete_status;
438 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
439 struct target *target = mx3_nf_info->target;
440
441 {
442 /*
443 * validate target state
444 */
445 int validate_target_result;
446 validate_target_result = validate_target_state (nand);
447 if (validate_target_result != ERROR_OK)
448 {
449 return validate_target_result;
450 }
451 }
452
453 do
454 {
455 target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
456 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
457 {
458 return tout;
459 }
460 alive_sleep (1);
461 }
462 while (tout-- > 0);
463 return tout;
464 }
465
466 static int imx31_write_page (struct nand_device *nand, uint32_t page,
467 uint8_t * data, uint32_t data_size, uint8_t * oob,
468 uint32_t oob_size)
469 {
470 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
471 struct target *target = mx3_nf_info->target;
472
473 if (data_size % 2)
474 {
475 LOG_ERROR (data_block_size_err_msg, data_size);
476 return ERROR_NAND_OPERATION_FAILED;
477 }
478 if (oob_size % 2)
479 {
480 LOG_ERROR (data_block_size_err_msg, oob_size);
481 return ERROR_NAND_OPERATION_FAILED;
482 }
483 if (!data)
484 {
485 LOG_ERROR ("nothing to program");
486 return ERROR_NAND_OPERATION_FAILED;
487 }
488 {
489 /*
490 * validate target state
491 */
492 int retval;
493 retval = validate_target_state (nand);
494 if (retval != ERROR_OK)
495 {
496 return retval;
497 }
498 }
499 {
500 int retval = ERROR_OK;
501 retval |= imx31_command(nand, NAND_CMD_SEQIN);
502 retval |= imx31_address(nand, 0x00);
503 retval |= imx31_address(nand, page & 0xff);
504 retval |= imx31_address(nand, (page >> 8) & 0xff);
505 if (nand->address_cycles >= 4)
506 {
507 retval |= imx31_address (nand, (page >> 16) & 0xff);
508 if (nand->address_cycles >= 5)
509 {
510 retval |= imx31_address (nand, (page >> 24) & 0xff);
511 }
512 }
513 target_write_buffer (target, MX3_NF_MAIN_BUFFER0, data_size, data);
514 if (oob)
515 {
516 if (mx3_nf_info->flags.hw_ecc_enabled)
517 {
518 /*
519 * part of spare block will be overrided by hardware
520 * ECC generator
521 */
522 LOG_DEBUG
523 ("part of spare block will be overrided by hardware ECC generator");
524 }
525 target_write_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
526 oob);
527 }
528 /*
529 * start data input operation (set MX3_NF_BIT_OP_DONE==0)
530 */
531 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FDI);
532 {
533 int poll_result;
534 poll_result = poll_for_complete_op (target, "data input");
535 if (poll_result != ERROR_OK)
536 {
537 return poll_result;
538 }
539 }
540 retval |= imx31_command (nand, NAND_CMD_PAGEPROG);
541 if (retval != ERROR_OK)
542 {
543 return retval;
544 }
545
546 /*
547 * check status register
548 */
549 {
550 uint16_t nand_status_content;
551 retval = ERROR_OK;
552 retval |= imx31_command(nand, NAND_CMD_STATUS);
553 retval |= imx31_address(nand, 0x00);
554 retval |= do_data_output(nand);
555 if (retval != ERROR_OK)
556 {
557 LOG_ERROR (get_status_register_err_msg);
558 return retval;
559 }
560 target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
561 if (nand_status_content & 0x0001)
562 {
563 /*
564 * is host-big-endian correctly ??
565 */
566 return ERROR_NAND_OPERATION_FAILED;
567 }
568 }
569 }
570 return ERROR_OK;
571 }
572
573 static int imx31_read_page (struct nand_device *nand, uint32_t page,
574 uint8_t * data, uint32_t data_size, uint8_t * oob,
575 uint32_t oob_size)
576 {
577 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
578 struct target *target = mx3_nf_info->target;
579
580 if (data_size % 2)
581 {
582 LOG_ERROR (data_block_size_err_msg, data_size);
583 return ERROR_NAND_OPERATION_FAILED;
584 }
585 if (oob_size % 2)
586 {
587 LOG_ERROR (data_block_size_err_msg, oob_size);
588 return ERROR_NAND_OPERATION_FAILED;
589 }
590
591 {
592 /*
593 * validate target state
594 */
595 int retval;
596 retval = validate_target_state(nand);
597 if (retval != ERROR_OK)
598 {
599 return retval;
600 }
601 }
602 {
603 int retval = ERROR_OK;
604 retval |= imx31_command(nand, NAND_CMD_READ0);
605 retval |= imx31_address(nand, 0x00);
606 retval |= imx31_address(nand, page & 0xff);
607 retval |= imx31_address(nand, (page >> 8) & 0xff);
608 if (nand->address_cycles >= 4)
609 {
610 retval |= imx31_address(nand, (page >> 16) & 0xff);
611 if (nand->address_cycles >= 5)
612 {
613 retval |= imx31_address(nand, (page >> 24) & 0xff);
614 retval |= imx31_command(nand, NAND_CMD_READSTART);
615 }
616 }
617 retval |= do_data_output (nand);
618 if (retval != ERROR_OK)
619 {
620 return retval;
621 }
622
623 if (data)
624 {
625 target_read_buffer (target, MX3_NF_MAIN_BUFFER0, data_size,
626 data);
627 }
628 if (oob)
629 {
630 target_read_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
631 oob);
632 }
633 }
634 return ERROR_OK;
635 }
636
637 static int test_iomux_settings (struct target * target, uint32_t address,
638 uint32_t mask, const char *text)
639 {
640 uint32_t register_content;
641 target_read_u32 (target, address, &register_content);
642 if ((register_content & mask) != (0x12121212 & mask))
643 {
644 LOG_ERROR ("IOMUX for {%s} is bad", text);
645 return ERROR_FAIL;
646 }
647 return ERROR_OK;
648 }
649
650 static int initialize_nf_controller (struct nand_device *nand)
651 {
652 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
653 struct target *target = mx3_nf_info->target;
654 /*
655 * resets NAND flash controller in zero time ? I dont know.
656 */
657 target_write_u16 (target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
658 {
659 uint16_t work_mode;
660 work_mode = MX3_NF_BIT_INT_DIS; /* disable interrupt */
661 if (target->endianness == TARGET_BIG_ENDIAN)
662 {
663 work_mode |= MX3_NF_BIT_BE_EN;
664 }
665 if (mx3_nf_info->flags.hw_ecc_enabled)
666 {
667 work_mode |= MX3_NF_BIT_ECC_EN;
668 }
669 target_write_u16 (target, MX3_NF_CFG1, work_mode);
670 }
671 /*
672 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
673 */
674 target_write_u16 (target, MX3_NF_BUFCFG, 2);
675 {
676 uint16_t temp;
677 target_read_u16 (target, MX3_NF_FWP, &temp);
678 if ((temp & 0x0007) == 1)
679 {
680 LOG_ERROR ("NAND flash is tight-locked, reset needed");
681 return ERROR_FAIL;
682 }
683
684 }
685 /*
686 * unlock NAND flash for write
687 */
688 target_write_u16 (target, MX3_NF_FWP, 4);
689 target_write_u16 (target, MX3_NF_LOCKSTART, 0x0000);
690 target_write_u16 (target, MX3_NF_LOCKEND, 0xFFFF);
691 /*
692 * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
693 */
694 target_write_u16 (target, MX3_NF_BUFADDR, 0x0000);
695 /*
696 * address of SRAM buffer
697 */
698 in_sram_address = MX3_NF_MAIN_BUFFER0;
699 sign_of_sequental_byte_read = 0;
700 return ERROR_OK;
701 }
702
703 static int get_next_byte_from_sram_buffer (struct target * target, uint8_t * value)
704 {
705 static uint8_t even_byte = 0;
706 /*
707 * host-big_endian ??
708 */
709 if (sign_of_sequental_byte_read == 0)
710 {
711 even_byte = 0;
712 }
713 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
714 {
715 LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
716 *value = 0;
717 sign_of_sequental_byte_read = 0;
718 even_byte = 0;
719 return ERROR_NAND_OPERATION_FAILED;
720 }
721 else
722 {
723 uint16_t temp;
724 target_read_u16 (target, in_sram_address, &temp);
725 if (even_byte)
726 {
727 *value = temp >> 8;
728 even_byte = 0;
729 in_sram_address += 2;
730 }
731 else
732 {
733 *value = temp & 0xff;
734 even_byte = 1;
735 }
736 }
737 sign_of_sequental_byte_read = 1;
738 return ERROR_OK;
739 }
740
741 static int get_next_halfword_from_sram_buffer (struct target * target,
742 uint16_t * value)
743 {
744 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
745 {
746 LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
747 *value = 0;
748 return ERROR_NAND_OPERATION_FAILED;
749 }
750 else
751 {
752 target_read_u16 (target, in_sram_address, value);
753 in_sram_address += 2;
754 }
755 return ERROR_OK;
756 }
757
758 static int poll_for_complete_op (struct target * target, const char *text)
759 {
760 uint16_t poll_complete_status;
761 for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++)
762 {
763 usleep (25);
764 target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
765 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
766 {
767 break;
768 }
769 }
770 if (!(poll_complete_status & MX3_NF_BIT_OP_DONE))
771 {
772 LOG_ERROR ("%s sending timeout", text);
773 return ERROR_NAND_OPERATION_FAILED;
774 }
775 return ERROR_OK;
776 }
777
778 static int validate_target_state (struct nand_device *nand)
779 {
780 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
781 struct target *target = mx3_nf_info->target;
782
783 if (target->state != TARGET_HALTED)
784 {
785 LOG_ERROR (target_not_halted_err_msg);
786 return ERROR_NAND_OPERATION_FAILED;
787 }
788
789 if (mx3_nf_info->flags.target_little_endian !=
790 (target->endianness == TARGET_LITTLE_ENDIAN))
791 {
792 /*
793 * endianness changed after NAND controller probed
794 */
795 return ERROR_NAND_OPERATION_FAILED;
796 }
797 return ERROR_OK;
798 }
799
800 static int do_data_output (struct nand_device *nand)
801 {
802 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
803 struct target *target = mx3_nf_info->target;
804 switch (mx3_nf_info->fin)
805 {
806 case MX3_NF_FIN_DATAOUT:
807 /*
808 * start data output operation (set MX3_NF_BIT_OP_DONE==0)
809 */
810 target_write_u16 (target, MX3_NF_CFG2,
811 MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info->
812 optype));
813 {
814 int poll_result;
815 poll_result = poll_for_complete_op (target, "data output");
816 if (poll_result != ERROR_OK)
817 {
818 return poll_result;
819 }
820 }
821 mx3_nf_info->fin = MX3_NF_FIN_NONE;
822 /*
823 * ECC stuff
824 */
825 if ((mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE)
826 && mx3_nf_info->flags.hw_ecc_enabled)
827 {
828 uint16_t ecc_status;
829 target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
830 switch (ecc_status & 0x000c)
831 {
832 case 1 << 2:
833 LOG_DEBUG
834 ("main area readed with 1 (correctable) error");
835 break;
836 case 2 << 2:
837 LOG_DEBUG
838 ("main area readed with more than 1 (incorrectable) error");
839 return ERROR_NAND_OPERATION_FAILED;
840 break;
841 }
842 switch (ecc_status & 0x0003)
843 {
844 case 1:
845 LOG_DEBUG
846 ("spare area readed with 1 (correctable) error");
847 break;
848 case 2:
849 LOG_DEBUG
850 ("main area readed with more than 1 (incorrectable) error");
851 return ERROR_NAND_OPERATION_FAILED;
852 break;
853 }
854 }
855 break;
856 case MX3_NF_FIN_NONE:
857 break;
858 }
859 return ERROR_OK;
860 }
861
862 struct nand_flash_controller imx31_nand_flash_controller = {
863 .name = "imx31",
864 .nand_device_command = &imx31_nand_device_command,
865 .init = &imx31_init,
866 .reset = &imx31_reset,
867 .command = &imx31_command,
868 .address = &imx31_address,
869 .write_data = &imx31_write_data,
870 .read_data = &imx31_read_data,
871 .write_page = &imx31_write_page,
872 .read_page = &imx31_read_page,
873 .nand_ready = &imx31_nand_ready,
874 };
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