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Change return value on error.
[openocd.git] / src / flash / nand / mx3.c
1
2 /***************************************************************************
3 * Copyright (C) 2009 by Alexei Babich *
4 * Rezonans plc., Chelyabinsk, Russia *
5 * impatt@mail.ru *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22
23 /*
24 * Freescale iMX3* OpenOCD NAND Flash controller support.
25 *
26 * Many thanks to Ben Dooks for writing s3c24xx driver.
27 */
28
29 /*
30 driver tested with STMicro NAND512W3A @imx31
31 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
32 get_next_halfword_from_sram_buffer() not tested
33 */
34 #ifdef HAVE_CONFIG_H
35 #include "config.h"
36 #endif
37
38 #include "imp.h"
39 #include "mx3.h"
40 #include <target/target.h>
41
42 static const char target_not_halted_err_msg[] =
43 "target must be halted to use mx3 NAND flash controller";
44 static const char data_block_size_err_msg[] =
45 "minimal granularity is one half-word, %" PRId32 " is incorrect";
46 static const char sram_buffer_bounds_err_msg[] =
47 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
48 static const char get_status_register_err_msg[] = "can't get NAND status";
49 static uint32_t in_sram_address;
50 static unsigned char sign_of_sequental_byte_read;
51
52 static int test_iomux_settings (struct target * target, uint32_t value,
53 uint32_t mask, const char *text);
54 static int initialize_nf_controller (struct nand_device *nand);
55 static int get_next_byte_from_sram_buffer (struct target * target, uint8_t * value);
56 static int get_next_halfword_from_sram_buffer (struct target * target,
57 uint16_t * value);
58 static int poll_for_complete_op (struct target * target, const char *text);
59 static int validate_target_state (struct nand_device *nand);
60 static int do_data_output (struct nand_device *nand);
61
62 static int imx31_command (struct nand_device *nand, uint8_t command);
63 static int imx31_address (struct nand_device *nand, uint8_t address);
64
65 NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command)
66 {
67 struct mx3_nf_controller *mx3_nf_info;
68 mx3_nf_info = malloc (sizeof (struct mx3_nf_controller));
69 if (mx3_nf_info == NULL)
70 {
71 LOG_ERROR ("no memory for nand controller");
72 return ERROR_FAIL;
73 }
74
75 nand->controller_priv = mx3_nf_info;
76
77 if (CMD_ARGC < 3)
78 {
79 return ERROR_COMMAND_SYNTAX_ERROR;
80 }
81 /*
82 * check hwecc requirements
83 */
84 {
85 int hwecc_needed;
86 hwecc_needed = strcmp (CMD_ARGV[2], "hwecc");
87 if (hwecc_needed == 0)
88 {
89 mx3_nf_info->flags.hw_ecc_enabled = 1;
90 }
91 else
92 {
93 mx3_nf_info->flags.hw_ecc_enabled = 0;
94 }
95 }
96
97 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
98 mx3_nf_info->fin = MX3_NF_FIN_NONE;
99 mx3_nf_info->flags.target_little_endian =
100 (nand->target->endianness == TARGET_LITTLE_ENDIAN);
101 /*
102 * testing host endianness
103 */
104 {
105 int x = 1;
106 if (*(char *) &x == 1)
107 {
108 mx3_nf_info->flags.host_little_endian = 1;
109 }
110 else
111 {
112 mx3_nf_info->flags.host_little_endian = 0;
113 }
114 }
115 return ERROR_OK;
116 }
117
118 static int imx31_init (struct nand_device *nand)
119 {
120 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
121 struct target *target = nand->target;
122
123 {
124 /*
125 * validate target state
126 */
127 int validate_target_result;
128 validate_target_result = validate_target_state(nand);
129 if (validate_target_result != ERROR_OK)
130 {
131 return validate_target_result;
132 }
133 }
134
135 {
136 uint16_t buffsize_register_content;
137 target_read_u16 (target, MX3_NF_BUFSIZ, &buffsize_register_content);
138 mx3_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
139 }
140
141 {
142 uint32_t pcsr_register_content;
143 target_read_u32 (target, MX3_PCSR, &pcsr_register_content);
144 if (!nand->bus_width)
145 {
146 nand->bus_width =
147 (pcsr_register_content & 0x80000000) ? 16 : 8;
148 }
149 else
150 {
151 pcsr_register_content |=
152 ((nand->bus_width == 16) ? 0x80000000 : 0x00000000);
153 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
154 }
155
156 if (!nand->page_size)
157 {
158 nand->page_size =
159 (pcsr_register_content & 0x40000000) ? 2048 : 512;
160 }
161 else
162 {
163 pcsr_register_content |=
164 ((nand->page_size == 2048) ? 0x40000000 : 0x00000000);
165 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
166 }
167 if (mx3_nf_info->flags.one_kb_sram && (nand->page_size == 2048))
168 {
169 LOG_ERROR
170 ("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it");
171 }
172 }
173
174 {
175 uint32_t cgr_register_content;
176 target_read_u32 (target, MX3_CCM_CGR2, &cgr_register_content);
177 if (!(cgr_register_content & 0x00000300))
178 {
179 LOG_ERROR ("clock gating to EMI disabled");
180 return ERROR_FAIL;
181 }
182 }
183
184 {
185 uint32_t gpr_register_content;
186 target_read_u32 (target, MX3_GPR, &gpr_register_content);
187 if (gpr_register_content & 0x00000060)
188 {
189 LOG_ERROR ("pins mode overrided by GPR");
190 return ERROR_FAIL;
191 }
192 }
193
194 {
195 /*
196 * testing IOMUX settings; must be in "functional-mode output and
197 * functional-mode input" mode
198 */
199 int test_iomux;
200 test_iomux = ERROR_OK;
201 test_iomux |=
202 test_iomux_settings (target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
203 test_iomux |=
204 test_iomux_settings (target, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
205 test_iomux |=
206 test_iomux_settings (target, 0x43fac0c8, 0x0000007f, "d7");
207 if (nand->bus_width == 16)
208 {
209 test_iomux |=
210 test_iomux_settings (target, 0x43fac0c8, 0x7f7f7f00,
211 "d8,d9,d10");
212 test_iomux |=
213 test_iomux_settings (target, 0x43fac0cc, 0x7f7f7f7f,
214 "d11,d12,d13,d14");
215 test_iomux |=
216 test_iomux_settings (target, 0x43fac0d0, 0x0000007f, "d15");
217 }
218 test_iomux |=
219 test_iomux_settings (target, 0x43fac0d0, 0x7f7f7f00,
220 "nfwp,nfce,nfrb");
221 test_iomux |=
222 test_iomux_settings (target, 0x43fac0d4, 0x7f7f7f7f,
223 "nfwe,nfre,nfale,nfcle");
224 if (test_iomux != ERROR_OK)
225 {
226 return ERROR_FAIL;
227 }
228 }
229
230 initialize_nf_controller (nand);
231
232 {
233 int retval;
234 uint16_t nand_status_content;
235 retval = ERROR_OK;
236 retval |= imx31_command (nand, NAND_CMD_STATUS);
237 retval |= imx31_address (nand, 0x00);
238 retval |= do_data_output (nand);
239 if (retval != ERROR_OK)
240 {
241 LOG_ERROR (get_status_register_err_msg);
242 return ERROR_FAIL;
243 }
244 target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
245 if (!(nand_status_content & 0x0080))
246 {
247 /*
248 * is host-big-endian correctly ??
249 */
250 LOG_INFO ("NAND read-only");
251 mx3_nf_info->flags.nand_readonly = 1;
252 }
253 else
254 {
255 mx3_nf_info->flags.nand_readonly = 0;
256 }
257 }
258 return ERROR_OK;
259 }
260
261 static int imx31_read_data (struct nand_device *nand, void *data)
262 {
263 struct target *target = nand->target;
264 {
265 /*
266 * validate target state
267 */
268 int validate_target_result;
269 validate_target_result = validate_target_state (nand);
270 if (validate_target_result != ERROR_OK)
271 {
272 return validate_target_result;
273 }
274 }
275
276 {
277 /*
278 * get data from nand chip
279 */
280 int try_data_output_from_nand_chip;
281 try_data_output_from_nand_chip = do_data_output (nand);
282 if (try_data_output_from_nand_chip != ERROR_OK)
283 {
284 return try_data_output_from_nand_chip;
285 }
286 }
287
288 if (nand->bus_width == 16)
289 {
290 get_next_halfword_from_sram_buffer (target, data);
291 }
292 else
293 {
294 get_next_byte_from_sram_buffer (target, data);
295 }
296
297 return ERROR_OK;
298 }
299
300 static int imx31_write_data (struct nand_device *nand, uint16_t data)
301 {
302 LOG_ERROR ("write_data() not implemented");
303 return ERROR_NAND_OPERATION_FAILED;
304 }
305
306 static int imx31_reset (struct nand_device *nand)
307 {
308 /*
309 * validate target state
310 */
311 int validate_target_result;
312 validate_target_result = validate_target_state (nand);
313 if (validate_target_result != ERROR_OK)
314 {
315 return validate_target_result;
316 }
317 initialize_nf_controller (nand);
318 return ERROR_OK;
319 }
320
321 static int imx31_command (struct nand_device *nand, uint8_t command)
322 {
323 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
324 struct target *target = nand->target;
325 {
326 /*
327 * validate target state
328 */
329 int validate_target_result;
330 validate_target_result = validate_target_state (nand);
331 if (validate_target_result != ERROR_OK)
332 {
333 return validate_target_result;
334 }
335 }
336
337 switch (command)
338 {
339 case NAND_CMD_READOOB:
340 command = NAND_CMD_READ0;
341 in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
342 * data_read() and
343 * read_block_data() to
344 * spare area in SRAM
345 * buffer */
346 break;
347 case NAND_CMD_READ1:
348 command = NAND_CMD_READ0;
349 /*
350 * offset == one half of page size
351 */
352 in_sram_address =
353 MX3_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
354 default:
355 in_sram_address = MX3_NF_MAIN_BUFFER0;
356 }
357
358 target_write_u16 (target, MX3_NF_FCMD, command);
359 /*
360 * start command input operation (set MX3_NF_BIT_OP_DONE==0)
361 */
362 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FCI);
363 {
364 int poll_result;
365 poll_result = poll_for_complete_op (target, "command");
366 if (poll_result != ERROR_OK)
367 {
368 return poll_result;
369 }
370 }
371 /*
372 * reset cursor to begin of the buffer
373 */
374 sign_of_sequental_byte_read = 0;
375 switch (command)
376 {
377 case NAND_CMD_READID:
378 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
379 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
380 break;
381 case NAND_CMD_STATUS:
382 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
383 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
384 break;
385 case NAND_CMD_READ0:
386 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
387 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
388 break;
389 default:
390 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
391 }
392 return ERROR_OK;
393 }
394
395 static int imx31_address (struct nand_device *nand, uint8_t address)
396 {
397 struct target *target = nand->target;
398 {
399 /*
400 * validate target state
401 */
402 int validate_target_result;
403 validate_target_result = validate_target_state (nand);
404 if (validate_target_result != ERROR_OK)
405 {
406 return validate_target_result;
407 }
408 }
409
410 target_write_u16 (target, MX3_NF_FADDR, address);
411 /*
412 * start address input operation (set MX3_NF_BIT_OP_DONE==0)
413 */
414 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FAI);
415 {
416 int poll_result;
417 poll_result = poll_for_complete_op (target, "address");
418 if (poll_result != ERROR_OK)
419 {
420 return poll_result;
421 }
422 }
423 return ERROR_OK;
424 }
425
426 static int imx31_nand_ready (struct nand_device *nand, int tout)
427 {
428 uint16_t poll_complete_status;
429 struct target *target = nand->target;
430
431 {
432 /*
433 * validate target state
434 */
435 int validate_target_result;
436 validate_target_result = validate_target_state (nand);
437 if (validate_target_result != ERROR_OK)
438 {
439 return validate_target_result;
440 }
441 }
442
443 do
444 {
445 target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
446 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
447 {
448 return tout;
449 }
450 alive_sleep (1);
451 }
452 while (tout-- > 0);
453 return tout;
454 }
455
456 static int imx31_write_page (struct nand_device *nand, uint32_t page,
457 uint8_t * data, uint32_t data_size, uint8_t * oob,
458 uint32_t oob_size)
459 {
460 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
461 struct target *target = nand->target;
462
463 if (data_size % 2)
464 {
465 LOG_ERROR (data_block_size_err_msg, data_size);
466 return ERROR_NAND_OPERATION_FAILED;
467 }
468 if (oob_size % 2)
469 {
470 LOG_ERROR (data_block_size_err_msg, oob_size);
471 return ERROR_NAND_OPERATION_FAILED;
472 }
473 if (!data)
474 {
475 LOG_ERROR ("nothing to program");
476 return ERROR_NAND_OPERATION_FAILED;
477 }
478 {
479 /*
480 * validate target state
481 */
482 int retval;
483 retval = validate_target_state (nand);
484 if (retval != ERROR_OK)
485 {
486 return retval;
487 }
488 }
489 {
490 int retval = ERROR_OK;
491 retval |= imx31_command(nand, NAND_CMD_SEQIN);
492 retval |= imx31_address(nand, 0x00);
493 retval |= imx31_address(nand, page & 0xff);
494 retval |= imx31_address(nand, (page >> 8) & 0xff);
495 if (nand->address_cycles >= 4)
496 {
497 retval |= imx31_address (nand, (page >> 16) & 0xff);
498 if (nand->address_cycles >= 5)
499 {
500 retval |= imx31_address (nand, (page >> 24) & 0xff);
501 }
502 }
503 target_write_buffer (target, MX3_NF_MAIN_BUFFER0, data_size, data);
504 if (oob)
505 {
506 if (mx3_nf_info->flags.hw_ecc_enabled)
507 {
508 /*
509 * part of spare block will be overrided by hardware
510 * ECC generator
511 */
512 LOG_DEBUG
513 ("part of spare block will be overrided by hardware ECC generator");
514 }
515 target_write_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
516 oob);
517 }
518 /*
519 * start data input operation (set MX3_NF_BIT_OP_DONE==0)
520 */
521 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FDI);
522 {
523 int poll_result;
524 poll_result = poll_for_complete_op (target, "data input");
525 if (poll_result != ERROR_OK)
526 {
527 return poll_result;
528 }
529 }
530 retval |= imx31_command (nand, NAND_CMD_PAGEPROG);
531 if (retval != ERROR_OK)
532 {
533 return retval;
534 }
535
536 /*
537 * check status register
538 */
539 {
540 uint16_t nand_status_content;
541 retval = ERROR_OK;
542 retval |= imx31_command(nand, NAND_CMD_STATUS);
543 retval |= imx31_address(nand, 0x00);
544 retval |= do_data_output(nand);
545 if (retval != ERROR_OK)
546 {
547 LOG_ERROR (get_status_register_err_msg);
548 return retval;
549 }
550 target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
551 if (nand_status_content & 0x0001)
552 {
553 /*
554 * is host-big-endian correctly ??
555 */
556 return ERROR_NAND_OPERATION_FAILED;
557 }
558 }
559 }
560 return ERROR_OK;
561 }
562
563 static int imx31_read_page (struct nand_device *nand, uint32_t page,
564 uint8_t * data, uint32_t data_size, uint8_t * oob,
565 uint32_t oob_size)
566 {
567 struct target *target = nand->target;
568
569 if (data_size % 2)
570 {
571 LOG_ERROR (data_block_size_err_msg, data_size);
572 return ERROR_NAND_OPERATION_FAILED;
573 }
574 if (oob_size % 2)
575 {
576 LOG_ERROR (data_block_size_err_msg, oob_size);
577 return ERROR_NAND_OPERATION_FAILED;
578 }
579
580 {
581 /*
582 * validate target state
583 */
584 int retval;
585 retval = validate_target_state(nand);
586 if (retval != ERROR_OK)
587 {
588 return retval;
589 }
590 }
591 {
592 int retval = ERROR_OK;
593 retval |= imx31_command(nand, NAND_CMD_READ0);
594 retval |= imx31_address(nand, 0x00);
595 retval |= imx31_address(nand, page & 0xff);
596 retval |= imx31_address(nand, (page >> 8) & 0xff);
597 if (nand->address_cycles >= 4)
598 {
599 retval |= imx31_address(nand, (page >> 16) & 0xff);
600 if (nand->address_cycles >= 5)
601 {
602 retval |= imx31_address(nand, (page >> 24) & 0xff);
603 retval |= imx31_command(nand, NAND_CMD_READSTART);
604 }
605 }
606 retval |= do_data_output (nand);
607 if (retval != ERROR_OK)
608 {
609 return retval;
610 }
611
612 if (data)
613 {
614 target_read_buffer (target, MX3_NF_MAIN_BUFFER0, data_size,
615 data);
616 }
617 if (oob)
618 {
619 target_read_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
620 oob);
621 }
622 }
623 return ERROR_OK;
624 }
625
626 static int test_iomux_settings (struct target * target, uint32_t address,
627 uint32_t mask, const char *text)
628 {
629 uint32_t register_content;
630 target_read_u32 (target, address, &register_content);
631 if ((register_content & mask) != (0x12121212 & mask))
632 {
633 LOG_ERROR ("IOMUX for {%s} is bad", text);
634 return ERROR_FAIL;
635 }
636 return ERROR_OK;
637 }
638
639 static int initialize_nf_controller (struct nand_device *nand)
640 {
641 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
642 struct target *target = nand->target;
643 /*
644 * resets NAND flash controller in zero time ? I dont know.
645 */
646 target_write_u16 (target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
647 {
648 uint16_t work_mode;
649 work_mode = MX3_NF_BIT_INT_DIS; /* disable interrupt */
650 if (target->endianness == TARGET_BIG_ENDIAN)
651 {
652 work_mode |= MX3_NF_BIT_BE_EN;
653 }
654 if (mx3_nf_info->flags.hw_ecc_enabled)
655 {
656 work_mode |= MX3_NF_BIT_ECC_EN;
657 }
658 target_write_u16 (target, MX3_NF_CFG1, work_mode);
659 }
660 /*
661 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
662 */
663 target_write_u16 (target, MX3_NF_BUFCFG, 2);
664 {
665 uint16_t temp;
666 target_read_u16 (target, MX3_NF_FWP, &temp);
667 if ((temp & 0x0007) == 1)
668 {
669 LOG_ERROR ("NAND flash is tight-locked, reset needed");
670 return ERROR_FAIL;
671 }
672
673 }
674 /*
675 * unlock NAND flash for write
676 */
677 target_write_u16 (target, MX3_NF_FWP, 4);
678 target_write_u16 (target, MX3_NF_LOCKSTART, 0x0000);
679 target_write_u16 (target, MX3_NF_LOCKEND, 0xFFFF);
680 /*
681 * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
682 */
683 target_write_u16 (target, MX3_NF_BUFADDR, 0x0000);
684 /*
685 * address of SRAM buffer
686 */
687 in_sram_address = MX3_NF_MAIN_BUFFER0;
688 sign_of_sequental_byte_read = 0;
689 return ERROR_OK;
690 }
691
692 static int get_next_byte_from_sram_buffer (struct target * target, uint8_t * value)
693 {
694 static uint8_t even_byte = 0;
695 /*
696 * host-big_endian ??
697 */
698 if (sign_of_sequental_byte_read == 0)
699 {
700 even_byte = 0;
701 }
702 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
703 {
704 LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
705 *value = 0;
706 sign_of_sequental_byte_read = 0;
707 even_byte = 0;
708 return ERROR_NAND_OPERATION_FAILED;
709 }
710 else
711 {
712 uint16_t temp;
713 target_read_u16 (target, in_sram_address, &temp);
714 if (even_byte)
715 {
716 *value = temp >> 8;
717 even_byte = 0;
718 in_sram_address += 2;
719 }
720 else
721 {
722 *value = temp & 0xff;
723 even_byte = 1;
724 }
725 }
726 sign_of_sequental_byte_read = 1;
727 return ERROR_OK;
728 }
729
730 static int get_next_halfword_from_sram_buffer (struct target * target,
731 uint16_t * value)
732 {
733 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
734 {
735 LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
736 *value = 0;
737 return ERROR_NAND_OPERATION_FAILED;
738 }
739 else
740 {
741 target_read_u16 (target, in_sram_address, value);
742 in_sram_address += 2;
743 }
744 return ERROR_OK;
745 }
746
747 static int poll_for_complete_op (struct target * target, const char *text)
748 {
749 uint16_t poll_complete_status;
750 for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++)
751 {
752 usleep (25);
753 target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
754 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
755 {
756 break;
757 }
758 }
759 if (!(poll_complete_status & MX3_NF_BIT_OP_DONE))
760 {
761 LOG_ERROR ("%s sending timeout", text);
762 return ERROR_NAND_OPERATION_FAILED;
763 }
764 return ERROR_OK;
765 }
766
767 static int validate_target_state (struct nand_device *nand)
768 {
769 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
770 struct target *target = nand->target;
771
772 if (target->state != TARGET_HALTED)
773 {
774 LOG_ERROR (target_not_halted_err_msg);
775 return ERROR_NAND_OPERATION_FAILED;
776 }
777
778 if (mx3_nf_info->flags.target_little_endian !=
779 (target->endianness == TARGET_LITTLE_ENDIAN))
780 {
781 /*
782 * endianness changed after NAND controller probed
783 */
784 return ERROR_NAND_OPERATION_FAILED;
785 }
786 return ERROR_OK;
787 }
788
789 static int do_data_output (struct nand_device *nand)
790 {
791 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
792 struct target *target = nand->target;
793 switch (mx3_nf_info->fin)
794 {
795 case MX3_NF_FIN_DATAOUT:
796 /*
797 * start data output operation (set MX3_NF_BIT_OP_DONE==0)
798 */
799 target_write_u16 (target, MX3_NF_CFG2,
800 MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info->
801 optype));
802 {
803 int poll_result;
804 poll_result = poll_for_complete_op (target, "data output");
805 if (poll_result != ERROR_OK)
806 {
807 return poll_result;
808 }
809 }
810 mx3_nf_info->fin = MX3_NF_FIN_NONE;
811 /*
812 * ECC stuff
813 */
814 if ((mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE)
815 && mx3_nf_info->flags.hw_ecc_enabled)
816 {
817 uint16_t ecc_status;
818 target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
819 switch (ecc_status & 0x000c)
820 {
821 case 1 << 2:
822 LOG_DEBUG
823 ("main area readed with 1 (correctable) error");
824 break;
825 case 2 << 2:
826 LOG_DEBUG
827 ("main area readed with more than 1 (incorrectable) error");
828 return ERROR_NAND_OPERATION_FAILED;
829 break;
830 }
831 switch (ecc_status & 0x0003)
832 {
833 case 1:
834 LOG_DEBUG
835 ("spare area readed with 1 (correctable) error");
836 break;
837 case 2:
838 LOG_DEBUG
839 ("main area readed with more than 1 (incorrectable) error");
840 return ERROR_NAND_OPERATION_FAILED;
841 break;
842 }
843 }
844 break;
845 case MX3_NF_FIN_NONE:
846 break;
847 }
848 return ERROR_OK;
849 }
850
851 struct nand_flash_controller imx31_nand_flash_controller = {
852 .name = "imx31",
853 .usage = "nand device imx31 target noecc|hwecc",
854 .nand_device_command = &imx31_nand_device_command,
855 .init = &imx31_init,
856 .reset = &imx31_reset,
857 .command = &imx31_command,
858 .address = &imx31_address,
859 .write_data = &imx31_write_data,
860 .read_data = &imx31_read_data,
861 .write_page = &imx31_write_page,
862 .read_page = &imx31_read_page,
863 .nand_ready = &imx31_nand_ready,
864 };
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