src/flash/nand/mx2.h

   1
   2 /***************************************************************************
   3  *   Copyright (C) 2009 by Alexei Babich                                   *
   4  *   Rezonans plc., Chelyabinsk, Russia                                    *
   5  *   impatt@mail.ru                                                        *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22
  23 /*
  24  * Freescale iMX2* OpenOCD NAND Flash controller support.
  25  * based on Freescale iMX3* OpenOCD NAND Flash controller support.
  26  *
  27  * Many thanks to Ben Dooks for writing s3c24xx driver.
  28  */
  29
  30 #define         MX2_NF_BASE_ADDR                0xd8000000
  31 #define         MX2_NF_BUFSIZ                   (MX2_NF_BASE_ADDR + 0xe00)
  32 #define         MX2_NF_BUFADDR                  (MX2_NF_BASE_ADDR + 0xe04)
  33 #define         MX2_NF_FADDR                    (MX2_NF_BASE_ADDR + 0xe06)
  34 #define         MX2_NF_FCMD                             (MX2_NF_BASE_ADDR + 0xe08)
  35 #define         MX2_NF_BUFCFG                   (MX2_NF_BASE_ADDR + 0xe0a)
  36 #define         MX2_NF_ECCSTATUS                        (MX2_NF_BASE_ADDR + 0xe0c)
  37 #define         MX2_NF_ECCMAINPOS                       (MX2_NF_BASE_ADDR + 0xe0e)
  38 #define         MX2_NF_ECCSPAREPOS                      (MX2_NF_BASE_ADDR + 0xe10)
  39 #define         MX2_NF_FWP                      (MX2_NF_BASE_ADDR + 0xe12)
  40 #define         MX2_NF_LOCKSTART                        (MX2_NF_BASE_ADDR + 0xe14)
  41 #define         MX2_NF_LOCKEND                  (MX2_NF_BASE_ADDR + 0xe16)
  42 #define         MX2_NF_FWPSTATUS                        (MX2_NF_BASE_ADDR + 0xe18)
  43  /*
  44   * all bits not marked as self-clearing bit
  45   */
  46 #define         MX2_NF_CFG1                     (MX2_NF_BASE_ADDR + 0xe1a)
  47 #define         MX2_NF_CFG2                     (MX2_NF_BASE_ADDR + 0xe1c)
  48
  49 #define         MX2_NF_MAIN_BUFFER0             (MX2_NF_BASE_ADDR + 0x0000)
  50 #define         MX2_NF_MAIN_BUFFER1             (MX2_NF_BASE_ADDR + 0x0200)
  51 #define         MX2_NF_MAIN_BUFFER2             (MX2_NF_BASE_ADDR + 0x0400)
  52 #define         MX2_NF_MAIN_BUFFER3             (MX2_NF_BASE_ADDR + 0x0600)
  53 #define         MX2_NF_SPARE_BUFFER0    (MX2_NF_BASE_ADDR + 0x0800)
  54 #define         MX2_NF_SPARE_BUFFER1    (MX2_NF_BASE_ADDR + 0x0810)
  55 #define         MX2_NF_SPARE_BUFFER2    (MX2_NF_BASE_ADDR + 0x0820)
  56 #define         MX2_NF_SPARE_BUFFER3    (MX2_NF_BASE_ADDR + 0x0830)
  57 #define         MX2_NF_MAIN_BUFFER_LEN  512
  58 #define         MX2_NF_SPARE_BUFFER_LEN 16
  59 #define         MX2_NF_LAST_BUFFER_ADDR ((MX2_NF_SPARE_BUFFER3) + MX2_NF_SPARE_BUFFER_LEN - 2)
  60
  61 /* bits in MX2_NF_CFG1 register */
  62 #define         MX2_NF_BIT_SPARE_ONLY_EN        (1<<2)
  63 #define         MX2_NF_BIT_ECC_EN                       (1<<3)
  64 #define         MX2_NF_BIT_INT_DIS                      (1<<4)
  65 #define         MX2_NF_BIT_BE_EN                        (1<<5)
  66 #define         MX2_NF_BIT_RESET_EN                     (1<<6)
  67 #define         MX2_NF_BIT_FORCE_CE                     (1<<7)
  68
  69 /* bits in MX2_NF_CFG2 register */
  70
  71 /*Flash Command Input*/
  72 #define         MX2_NF_BIT_OP_FCI                       (1<<0)
  73  /*
  74   * Flash Address Input
  75   */
  76 #define         MX2_NF_BIT_OP_FAI                       (1<<1)
  77  /*
  78   * Flash Data Input
  79   */
  80 #define         MX2_NF_BIT_OP_FDI                       (1<<2)
  81
  82 /* see "enum mx_dataout_type" below */
  83 #define         MX2_NF_BIT_DATAOUT_TYPE(x)      ((x)<<3)
  84 #define         MX2_NF_BIT_OP_DONE                      (1<<15)
  85
  86 #define         MX2_CCM_CGR2            0x53f80028
  87 #define         MX2_GPR                         0x43fac008
  88 //#define               MX2_PCSR                        0x53f8000c
  89 #define         MX2_FMCR                        0x10027814
  90 #define         MX2_FMCR_NF_16BIT_SEL           (1<<4)
  91 #define         MX2_FMCR_NF_FMS                 (1<<5)
  92
  93 enum mx_dataout_type
  94 {
  95         MX2_NF_DATAOUT_PAGE = 1,
  96         MX2_NF_DATAOUT_NANDID = 2,
  97         MX2_NF_DATAOUT_NANDSTATUS = 4,
  98 };
  99 enum mx_nf_finalize_action
 100 {
 101         MX2_NF_FIN_NONE,
 102         MX2_NF_FIN_DATAOUT,
 103 };
 104
 105 struct mx2_nf_flags
 106 {
 107         unsigned host_little_endian:1;
 108         unsigned target_little_endian:1;
 109         unsigned nand_readonly:1;
 110         unsigned one_kb_sram:1;
 111         unsigned hw_ecc_enabled:1;
 112 };
 113
 114 struct mx2_nf_controller
 115 {
 116         struct target *target;
 117         enum mx_dataout_type optype;
 118         enum mx_nf_finalize_action fin;
 119         struct mx2_nf_flags flags;
 120 };