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Added board type as a parameter to mx2 NFC as they have different base addresses.
[openocd.git] / src / flash / nand / mx2.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Alexei Babich *
3 * Rezonans plc., Chelyabinsk, Russia *
4 * impatt@mail.ru *
5 * *
6 * Copyright (C) 2010 by Gaetan CARLIER *
7 * Trump s.a., Belgium *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 /*
26 * Freescale iMX OpenOCD NAND Flash controller support.
27 * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
28 */
29
30 /*
31 * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
32 * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
33 * "nand write # file 0", "nand verify"
34 *
35 * get_next_halfword_from_sram_buffer() not tested
36 * !! all function only tested with 2k page nand device; mxc_write_page
37 * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
38 * !! oob must be be used due to NFS bug
39 */
40 #ifdef HAVE_CONFIG_H
41 #include "config.h"
42 #endif
43
44 #include "imp.h"
45 #include "mx2.h"
46 #include <target/target.h>
47
48 /* This permits to print (in LOG_INFO) how much bytes
49 * has been written after a page read or write.
50 * This is useful when OpenOCD is used with a graphical
51 * front-end to estimate progression of the global read/write
52 */
53 #undef _MXC_PRINT_STAT
54 /* #define _MXC_PRINT_STAT */
55
56 static const char target_not_halted_err_msg[] =
57 "target must be halted to use mxc NAND flash controller";
58 static const char data_block_size_err_msg[] =
59 "minimal granularity is one half-word, %" PRId32 " is incorrect";
60 static const char sram_buffer_bounds_err_msg[] =
61 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
62 static const char get_status_register_err_msg[] = "can't get NAND status";
63 static uint32_t in_sram_address;
64 static unsigned char sign_of_sequental_byte_read;
65
66 static int initialize_nf_controller(struct nand_device *nand);
67 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value);
68 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value);
69 static int poll_for_complete_op(struct nand_device *nand, const char *text);
70 static int validate_target_state(struct nand_device *nand);
71 static int do_data_output(struct nand_device *nand);
72
73 static int mxc_command(struct nand_device *nand, uint8_t command);
74 static int mxc_address(struct nand_device *nand, uint8_t address);
75
76 NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
77 {
78 struct mxc_nf_controller *mxc_nf_info;
79 int hwecc_needed;
80 int x;
81
82 mxc_nf_info = malloc(sizeof(struct mxc_nf_controller));
83 if (mxc_nf_info == NULL) {
84 LOG_ERROR("no memory for nand controller");
85 return ERROR_FAIL;
86 }
87 nand->controller_priv = mxc_nf_info;
88
89 if (CMD_ARGC < 4) {
90 LOG_ERROR("use \"nand device mxc target mx27|mx31|mx35 noecc|hwecc\"");
91 return ERROR_FAIL;
92 }
93
94 /*
95 * check board type
96 */
97 if (strcmp(CMD_ARGV[2], "mx27") == 0)
98 mxc_nf_info->mxc_base_addr = 0xD8000000;
99 else if (strcmp(CMD_ARGV[2], "mx31") == 0)
100 mxc_nf_info->mxc_base_addr = 0xB8000000;
101 else if (strcmp(CMD_ARGV[2], "mx35") == 0)
102 mxc_nf_info->mxc_base_addr = 0xBB000000;
103
104 /*
105 * check hwecc requirements
106 */
107 hwecc_needed = strcmp(CMD_ARGV[3], "hwecc");
108 if (hwecc_needed == 0)
109 mxc_nf_info->flags.hw_ecc_enabled = 1;
110 else
111 mxc_nf_info->flags.hw_ecc_enabled = 0;
112
113 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
114 mxc_nf_info->fin = MXC_NF_FIN_NONE;
115 mxc_nf_info->flags.target_little_endian =
116 (nand->target->endianness == TARGET_LITTLE_ENDIAN);
117
118 /*
119 * testing host endianness
120 */
121 x = 1;
122 if (*(char *) &x == 1)
123 mxc_nf_info->flags.host_little_endian = 1;
124 else
125 mxc_nf_info->flags.host_little_endian = 0;
126 return ERROR_OK;
127 }
128
129 static int mxc_init(struct nand_device *nand)
130 {
131 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
132 struct target *target = nand->target;
133
134 int validate_target_result;
135 uint16_t buffsize_register_content;
136 uint32_t pcsr_register_content;
137 int retval;
138 uint16_t nand_status_content;
139 /*
140 * validate target state
141 */
142 validate_target_result = validate_target_state(nand);
143 if (validate_target_result != ERROR_OK)
144 return validate_target_result;
145
146 target_read_u16(target, MXC_NF_BUFSIZ, &buffsize_register_content);
147 mxc_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
148
149 target_read_u32(target, MXC_FMCR, &pcsr_register_content);
150 if (!nand->bus_width) {
151 /* bus_width not yet defined. Read it from MXC_FMCR */
152 nand->bus_width =
153 (pcsr_register_content & MXC_FMCR_NF_16BIT_SEL) ? 16 : 8;
154 } else {
155 /* bus_width forced in soft. Sync it to MXC_FMCR */
156 pcsr_register_content |=
157 ((nand->bus_width == 16) ? MXC_FMCR_NF_16BIT_SEL : 0x00000000);
158 target_write_u32(target, MXC_FMCR, pcsr_register_content);
159 }
160 if (nand->bus_width == 16)
161 LOG_DEBUG("MXC_NF : bus is 16-bit width");
162 else
163 LOG_DEBUG("MXC_NF : bus is 8-bit width");
164
165 if (!nand->page_size) {
166 nand->page_size = (pcsr_register_content & MXC_FMCR_NF_FMS) ? 2048 : 512;
167 } else {
168 pcsr_register_content |=
169 ((nand->page_size == 2048) ? MXC_FMCR_NF_FMS : 0x00000000);
170 target_write_u32(target, MXC_FMCR, pcsr_register_content);
171 }
172 if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
173 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
174 "pagesize 2048 is incompatible with it");
175 } else {
176 LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
177 }
178
179 initialize_nf_controller(nand);
180
181 retval = ERROR_OK;
182 retval |= mxc_command(nand, NAND_CMD_STATUS);
183 retval |= mxc_address(nand, 0x00);
184 retval |= do_data_output(nand);
185 if (retval != ERROR_OK) {
186 LOG_ERROR(get_status_register_err_msg);
187 return ERROR_FAIL;
188 }
189 target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
190 if (!(nand_status_content & 0x0080)) {
191 LOG_INFO("NAND read-only");
192 mxc_nf_info->flags.nand_readonly = 1;
193 } else {
194 mxc_nf_info->flags.nand_readonly = 0;
195 }
196 return ERROR_OK;
197 }
198
199 static int mxc_read_data(struct nand_device *nand, void *data)
200 {
201 int validate_target_result;
202 int try_data_output_from_nand_chip;
203 /*
204 * validate target state
205 */
206 validate_target_result = validate_target_state(nand);
207 if (validate_target_result != ERROR_OK)
208 return validate_target_result;
209
210 /*
211 * get data from nand chip
212 */
213 try_data_output_from_nand_chip = do_data_output(nand);
214 if (try_data_output_from_nand_chip != ERROR_OK) {
215 LOG_ERROR("mxc_read_data : read data failed : '%x'",
216 try_data_output_from_nand_chip);
217 return try_data_output_from_nand_chip;
218 }
219
220 if (nand->bus_width == 16)
221 get_next_halfword_from_sram_buffer(nand, data);
222 else
223 get_next_byte_from_sram_buffer(nand, data);
224
225 return ERROR_OK;
226 }
227
228 static int mxc_write_data(struct nand_device *nand, uint16_t data)
229 {
230 LOG_ERROR("write_data() not implemented");
231 return ERROR_NAND_OPERATION_FAILED;
232 }
233
234 static int mxc_reset(struct nand_device *nand)
235 {
236 /*
237 * validate target state
238 */
239 int validate_target_result;
240 validate_target_result = validate_target_state(nand);
241 if (validate_target_result != ERROR_OK)
242 return validate_target_result;
243 initialize_nf_controller(nand);
244 return ERROR_OK;
245 }
246
247 static int mxc_command(struct nand_device *nand, uint8_t command)
248 {
249 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
250 struct target *target = nand->target;
251 int validate_target_result;
252 int poll_result;
253 /*
254 * validate target state
255 */
256 validate_target_result = validate_target_state(nand);
257 if (validate_target_result != ERROR_OK)
258 return validate_target_result;
259
260 switch (command) {
261 case NAND_CMD_READOOB:
262 command = NAND_CMD_READ0;
263 /* set read point for data_read() and read_block_data() to
264 * spare area in SRAM buffer
265 */
266 in_sram_address = MXC_NF_SPARE_BUFFER0;
267 break;
268 case NAND_CMD_READ1:
269 command = NAND_CMD_READ0;
270 /*
271 * offset == one half of page size
272 */
273 in_sram_address = MXC_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
274 break;
275 default:
276 in_sram_address = MXC_NF_MAIN_BUFFER0;
277 break;
278 }
279
280 target_write_u16(target, MXC_NF_FCMD, command);
281 /*
282 * start command input operation (set MXC_NF_BIT_OP_DONE==0)
283 */
284 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FCI);
285 poll_result = poll_for_complete_op(nand, "command");
286 if (poll_result != ERROR_OK)
287 return poll_result;
288 /*
289 * reset cursor to begin of the buffer
290 */
291 sign_of_sequental_byte_read = 0;
292 /* Handle special read command and adjust NF_CFG2(FDO) */
293 switch (command) {
294 case NAND_CMD_READID:
295 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDID;
296 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
297 break;
298 case NAND_CMD_STATUS:
299 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
300 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
301 target_write_u16 (target, MXC_NF_BUFADDR, 0);
302 in_sram_address = 0;
303 break;
304 case NAND_CMD_READ0:
305 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
306 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
307 break;
308 default:
309 /* Ohter command use the default 'One page data out' FDO */
310 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
311 break;
312 }
313 return ERROR_OK;
314 }
315
316 static int mxc_address(struct nand_device *nand, uint8_t address)
317 {
318 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
319 struct target *target = nand->target;
320 int validate_target_result;
321 int poll_result;
322 /*
323 * validate target state
324 */
325 validate_target_result = validate_target_state(nand);
326 if (validate_target_result != ERROR_OK)
327 return validate_target_result;
328
329 target_write_u16(target, MXC_NF_FADDR, address);
330 /*
331 * start address input operation (set MXC_NF_BIT_OP_DONE==0)
332 */
333 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FAI);
334 poll_result = poll_for_complete_op(nand, "address");
335 if (poll_result != ERROR_OK)
336 return poll_result;
337
338 return ERROR_OK;
339 }
340
341 static int mxc_nand_ready(struct nand_device *nand, int tout)
342 {
343 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
344 struct target *target = nand->target;
345 uint16_t poll_complete_status;
346 int validate_target_result;
347
348 /*
349 * validate target state
350 */
351 validate_target_result = validate_target_state(nand);
352 if (validate_target_result != ERROR_OK)
353 return validate_target_result;
354
355 do {
356 target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
357 if (poll_complete_status & MXC_NF_BIT_OP_DONE)
358 return tout;
359
360 alive_sleep(1);
361 }
362 while (tout-- > 0);
363 return tout;
364 }
365
366 static int mxc_write_page(struct nand_device *nand, uint32_t page,
367 uint8_t *data, uint32_t data_size,
368 uint8_t *oob, uint32_t oob_size)
369 {
370 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
371 struct target *target = nand->target;
372 int retval;
373 uint16_t nand_status_content;
374 uint16_t swap1, swap2, new_swap1;
375 int poll_result;
376 if (data_size % 2) {
377 LOG_ERROR(data_block_size_err_msg, data_size);
378 return ERROR_NAND_OPERATION_FAILED;
379 }
380 if (oob_size % 2) {
381 LOG_ERROR(data_block_size_err_msg, oob_size);
382 return ERROR_NAND_OPERATION_FAILED;
383 }
384 if (!data) {
385 LOG_ERROR("nothing to program");
386 return ERROR_NAND_OPERATION_FAILED;
387 }
388 /*
389 * validate target state
390 */
391 retval = validate_target_state(nand);
392 if (retval != ERROR_OK)
393 return retval;
394
395 in_sram_address = MXC_NF_MAIN_BUFFER0;
396 sign_of_sequental_byte_read = 0;
397 retval = ERROR_OK;
398 retval |= mxc_command(nand, NAND_CMD_SEQIN);
399 retval |= mxc_address(nand, 0); /* col */
400 retval |= mxc_address(nand, 0); /* col */
401 retval |= mxc_address(nand, page & 0xff); /* page address */
402 retval |= mxc_address(nand, (page >> 8) & 0xff); /* page address */
403 retval |= mxc_address(nand, (page >> 16) & 0xff); /* page address */
404
405 target_write_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
406 if (oob) {
407 if (mxc_nf_info->flags.hw_ecc_enabled) {
408 /*
409 * part of spare block will be overrided by hardware
410 * ECC generator
411 */
412 LOG_DEBUG("part of spare block will be overrided "
413 "by hardware ECC generator");
414 }
415 target_write_buffer(target, MXC_NF_SPARE_BUFFER0, oob_size, oob);
416 }
417 /* BI-swap - work-around of mxc NFC for NAND device with page == 2kb */
418 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
419 if (oob) {
420 LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
421 return ERROR_NAND_OPERATION_FAILED;
422 }
423 swap2 = 0xffff; /* Spare buffer unused forced to 0xffff */
424 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
425 swap2 = (swap1 << 8) | (swap2 & 0xFF);
426
427 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
428 target_write_u16(target, MXC_NF_SPARE_BUFFER3 + 4, swap2);
429 /*
430 * start data input operation (set MXC_NF_BIT_OP_DONE==0)
431 */
432 target_write_u16(target, MXC_NF_BUFADDR, 0);
433 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
434 poll_result = poll_for_complete_op(nand, "data input");
435 if (poll_result != ERROR_OK)
436 return poll_result;
437
438 target_write_u16(target, MXC_NF_BUFADDR, 1);
439 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
440 poll_result = poll_for_complete_op(nand, "data input");
441 if (poll_result != ERROR_OK)
442 return poll_result;
443
444 target_write_u16(target, MXC_NF_BUFADDR, 2);
445 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
446 poll_result = poll_for_complete_op(nand, "data input");
447 if (poll_result != ERROR_OK)
448 return poll_result;
449
450 target_write_u16(target, MXC_NF_BUFADDR, 3);
451 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
452 poll_result = poll_for_complete_op(nand, "data input");
453 if (poll_result != ERROR_OK)
454 return poll_result;
455
456 retval |= mxc_command(nand, NAND_CMD_PAGEPROG);
457 if (retval != ERROR_OK)
458 return retval;
459
460 /*
461 * check status register
462 */
463 retval = ERROR_OK;
464 retval |= mxc_command(nand, NAND_CMD_STATUS);
465 target_write_u16 (target, MXC_NF_BUFADDR, 0);
466 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
467 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
468 retval |= do_data_output(nand);
469 if (retval != ERROR_OK) {
470 LOG_ERROR(get_status_register_err_msg);
471 return retval;
472 }
473 target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
474 if (nand_status_content & 0x0001) {
475 /*
476 * page not correctly written
477 */
478 return ERROR_NAND_OPERATION_FAILED;
479 }
480 #ifdef _MXC_PRINT_STAT
481 LOG_INFO("%d bytes newly written", data_size);
482 #endif
483 return ERROR_OK;
484 }
485
486 static int mxc_read_page(struct nand_device *nand, uint32_t page,
487 uint8_t *data, uint32_t data_size,
488 uint8_t *oob, uint32_t oob_size)
489 {
490 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
491 struct target *target = nand->target;
492 int retval;
493 uint16_t swap1, swap2, new_swap1;
494
495 if (data_size % 2) {
496 LOG_ERROR(data_block_size_err_msg, data_size);
497 return ERROR_NAND_OPERATION_FAILED;
498 }
499 if (oob_size % 2) {
500 LOG_ERROR(data_block_size_err_msg, oob_size);
501 return ERROR_NAND_OPERATION_FAILED;
502 }
503
504 /*
505 * validate target state
506 */
507 retval = validate_target_state(nand);
508 if (retval != ERROR_OK) {
509 return retval;
510 }
511 /* Reset address_cycles before mxc_command ?? */
512 retval = mxc_command(nand, NAND_CMD_READ0);
513 if (retval != ERROR_OK) return retval;
514 retval = mxc_address(nand, 0); /* col */
515 if (retval != ERROR_OK) return retval;
516 retval = mxc_address(nand, 0); /* col */
517 if (retval != ERROR_OK) return retval;
518 retval = mxc_address(nand, page & 0xff); /* page address */
519 if (retval != ERROR_OK) return retval;
520 retval = mxc_address(nand, (page >> 8) & 0xff); /* page address */
521 if (retval != ERROR_OK) return retval;
522 retval = mxc_address(nand, (page >> 16) & 0xff); /* page address */
523 if (retval != ERROR_OK) return retval;
524 retval = mxc_command(nand, NAND_CMD_READSTART);
525 if (retval != ERROR_OK) return retval;
526
527 target_write_u16(target, MXC_NF_BUFADDR, 0);
528 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
529 retval = do_data_output(nand);
530 if (retval != ERROR_OK) {
531 LOG_ERROR("MXC_NF : Error reading page 0");
532 return retval;
533 }
534 /* Test nand page size to know how much MAIN_BUFFER must be written */
535 target_write_u16(target, MXC_NF_BUFADDR, 1);
536 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
537 retval = do_data_output(nand);
538 if (retval != ERROR_OK) {
539 LOG_ERROR("MXC_NF : Error reading page 1");
540 return retval;
541 }
542 target_write_u16(target, MXC_NF_BUFADDR, 2);
543 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
544 retval = do_data_output(nand);
545 if (retval != ERROR_OK) {
546 LOG_ERROR("MXC_NF : Error reading page 2");
547 return retval;
548 }
549 target_write_u16(target, MXC_NF_BUFADDR, 3);
550 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
551 retval = do_data_output(nand);
552 if (retval != ERROR_OK) {
553 LOG_ERROR("MXC_NF : Error reading page 3");
554 return retval;
555 }
556 /* BI-swap - work-around of mxc NFC for NAND device with page == 2k */
557 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
558 target_read_u16(target, MXC_NF_SPARE_BUFFER3 + 4, &swap2);
559 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
560 swap2 = (swap1 << 8) | (swap2 & 0xFF);
561 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
562 target_write_u16(target, MXC_NF_SPARE_BUFFER3 + 4, swap2);
563
564 if (data)
565 target_read_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
566 if (oob)
567 target_read_buffer(target, MXC_NF_SPARE_BUFFER0, oob_size, oob);
568
569 #ifdef _MXC_PRINT_STAT
570 if (data_size > 0) {
571 /* When Operation Status is read (when page is erased),
572 * this function is used but data_size is null.
573 */
574 LOG_INFO("%d bytes newly read", data_size);
575 }
576 #endif
577 return ERROR_OK;
578 }
579
580 static int initialize_nf_controller(struct nand_device *nand)
581 {
582 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
583 struct target *target = nand->target;
584 uint16_t work_mode;
585 uint16_t temp;
586 /*
587 * resets NAND flash controller in zero time ? I dont know.
588 */
589 target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
590 work_mode = MXC_NF_BIT_INT_DIS; /* disable interrupt */
591 if (target->endianness == TARGET_BIG_ENDIAN) {
592 LOG_DEBUG("MXC_NF : work in Big Endian mode");
593 work_mode |= MXC_NF_BIT_BE_EN;
594 } else {
595 LOG_DEBUG("MXC_NF : work in Little Endian mode");
596 }
597 if (mxc_nf_info->flags.hw_ecc_enabled) {
598 LOG_DEBUG("MXC_NF : work with ECC mode");
599 work_mode |= MXC_NF_BIT_ECC_EN;
600 } else {
601 LOG_DEBUG("MXC_NF : work without ECC mode");
602 }
603 target_write_u16(target, MXC_NF_CFG1, work_mode);
604 /*
605 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
606 */
607 target_write_u16(target, MXC_NF_BUFCFG, 2);
608 target_read_u16(target, MXC_NF_FWP, &temp);
609 if ((temp & 0x0007) == 1) {
610 LOG_ERROR("NAND flash is tight-locked, reset needed");
611 return ERROR_FAIL;
612 }
613
614 /*
615 * unlock NAND flash for write
616 */
617 target_write_u16(target, MXC_NF_FWP, 4);
618 target_write_u16(target, MXC_NF_LOCKSTART, 0x0000);
619 target_write_u16(target, MXC_NF_LOCKEND, 0xFFFF);
620 /*
621 * 0x0000 means that first SRAM buffer @0xD800_0000 will be used
622 */
623 target_write_u16(target, MXC_NF_BUFADDR, 0x0000);
624 /*
625 * address of SRAM buffer
626 */
627 in_sram_address = MXC_NF_MAIN_BUFFER0;
628 sign_of_sequental_byte_read = 0;
629 return ERROR_OK;
630 }
631
632 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value)
633 {
634 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
635 struct target *target = nand->target;
636 static uint8_t even_byte = 0;
637 uint16_t temp;
638 /*
639 * host-big_endian ??
640 */
641 if (sign_of_sequental_byte_read == 0)
642 even_byte = 0;
643
644 if (in_sram_address > MXC_NF_LAST_BUFFER_ADDR) {
645 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
646 *value = 0;
647 sign_of_sequental_byte_read = 0;
648 even_byte = 0;
649 return ERROR_NAND_OPERATION_FAILED;
650 } else {
651 target_read_u16(target, in_sram_address, &temp);
652 if (even_byte) {
653 *value = temp >> 8;
654 even_byte = 0;
655 in_sram_address += 2;
656 } else {
657 *value = temp & 0xff;
658 even_byte = 1;
659 }
660 }
661 sign_of_sequental_byte_read = 1;
662 return ERROR_OK;
663 }
664
665 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value)
666 {
667 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
668 struct target *target = nand->target;
669
670 if (in_sram_address > MXC_NF_LAST_BUFFER_ADDR) {
671 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
672 *value = 0;
673 return ERROR_NAND_OPERATION_FAILED;
674 } else {
675 target_read_u16(target, in_sram_address, value);
676 in_sram_address += 2;
677 }
678 return ERROR_OK;
679 }
680
681 static int poll_for_complete_op(struct nand_device *nand, const char *text)
682 {
683 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
684 struct target *target = nand->target;
685 uint16_t poll_complete_status;
686
687 for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) {
688 target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
689 if (poll_complete_status & MXC_NF_BIT_OP_DONE)
690 break;
691
692 usleep(10);
693 }
694 if (!(poll_complete_status & MXC_NF_BIT_OP_DONE)) {
695 LOG_ERROR("%s sending timeout", text);
696 return ERROR_NAND_OPERATION_FAILED;
697 }
698 return ERROR_OK;
699 }
700
701 static int validate_target_state(struct nand_device *nand)
702 {
703 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
704 struct target *target = nand->target;
705
706 if (target->state != TARGET_HALTED) {
707 LOG_ERROR(target_not_halted_err_msg);
708 return ERROR_NAND_OPERATION_FAILED;
709 }
710
711 if (mxc_nf_info->flags.target_little_endian !=
712 (target->endianness == TARGET_LITTLE_ENDIAN)) {
713 /*
714 * endianness changed after NAND controller probed
715 */
716 return ERROR_NAND_OPERATION_FAILED;
717 }
718 return ERROR_OK;
719 }
720
721 static int do_data_output(struct nand_device *nand)
722 {
723 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
724 struct target *target = nand->target;
725 int poll_result;
726 uint16_t ecc_status;
727 switch (mxc_nf_info->fin) {
728 case MXC_NF_FIN_DATAOUT:
729 /*
730 * start data output operation (set MXC_NF_BIT_OP_DONE==0)
731 */
732 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info->optype));
733 poll_result = poll_for_complete_op(nand, "data output");
734 if (poll_result != ERROR_OK)
735 return poll_result;
736
737 mxc_nf_info->fin = MXC_NF_FIN_NONE;
738 /*
739 * ECC stuff
740 */
741 if ((mxc_nf_info->optype == MXC_NF_DATAOUT_PAGE) &&
742 mxc_nf_info->flags.hw_ecc_enabled) {
743 target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
744 switch (ecc_status & 0x000c) {
745 case 1 << 2:
746 LOG_INFO("main area readed with 1 (correctable) error");
747 break;
748 case 2 << 2:
749 LOG_INFO("main area readed with more than 1 (incorrectable) error");
750 return ERROR_NAND_OPERATION_FAILED;
751 break;
752 }
753 switch (ecc_status & 0x0003) {
754 case 1:
755 LOG_INFO("spare area readed with 1 (correctable) error");
756 break;
757 case 2:
758 LOG_INFO("main area readed with more than 1 (incorrectable) error");
759 return ERROR_NAND_OPERATION_FAILED;
760 break;
761 }
762 }
763 break;
764 case MXC_NF_FIN_NONE:
765 break;
766 }
767 return ERROR_OK;
768 }
769
770 struct nand_flash_controller mxc_nand_flash_controller = {
771 .name = "mxc",
772 .nand_device_command = &mxc_nand_device_command,
773 .init = &mxc_init,
774 .reset = &mxc_reset,
775 .command = &mxc_command,
776 .address = &mxc_address,
777 .write_data = &mxc_write_data,
778 .read_data = &mxc_read_data,
779 .write_page = &mxc_write_page,
780 .read_page = &mxc_read_page,
781 .nand_ready = &mxc_nand_ready,
782 };
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