1 /***************************************************************************
2 * Copyright (C) 2009 by Alexei Babich *
3 * Rezonans plc., Chelyabinsk, Russia *
6 * Copyright (C) 2010 by Gaetan CARLIER *
7 * Trump s.a., Belgium *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
26 * Freescale iMX OpenOCD NAND Flash controller support.
27 * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
31 * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
32 * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
33 * "nand write # file 0", "nand verify"
35 * get_next_halfword_from_sram_buffer() not tested
36 * !! all function only tested with 2k page nand device; mxc_write_page
37 * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
38 * !! oob must be be used due to NFS bug
46 #include <target/target.h>
48 /* This permits to print (in LOG_INFO) how much bytes
49 * has been written after a page read or write.
50 * This is useful when OpenOCD is used with a graphical
51 * front-end to estimate progression of the global read/write
53 #undef _MXC_PRINT_STAT
54 /* #define _MXC_PRINT_STAT */
56 static const char target_not_halted_err_msg
[] =
57 "target must be halted to use mxc NAND flash controller";
58 static const char data_block_size_err_msg
[] =
59 "minimal granularity is one half-word, %" PRId32
" is incorrect";
60 static const char sram_buffer_bounds_err_msg
[] =
61 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32
")";
62 static const char get_status_register_err_msg
[] = "can't get NAND status";
63 static uint32_t in_sram_address
;
64 static unsigned char sign_of_sequental_byte_read
;
66 static int initialize_nf_controller(struct nand_device
*nand
);
67 static int get_next_byte_from_sram_buffer(struct nand_device
*nand
, uint8_t *value
);
68 static int get_next_halfword_from_sram_buffer(struct nand_device
*nand
, uint16_t *value
);
69 static int poll_for_complete_op(struct nand_device
*nand
, const char *text
);
70 static int validate_target_state(struct nand_device
*nand
);
71 static int do_data_output(struct nand_device
*nand
);
73 static int mxc_command(struct nand_device
*nand
, uint8_t command
);
74 static int mxc_address(struct nand_device
*nand
, uint8_t address
);
76 NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command
)
78 struct mxc_nf_controller
*mxc_nf_info
;
82 mxc_nf_info
= malloc(sizeof(struct mxc_nf_controller
));
83 if (mxc_nf_info
== NULL
) {
84 LOG_ERROR("no memory for nand controller");
87 nand
->controller_priv
= mxc_nf_info
;
90 LOG_ERROR("use \"nand device mxc target mx27|mx31|mx35 noecc|hwecc\"");
97 if (strcmp(CMD_ARGV
[2], "mx27") == 0)
98 mxc_nf_info
->mxc_base_addr
= 0xD8000000;
99 else if (strcmp(CMD_ARGV
[2], "mx31") == 0)
100 mxc_nf_info
->mxc_base_addr
= 0xB8000000;
101 else if (strcmp(CMD_ARGV
[2], "mx35") == 0)
102 mxc_nf_info
->mxc_base_addr
= 0xBB000000;
105 * check hwecc requirements
107 hwecc_needed
= strcmp(CMD_ARGV
[3], "hwecc");
108 if (hwecc_needed
== 0)
109 mxc_nf_info
->flags
.hw_ecc_enabled
= 1;
111 mxc_nf_info
->flags
.hw_ecc_enabled
= 0;
113 mxc_nf_info
->optype
= MXC_NF_DATAOUT_PAGE
;
114 mxc_nf_info
->fin
= MXC_NF_FIN_NONE
;
115 mxc_nf_info
->flags
.target_little_endian
=
116 (nand
->target
->endianness
== TARGET_LITTLE_ENDIAN
);
119 * testing host endianness
122 if (*(char *) &x
== 1)
123 mxc_nf_info
->flags
.host_little_endian
= 1;
125 mxc_nf_info
->flags
.host_little_endian
= 0;
129 static int mxc_init(struct nand_device
*nand
)
131 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
132 struct target
*target
= nand
->target
;
134 int validate_target_result
;
135 uint16_t buffsize_register_content
;
136 uint32_t pcsr_register_content
;
138 uint16_t nand_status_content
;
140 * validate target state
142 validate_target_result
= validate_target_state(nand
);
143 if (validate_target_result
!= ERROR_OK
)
144 return validate_target_result
;
146 target_read_u16(target
, MXC_NF_BUFSIZ
, &buffsize_register_content
);
147 mxc_nf_info
->flags
.one_kb_sram
= !(buffsize_register_content
& 0x000f);
149 target_read_u32(target
, MXC_FMCR
, &pcsr_register_content
);
150 if (!nand
->bus_width
) {
151 /* bus_width not yet defined. Read it from MXC_FMCR */
153 (pcsr_register_content
& MXC_FMCR_NF_16BIT_SEL
) ? 16 : 8;
155 /* bus_width forced in soft. Sync it to MXC_FMCR */
156 pcsr_register_content
|=
157 ((nand
->bus_width
== 16) ? MXC_FMCR_NF_16BIT_SEL
: 0x00000000);
158 target_write_u32(target
, MXC_FMCR
, pcsr_register_content
);
160 if (nand
->bus_width
== 16)
161 LOG_DEBUG("MXC_NF : bus is 16-bit width");
163 LOG_DEBUG("MXC_NF : bus is 8-bit width");
165 if (!nand
->page_size
) {
166 nand
->page_size
= (pcsr_register_content
& MXC_FMCR_NF_FMS
) ? 2048 : 512;
168 pcsr_register_content
|=
169 ((nand
->page_size
== 2048) ? MXC_FMCR_NF_FMS
: 0x00000000);
170 target_write_u32(target
, MXC_FMCR
, pcsr_register_content
);
172 if (mxc_nf_info
->flags
.one_kb_sram
&& (nand
->page_size
== 2048)) {
173 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
174 "pagesize 2048 is incompatible with it");
176 LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
179 initialize_nf_controller(nand
);
182 retval
|= mxc_command(nand
, NAND_CMD_STATUS
);
183 retval
|= mxc_address(nand
, 0x00);
184 retval
|= do_data_output(nand
);
185 if (retval
!= ERROR_OK
) {
186 LOG_ERROR(get_status_register_err_msg
);
189 target_read_u16(target
, MXC_NF_MAIN_BUFFER0
, &nand_status_content
);
190 if (!(nand_status_content
& 0x0080)) {
191 LOG_INFO("NAND read-only");
192 mxc_nf_info
->flags
.nand_readonly
= 1;
194 mxc_nf_info
->flags
.nand_readonly
= 0;
199 static int mxc_read_data(struct nand_device
*nand
, void *data
)
201 int validate_target_result
;
202 int try_data_output_from_nand_chip
;
204 * validate target state
206 validate_target_result
= validate_target_state(nand
);
207 if (validate_target_result
!= ERROR_OK
)
208 return validate_target_result
;
211 * get data from nand chip
213 try_data_output_from_nand_chip
= do_data_output(nand
);
214 if (try_data_output_from_nand_chip
!= ERROR_OK
) {
215 LOG_ERROR("mxc_read_data : read data failed : '%x'",
216 try_data_output_from_nand_chip
);
217 return try_data_output_from_nand_chip
;
220 if (nand
->bus_width
== 16)
221 get_next_halfword_from_sram_buffer(nand
, data
);
223 get_next_byte_from_sram_buffer(nand
, data
);
228 static int mxc_write_data(struct nand_device
*nand
, uint16_t data
)
230 LOG_ERROR("write_data() not implemented");
231 return ERROR_NAND_OPERATION_FAILED
;
234 static int mxc_reset(struct nand_device
*nand
)
237 * validate target state
239 int validate_target_result
;
240 validate_target_result
= validate_target_state(nand
);
241 if (validate_target_result
!= ERROR_OK
)
242 return validate_target_result
;
243 initialize_nf_controller(nand
);
247 static int mxc_command(struct nand_device
*nand
, uint8_t command
)
249 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
250 struct target
*target
= nand
->target
;
251 int validate_target_result
;
254 * validate target state
256 validate_target_result
= validate_target_state(nand
);
257 if (validate_target_result
!= ERROR_OK
)
258 return validate_target_result
;
261 case NAND_CMD_READOOB
:
262 command
= NAND_CMD_READ0
;
263 /* set read point for data_read() and read_block_data() to
264 * spare area in SRAM buffer
266 in_sram_address
= MXC_NF_SPARE_BUFFER0
;
269 command
= NAND_CMD_READ0
;
271 * offset == one half of page size
273 in_sram_address
= MXC_NF_MAIN_BUFFER0
+ (nand
->page_size
>> 1);
276 in_sram_address
= MXC_NF_MAIN_BUFFER0
;
280 target_write_u16(target
, MXC_NF_FCMD
, command
);
282 * start command input operation (set MXC_NF_BIT_OP_DONE==0)
284 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_OP_FCI
);
285 poll_result
= poll_for_complete_op(nand
, "command");
286 if (poll_result
!= ERROR_OK
)
289 * reset cursor to begin of the buffer
291 sign_of_sequental_byte_read
= 0;
292 /* Handle special read command and adjust NF_CFG2(FDO) */
294 case NAND_CMD_READID
:
295 mxc_nf_info
->optype
= MXC_NF_DATAOUT_NANDID
;
296 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
298 case NAND_CMD_STATUS
:
299 mxc_nf_info
->optype
= MXC_NF_DATAOUT_NANDSTATUS
;
300 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
301 target_write_u16 (target
, MXC_NF_BUFADDR
, 0);
305 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
306 mxc_nf_info
->optype
= MXC_NF_DATAOUT_PAGE
;
309 /* Ohter command use the default 'One page data out' FDO */
310 mxc_nf_info
->optype
= MXC_NF_DATAOUT_PAGE
;
316 static int mxc_address(struct nand_device
*nand
, uint8_t address
)
318 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
319 struct target
*target
= nand
->target
;
320 int validate_target_result
;
323 * validate target state
325 validate_target_result
= validate_target_state(nand
);
326 if (validate_target_result
!= ERROR_OK
)
327 return validate_target_result
;
329 target_write_u16(target
, MXC_NF_FADDR
, address
);
331 * start address input operation (set MXC_NF_BIT_OP_DONE==0)
333 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_OP_FAI
);
334 poll_result
= poll_for_complete_op(nand
, "address");
335 if (poll_result
!= ERROR_OK
)
341 static int mxc_nand_ready(struct nand_device
*nand
, int tout
)
343 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
344 struct target
*target
= nand
->target
;
345 uint16_t poll_complete_status
;
346 int validate_target_result
;
349 * validate target state
351 validate_target_result
= validate_target_state(nand
);
352 if (validate_target_result
!= ERROR_OK
)
353 return validate_target_result
;
356 target_read_u16(target
, MXC_NF_CFG2
, &poll_complete_status
);
357 if (poll_complete_status
& MXC_NF_BIT_OP_DONE
)
366 static int mxc_write_page(struct nand_device
*nand
, uint32_t page
,
367 uint8_t *data
, uint32_t data_size
,
368 uint8_t *oob
, uint32_t oob_size
)
370 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
371 struct target
*target
= nand
->target
;
373 uint16_t nand_status_content
;
374 uint16_t swap1
, swap2
, new_swap1
;
377 LOG_ERROR(data_block_size_err_msg
, data_size
);
378 return ERROR_NAND_OPERATION_FAILED
;
381 LOG_ERROR(data_block_size_err_msg
, oob_size
);
382 return ERROR_NAND_OPERATION_FAILED
;
385 LOG_ERROR("nothing to program");
386 return ERROR_NAND_OPERATION_FAILED
;
389 * validate target state
391 retval
= validate_target_state(nand
);
392 if (retval
!= ERROR_OK
)
395 in_sram_address
= MXC_NF_MAIN_BUFFER0
;
396 sign_of_sequental_byte_read
= 0;
398 retval
|= mxc_command(nand
, NAND_CMD_SEQIN
);
399 retval
|= mxc_address(nand
, 0); /* col */
400 retval
|= mxc_address(nand
, 0); /* col */
401 retval
|= mxc_address(nand
, page
& 0xff); /* page address */
402 retval
|= mxc_address(nand
, (page
>> 8) & 0xff); /* page address */
403 retval
|= mxc_address(nand
, (page
>> 16) & 0xff); /* page address */
405 target_write_buffer(target
, MXC_NF_MAIN_BUFFER0
, data_size
, data
);
407 if (mxc_nf_info
->flags
.hw_ecc_enabled
) {
409 * part of spare block will be overrided by hardware
412 LOG_DEBUG("part of spare block will be overrided "
413 "by hardware ECC generator");
415 target_write_buffer(target
, MXC_NF_SPARE_BUFFER0
, oob_size
, oob
);
417 /* BI-swap - work-around of mxc NFC for NAND device with page == 2kb */
418 target_read_u16(target
, MXC_NF_MAIN_BUFFER3
+ 464, &swap1
);
420 LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
421 return ERROR_NAND_OPERATION_FAILED
;
423 swap2
= 0xffff; /* Spare buffer unused forced to 0xffff */
424 new_swap1
= (swap1
& 0xFF00) | (swap2
>> 8);
425 swap2
= (swap1
<< 8) | (swap2
& 0xFF);
427 target_write_u16(target
, MXC_NF_MAIN_BUFFER3
+ 464, new_swap1
);
428 target_write_u16(target
, MXC_NF_SPARE_BUFFER3
+ 4, swap2
);
430 * start data input operation (set MXC_NF_BIT_OP_DONE==0)
432 target_write_u16(target
, MXC_NF_BUFADDR
, 0);
433 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_OP_FDI
);
434 poll_result
= poll_for_complete_op(nand
, "data input");
435 if (poll_result
!= ERROR_OK
)
438 target_write_u16(target
, MXC_NF_BUFADDR
, 1);
439 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_OP_FDI
);
440 poll_result
= poll_for_complete_op(nand
, "data input");
441 if (poll_result
!= ERROR_OK
)
444 target_write_u16(target
, MXC_NF_BUFADDR
, 2);
445 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_OP_FDI
);
446 poll_result
= poll_for_complete_op(nand
, "data input");
447 if (poll_result
!= ERROR_OK
)
450 target_write_u16(target
, MXC_NF_BUFADDR
, 3);
451 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_OP_FDI
);
452 poll_result
= poll_for_complete_op(nand
, "data input");
453 if (poll_result
!= ERROR_OK
)
456 retval
|= mxc_command(nand
, NAND_CMD_PAGEPROG
);
457 if (retval
!= ERROR_OK
)
461 * check status register
464 retval
|= mxc_command(nand
, NAND_CMD_STATUS
);
465 target_write_u16 (target
, MXC_NF_BUFADDR
, 0);
466 mxc_nf_info
->optype
= MXC_NF_DATAOUT_NANDSTATUS
;
467 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
468 retval
|= do_data_output(nand
);
469 if (retval
!= ERROR_OK
) {
470 LOG_ERROR(get_status_register_err_msg
);
473 target_read_u16(target
, MXC_NF_MAIN_BUFFER0
, &nand_status_content
);
474 if (nand_status_content
& 0x0001) {
476 * page not correctly written
478 return ERROR_NAND_OPERATION_FAILED
;
480 #ifdef _MXC_PRINT_STAT
481 LOG_INFO("%d bytes newly written", data_size
);
486 static int mxc_read_page(struct nand_device
*nand
, uint32_t page
,
487 uint8_t *data
, uint32_t data_size
,
488 uint8_t *oob
, uint32_t oob_size
)
490 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
491 struct target
*target
= nand
->target
;
493 uint16_t swap1
, swap2
, new_swap1
;
496 LOG_ERROR(data_block_size_err_msg
, data_size
);
497 return ERROR_NAND_OPERATION_FAILED
;
500 LOG_ERROR(data_block_size_err_msg
, oob_size
);
501 return ERROR_NAND_OPERATION_FAILED
;
505 * validate target state
507 retval
= validate_target_state(nand
);
508 if (retval
!= ERROR_OK
) {
511 /* Reset address_cycles before mxc_command ?? */
512 retval
= mxc_command(nand
, NAND_CMD_READ0
);
513 if (retval
!= ERROR_OK
) return retval
;
514 retval
= mxc_address(nand
, 0); /* col */
515 if (retval
!= ERROR_OK
) return retval
;
516 retval
= mxc_address(nand
, 0); /* col */
517 if (retval
!= ERROR_OK
) return retval
;
518 retval
= mxc_address(nand
, page
& 0xff); /* page address */
519 if (retval
!= ERROR_OK
) return retval
;
520 retval
= mxc_address(nand
, (page
>> 8) & 0xff); /* page address */
521 if (retval
!= ERROR_OK
) return retval
;
522 retval
= mxc_address(nand
, (page
>> 16) & 0xff); /* page address */
523 if (retval
!= ERROR_OK
) return retval
;
524 retval
= mxc_command(nand
, NAND_CMD_READSTART
);
525 if (retval
!= ERROR_OK
) return retval
;
527 target_write_u16(target
, MXC_NF_BUFADDR
, 0);
528 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
529 retval
= do_data_output(nand
);
530 if (retval
!= ERROR_OK
) {
531 LOG_ERROR("MXC_NF : Error reading page 0");
534 /* Test nand page size to know how much MAIN_BUFFER must be written */
535 target_write_u16(target
, MXC_NF_BUFADDR
, 1);
536 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
537 retval
= do_data_output(nand
);
538 if (retval
!= ERROR_OK
) {
539 LOG_ERROR("MXC_NF : Error reading page 1");
542 target_write_u16(target
, MXC_NF_BUFADDR
, 2);
543 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
544 retval
= do_data_output(nand
);
545 if (retval
!= ERROR_OK
) {
546 LOG_ERROR("MXC_NF : Error reading page 2");
549 target_write_u16(target
, MXC_NF_BUFADDR
, 3);
550 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
551 retval
= do_data_output(nand
);
552 if (retval
!= ERROR_OK
) {
553 LOG_ERROR("MXC_NF : Error reading page 3");
556 /* BI-swap - work-around of mxc NFC for NAND device with page == 2k */
557 target_read_u16(target
, MXC_NF_MAIN_BUFFER3
+ 464, &swap1
);
558 target_read_u16(target
, MXC_NF_SPARE_BUFFER3
+ 4, &swap2
);
559 new_swap1
= (swap1
& 0xFF00) | (swap2
>> 8);
560 swap2
= (swap1
<< 8) | (swap2
& 0xFF);
561 target_write_u16(target
, MXC_NF_MAIN_BUFFER3
+ 464, new_swap1
);
562 target_write_u16(target
, MXC_NF_SPARE_BUFFER3
+ 4, swap2
);
565 target_read_buffer(target
, MXC_NF_MAIN_BUFFER0
, data_size
, data
);
567 target_read_buffer(target
, MXC_NF_SPARE_BUFFER0
, oob_size
, oob
);
569 #ifdef _MXC_PRINT_STAT
571 /* When Operation Status is read (when page is erased),
572 * this function is used but data_size is null.
574 LOG_INFO("%d bytes newly read", data_size
);
580 static int initialize_nf_controller(struct nand_device
*nand
)
582 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
583 struct target
*target
= nand
->target
;
587 * resets NAND flash controller in zero time ? I dont know.
589 target_write_u16(target
, MXC_NF_CFG1
, MXC_NF_BIT_RESET_EN
);
590 work_mode
= MXC_NF_BIT_INT_DIS
; /* disable interrupt */
591 if (target
->endianness
== TARGET_BIG_ENDIAN
) {
592 LOG_DEBUG("MXC_NF : work in Big Endian mode");
593 work_mode
|= MXC_NF_BIT_BE_EN
;
595 LOG_DEBUG("MXC_NF : work in Little Endian mode");
597 if (mxc_nf_info
->flags
.hw_ecc_enabled
) {
598 LOG_DEBUG("MXC_NF : work with ECC mode");
599 work_mode
|= MXC_NF_BIT_ECC_EN
;
601 LOG_DEBUG("MXC_NF : work without ECC mode");
603 target_write_u16(target
, MXC_NF_CFG1
, work_mode
);
605 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
607 target_write_u16(target
, MXC_NF_BUFCFG
, 2);
608 target_read_u16(target
, MXC_NF_FWP
, &temp
);
609 if ((temp
& 0x0007) == 1) {
610 LOG_ERROR("NAND flash is tight-locked, reset needed");
615 * unlock NAND flash for write
617 target_write_u16(target
, MXC_NF_FWP
, 4);
618 target_write_u16(target
, MXC_NF_LOCKSTART
, 0x0000);
619 target_write_u16(target
, MXC_NF_LOCKEND
, 0xFFFF);
621 * 0x0000 means that first SRAM buffer @0xD800_0000 will be used
623 target_write_u16(target
, MXC_NF_BUFADDR
, 0x0000);
625 * address of SRAM buffer
627 in_sram_address
= MXC_NF_MAIN_BUFFER0
;
628 sign_of_sequental_byte_read
= 0;
632 static int get_next_byte_from_sram_buffer(struct nand_device
*nand
, uint8_t *value
)
634 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
635 struct target
*target
= nand
->target
;
636 static uint8_t even_byte
= 0;
641 if (sign_of_sequental_byte_read
== 0)
644 if (in_sram_address
> MXC_NF_LAST_BUFFER_ADDR
) {
645 LOG_ERROR(sram_buffer_bounds_err_msg
, in_sram_address
);
647 sign_of_sequental_byte_read
= 0;
649 return ERROR_NAND_OPERATION_FAILED
;
651 target_read_u16(target
, in_sram_address
, &temp
);
655 in_sram_address
+= 2;
657 *value
= temp
& 0xff;
661 sign_of_sequental_byte_read
= 1;
665 static int get_next_halfword_from_sram_buffer(struct nand_device
*nand
, uint16_t *value
)
667 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
668 struct target
*target
= nand
->target
;
670 if (in_sram_address
> MXC_NF_LAST_BUFFER_ADDR
) {
671 LOG_ERROR(sram_buffer_bounds_err_msg
, in_sram_address
);
673 return ERROR_NAND_OPERATION_FAILED
;
675 target_read_u16(target
, in_sram_address
, value
);
676 in_sram_address
+= 2;
681 static int poll_for_complete_op(struct nand_device
*nand
, const char *text
)
683 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
684 struct target
*target
= nand
->target
;
685 uint16_t poll_complete_status
;
687 for (int poll_cycle_count
= 0; poll_cycle_count
< 100; poll_cycle_count
++) {
688 target_read_u16(target
, MXC_NF_CFG2
, &poll_complete_status
);
689 if (poll_complete_status
& MXC_NF_BIT_OP_DONE
)
694 if (!(poll_complete_status
& MXC_NF_BIT_OP_DONE
)) {
695 LOG_ERROR("%s sending timeout", text
);
696 return ERROR_NAND_OPERATION_FAILED
;
701 static int validate_target_state(struct nand_device
*nand
)
703 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
704 struct target
*target
= nand
->target
;
706 if (target
->state
!= TARGET_HALTED
) {
707 LOG_ERROR(target_not_halted_err_msg
);
708 return ERROR_NAND_OPERATION_FAILED
;
711 if (mxc_nf_info
->flags
.target_little_endian
!=
712 (target
->endianness
== TARGET_LITTLE_ENDIAN
)) {
714 * endianness changed after NAND controller probed
716 return ERROR_NAND_OPERATION_FAILED
;
721 static int do_data_output(struct nand_device
*nand
)
723 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
724 struct target
*target
= nand
->target
;
727 switch (mxc_nf_info
->fin
) {
728 case MXC_NF_FIN_DATAOUT
:
730 * start data output operation (set MXC_NF_BIT_OP_DONE==0)
732 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info
->optype
));
733 poll_result
= poll_for_complete_op(nand
, "data output");
734 if (poll_result
!= ERROR_OK
)
737 mxc_nf_info
->fin
= MXC_NF_FIN_NONE
;
741 if ((mxc_nf_info
->optype
== MXC_NF_DATAOUT_PAGE
) &&
742 mxc_nf_info
->flags
.hw_ecc_enabled
) {
743 target_read_u16(target
, MXC_NF_ECCSTATUS
, &ecc_status
);
744 switch (ecc_status
& 0x000c) {
746 LOG_INFO("main area readed with 1 (correctable) error");
749 LOG_INFO("main area readed with more than 1 (incorrectable) error");
750 return ERROR_NAND_OPERATION_FAILED
;
753 switch (ecc_status
& 0x0003) {
755 LOG_INFO("spare area readed with 1 (correctable) error");
758 LOG_INFO("main area readed with more than 1 (incorrectable) error");
759 return ERROR_NAND_OPERATION_FAILED
;
764 case MXC_NF_FIN_NONE
:
770 struct nand_flash_controller mxc_nand_flash_controller
= {
772 .nand_device_command
= &mxc_nand_device_command
,
775 .command
= &mxc_command
,
776 .address
= &mxc_address
,
777 .write_data
= &mxc_write_data
,
778 .read_data
= &mxc_read_data
,
779 .write_page
= &mxc_write_page
,
780 .read_page
= &mxc_read_page
,
781 .nand_ready
= &mxc_nand_ready
,
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