1 /***************************************************************************
2 * Copyright (C) 2009 by Alexei Babich *
3 * Rezonans plc., Chelyabinsk, Russia *
6 * Copyright (C) 2010 by Gaetan CARLIER *
7 * Trump s.a., Belgium *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
26 * Freescale iMX2* OpenOCD NAND Flash controller support.
27 * based on Freescale iMX3* OpenOCD NAND Flash controller support.
31 * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @imx27
32 * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
33 * "nand write # file 0", "nand verify"
35 * get_next_halfword_from_sram_buffer() not tested
36 * !! all function only tested with 2k page nand device; imx27_write_page
37 * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
38 * !! oob must be be used due to NFS bug
46 #include <target/target.h>
48 /* This permits to print (in LOG_INFO) how much bytes
49 * has been written after a page read or write.
50 * This is useful when OpenOCD is used with a graphical
51 * front-end to estimate progression of the global read/write
53 #undef _MX2_PRINT_STAT
54 //#define _MX2_PRINT_STAT
56 static const char target_not_halted_err_msg
[] =
57 "target must be halted to use mx2 NAND flash controller";
58 static const char data_block_size_err_msg
[] =
59 "minimal granularity is one half-word, %" PRId32
" is incorrect";
60 static const char sram_buffer_bounds_err_msg
[] =
61 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32
")";
62 static const char get_status_register_err_msg
[] = "can't get NAND status";
63 static uint32_t in_sram_address
;
64 static unsigned char sign_of_sequental_byte_read
;
66 static int initialize_nf_controller(struct nand_device
*nand
);
67 static int get_next_byte_from_sram_buffer(struct target
* target
, uint8_t * value
);
68 static int get_next_halfword_from_sram_buffer(struct target
* target
,
70 static int poll_for_complete_op(struct target
* target
, const char *text
);
71 static int validate_target_state(struct nand_device
*nand
);
72 static int do_data_output(struct nand_device
*nand
);
74 static int imx27_command(struct nand_device
*nand
, uint8_t command
);
75 static int imx27_address(struct nand_device
*nand
, uint8_t address
);
77 NAND_DEVICE_COMMAND_HANDLER(imx27_nand_device_command
)
79 struct mx2_nf_controller
*mx2_nf_info
;
82 mx2_nf_info
= malloc(sizeof(struct mx2_nf_controller
));
83 if (mx2_nf_info
== NULL
) {
84 LOG_ERROR("no memory for nand controller");
88 nand
->controller_priv
= mx2_nf_info
;
89 mx2_nf_info
->target
= get_target(CMD_ARGV
[1]);
90 if (mx2_nf_info
->target
== NULL
) {
91 LOG_ERROR("target '%s' not defined", CMD_ARGV
[1]);
95 LOG_ERROR("use \"nand device imx27 target noecc|hwecc\"");
99 * check hwecc requirements
102 hwecc_needed
= strcmp(CMD_ARGV
[2], "hwecc");
103 if (hwecc_needed
== 0)
104 mx2_nf_info
->flags
.hw_ecc_enabled
= 1;
106 mx2_nf_info
->flags
.hw_ecc_enabled
= 0;
108 mx2_nf_info
->optype
= MX2_NF_DATAOUT_PAGE
;
109 mx2_nf_info
->fin
= MX2_NF_FIN_NONE
;
110 mx2_nf_info
->flags
.target_little_endian
=
111 (mx2_nf_info
->target
->endianness
== TARGET_LITTLE_ENDIAN
);
113 * testing host endianess
116 if (*(char *) &x
== 1)
117 mx2_nf_info
->flags
.host_little_endian
= 1;
119 mx2_nf_info
->flags
.host_little_endian
= 0;
123 static int imx27_init(struct nand_device
*nand
)
125 struct mx2_nf_controller
*mx2_nf_info
= nand
->controller_priv
;
126 struct target
*target
= mx2_nf_info
->target
;
128 int validate_target_result
;
129 uint16_t buffsize_register_content
;
130 uint32_t pcsr_register_content
;
132 uint16_t nand_status_content
;
134 * validate target state
136 validate_target_result
= validate_target_state(nand
);
137 if (validate_target_result
!= ERROR_OK
)
138 return validate_target_result
;
140 target_read_u16(target
, MX2_NF_BUFSIZ
, &buffsize_register_content
);
141 mx2_nf_info
->flags
.one_kb_sram
= !(buffsize_register_content
& 0x000f);
143 target_read_u32(target
, MX2_FMCR
, &pcsr_register_content
);
144 if (!nand
->bus_width
) {
145 /* bus_width not yet defined. Read it from MX2_FMCR */
147 (pcsr_register_content
& MX2_FMCR_NF_16BIT_SEL
) ? 16 : 8;
149 /* bus_width forced in soft. Sync it to MX2_FMCR */
150 pcsr_register_content
|=
151 ((nand
->bus_width
== 16) ? MX2_FMCR_NF_16BIT_SEL
: 0x00000000);
152 target_write_u32(target
, MX2_FMCR
, pcsr_register_content
);
154 if (nand
->bus_width
== 16)
155 LOG_DEBUG("MX2_NF : bus is 16-bit width");
157 LOG_DEBUG("MX2_NF : bus is 8-bit width");
159 if (!nand
->page_size
) {
161 (pcsr_register_content
& MX2_FMCR_NF_FMS
) ? 2048 : 512;
163 pcsr_register_content
|=
164 ((nand
->page_size
== 2048) ? MX2_FMCR_NF_FMS
: 0x00000000);
165 target_write_u32(target
, MX2_FMCR
, pcsr_register_content
);
167 if (mx2_nf_info
->flags
.one_kb_sram
&& (nand
->page_size
== 2048)) {
168 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
169 "pagesize 2048 is incompatible with it");
171 LOG_DEBUG("MX2_NF : NAND controller can handle pagesize of 2048");
174 initialize_nf_controller(nand
);
177 retval
|= imx27_command(nand
, NAND_CMD_STATUS
);
178 retval
|= imx27_address(nand
, 0x00);
179 retval
|= do_data_output(nand
);
180 if (retval
!= ERROR_OK
) {
181 LOG_ERROR(get_status_register_err_msg
);
184 target_read_u16(target
, MX2_NF_MAIN_BUFFER0
, &nand_status_content
);
185 if (!(nand_status_content
& 0x0080)) {
186 LOG_INFO("NAND read-only");
187 mx2_nf_info
->flags
.nand_readonly
= 1;
189 mx2_nf_info
->flags
.nand_readonly
= 0;
194 static int imx27_read_data(struct nand_device
*nand
, void *data
)
196 struct mx2_nf_controller
*mx2_nf_info
= nand
->controller_priv
;
197 struct target
*target
= mx2_nf_info
->target
;
198 int validate_target_result
;
199 int try_data_output_from_nand_chip
;
201 * validate target state
203 validate_target_result
= validate_target_state(nand
);
204 if (validate_target_result
!= ERROR_OK
)
205 return validate_target_result
;
208 * get data from nand chip
210 try_data_output_from_nand_chip
= do_data_output(nand
);
211 if (try_data_output_from_nand_chip
!= ERROR_OK
) {
212 LOG_ERROR("imx27_read_data : read data failed : '%x'",
213 try_data_output_from_nand_chip
);
214 return try_data_output_from_nand_chip
;
217 if (nand
->bus_width
== 16)
218 get_next_halfword_from_sram_buffer(target
, data
);
220 get_next_byte_from_sram_buffer(target
, data
);
225 static int imx27_write_data(struct nand_device
*nand
, uint16_t data
)
227 LOG_ERROR("write_data() not implemented");
228 return ERROR_NAND_OPERATION_FAILED
;
231 static int imx27_reset(struct nand_device
*nand
)
234 * validate target state
236 int validate_target_result
;
237 validate_target_result
= validate_target_state(nand
);
238 if (validate_target_result
!= ERROR_OK
)
239 return validate_target_result
;
240 initialize_nf_controller(nand
);
244 static int imx27_command(struct nand_device
*nand
, uint8_t command
)
246 struct mx2_nf_controller
*mx2_nf_info
= nand
->controller_priv
;
247 struct target
*target
= mx2_nf_info
->target
;
248 int validate_target_result
;
251 * validate target state
253 validate_target_result
= validate_target_state(nand
);
254 if (validate_target_result
!= ERROR_OK
)
255 return validate_target_result
;
258 case NAND_CMD_READOOB
:
259 command
= NAND_CMD_READ0
;
260 /* set read point for data_read() and read_block_data() to
261 * spare area in SRAM buffer
263 in_sram_address
= MX2_NF_SPARE_BUFFER0
;
266 command
= NAND_CMD_READ0
;
268 * offset == one half of page size
271 MX2_NF_MAIN_BUFFER0
+ (nand
->page_size
>> 1);
274 in_sram_address
= MX2_NF_MAIN_BUFFER0
;
278 target_write_u16(target
, MX2_NF_FCMD
, command
);
280 * start command input operation (set MX2_NF_BIT_OP_DONE==0)
282 target_write_u16(target
, MX2_NF_CFG2
, MX2_NF_BIT_OP_FCI
);
283 poll_result
= poll_for_complete_op(target
, "command");
284 if (poll_result
!= ERROR_OK
)
287 * reset cursor to begin of the buffer
289 sign_of_sequental_byte_read
= 0;
290 /* Handle special read command and adjust NF_CFG2(FDO) */
292 case NAND_CMD_READID
:
293 mx2_nf_info
->optype
= MX2_NF_DATAOUT_NANDID
;
294 mx2_nf_info
->fin
= MX2_NF_FIN_DATAOUT
;
296 case NAND_CMD_STATUS
:
297 mx2_nf_info
->optype
= MX2_NF_DATAOUT_NANDSTATUS
;
298 mx2_nf_info
->fin
= MX2_NF_FIN_DATAOUT
;
299 target_write_u16 (target
, MX2_NF_BUFADDR
, 0);
303 mx2_nf_info
->fin
= MX2_NF_FIN_DATAOUT
;
304 mx2_nf_info
->optype
= MX2_NF_DATAOUT_PAGE
;
307 /* Ohter command use the default 'One page data out' FDO */
308 mx2_nf_info
->optype
= MX2_NF_DATAOUT_PAGE
;
314 static int imx27_address(struct nand_device
*nand
, uint8_t address
)
316 struct mx2_nf_controller
*mx2_nf_info
= nand
->controller_priv
;
317 struct target
*target
= mx2_nf_info
->target
;
318 int validate_target_result
;
321 * validate target state
323 validate_target_result
= validate_target_state(nand
);
324 if (validate_target_result
!= ERROR_OK
)
325 return validate_target_result
;
327 target_write_u16(target
, MX2_NF_FADDR
, address
);
329 * start address input operation (set MX2_NF_BIT_OP_DONE==0)
331 target_write_u16(target
, MX2_NF_CFG2
, MX2_NF_BIT_OP_FAI
);
332 poll_result
= poll_for_complete_op(target
, "address");
333 if (poll_result
!= ERROR_OK
)
339 static int imx27_nand_ready(struct nand_device
*nand
, int tout
)
341 uint16_t poll_complete_status
;
342 struct mx2_nf_controller
*mx2_nf_info
= nand
->controller_priv
;
343 struct target
*target
= mx2_nf_info
->target
;
344 int validate_target_result
;
347 * validate target state
349 validate_target_result
= validate_target_state(nand
);
350 if (validate_target_result
!= ERROR_OK
)
351 return validate_target_result
;
354 target_read_u16(target
, MX2_NF_CFG2
, &poll_complete_status
);
355 if (poll_complete_status
& MX2_NF_BIT_OP_DONE
)
364 static int imx27_write_page(struct nand_device
*nand
, uint32_t page
,
365 uint8_t * data
, uint32_t data_size
, uint8_t * oob
,
368 struct mx2_nf_controller
*mx2_nf_info
= nand
->controller_priv
;
369 struct target
*target
= mx2_nf_info
->target
;
371 uint16_t nand_status_content
;
372 uint16_t swap1
, swap2
, new_swap1
;
375 LOG_ERROR(data_block_size_err_msg
, data_size
);
376 return ERROR_NAND_OPERATION_FAILED
;
379 LOG_ERROR(data_block_size_err_msg
, oob_size
);
380 return ERROR_NAND_OPERATION_FAILED
;
383 LOG_ERROR("nothing to program");
384 return ERROR_NAND_OPERATION_FAILED
;
387 * validate target state
389 retval
= validate_target_state(nand
);
390 if (retval
!= ERROR_OK
)
393 in_sram_address
= MX2_NF_MAIN_BUFFER0
;
394 sign_of_sequental_byte_read
= 0;
396 retval
|= imx27_command(nand
, NAND_CMD_SEQIN
);
397 retval
|= imx27_address(nand
, 0); //col
398 retval
|= imx27_address(nand
, 0); //col
399 retval
|= imx27_address(nand
, page
& 0xff); //page address
400 retval
|= imx27_address(nand
, (page
>> 8) & 0xff); //page address
401 retval
|= imx27_address(nand
, (page
>> 16) & 0xff); //page address
403 target_write_buffer(target
, MX2_NF_MAIN_BUFFER0
, data_size
, data
);
405 if (mx2_nf_info
->flags
.hw_ecc_enabled
) {
407 * part of spare block will be overrided by hardware
410 LOG_DEBUG("part of spare block will be overrided "
411 "by hardware ECC generator");
413 target_write_buffer(target
, MX2_NF_SPARE_BUFFER0
, oob_size
,
416 //BI-swap - work-around of imx27 NFC for NAND device with page == 2kb
417 target_read_u16(target
, MX2_NF_MAIN_BUFFER3
+ 464, &swap1
);
419 LOG_ERROR("Due to NFC Bug, oob is not correctly implemented "
421 return ERROR_NAND_OPERATION_FAILED
;
423 //target_read_u16 (target, MX2_NF_SPARE_BUFFER3 + 4, &swap2);
424 swap2
= 0xffff; //Spare buffer unused forced to 0xffff
425 new_swap1
= (swap1
& 0xFF00) | (swap2
>> 8);
426 swap2
= (swap1
<< 8) | (swap2
& 0xFF);
428 target_write_u16(target
, MX2_NF_MAIN_BUFFER3
+ 464, new_swap1
);
429 target_write_u16(target
, MX2_NF_SPARE_BUFFER3
+ 4, swap2
);
431 * start data input operation (set MX2_NF_BIT_OP_DONE==0)
433 target_write_u16(target
, MX2_NF_BUFADDR
, 0);
434 target_write_u16(target
, MX2_NF_CFG2
, MX2_NF_BIT_OP_FDI
);
435 poll_result
= poll_for_complete_op(target
, "data input");
436 if (poll_result
!= ERROR_OK
)
439 target_write_u16(target
, MX2_NF_BUFADDR
, 1);
440 target_write_u16(target
, MX2_NF_CFG2
, MX2_NF_BIT_OP_FDI
);
441 poll_result
= poll_for_complete_op(target
, "data input");
442 if (poll_result
!= ERROR_OK
)
445 target_write_u16(target
, MX2_NF_BUFADDR
, 2);
446 target_write_u16(target
, MX2_NF_CFG2
, MX2_NF_BIT_OP_FDI
);
447 poll_result
= poll_for_complete_op(target
, "data input");
448 if (poll_result
!= ERROR_OK
)
451 target_write_u16(target
, MX2_NF_BUFADDR
, 3);
452 target_write_u16(target
, MX2_NF_CFG2
, MX2_NF_BIT_OP_FDI
);
453 poll_result
= poll_for_complete_op(target
, "data input");
454 if (poll_result
!= ERROR_OK
)
457 retval
|= imx27_command(nand
, NAND_CMD_PAGEPROG
);
458 if (retval
!= ERROR_OK
)
462 * check status register
465 retval
|= imx27_command(nand
, NAND_CMD_STATUS
);
466 target_write_u16 (target
, MX2_NF_BUFADDR
, 0);
467 mx2_nf_info
->optype
= MX2_NF_DATAOUT_NANDSTATUS
;
468 mx2_nf_info
->fin
= MX2_NF_FIN_DATAOUT
;
469 retval
|= do_data_output(nand
);
470 if (retval
!= ERROR_OK
) {
471 LOG_ERROR (get_status_register_err_msg
);
474 target_read_u16 (target
, MX2_NF_MAIN_BUFFER0
, &nand_status_content
);
475 if (nand_status_content
& 0x0001) {
477 * page not correctly written
479 return ERROR_NAND_OPERATION_FAILED
;
481 #ifdef _MX2_PRINT_STAT
482 LOG_INFO("%d bytes newly written", data_size
);
487 static int imx27_read_page(struct nand_device
*nand
, uint32_t page
,
488 uint8_t * data
, uint32_t data_size
, uint8_t * oob
,
491 struct mx2_nf_controller
*mx2_nf_info
= nand
->controller_priv
;
492 struct target
*target
= mx2_nf_info
->target
;
494 uint16_t swap1
, swap2
, new_swap1
;
496 LOG_ERROR(data_block_size_err_msg
, data_size
);
497 return ERROR_NAND_OPERATION_FAILED
;
500 LOG_ERROR(data_block_size_err_msg
, oob_size
);
501 return ERROR_NAND_OPERATION_FAILED
;
505 * validate target state
507 retval
= validate_target_state(nand
);
508 if (retval
!= ERROR_OK
) {
511 /* Reset address_cycles before imx27_command ?? */
513 retval
|= imx27_command(nand
, NAND_CMD_READ0
);
515 retval
|= imx27_address(nand
, 0); //col
516 retval
|= imx27_address(nand
, 0); //col
517 retval
|= imx27_address(nand
, page
& 0xff); //page address
518 retval
|= imx27_address(nand
, (page
>> 8) & 0xff); //page address
519 retval
|= imx27_address(nand
, (page
>> 16) & 0xff); //page address
520 retval
|= imx27_command(nand
, NAND_CMD_READSTART
);
522 target_write_u16(target
, MX2_NF_BUFADDR
, 0);
523 mx2_nf_info
->fin
= MX2_NF_FIN_DATAOUT
;
524 retval
= do_data_output(nand
);
525 if (retval
!= ERROR_OK
) {
526 LOG_ERROR("MX2_NF : Error reading page 0");
529 //Test nand page size to know how much MAIN_BUFFER must be written
530 target_write_u16(target
, MX2_NF_BUFADDR
, 1);
531 mx2_nf_info
->fin
= MX2_NF_FIN_DATAOUT
;
532 retval
= do_data_output(nand
);
533 if (retval
!= ERROR_OK
) {
534 LOG_ERROR("MX2_NF : Error reading page 1");
537 target_write_u16(target
, MX2_NF_BUFADDR
, 2);
538 mx2_nf_info
->fin
= MX2_NF_FIN_DATAOUT
;
539 retval
= do_data_output(nand
);
540 if (retval
!= ERROR_OK
) {
541 LOG_ERROR("MX2_NF : Error reading page 2");
544 target_write_u16(target
, MX2_NF_BUFADDR
, 3);
545 mx2_nf_info
->fin
= MX2_NF_FIN_DATAOUT
;
546 retval
= do_data_output(nand
);
547 if (retval
!= ERROR_OK
) {
548 LOG_ERROR("MX2_NF : Error reading page 3");
551 //BI-swap - work-around of imx27 NFC for NAND device with page == 2k
552 target_read_u16(target
, MX2_NF_MAIN_BUFFER3
+ 464, &swap1
);
553 target_read_u16(target
, MX2_NF_SPARE_BUFFER3
+ 4, &swap2
);
554 new_swap1
= (swap1
& 0xFF00) | (swap2
>> 8);
555 swap2
= (swap1
<< 8) | (swap2
& 0xFF);
556 target_write_u16(target
, MX2_NF_MAIN_BUFFER3
+ 464, new_swap1
);
557 target_write_u16(target
, MX2_NF_SPARE_BUFFER3
+ 4, swap2
);
560 target_read_buffer(target
, MX2_NF_MAIN_BUFFER0
, data_size
, data
);
562 target_read_buffer(target
, MX2_NF_SPARE_BUFFER0
, oob_size
,
564 #ifdef _MX2_PRINT_STAT
566 /* When Operation Status is read (when page is erased),
567 * this function is used but data_size is null.
569 LOG_INFO("%d bytes newly read", data_size
);
575 static int initialize_nf_controller(struct nand_device
*nand
)
577 struct mx2_nf_controller
*mx2_nf_info
= nand
->controller_priv
;
578 struct target
*target
= mx2_nf_info
->target
;
582 * resets NAND flash controller in zero time ? I dont know.
584 target_write_u16(target
, MX2_NF_CFG1
, MX2_NF_BIT_RESET_EN
);
585 work_mode
= MX2_NF_BIT_INT_DIS
; /* disable interrupt */
586 if (target
->endianness
== TARGET_BIG_ENDIAN
) {
587 LOG_DEBUG("MX2_NF : work in Big Endian mode");
588 work_mode
|= MX2_NF_BIT_BE_EN
;
590 LOG_DEBUG("MX2_NF : work in Little Endian mode");
592 if (mx2_nf_info
->flags
.hw_ecc_enabled
) {
593 LOG_DEBUG("MX2_NF : work with ECC mode");
594 work_mode
|= MX2_NF_BIT_ECC_EN
;
596 LOG_DEBUG("MX2_NF : work without ECC mode");
598 target_write_u16(target
, MX2_NF_CFG1
, work_mode
);
600 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
602 target_write_u16(target
, MX2_NF_BUFCFG
, 2);
603 target_read_u16(target
, MX2_NF_FWP
, &temp
);
604 if ((temp
& 0x0007) == 1) {
605 LOG_ERROR("NAND flash is tight-locked, reset needed");
610 * unlock NAND flash for write
612 target_write_u16(target
, MX2_NF_FWP
, 4);
613 target_write_u16(target
, MX2_NF_LOCKSTART
, 0x0000);
614 target_write_u16(target
, MX2_NF_LOCKEND
, 0xFFFF);
616 * 0x0000 means that first SRAM buffer @0xD800_0000 will be used
618 target_write_u16(target
, MX2_NF_BUFADDR
, 0x0000);
620 * address of SRAM buffer
622 in_sram_address
= MX2_NF_MAIN_BUFFER0
;
623 sign_of_sequental_byte_read
= 0;
627 static int get_next_byte_from_sram_buffer(struct target
* target
, uint8_t * value
)
629 static uint8_t even_byte
= 0;
634 if (sign_of_sequental_byte_read
== 0)
637 if (in_sram_address
> MX2_NF_LAST_BUFFER_ADDR
) {
638 LOG_ERROR(sram_buffer_bounds_err_msg
, in_sram_address
);
640 sign_of_sequental_byte_read
= 0;
642 return ERROR_NAND_OPERATION_FAILED
;
644 target_read_u16(target
, in_sram_address
, &temp
);
648 in_sram_address
+= 2;
650 *value
= temp
& 0xff;
654 sign_of_sequental_byte_read
= 1;
658 static int get_next_halfword_from_sram_buffer(struct target
* target
,
661 if (in_sram_address
> MX2_NF_LAST_BUFFER_ADDR
) {
662 LOG_ERROR(sram_buffer_bounds_err_msg
, in_sram_address
);
664 return ERROR_NAND_OPERATION_FAILED
;
666 target_read_u16(target
, in_sram_address
, value
);
667 in_sram_address
+= 2;
672 static int poll_for_complete_op(struct target
* target
, const char *text
)
674 uint16_t poll_complete_status
;
675 for (int poll_cycle_count
= 0; poll_cycle_count
< 100; poll_cycle_count
++) {
676 target_read_u16(target
, MX2_NF_CFG2
, &poll_complete_status
);
677 if (poll_complete_status
& MX2_NF_BIT_OP_DONE
)
682 if (!(poll_complete_status
& MX2_NF_BIT_OP_DONE
)) {
683 LOG_ERROR("%s sending timeout", text
);
684 return ERROR_NAND_OPERATION_FAILED
;
689 static int validate_target_state(struct nand_device
*nand
)
691 struct mx2_nf_controller
*mx2_nf_info
= nand
->controller_priv
;
692 struct target
*target
= mx2_nf_info
->target
;
694 if (target
->state
!= TARGET_HALTED
) {
695 LOG_ERROR(target_not_halted_err_msg
);
696 return ERROR_NAND_OPERATION_FAILED
;
699 if (mx2_nf_info
->flags
.target_little_endian
!=
700 (target
->endianness
== TARGET_LITTLE_ENDIAN
)) {
702 * endianness changed after NAND controller probed
704 return ERROR_NAND_OPERATION_FAILED
;
709 static int do_data_output(struct nand_device
*nand
)
711 struct mx2_nf_controller
*mx2_nf_info
= nand
->controller_priv
;
712 struct target
*target
= mx2_nf_info
->target
;
715 switch(mx2_nf_info
->fin
) {
716 case MX2_NF_FIN_DATAOUT
:
718 * start data output operation (set MX2_NF_BIT_OP_DONE==0)
720 target_write_u16(target
, MX2_NF_CFG2
, MX2_NF_BIT_DATAOUT_TYPE(mx2_nf_info
->optype
));
721 poll_result
= poll_for_complete_op(target
, "data output");
722 if (poll_result
!= ERROR_OK
)
725 mx2_nf_info
->fin
= MX2_NF_FIN_NONE
;
729 if ((mx2_nf_info
->optype
== MX2_NF_DATAOUT_PAGE
) && mx2_nf_info
->flags
.hw_ecc_enabled
) {
730 target_read_u16(target
, MX2_NF_ECCSTATUS
, &ecc_status
);
731 switch(ecc_status
& 0x000c) {
733 LOG_INFO("main area readed with 1 (correctable) error");
736 LOG_INFO("main area readed with more than 1 (incorrectable) error");
737 return ERROR_NAND_OPERATION_FAILED
;
740 switch(ecc_status
& 0x0003) {
742 LOG_INFO("spare area readed with 1 (correctable) error");
745 LOG_INFO("main area readed with more than 1 (incorrectable) error");
746 return ERROR_NAND_OPERATION_FAILED
;
751 case MX2_NF_FIN_NONE
:
757 struct nand_flash_controller imx27_nand_flash_controller
= {
759 .nand_device_command
= &imx27_nand_device_command
,
761 .reset
= &imx27_reset
,
762 .command
= &imx27_command
,
763 .address
= &imx27_address
,
764 .write_data
= &imx27_write_data
,
765 .read_data
= &imx27_read_data
,
766 .write_page
= &imx27_write_page
,
767 .read_page
= &imx27_read_page
,
768 .nand_ready
= &imx27_nand_ready
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)