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update files to correct FSF address
[openocd.git] / src / flash / nand / lpc32xx.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2011 Bjarne Steinsbo <bsteinsbo@gmail.com> *
6 * Copyright (C) 2010 richard vegh <vegh.ricsi@gmail.com> *
7 * Copyright (C) 2010 Oyvind Harboe <oyvind.harboe@zylin.com> *
8 * *
9 * Based on a combination of the lpc3180 driver and code from *
10 * uboot-2009.03-lpc32xx by Kevin Wells. *
11 * Any bugs are mine. --BSt *
12 * *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
17 * *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
22 * *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
27 ***************************************************************************/
28
29 #ifdef HAVE_CONFIG_H
30 #include "config.h"
31 #endif
32
33 #include "imp.h"
34 #include "lpc32xx.h"
35 #include <target/target.h>
36
37 static int lpc32xx_reset(struct nand_device *nand);
38 static int lpc32xx_controller_ready(struct nand_device *nand, int timeout);
39 static int lpc32xx_tc_ready(struct nand_device *nand, int timeout);
40 extern int nand_correct_data(struct nand_device *nand, u_char *dat,
41 u_char *read_ecc, u_char *calc_ecc);
42
43 /* These are offset with the working area in IRAM when using DMA to
44 * read/write data to the SLC controller.
45 * - DMA descriptors will be put at start of working area,
46 * - Hardware generated ECC will be stored at ECC_OFFS
47 * - OOB wil be read/written from/to SPARE_OFFS
48 * - Actual page data will be read from/to DATA_OFFS
49 * There are unused holes between the used areas.
50 */
51 #define ECC_OFFS 0x120
52 #define SPARE_OFFS 0x140
53 #define DATA_OFFS 0x200
54
55 static int sp_ooblayout[] = {
56 10, 11, 12, 13, 14, 15
57 };
58 static int lp_ooblayout[] = {
59 40, 41, 42, 43, 44, 45,
60 46, 47, 48, 49, 50, 51,
61 52, 53, 54, 55, 56, 57,
62 58, 59, 60, 61, 62, 63
63 };
64
65 typedef struct {
66 volatile uint32_t dma_src;
67 volatile uint32_t dma_dest;
68 volatile uint32_t next_lli;
69 volatile uint32_t next_ctrl;
70 } dmac_ll_t;
71
72 static dmac_ll_t dmalist[(2048/256) * 2 + 1];
73
74 /* nand device lpc32xx <target#> <oscillator_frequency>
75 */
76 NAND_DEVICE_COMMAND_HANDLER(lpc32xx_nand_device_command)
77 {
78 if (CMD_ARGC < 3)
79 return ERROR_COMMAND_SYNTAX_ERROR;
80
81 uint32_t osc_freq;
82 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], osc_freq);
83
84 struct lpc32xx_nand_controller *lpc32xx_info;
85 lpc32xx_info = malloc(sizeof(struct lpc32xx_nand_controller));
86 nand->controller_priv = lpc32xx_info;
87
88 lpc32xx_info->osc_freq = osc_freq;
89
90 if ((lpc32xx_info->osc_freq < 1000) || (lpc32xx_info->osc_freq > 20000))
91 LOG_WARNING("LPC32xx oscillator frequency should be between "
92 "1000 and 20000 kHz, was %i",
93 lpc32xx_info->osc_freq);
94
95 lpc32xx_info->selected_controller = LPC32xx_NO_CONTROLLER;
96 lpc32xx_info->sw_write_protection = 0;
97 lpc32xx_info->sw_wp_lower_bound = 0x0;
98 lpc32xx_info->sw_wp_upper_bound = 0x0;
99
100 return ERROR_OK;
101 }
102
103 static int lpc32xx_pll(int fclkin, uint32_t pll_ctrl)
104 {
105 int bypass = (pll_ctrl & 0x8000) >> 15;
106 int direct = (pll_ctrl & 0x4000) >> 14;
107 int feedback = (pll_ctrl & 0x2000) >> 13;
108 int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
109 int n = ((pll_ctrl & 0x0600) >> 9) + 1;
110 int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
111 int lock = (pll_ctrl & 0x1);
112
113 if (!lock)
114 LOG_WARNING("PLL is not locked");
115
116 if (!bypass && direct) /* direct mode */
117 return (m * fclkin) / n;
118
119 if (bypass && !direct) /* bypass mode */
120 return fclkin / (2 * p);
121
122 if (bypass & direct) /* direct bypass mode */
123 return fclkin;
124
125 if (feedback) /* integer mode */
126 return m * (fclkin / n);
127 else /* non-integer mode */
128 return (m / (2 * p)) * (fclkin / n);
129 }
130
131 static float lpc32xx_cycle_time(struct nand_device *nand)
132 {
133 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
134 struct target *target = nand->target;
135 uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
136 int sysclk;
137 int hclk;
138 int hclk_pll;
139 float cycle;
140 int retval;
141
142 /* calculate timings */
143
144 /* determine current SYSCLK (13'MHz or main oscillator) */
145 retval = target_read_u32(target, 0x40004050, &sysclk_ctrl);
146 if (ERROR_OK != retval) {
147 LOG_ERROR("could not read SYSCLK_CTRL");
148 return ERROR_NAND_OPERATION_FAILED;
149 }
150
151 if ((sysclk_ctrl & 1) == 0)
152 sysclk = lpc32xx_info->osc_freq;
153 else
154 sysclk = 13000;
155
156 /* determine selected HCLK source */
157 retval = target_read_u32(target, 0x40004044, &pwr_ctrl);
158 if (ERROR_OK != retval) {
159 LOG_ERROR("could not read HCLK_CTRL");
160 return ERROR_NAND_OPERATION_FAILED;
161 }
162
163 if ((pwr_ctrl & (1 << 2)) == 0) /* DIRECT RUN mode */
164 hclk = sysclk;
165 else {
166 retval = target_read_u32(target, 0x40004058, &hclkpll_ctrl);
167 if (ERROR_OK != retval) {
168 LOG_ERROR("could not read HCLKPLL_CTRL");
169 return ERROR_NAND_OPERATION_FAILED;
170 }
171 hclk_pll = lpc32xx_pll(sysclk, hclkpll_ctrl);
172
173 retval = target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
174 if (ERROR_OK != retval) {
175 LOG_ERROR("could not read CLKDIV_CTRL");
176 return ERROR_NAND_OPERATION_FAILED;
177 }
178
179 if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
180 hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
181 else /* HCLK uses HCLK_PLL */
182 hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
183 }
184
185 LOG_DEBUG("LPC32xx HCLK currently clocked at %i kHz", hclk);
186
187 cycle = (1.0 / hclk) * 1000000.0;
188
189 return cycle;
190 }
191
192 static int lpc32xx_init(struct nand_device *nand)
193 {
194 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
195 struct target *target = nand->target;
196 int bus_width = nand->bus_width ? : 8;
197 int address_cycles = nand->address_cycles ? : 3;
198 int page_size = nand->page_size ? : 512;
199 int retval;
200
201 if (target->state != TARGET_HALTED) {
202 LOG_ERROR("target must be halted to use LPC32xx "
203 "NAND flash controller");
204 return ERROR_NAND_OPERATION_FAILED;
205 }
206
207 /* sanitize arguments */
208 if (bus_width != 8) {
209 LOG_ERROR("LPC32xx doesn't support %i", bus_width);
210 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
211 }
212
213 /* inform calling code about selected bus width */
214 nand->bus_width = bus_width;
215
216 if ((address_cycles < 3) || (address_cycles > 5)) {
217 LOG_ERROR("LPC32xx driver doesn't support %i address cycles", address_cycles);
218 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
219 }
220
221 if ((page_size != 512) && (page_size != 2048)) {
222 LOG_ERROR("LPC32xx doesn't support page size %i", page_size);
223 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
224 }
225
226 /* select MLC controller if none is currently selected */
227 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
228 LOG_DEBUG("no LPC32xx NAND flash controller selected, "
229 "using default 'slc'");
230 lpc32xx_info->selected_controller = LPC32xx_SLC_CONTROLLER;
231 }
232
233 if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
234 uint32_t mlc_icr_value = 0x0;
235 float cycle;
236 int twp, twh, trp, treh, trhz, trbwb, tcea;
237
238 /* FLASHCLK_CTRL = 0x22 (enable clk for MLC) */
239 retval = target_write_u32(target, 0x400040c8, 0x22);
240 if (ERROR_OK != retval) {
241 LOG_ERROR("could not set FLASHCLK_CTRL");
242 return ERROR_NAND_OPERATION_FAILED;
243 }
244
245 /* MLC_CEH = 0x0 (Force nCE assert) */
246 retval = target_write_u32(target, 0x200b804c, 0x0);
247 if (ERROR_OK != retval) {
248 LOG_ERROR("could not set MLC_CEH");
249 return ERROR_NAND_OPERATION_FAILED;
250 }
251
252 /* MLC_LOCK = 0xa25e (unlock protected registers) */
253 retval = target_write_u32(target, 0x200b8044, 0xa25e);
254 if (ERROR_OK != retval) {
255 LOG_ERROR("could not set MLC_LOCK");
256 return ERROR_NAND_OPERATION_FAILED;
257 }
258
259 /* MLC_ICR = configuration */
260 if (lpc32xx_info->sw_write_protection)
261 mlc_icr_value |= 0x8;
262 if (page_size == 2048)
263 mlc_icr_value |= 0x4;
264 if (address_cycles == 4)
265 mlc_icr_value |= 0x2;
266 if (bus_width == 16)
267 mlc_icr_value |= 0x1;
268 retval = target_write_u32(target, 0x200b8030, mlc_icr_value);
269 if (ERROR_OK != retval) {
270 LOG_ERROR("could not set MLC_ICR");
271 return ERROR_NAND_OPERATION_FAILED;
272 }
273
274 /* calculate NAND controller timings */
275 cycle = lpc32xx_cycle_time(nand);
276
277 twp = ((40 / cycle) + 1);
278 twh = ((20 / cycle) + 1);
279 trp = ((30 / cycle) + 1);
280 treh = ((15 / cycle) + 1);
281 trhz = ((30 / cycle) + 1);
282 trbwb = ((100 / cycle) + 1);
283 tcea = ((45 / cycle) + 1);
284
285 /* MLC_LOCK = 0xa25e (unlock protected registers) */
286 retval = target_write_u32(target, 0x200b8044, 0xa25e);
287 if (ERROR_OK != retval) {
288 LOG_ERROR("could not set MLC_LOCK");
289 return ERROR_NAND_OPERATION_FAILED;
290 }
291
292 /* MLC_TIME_REG */
293 retval = target_write_u32(target, 0x200b8034,
294 (twp & 0xf)
295 | ((twh & 0xf) << 4)
296 | ((trp & 0xf) << 8)
297 | ((treh & 0xf) << 12)
298 | ((trhz & 0x7) << 16)
299 | ((trbwb & 0x1f) << 19)
300 | ((tcea & 0x3) << 24));
301 if (ERROR_OK != retval) {
302 LOG_ERROR("could not set MLC_TIME_REG");
303 return ERROR_NAND_OPERATION_FAILED;
304 }
305
306 retval = lpc32xx_reset(nand);
307 if (ERROR_OK != retval)
308 return ERROR_NAND_OPERATION_FAILED;
309 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
310 float cycle;
311 int r_setup, r_hold, r_width, r_rdy;
312 int w_setup, w_hold, w_width, w_rdy;
313
314 /* FLASHCLK_CTRL = 0x05 (enable clk for SLC) */
315 retval = target_write_u32(target, 0x400040c8, 0x05);
316 if (ERROR_OK != retval) {
317 LOG_ERROR("could not set FLASHCLK_CTRL");
318 return ERROR_NAND_OPERATION_FAILED;
319 }
320
321 /* after reset set other registers of SLC,
322 * so reset calling is here at the begining
323 */
324 retval = lpc32xx_reset(nand);
325 if (ERROR_OK != retval)
326 return ERROR_NAND_OPERATION_FAILED;
327
328 /* SLC_CFG =
329 Force nCE assert,
330 DMA ECC enabled,
331 ECC enabled,
332 DMA burst enabled,
333 DMA read from SLC,
334 WIDTH = bus_width)
335 */
336 retval = target_write_u32(target, 0x20020014,
337 0x3e | (bus_width == 16) ? 1 : 0);
338 if (ERROR_OK != retval) {
339 LOG_ERROR("could not set SLC_CFG");
340 return ERROR_NAND_OPERATION_FAILED;
341 }
342
343 /* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
344 retval = target_write_u32(target, 0x20020020, 0x03);
345 if (ERROR_OK != retval) {
346 LOG_ERROR("could not set SLC_IEN");
347 return ERROR_NAND_OPERATION_FAILED;
348 }
349
350 /* DMA configuration */
351
352 /* DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
353 retval = target_write_u32(target, 0x400040e8, 0x01);
354 if (ERROR_OK != retval) {
355 LOG_ERROR("could not set DMACLK_CTRL");
356 return ERROR_NAND_OPERATION_FAILED;
357 }
358
359 /* DMACConfig = DMA enabled*/
360 retval = target_write_u32(target, 0x31000030, 0x01);
361 if (ERROR_OK != retval) {
362 LOG_ERROR("could not set DMACConfig");
363 return ERROR_NAND_OPERATION_FAILED;
364 }
365
366 /* calculate NAND controller timings */
367 cycle = lpc32xx_cycle_time(nand);
368
369 r_setup = w_setup = 0;
370 r_hold = w_hold = 10 / cycle;
371 r_width = 30 / cycle;
372 w_width = 40 / cycle;
373 r_rdy = w_rdy = 100 / cycle;
374
375 /* SLC_TAC: SLC timing arcs register */
376 retval = target_write_u32(target, 0x2002002c,
377 (r_setup & 0xf)
378 | ((r_hold & 0xf) << 4)
379 | ((r_width & 0xf) << 8)
380 | ((r_rdy & 0xf) << 12)
381 | ((w_setup & 0xf) << 16)
382 | ((w_hold & 0xf) << 20)
383 | ((w_width & 0xf) << 24)
384 | ((w_rdy & 0xf) << 28));
385 if (ERROR_OK != retval) {
386 LOG_ERROR("could not set SLC_TAC");
387 return ERROR_NAND_OPERATION_FAILED;
388 }
389 }
390
391 return ERROR_OK;
392 }
393
394 static int lpc32xx_reset(struct nand_device *nand)
395 {
396 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
397 struct target *target = nand->target;
398 int retval;
399
400 if (target->state != TARGET_HALTED) {
401 LOG_ERROR("target must be halted to use "
402 "LPC32xx NAND flash controller");
403 return ERROR_NAND_OPERATION_FAILED;
404 }
405
406 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
407 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
408 return ERROR_NAND_OPERATION_FAILED;
409 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
410 /* MLC_CMD = 0xff (reset controller and NAND device) */
411 retval = target_write_u32(target, 0x200b8000, 0xff);
412 if (ERROR_OK != retval) {
413 LOG_ERROR("could not set MLC_CMD");
414 return ERROR_NAND_OPERATION_FAILED;
415 }
416
417 if (!lpc32xx_controller_ready(nand, 100)) {
418 LOG_ERROR("LPC32xx MLC NAND controller timed out "
419 "after reset");
420 return ERROR_NAND_OPERATION_TIMEOUT;
421 }
422 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
423 /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
424 retval = target_write_u32(target, 0x20020010, 0x6);
425 if (ERROR_OK != retval) {
426 LOG_ERROR("could not set SLC_CTRL");
427 return ERROR_NAND_OPERATION_FAILED;
428 }
429
430 if (!lpc32xx_controller_ready(nand, 100)) {
431 LOG_ERROR("LPC32xx SLC NAND controller timed out "
432 "after reset");
433 return ERROR_NAND_OPERATION_TIMEOUT;
434 }
435 }
436
437 return ERROR_OK;
438 }
439
440 static int lpc32xx_command(struct nand_device *nand, uint8_t command)
441 {
442 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
443 struct target *target = nand->target;
444 int retval;
445
446 if (target->state != TARGET_HALTED) {
447 LOG_ERROR("target must be halted to use "
448 "LPC32xx NAND flash controller");
449 return ERROR_NAND_OPERATION_FAILED;
450 }
451
452 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
453 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
454 return ERROR_NAND_OPERATION_FAILED;
455 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
456 /* MLC_CMD = command */
457 retval = target_write_u32(target, 0x200b8000, command);
458 if (ERROR_OK != retval) {
459 LOG_ERROR("could not set MLC_CMD");
460 return ERROR_NAND_OPERATION_FAILED;
461 }
462 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
463 /* SLC_CMD = command */
464 retval = target_write_u32(target, 0x20020008, command);
465 if (ERROR_OK != retval) {
466 LOG_ERROR("could not set SLC_CMD");
467 return ERROR_NAND_OPERATION_FAILED;
468 }
469 }
470
471 return ERROR_OK;
472 }
473
474 static int lpc32xx_address(struct nand_device *nand, uint8_t address)
475 {
476 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
477 struct target *target = nand->target;
478 int retval;
479
480 if (target->state != TARGET_HALTED) {
481 LOG_ERROR("target must be halted to use "
482 "LPC32xx NAND flash controller");
483 return ERROR_NAND_OPERATION_FAILED;
484 }
485
486 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
487 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
488 return ERROR_NAND_OPERATION_FAILED;
489 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
490 /* MLC_ADDR = address */
491 retval = target_write_u32(target, 0x200b8004, address);
492 if (ERROR_OK != retval) {
493 LOG_ERROR("could not set MLC_ADDR");
494 return ERROR_NAND_OPERATION_FAILED;
495 }
496 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
497 /* SLC_ADDR = address */
498 retval = target_write_u32(target, 0x20020004, address);
499 if (ERROR_OK != retval) {
500 LOG_ERROR("could not set SLC_ADDR");
501 return ERROR_NAND_OPERATION_FAILED;
502 }
503 }
504
505 return ERROR_OK;
506 }
507
508 static int lpc32xx_write_data(struct nand_device *nand, uint16_t data)
509 {
510 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
511 struct target *target = nand->target;
512 int retval;
513
514 if (target->state != TARGET_HALTED) {
515 LOG_ERROR("target must be halted to use "
516 "LPC32xx NAND flash controller");
517 return ERROR_NAND_OPERATION_FAILED;
518 }
519
520 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
521 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
522 return ERROR_NAND_OPERATION_FAILED;
523 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
524 /* MLC_DATA = data */
525 retval = target_write_u32(target, 0x200b0000, data);
526 if (ERROR_OK != retval) {
527 LOG_ERROR("could not set MLC_DATA");
528 return ERROR_NAND_OPERATION_FAILED;
529 }
530 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
531 /* SLC_DATA = data */
532 retval = target_write_u32(target, 0x20020000, data);
533 if (ERROR_OK != retval) {
534 LOG_ERROR("could not set SLC_DATA");
535 return ERROR_NAND_OPERATION_FAILED;
536 }
537 }
538
539 return ERROR_OK;
540 }
541
542 static int lpc32xx_read_data(struct nand_device *nand, void *data)
543 {
544 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
545 struct target *target = nand->target;
546 int retval;
547
548 if (target->state != TARGET_HALTED) {
549 LOG_ERROR("target must be halted to use LPC32xx "
550 "NAND flash controller");
551 return ERROR_NAND_OPERATION_FAILED;
552 }
553
554 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
555 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
556 return ERROR_NAND_OPERATION_FAILED;
557 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
558 /* data = MLC_DATA, use sized access */
559 if (nand->bus_width == 8) {
560 uint8_t *data8 = data;
561 retval = target_read_u8(target, 0x200b0000, data8);
562 } else {
563 LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
564 return ERROR_NAND_OPERATION_FAILED;
565 }
566 if (ERROR_OK != retval) {
567 LOG_ERROR("could not read MLC_DATA");
568 return ERROR_NAND_OPERATION_FAILED;
569 }
570 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
571 uint32_t data32;
572
573 /* data = SLC_DATA, must use 32-bit access */
574 retval = target_read_u32(target, 0x20020000, &data32);
575 if (ERROR_OK != retval) {
576 LOG_ERROR("could not read SLC_DATA");
577 return ERROR_NAND_OPERATION_FAILED;
578 }
579
580 if (nand->bus_width == 8) {
581 uint8_t *data8 = data;
582 *data8 = data32 & 0xff;
583 } else {
584 LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
585 return ERROR_NAND_OPERATION_FAILED;
586 }
587 }
588
589 return ERROR_OK;
590 }
591
592 static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page,
593 uint8_t *data, uint32_t data_size,
594 uint8_t *oob, uint32_t oob_size)
595 {
596 struct target *target = nand->target;
597 int retval;
598 uint8_t status;
599 static uint8_t page_buffer[512];
600 static uint8_t oob_buffer[6];
601 int quarter, num_quarters;
602
603 /* MLC_CMD = sequential input */
604 retval = target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
605 if (ERROR_OK != retval) {
606 LOG_ERROR("could not set MLC_CMD");
607 return ERROR_NAND_OPERATION_FAILED;
608 }
609
610 if (nand->page_size == 512) {
611 /* MLC_ADDR = 0x0 (one column cycle) */
612 retval = target_write_u32(target, 0x200b8004, 0x0);
613 if (ERROR_OK != retval) {
614 LOG_ERROR("could not set MLC_ADDR");
615 return ERROR_NAND_OPERATION_FAILED;
616 }
617
618 /* MLC_ADDR = row */
619 retval = target_write_u32(target, 0x200b8004, page & 0xff);
620 if (ERROR_OK != retval) {
621 LOG_ERROR("could not set MLC_ADDR");
622 return ERROR_NAND_OPERATION_FAILED;
623 }
624 retval = target_write_u32(target, 0x200b8004,
625 (page >> 8) & 0xff);
626 if (ERROR_OK != retval) {
627 LOG_ERROR("could not set MLC_ADDR");
628 return ERROR_NAND_OPERATION_FAILED;
629 }
630
631 if (nand->address_cycles == 4) {
632 retval = target_write_u32(target, 0x200b8004,
633 (page >> 16) & 0xff);
634 if (ERROR_OK != retval) {
635 LOG_ERROR("could not set MLC_ADDR");
636 return ERROR_NAND_OPERATION_FAILED;
637 }
638 }
639 } else {
640 /* MLC_ADDR = 0x0 (two column cycles) */
641 retval = target_write_u32(target, 0x200b8004, 0x0);
642 if (ERROR_OK != retval) {
643 LOG_ERROR("could not set MLC_ADDR");
644 return ERROR_NAND_OPERATION_FAILED;
645 }
646 retval = target_write_u32(target, 0x200b8004, 0x0);
647 if (ERROR_OK != retval) {
648 LOG_ERROR("could not set MLC_ADDR");
649 return ERROR_NAND_OPERATION_FAILED;
650 }
651
652 /* MLC_ADDR = row */
653 retval = target_write_u32(target, 0x200b8004, page & 0xff);
654 if (ERROR_OK != retval) {
655 LOG_ERROR("could not set MLC_ADDR");
656 return ERROR_NAND_OPERATION_FAILED;
657 }
658 retval = target_write_u32(target, 0x200b8004,
659 (page >> 8) & 0xff);
660 if (ERROR_OK != retval) {
661 LOG_ERROR("could not set MLC_ADDR");
662 return ERROR_NAND_OPERATION_FAILED;
663 }
664 }
665
666 /* when using the MLC controller, we have to treat a large page device
667 * as being made out of four quarters, each the size of a small page
668 * device
669 */
670 num_quarters = (nand->page_size == 2048) ? 4 : 1;
671
672 for (quarter = 0; quarter < num_quarters; quarter++) {
673 int thisrun_data_size = (data_size > 512) ? 512 : data_size;
674 int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
675
676 memset(page_buffer, 0xff, 512);
677 if (data) {
678 memcpy(page_buffer, data, thisrun_data_size);
679 data_size -= thisrun_data_size;
680 data += thisrun_data_size;
681 }
682
683 memset(oob_buffer, 0xff, 6);
684 if (oob) {
685 memcpy(oob_buffer, oob, thisrun_oob_size);
686 oob_size -= thisrun_oob_size;
687 oob += thisrun_oob_size;
688 }
689
690 /* write MLC_ECC_ENC_REG to start encode cycle */
691 retval = target_write_u32(target, 0x200b8008, 0x0);
692 if (ERROR_OK != retval) {
693 LOG_ERROR("could not set MLC_ECC_ENC_REG");
694 return ERROR_NAND_OPERATION_FAILED;
695 }
696
697 retval = target_write_memory(target, 0x200a8000,
698 4, 128, page_buffer);
699 if (ERROR_OK != retval) {
700 LOG_ERROR("could not set MLC_BUF (data)");
701 return ERROR_NAND_OPERATION_FAILED;
702 }
703 retval = target_write_memory(target, 0x200a8000,
704 1, 6, oob_buffer);
705 if (ERROR_OK != retval) {
706 LOG_ERROR("could not set MLC_BUF (oob)");
707 return ERROR_NAND_OPERATION_FAILED;
708 }
709
710 /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
711 retval = target_write_u32(target, 0x200b8010, 0x0);
712 if (ERROR_OK != retval) {
713 LOG_ERROR("could not set MLC_ECC_AUTO_ENC_REG");
714 return ERROR_NAND_OPERATION_FAILED;
715 }
716
717 if (!lpc32xx_controller_ready(nand, 1000)) {
718 LOG_ERROR("timeout while waiting for "
719 "completion of auto encode cycle");
720 return ERROR_NAND_OPERATION_FAILED;
721 }
722 }
723
724 /* MLC_CMD = auto program command */
725 retval = target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
726 if (ERROR_OK != retval) {
727 LOG_ERROR("could not set MLC_CMD");
728 return ERROR_NAND_OPERATION_FAILED;
729 }
730
731 retval = nand_read_status(nand, &status);
732 if (retval != ERROR_OK) {
733 LOG_ERROR("couldn't read status");
734 return ERROR_NAND_OPERATION_FAILED;
735 }
736
737 if (status & NAND_STATUS_FAIL) {
738 LOG_ERROR("write operation didn't pass, status: 0x%2.2x",
739 status);
740 return ERROR_NAND_OPERATION_FAILED;
741 }
742
743 return ERROR_OK;
744 }
745
746 /* SLC controller in !raw mode will use target cpu to read/write nand from/to
747 * target internal memory. The transfer to/from flash is done by DMA. This
748 * function sets up the dma linked list in host memory for later transfer to
749 * target.
750 */
751 static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
752 int do_read)
753 {
754 uint32_t i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst;
755
756 /* DMACCxControl =
757 TransferSize =64,
758 Source burst size =16,
759 Destination burst size = 16,
760 Source transfer width = 32 bit,
761 Destination transfer width = 32 bit,
762 Source AHB master select = M0,
763 Destination AHB master select = M0,
764 Source increment = 0, // set later
765 Destination increment = 0, // set later
766 Terminal count interrupt enable bit = 0 // set on last
767 */ /*
768 * Write Operation Sequence for Small Block NAND
769 * ----------------------------------------------------------
770 * 1. X'fer 256 bytes of data from Memory to Flash.
771 * 2. Copy generated ECC data from Register to Spare Area
772 * 3. X'fer next 256 bytes of data from Memory to Flash.
773 * 4. Copy generated ECC data from Register to Spare Area.
774 * 5. X'fer 16 byets of Spare area from Memory to Flash.
775 * Read Operation Sequence for Small Block NAND
776 * ----------------------------------------------------------
777 * 1. X'fer 256 bytes of data from Flash to Memory.
778 * 2. Copy generated ECC data from Register to ECC calc Buffer.
779 * 3. X'fer next 256 bytes of data from Flash to Memory.
780 * 4. Copy generated ECC data from Register to ECC calc Buffer.
781 * 5. X'fer 16 bytes of Spare area from Flash to Memory.
782 * Write Operation Sequence for Large Block NAND
783 * ----------------------------------------------------------
784 * 1. Steps(1-4) of Write Operations repeate for four times
785 * which generates 16 DMA descriptors to X'fer 2048 bytes of
786 * data & 32 bytes of ECC data.
787 * 2. X'fer 64 bytes of Spare area from Memory to Flash.
788 * Read Operation Sequence for Large Block NAND
789 * ----------------------------------------------------------
790 * 1. Steps(1-4) of Read Operations repeate for four times
791 * which generates 16 DMA descriptors to X'fer 2048 bytes of
792 * data & 32 bytes of ECC data.
793 * 2. X'fer 64 bytes of Spare area from Flash to Memory.
794 */
795
796 ctrl = (0x40 | 3 << 12 | 3 << 15 | 2 << 18 | 2 << 21 | 0 << 24
797 | 0 << 25 | 0 << 26 | 0 << 27 | 0 << 31);
798
799 /* DMACCxControl =
800 TransferSize =1,
801 Source burst size =4,
802 Destination burst size = 4,
803 Source transfer width = 32 bit,
804 Destination transfer width = 32 bit,
805 Source AHB master select = M0,
806 Destination AHB master select = M0,
807 Source increment = 0,
808 Destination increment = 1,
809 Terminal count interrupt enable bit = 0
810 */
811 ecc_ctrl = 0x01 | 1 << 12 | 1 << 15 | 2 << 18 | 2 << 21 | 0 << 24
812 | 0 << 25 | 0 << 26 | 1 << 27 | 0 << 31;
813
814 /* DMACCxControl =
815 TransferSize =16 for lp or 4 for sp,
816 Source burst size =16,
817 Destination burst size = 16,
818 Source transfer width = 32 bit,
819 Destination transfer width = 32 bit,
820 Source AHB master select = M0,
821 Destination AHB master select = M0,
822 Source increment = 0, // set later
823 Destination increment = 0, // set later
824 Terminal count interrupt enable bit = 1 // set on last
825 */
826 oob_ctrl = (page_size == 2048 ? 0x10 : 0x04)
827 | 3 << 12 | 3 << 15 | 2 << 18 | 2 << 21 | 0 << 24
828 | 0 << 25 | 0 << 26 | 0 << 27 | 1 << 31;
829 if (do_read) {
830 ctrl |= 1 << 27;/* Destination increment = 1 */
831 oob_ctrl |= 1 << 27; /* Destination increment = 1 */
832 dmasrc = 0x20020038; /* SLC_DMA_DATA */
833 dmadst = target_mem_base + DATA_OFFS;
834 } else {
835 ctrl |= 1 << 26;/* Source increment = 1 */
836 oob_ctrl |= 1 << 26; /* Source increment = 1 */
837 dmasrc = target_mem_base + DATA_OFFS;
838 dmadst = 0x20020038; /* SLC_DMA_DATA */
839 }
840 /*
841 * Write Operation Sequence for Small Block NAND
842 * ----------------------------------------------------------
843 * 1. X'fer 256 bytes of data from Memory to Flash.
844 * 2. Copy generated ECC data from Register to Spare Area
845 * 3. X'fer next 256 bytes of data from Memory to Flash.
846 * 4. Copy generated ECC data from Register to Spare Area.
847 * 5. X'fer 16 byets of Spare area from Memory to Flash.
848 * Read Operation Sequence for Small Block NAND
849 * ----------------------------------------------------------
850 * 1. X'fer 256 bytes of data from Flash to Memory.
851 * 2. Copy generated ECC data from Register to ECC calc Buffer.
852 * 3. X'fer next 256 bytes of data from Flash to Memory.
853 * 4. Copy generated ECC data from Register to ECC calc Buffer.
854 * 5. X'fer 16 bytes of Spare area from Flash to Memory.
855 * Write Operation Sequence for Large Block NAND
856 * ----------------------------------------------------------
857 * 1. Steps(1-4) of Write Operations repeate for four times
858 * which generates 16 DMA descriptors to X'fer 2048 bytes of
859 * data & 32 bytes of ECC data.
860 * 2. X'fer 64 bytes of Spare area from Memory to Flash.
861 * Read Operation Sequence for Large Block NAND
862 * ----------------------------------------------------------
863 * 1. Steps(1-4) of Read Operations repeate for four times
864 * which generates 16 DMA descriptors to X'fer 2048 bytes of
865 * data & 32 bytes of ECC data.
866 * 2. X'fer 64 bytes of Spare area from Flash to Memory.
867 */
868 for (i = 0; i < page_size/0x100; i++) {
869 dmalist[i*2].dma_src = (do_read ? dmasrc : (dmasrc + i * 256));
870 dmalist[i*2].dma_dest = (do_read ? (dmadst + i * 256) : dmadst);
871 dmalist[i*2].next_lli =
872 target_mem_base + (i*2 + 1) * sizeof(dmac_ll_t);
873 dmalist[i*2].next_ctrl = ctrl;
874
875 dmalist[(i*2) + 1].dma_src = 0x20020034;/* SLC_ECC */
876 dmalist[(i*2) + 1].dma_dest =
877 target_mem_base + ECC_OFFS + i * 4;
878 dmalist[(i*2) + 1].next_lli =
879 target_mem_base + (i*2 + 2) * sizeof(dmac_ll_t);
880 dmalist[(i*2) + 1].next_ctrl = ecc_ctrl;
881
882 }
883 if (do_read)
884 dmadst = target_mem_base + SPARE_OFFS;
885 else {
886 dmasrc = target_mem_base + SPARE_OFFS;
887 dmalist[(i*2) - 1].next_lli = 0;/* last link = null on write */
888 dmalist[(i*2) - 1].next_ctrl |= (1 << 31); /* Set TC enable */
889 }
890 dmalist[i*2].dma_src = dmasrc;
891 dmalist[i*2].dma_dest = dmadst;
892 dmalist[i*2].next_lli = 0;
893 dmalist[i*2].next_ctrl = oob_ctrl;
894
895 return i * 2 + 1; /* Number of descriptors */
896 }
897
898 static int lpc32xx_start_slc_dma(struct nand_device *nand, uint32_t count,
899 int do_wait)
900 {
901 struct target *target = nand->target;
902 int retval;
903
904 /* DMACIntTCClear = ch0 */
905 retval = target_write_u32(target, 0x31000008, 1);
906 if (ERROR_OK != retval) {
907 LOG_ERROR("Could not set DMACIntTCClear");
908 return retval;
909 }
910
911 /* DMACIntErrClear = ch0 */
912 retval = target_write_u32(target, 0x31000010, 1);
913 if (ERROR_OK != retval) {
914 LOG_ERROR("Could not set DMACIntErrClear");
915 return retval;
916 }
917
918 /* DMACCxConfig=
919 E=1,
920 SrcPeripheral = 1 (SLC),
921 DestPeripheral = 1 (SLC),
922 FlowCntrl = 2 (Pher -> Mem, DMA),
923 IE = 0,
924 ITC = 0,
925 L= 0,
926 H=0
927 */
928 retval = target_write_u32(target, 0x31000110,
929 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
930 | 0<<15 | 0<<16 | 0<<18);
931 if (ERROR_OK != retval) {
932 LOG_ERROR("Could not set DMACC0Config");
933 return retval;
934 }
935
936 /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
937 retval = target_write_u32(target, 0x20020010, 0x3);
938 if (ERROR_OK != retval) {
939 LOG_ERROR("Could not set SLC_CTRL");
940 return retval;
941 }
942
943 /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
944 retval = target_write_u32(target, 0x20020028, 2);
945 if (ERROR_OK != retval) {
946 LOG_ERROR("Could not set SLC_ICR");
947 return retval;
948 }
949
950 /* SLC_TC */
951 retval = target_write_u32(target, 0x20020030, count);
952 if (ERROR_OK != retval) {
953 LOG_ERROR("lpc32xx_start_slc_dma: Could not set SLC_TC");
954 return retval;
955 }
956
957 /* Wait finish */
958 if (do_wait && !lpc32xx_tc_ready(nand, 100)) {
959 LOG_ERROR("timeout while waiting for completion of DMA");
960 return ERROR_NAND_OPERATION_FAILED;
961 }
962
963 return retval;
964 }
965
966 static int lpc32xx_dma_ready(struct nand_device *nand, int timeout)
967 {
968 struct target *target = nand->target;
969
970 LOG_DEBUG("lpc32xx_dma_ready count start=%d", timeout);
971
972 do {
973 uint32_t tc_stat;
974 uint32_t err_stat;
975 int retval;
976
977 /* Read DMACRawIntTCStat */
978 retval = target_read_u32(target, 0x31000014, &tc_stat);
979 if (ERROR_OK != retval) {
980 LOG_ERROR("Could not read DMACRawIntTCStat");
981 return 0;
982 }
983 /* Read DMACRawIntErrStat */
984 retval = target_read_u32(target, 0x31000018, &err_stat);
985 if (ERROR_OK != retval) {
986 LOG_ERROR("Could not read DMACRawIntErrStat");
987 return 0;
988 }
989 if ((tc_stat | err_stat) & 1) {
990 LOG_DEBUG("lpc32xx_dma_ready count=%d",
991 timeout);
992 if (err_stat & 1) {
993 LOG_ERROR("lpc32xx_dma_ready "
994 "DMA error, aborted");
995 return 0;
996 } else
997 return 1;
998 }
999
1000 alive_sleep(1);
1001 } while (timeout-- > 0);
1002
1003 return 0;
1004 }
1005
1006 static uint32_t slc_ecc_copy_to_buffer(uint8_t *spare,
1007 const uint32_t *ecc, int count)
1008 {
1009 int i;
1010 for (i = 0; i < (count * 3); i += 3) {
1011 uint32_t ce = ecc[i/3];
1012 ce = ~(ce << 2) & 0xFFFFFF;
1013 spare[i+2] = (uint8_t)(ce & 0xFF); ce >>= 8;
1014 spare[i+1] = (uint8_t)(ce & 0xFF); ce >>= 8;
1015 spare[i] = (uint8_t)(ce & 0xFF);
1016 }
1017 return 0;
1018 }
1019
1020 static void lpc32xx_dump_oob(uint8_t *oob, uint32_t oob_size)
1021 {
1022 int addr = 0;
1023 while (oob_size > 0) {
1024 LOG_DEBUG("%02x: %02x %02x %02x %02x %02x %02x %02x %02x", addr,
1025 oob[0], oob[1], oob[2], oob[3],
1026 oob[4], oob[5], oob[6], oob[7]);
1027 oob += 8;
1028 addr += 8;
1029 oob_size -= 8;
1030 }
1031 }
1032
1033 static int lpc32xx_write_page_slc(struct nand_device *nand,
1034 struct working_area *pworking_area,
1035 uint32_t page, uint8_t *data,
1036 uint32_t data_size, uint8_t *oob,
1037 uint32_t oob_size)
1038 {
1039 struct target *target = nand->target;
1040 int retval;
1041 uint32_t target_mem_base;
1042
1043 LOG_DEBUG("SLC write page %x data=%d, oob=%d, "
1044 "data_size=%d, oob_size=%d",
1045 page, data != 0, oob != 0, data_size, oob_size);
1046
1047 target_mem_base = pworking_area->address;
1048 /*
1049 * Skip writting page which has all 0xFF data as this will
1050 * generate 0x0 value.
1051 */
1052 if (data && !oob) {
1053 uint32_t i, all_ff = 1;
1054 for (i = 0; i < data_size; i++)
1055 if (data[i] != 0xFF) {
1056 all_ff = 0;
1057 break;
1058 }
1059 if (all_ff)
1060 return ERROR_OK;
1061 }
1062 /* Make the dma descriptors in local memory */
1063 int nll = lpc32xx_make_dma_list(target_mem_base, nand->page_size, 0);
1064 /* Write them to target.
1065 XXX: Assumes host and target have same byte sex.
1066 */
1067 retval = target_write_memory(target, target_mem_base, 4,
1068 nll * sizeof(dmac_ll_t) / 4,
1069 (uint8_t *)dmalist);
1070 if (ERROR_OK != retval) {
1071 LOG_ERROR("Could not write DMA descriptors to IRAM");
1072 return retval;
1073 }
1074
1075 retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
1076 if (ERROR_OK != retval) {
1077 LOG_ERROR("NAND_CMD_SEQIN failed");
1078 return retval;
1079 }
1080
1081 /* SLC_CFG =
1082 Force nCE assert,
1083 DMA ECC enabled,
1084 ECC enabled,
1085 DMA burst enabled,
1086 DMA write to SLC,
1087 WIDTH = bus_width
1088 */
1089 retval = target_write_u32(target, 0x20020014, 0x3c);
1090 if (ERROR_OK != retval) {
1091 LOG_ERROR("Could not set SLC_CFG");
1092 return retval;
1093 }
1094 if (data) {
1095 /* Write data to target */
1096 static uint8_t fdata[2048];
1097 memset(fdata, 0xFF, nand->page_size);
1098 memcpy(fdata, data, data_size);
1099 retval = target_write_memory(target,
1100 target_mem_base + DATA_OFFS,
1101 4, nand->page_size/4, fdata);
1102 if (ERROR_OK != retval) {
1103 LOG_ERROR("Could not write data to IRAM");
1104 return retval;
1105 }
1106
1107 /* Write first decriptor to DMA controller */
1108 retval = target_write_memory(target, 0x31000100, 4,
1109 sizeof(dmac_ll_t) / 4,
1110 (uint8_t *)dmalist);
1111 if (ERROR_OK != retval) {
1112 LOG_ERROR("Could not write DMA descriptor to DMAC");
1113 return retval;
1114 }
1115
1116 /* Start xfer of data from iram to flash using DMA */
1117 int tot_size = nand->page_size;
1118 tot_size += tot_size == 2048 ? 64 : 16;
1119 retval = lpc32xx_start_slc_dma(nand, tot_size, 0);
1120 if (ERROR_OK != retval) {
1121 LOG_ERROR("DMA failed");
1122 return retval;
1123 }
1124
1125 /* Wait for DMA to finish. SLC is not finished at this stage */
1126 if (!lpc32xx_dma_ready(nand, 100)) {
1127 LOG_ERROR("Data DMA failed during write");
1128 return ERROR_FLASH_OPERATION_FAILED;
1129 }
1130 } /* data xfer */
1131
1132 /* Copy OOB to iram */
1133 static uint8_t foob[64];
1134 int foob_size = nand->page_size == 2048 ? 64 : 16;
1135 memset(foob, 0xFF, foob_size);
1136 if (oob) /* Raw mode */
1137 memcpy(foob, oob, oob_size);
1138 else {
1139 /* Get HW generated ECC, made while writing data */
1140 int ecc_count = nand->page_size == 2048 ? 8 : 2;
1141 static uint32_t hw_ecc[8];
1142 retval = target_read_memory(target, target_mem_base + ECC_OFFS,
1143 4, ecc_count, (uint8_t *)hw_ecc);
1144 if (ERROR_OK != retval) {
1145 LOG_ERROR("Reading hw generated ECC from IRAM failed");
1146 return retval;
1147 }
1148 /* Copy to oob, at correct offsets */
1149 static uint8_t ecc[24];
1150 slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
1151 int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
1152 int i;
1153 for (i = 0; i < ecc_count * 3; i++)
1154 foob[layout[i]] = ecc[i];
1155 lpc32xx_dump_oob(foob, foob_size);
1156 }
1157 retval = target_write_memory(target, target_mem_base + SPARE_OFFS, 4,
1158 foob_size / 4, foob);
1159 if (ERROR_OK != retval) {
1160 LOG_ERROR("Writing OOB to IRAM failed");
1161 return retval;
1162 }
1163
1164 /* Write OOB decriptor to DMA controller */
1165 retval = target_write_memory(target, 0x31000100, 4,
1166 sizeof(dmac_ll_t) / 4,
1167 (uint8_t *)(&dmalist[nll-1]));
1168 if (ERROR_OK != retval) {
1169 LOG_ERROR("Could not write OOB DMA descriptor to DMAC");
1170 return retval;
1171 }
1172 if (data) {
1173 /* Only restart DMA with last descriptor,
1174 * don't setup SLC again */
1175
1176 /* DMACIntTCClear = ch0 */
1177 retval = target_write_u32(target, 0x31000008, 1);
1178 if (ERROR_OK != retval) {
1179 LOG_ERROR("Could not set DMACIntTCClear");
1180 return retval;
1181 }
1182 /* DMACCxConfig=
1183 * E=1,
1184 * SrcPeripheral = 1 (SLC),
1185 * DestPeripheral = 1 (SLC),
1186 * FlowCntrl = 2 (Pher -> Mem, DMA),
1187 * IE = 0,
1188 * ITC = 0,
1189 * L= 0,
1190 * H=0
1191 */
1192 retval = target_write_u32(target, 0x31000110,
1193 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
1194 | 0<<15 | 0<<16 | 0<<18);
1195 if (ERROR_OK != retval) {
1196 LOG_ERROR("Could not set DMACC0Config");
1197 return retval;
1198 }
1199 /* Wait finish */
1200 if (!lpc32xx_tc_ready(nand, 100)) {
1201 LOG_ERROR("timeout while waiting for "
1202 "completion of DMA");
1203 return ERROR_NAND_OPERATION_FAILED;
1204 }
1205 } else {
1206 /* Start xfer of data from iram to flash using DMA */
1207 retval = lpc32xx_start_slc_dma(nand, foob_size, 1);
1208 if (ERROR_OK != retval) {
1209 LOG_ERROR("DMA OOB failed");
1210 return retval;
1211 }
1212 }
1213
1214 /* Let NAND start actual writing */
1215 retval = nand_write_finish(nand);
1216 if (ERROR_OK != retval) {
1217 LOG_ERROR("nand_write_finish failed");
1218 return retval;
1219 }
1220
1221 return ERROR_OK;
1222 }
1223
1224 static int lpc32xx_write_page(struct nand_device *nand, uint32_t page,
1225 uint8_t *data, uint32_t data_size,
1226 uint8_t *oob, uint32_t oob_size)
1227 {
1228 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1229 struct target *target = nand->target;
1230 int retval = ERROR_OK;
1231
1232 if (target->state != TARGET_HALTED) {
1233 LOG_ERROR("target must be halted to use LPC32xx "
1234 "NAND flash controller");
1235 return ERROR_NAND_OPERATION_FAILED;
1236 }
1237
1238 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
1239 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
1240 return ERROR_NAND_OPERATION_FAILED;
1241 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
1242 if (!data && oob) {
1243 LOG_ERROR("LPC32xx MLC controller can't write "
1244 "OOB data only");
1245 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1246 }
1247
1248 if (oob && (oob_size > 24)) {
1249 LOG_ERROR("LPC32xx MLC controller can't write more "
1250 "than 6 bytes for each quarter's OOB data");
1251 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1252 }
1253
1254 if (data_size > (uint32_t)nand->page_size) {
1255 LOG_ERROR("data size exceeds page size");
1256 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1257 }
1258
1259 retval = lpc32xx_write_page_mlc(nand, page, data, data_size,
1260 oob, oob_size);
1261 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
1262 struct working_area *pworking_area;
1263 if (!data && oob) {
1264 /*
1265 * if oob only mode is active original method is used
1266 * as SLC controller hangs during DMA interworking. (?)
1267 * Anyway the code supports the oob only mode below.
1268 */
1269 return nand_write_page_raw(nand, page, data,
1270 data_size, oob, oob_size);
1271 }
1272 retval = target_alloc_working_area(target,
1273 nand->page_size + DATA_OFFS,
1274 &pworking_area);
1275 if (retval != ERROR_OK) {
1276 LOG_ERROR("Can't allocate working area in "
1277 "LPC internal RAM");
1278 return ERROR_FLASH_OPERATION_FAILED;
1279 }
1280 retval = lpc32xx_write_page_slc(nand, pworking_area, page,
1281 data, data_size, oob, oob_size);
1282 target_free_working_area(target, pworking_area);
1283 }
1284
1285 return retval;
1286 }
1287
1288 static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page,
1289 uint8_t *data, uint32_t data_size,
1290 uint8_t *oob, uint32_t oob_size)
1291 {
1292 struct target *target = nand->target;
1293 static uint8_t page_buffer[2048];
1294 static uint8_t oob_buffer[64];
1295 uint32_t page_bytes_done = 0;
1296 uint32_t oob_bytes_done = 0;
1297 uint32_t mlc_isr;
1298 int retval;
1299
1300 if (!data && oob) {
1301 /* MLC_CMD = Read OOB
1302 * we can use the READOOB command on both small and large page
1303 * devices, as the controller translates the 0x50 command to
1304 * a 0x0 with appropriate positioning of the serial buffer
1305 * read pointer
1306 */
1307 retval = target_write_u32(target, 0x200b8000, NAND_CMD_READOOB);
1308 } else {
1309 /* MLC_CMD = Read0 */
1310 retval = target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
1311 }
1312 if (ERROR_OK != retval) {
1313 LOG_ERROR("could not set MLC_CMD");
1314 return ERROR_NAND_OPERATION_FAILED;
1315 }
1316 if (nand->page_size == 512) {
1317 /* small page device
1318 * MLC_ADDR = 0x0 (one column cycle) */
1319 retval = target_write_u32(target, 0x200b8004, 0x0);
1320 if (ERROR_OK != retval) {
1321 LOG_ERROR("could not set MLC_ADDR");
1322 return ERROR_NAND_OPERATION_FAILED;
1323 }
1324
1325 /* MLC_ADDR = row */
1326 retval = target_write_u32(target, 0x200b8004, page & 0xff);
1327 if (ERROR_OK != retval) {
1328 LOG_ERROR("could not set MLC_ADDR");
1329 return ERROR_NAND_OPERATION_FAILED;
1330 }
1331 retval = target_write_u32(target, 0x200b8004,
1332 (page >> 8) & 0xff);
1333 if (ERROR_OK != retval) {
1334 LOG_ERROR("could not set MLC_ADDR");
1335 return ERROR_NAND_OPERATION_FAILED;
1336 }
1337
1338 if (nand->address_cycles == 4) {
1339 retval = target_write_u32(target, 0x200b8004,
1340 (page >> 16) & 0xff);
1341 if (ERROR_OK != retval) {
1342 LOG_ERROR("could not set MLC_ADDR");
1343 return ERROR_NAND_OPERATION_FAILED;
1344 }
1345 }
1346 } else {
1347 /* large page device
1348 * MLC_ADDR = 0x0 (two column cycles) */
1349 retval = target_write_u32(target, 0x200b8004, 0x0);
1350 if (ERROR_OK != retval) {
1351 LOG_ERROR("could not set MLC_ADDR");
1352 return ERROR_NAND_OPERATION_FAILED;
1353 }
1354 retval = target_write_u32(target, 0x200b8004, 0x0);
1355 if (ERROR_OK != retval) {
1356 LOG_ERROR("could not set MLC_ADDR");
1357 return ERROR_NAND_OPERATION_FAILED;
1358 }
1359
1360 /* MLC_ADDR = row */
1361 retval = target_write_u32(target, 0x200b8004, page & 0xff);
1362 if (ERROR_OK != retval) {
1363 LOG_ERROR("could not set MLC_ADDR");
1364 return ERROR_NAND_OPERATION_FAILED;
1365 }
1366 retval = target_write_u32(target, 0x200b8004,
1367 (page >> 8) & 0xff);
1368 if (ERROR_OK != retval) {
1369 LOG_ERROR("could not set MLC_ADDR");
1370 return ERROR_NAND_OPERATION_FAILED;
1371 }
1372
1373 /* MLC_CMD = Read Start */
1374 retval = target_write_u32(target, 0x200b8000,
1375 NAND_CMD_READSTART);
1376 if (ERROR_OK != retval) {
1377 LOG_ERROR("could not set MLC_CMD");
1378 return ERROR_NAND_OPERATION_FAILED;
1379 }
1380 }
1381
1382 while (page_bytes_done < (uint32_t)nand->page_size) {
1383 /* MLC_ECC_AUTO_DEC_REG = dummy */
1384 retval = target_write_u32(target, 0x200b8014, 0xaa55aa55);
1385 if (ERROR_OK != retval) {
1386 LOG_ERROR("could not set MLC_ECC_AUTO_DEC_REG");
1387 return ERROR_NAND_OPERATION_FAILED;
1388 }
1389
1390 if (!lpc32xx_controller_ready(nand, 1000)) {
1391 LOG_ERROR("timeout while waiting for "
1392 "completion of auto decode cycle");
1393 return ERROR_NAND_OPERATION_FAILED;
1394 }
1395
1396 retval = target_read_u32(target, 0x200b8048, &mlc_isr);
1397 if (ERROR_OK != retval) {
1398 LOG_ERROR("could not read MLC_ISR");
1399 return ERROR_NAND_OPERATION_FAILED;
1400 }
1401
1402 if (mlc_isr & 0x8) {
1403 if (mlc_isr & 0x40) {
1404 LOG_ERROR("uncorrectable error detected: "
1405 "0x%2.2x", (unsigned)mlc_isr);
1406 return ERROR_NAND_OPERATION_FAILED;
1407 }
1408
1409 LOG_WARNING("%i symbol error detected and corrected",
1410 ((int)(((mlc_isr & 0x30) >> 4) + 1)));
1411 }
1412
1413 if (data) {
1414 retval = target_read_memory(target, 0x200a8000, 4, 128,
1415 page_buffer + page_bytes_done);
1416 if (ERROR_OK != retval) {
1417 LOG_ERROR("could not read MLC_BUF (data)");
1418 return ERROR_NAND_OPERATION_FAILED;
1419 }
1420 }
1421
1422 if (oob) {
1423 retval = target_read_memory(target, 0x200a8000, 4, 4,
1424 oob_buffer + oob_bytes_done);
1425 if (ERROR_OK != retval) {
1426 LOG_ERROR("could not read MLC_BUF (oob)");
1427 return ERROR_NAND_OPERATION_FAILED;
1428 }
1429 }
1430
1431 page_bytes_done += 512;
1432 oob_bytes_done += 16;
1433 }
1434
1435 if (data)
1436 memcpy(data, page_buffer, data_size);
1437
1438 if (oob)
1439 memcpy(oob, oob_buffer, oob_size);
1440
1441 return ERROR_OK;
1442 }
1443
1444 static int lpc32xx_read_page_slc(struct nand_device *nand,
1445 struct working_area *pworking_area,
1446 uint32_t page, uint8_t *data,
1447 uint32_t data_size, uint8_t *oob,
1448 uint32_t oob_size)
1449 {
1450 struct target *target = nand->target;
1451 int retval;
1452 uint32_t target_mem_base;
1453
1454 LOG_DEBUG("SLC read page %x data=%d, oob=%d",
1455 page, data_size, oob_size);
1456
1457 target_mem_base = pworking_area->address;
1458
1459 /* Make the dma descriptors in local memory */
1460 int nll = lpc32xx_make_dma_list(target_mem_base, nand->page_size, 1);
1461 /* Write them to target.
1462 XXX: Assumes host and target have same byte sex.
1463 */
1464 retval = target_write_memory(target, target_mem_base, 4,
1465 nll * sizeof(dmac_ll_t) / 4,
1466 (uint8_t *)dmalist);
1467 if (ERROR_OK != retval) {
1468 LOG_ERROR("Could not write DMA descriptors to IRAM");
1469 return retval;
1470 }
1471
1472 retval = nand_page_command(nand, page, NAND_CMD_READ0, 0);
1473 if (ERROR_OK != retval) {
1474 LOG_ERROR("lpc32xx_read_page_slc: NAND_CMD_READ0 failed");
1475 return retval;
1476 }
1477
1478 /* SLC_CFG =
1479 Force nCE assert,
1480 DMA ECC enabled,
1481 ECC enabled,
1482 DMA burst enabled,
1483 DMA read from SLC,
1484 WIDTH = bus_width
1485 */
1486 retval = target_write_u32(target, 0x20020014, 0x3e);
1487 if (ERROR_OK != retval) {
1488 LOG_ERROR("lpc32xx_read_page_slc: Could not set SLC_CFG");
1489 return retval;
1490 }
1491
1492 /* Write first decriptor to DMA controller */
1493 retval = target_write_memory(target, 0x31000100, 4,
1494 sizeof(dmac_ll_t) / 4, (uint8_t *)dmalist);
1495 if (ERROR_OK != retval) {
1496 LOG_ERROR("Could not write DMA descriptor to DMAC");
1497 return retval;
1498 }
1499
1500 /* Start xfer of data from flash to iram using DMA */
1501 int tot_size = nand->page_size;
1502 tot_size += nand->page_size == 2048 ? 64 : 16;
1503 retval = lpc32xx_start_slc_dma(nand, tot_size, 1);
1504 if (ERROR_OK != retval) {
1505 LOG_ERROR("lpc32xx_read_page_slc: DMA read failed");
1506 return retval;
1507 }
1508
1509 /* Copy data from iram */
1510 if (data) {
1511 retval = target_read_memory(target, target_mem_base + DATA_OFFS,
1512 4, data_size/4, data);
1513 if (ERROR_OK != retval) {
1514 LOG_ERROR("Could not read data from IRAM");
1515 return retval;
1516 }
1517 }
1518 if (oob) {
1519 /* No error correction, just return data as read from flash */
1520 retval = target_read_memory(target,
1521 target_mem_base + SPARE_OFFS, 4,
1522 oob_size/4, oob);
1523 if (ERROR_OK != retval) {
1524 LOG_ERROR("Could not read OOB from IRAM");
1525 return retval;
1526 }
1527 return ERROR_OK;
1528 }
1529
1530 /* Copy OOB from flash, stored in IRAM */
1531 static uint8_t foob[64];
1532 retval = target_read_memory(target, target_mem_base + SPARE_OFFS,
1533 4, nand->page_size == 2048 ? 16 : 4, foob);
1534 lpc32xx_dump_oob(foob, nand->page_size == 2048 ? 64 : 16);
1535 if (ERROR_OK != retval) {
1536 LOG_ERROR("Could not read OOB from IRAM");
1537 return retval;
1538 }
1539 /* Copy ECC from HW, generated while reading */
1540 int ecc_count = nand->page_size == 2048 ? 8 : 2;
1541 static uint32_t hw_ecc[8]; /* max size */
1542 retval = target_read_memory(target, target_mem_base + ECC_OFFS, 4,
1543 ecc_count, (uint8_t *)hw_ecc);
1544 if (ERROR_OK != retval) {
1545 LOG_ERROR("Could not read hw generated ECC from IRAM");
1546 return retval;
1547 }
1548 static uint8_t ecc[24];
1549 slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
1550 /* Copy ECC from flash using correct layout */
1551 static uint8_t fecc[24];/* max size */
1552 int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
1553 int i;
1554 for (i = 0; i < ecc_count * 3; i++)
1555 fecc[i] = foob[layout[i]];
1556 /* Compare ECC and possibly correct data */
1557 for (i = 0; i < ecc_count; i++) {
1558 retval = nand_correct_data(nand, data + 256*i, &fecc[i * 3],
1559 &ecc[i * 3]);
1560 if (retval > 0)
1561 LOG_WARNING("error detected and corrected: %d/%d",
1562 page, i);
1563 if (retval < 0)
1564 break;
1565 }
1566 if (i == ecc_count)
1567 retval = ERROR_OK;
1568 else {
1569 LOG_ERROR("uncorrectable error detected: %d/%d", page, i);
1570 retval = ERROR_NAND_OPERATION_FAILED;
1571 }
1572 return retval;
1573 }
1574
1575 static int lpc32xx_read_page(struct nand_device *nand, uint32_t page,
1576 uint8_t *data, uint32_t data_size,
1577 uint8_t *oob, uint32_t oob_size)
1578 {
1579 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1580 struct target *target = nand->target;
1581 int retval = ERROR_OK;
1582
1583 if (target->state != TARGET_HALTED) {
1584 LOG_ERROR("target must be halted to use LPC32xx "
1585 "NAND flash controller");
1586 return ERROR_NAND_OPERATION_FAILED;
1587 }
1588
1589 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
1590 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
1591 return ERROR_NAND_OPERATION_FAILED;
1592 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
1593 if (data_size > (uint32_t)nand->page_size) {
1594 LOG_ERROR("data size exceeds page size");
1595 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1596 }
1597 retval = lpc32xx_read_page_mlc(nand, page, data, data_size,
1598 oob, oob_size);
1599 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
1600 struct working_area *pworking_area;
1601
1602 retval = target_alloc_working_area(target,
1603 nand->page_size + 0x200,
1604 &pworking_area);
1605 if (retval != ERROR_OK) {
1606 LOG_ERROR("Can't allocate working area in "
1607 "LPC internal RAM");
1608 return ERROR_FLASH_OPERATION_FAILED;
1609 }
1610 retval = lpc32xx_read_page_slc(nand, pworking_area, page,
1611 data, data_size, oob, oob_size);
1612 target_free_working_area(target, pworking_area);
1613 }
1614
1615 return retval;
1616 }
1617
1618 static int lpc32xx_controller_ready(struct nand_device *nand, int timeout)
1619 {
1620 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1621 struct target *target = nand->target;
1622 int retval;
1623
1624 if (target->state != TARGET_HALTED) {
1625 LOG_ERROR("target must be halted to use LPC32xx "
1626 "NAND flash controller");
1627 return ERROR_NAND_OPERATION_FAILED;
1628 }
1629
1630 LOG_DEBUG("lpc32xx_controller_ready count start=%d", timeout);
1631
1632 do {
1633 if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
1634 uint8_t status;
1635
1636 /* Read MLC_ISR, wait for controller to become ready */
1637 retval = target_read_u8(target, 0x200b8048, &status);
1638 if (ERROR_OK != retval) {
1639 LOG_ERROR("could not set MLC_STAT");
1640 return ERROR_NAND_OPERATION_FAILED;
1641 }
1642
1643 if (status & 2) {
1644 LOG_DEBUG("lpc32xx_controller_ready count=%d",
1645 timeout);
1646 return 1;
1647 }
1648 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
1649 uint32_t status;
1650
1651 /* Read SLC_STAT and check READY bit */
1652 retval = target_read_u32(target, 0x20020018, &status);
1653 if (ERROR_OK != retval) {
1654 LOG_ERROR("could not set SLC_STAT");
1655 return ERROR_NAND_OPERATION_FAILED;
1656 }
1657
1658 if (status & 1) {
1659 LOG_DEBUG("lpc32xx_controller_ready count=%d",
1660 timeout);
1661 return 1;
1662 }
1663 }
1664
1665 alive_sleep(1);
1666 } while (timeout-- > 0);
1667
1668 return 0;
1669 }
1670
1671 static int lpc32xx_nand_ready(struct nand_device *nand, int timeout)
1672 {
1673 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1674 struct target *target = nand->target;
1675 int retval;
1676
1677 if (target->state != TARGET_HALTED) {
1678 LOG_ERROR("target must be halted to use LPC32xx "
1679 "NAND flash controller");
1680 return ERROR_NAND_OPERATION_FAILED;
1681 }
1682
1683 LOG_DEBUG("lpc32xx_nand_ready count start=%d", timeout);
1684
1685 do {
1686 if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
1687 uint8_t status = 0x0;
1688
1689 /* Read MLC_ISR, wait for NAND flash device to
1690 * become ready */
1691 retval = target_read_u8(target, 0x200b8048, &status);
1692 if (ERROR_OK != retval) {
1693 LOG_ERROR("could not read MLC_ISR");
1694 return ERROR_NAND_OPERATION_FAILED;
1695 }
1696
1697 if (status & 1) {
1698 LOG_DEBUG("lpc32xx_nand_ready count end=%d",
1699 timeout);
1700 return 1;
1701 }
1702 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
1703 uint32_t status = 0x0;
1704
1705 /* Read SLC_STAT and check READY bit */
1706 retval = target_read_u32(target, 0x20020018, &status);
1707 if (ERROR_OK != retval) {
1708 LOG_ERROR("could not read SLC_STAT");
1709 return ERROR_NAND_OPERATION_FAILED;
1710 }
1711
1712 if (status & 1) {
1713 LOG_DEBUG("lpc32xx_nand_ready count end=%d",
1714 timeout);
1715 return 1;
1716 }
1717 }
1718
1719 alive_sleep(1);
1720 } while (timeout-- > 0);
1721
1722 return 0;
1723 }
1724
1725 static int lpc32xx_tc_ready(struct nand_device *nand, int timeout)
1726 {
1727 struct target *target = nand->target;
1728
1729 LOG_DEBUG("lpc32xx_tc_ready count start=%d", timeout);
1730
1731 do {
1732 uint32_t status = 0x0;
1733 int retval;
1734 /* Read SLC_INT_STAT and check INT_TC_STAT bit */
1735 retval = target_read_u32(target, 0x2002001c, &status);
1736 if (ERROR_OK != retval) {
1737 LOG_ERROR("Could not read SLC_INT_STAT");
1738 return 0;
1739 }
1740 if (status & 2) {
1741 LOG_DEBUG("lpc32xx_tc_ready count=%d", timeout);
1742 return 1;
1743 }
1744
1745 alive_sleep(1);
1746 } while (timeout-- > 0);
1747
1748 return 0;
1749 }
1750
1751 COMMAND_HANDLER(handle_lpc32xx_select_command)
1752 {
1753 struct lpc32xx_nand_controller *lpc32xx_info = NULL;
1754 char *selected[] = {
1755 "no", "mlc", "slc"
1756 };
1757
1758 if ((CMD_ARGC < 1) || (CMD_ARGC > 3))
1759 return ERROR_COMMAND_SYNTAX_ERROR;
1760
1761 unsigned num;
1762 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
1763 struct nand_device *nand = get_nand_device_by_num(num);
1764 if (!nand) {
1765 command_print(CMD_CTX, "nand device '#%s' is out of bounds",
1766 CMD_ARGV[0]);
1767 return ERROR_OK;
1768 }
1769
1770 lpc32xx_info = nand->controller_priv;
1771
1772 if (CMD_ARGC >= 2) {
1773 if (strcmp(CMD_ARGV[1], "mlc") == 0) {
1774 lpc32xx_info->selected_controller =
1775 LPC32xx_MLC_CONTROLLER;
1776 } else if (strcmp(CMD_ARGV[1], "slc") == 0) {
1777 lpc32xx_info->selected_controller =
1778 LPC32xx_SLC_CONTROLLER;
1779 } else
1780 return ERROR_COMMAND_SYNTAX_ERROR;
1781 }
1782
1783 command_print(CMD_CTX, "%s controller selected",
1784 selected[lpc32xx_info->selected_controller]);
1785
1786 return ERROR_OK;
1787 }
1788
1789 static const struct command_registration lpc32xx_exec_command_handlers[] = {
1790 {
1791 .name = "select",
1792 .handler = handle_lpc32xx_select_command,
1793 .mode = COMMAND_EXEC,
1794 .help = "select MLC or SLC controller (default is MLC)",
1795 .usage = "bank_id ['mlc'|'slc' ]",
1796 },
1797 COMMAND_REGISTRATION_DONE
1798 };
1799 static const struct command_registration lpc32xx_command_handler[] = {
1800 {
1801 .name = "lpc32xx",
1802 .mode = COMMAND_ANY,
1803 .help = "LPC32xx NAND flash controller commands",
1804 .usage = "",
1805 .chain = lpc32xx_exec_command_handlers,
1806 },
1807 COMMAND_REGISTRATION_DONE
1808 };
1809
1810 struct nand_flash_controller lpc32xx_nand_controller = {
1811 .name = "lpc32xx",
1812 .commands = lpc32xx_command_handler,
1813 .nand_device_command = lpc32xx_nand_device_command,
1814 .init = lpc32xx_init,
1815 .reset = lpc32xx_reset,
1816 .command = lpc32xx_command,
1817 .address = lpc32xx_address,
1818 .write_data = lpc32xx_write_data,
1819 .read_data = lpc32xx_read_data,
1820 .write_page = lpc32xx_write_page,
1821 .read_page = lpc32xx_read_page,
1822 .nand_ready = lpc32xx_nand_ready,
1823 };
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|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)