src/flash/nand/core.h

   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath <Dominic.Rath@gmx.de>              *
   3  *   Copyright (C) 2009 Zachary T Welch <zw@superlucidity.net>             *
   4  *                                                                         *
   5  *   Partially based on linux/include/linux/mtd/nand.h                     *
   6  *   Copyright (C) 2000 David Woodhouse <dwmw2@mvhi.com>                   *
   7  *   Copyright (C) 2000 Steven J. Hill <sjhill@realitydiluted.com>         *
   8  *   Copyright (C) 2000 Thomas Gleixner <tglx@linutronix.de>               *
   9  *                                                                         *
  10  *   This program is free software; you can redistribute it and/or modify  *
  11  *   it under the terms of the GNU General Public License as published by  *
  12  *   the Free Software Foundation; either version 2 of the License, or     *
  13  *   (at your option) any later version.                                   *
  14  *                                                                         *
  15  *   This program is distributed in the hope that it will be useful,       *
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  *   GNU General Public License for more details.                          *
  19  *                                                                         *
  20  *   You should have received a copy of the GNU General Public License     *
  21  *   along with this program; if not, write to the                         *
  22  *   Free Software Foundation, Inc.,                                       *
  23  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  24  ***************************************************************************/
  25
  26 #ifndef FLASH_NAND_CORE_H
  27 #define FLASH_NAND_CORE_H
  28
  29 #include <flash/common.h>
  30
  31 /**
  32  * Representation of a single NAND block in a NAND device.
  33  */
  34 struct nand_block {
  35         /** Offset to the block. */
  36         uint32_t offset;
  37
  38         /** Size of the block. */
  39         uint32_t size;
  40
  41         /** True if the block has been erased. */
  42         int is_erased;
  43
  44         /** True if the block is bad. */
  45         int is_bad;
  46 };
  47
  48 struct nand_oobfree {
  49         int offset;
  50         int length;
  51 };
  52
  53 struct nand_ecclayout {
  54         int eccbytes;
  55         int eccpos[64];
  56         int oobavail;
  57         struct nand_oobfree oobfree[2];
  58 };
  59
  60 struct nand_device {
  61         const char *name;
  62         struct target *target;
  63         struct nand_flash_controller *controller;
  64         void *controller_priv;
  65         struct nand_manufacturer *manufacturer;
  66         struct nand_info *device;
  67         int bus_width;
  68         int address_cycles;
  69         int page_size;
  70         int erase_size;
  71         int use_raw;
  72         int num_blocks;
  73         struct nand_block *blocks;
  74         struct nand_device *next;
  75 };
  76
  77 /* NAND Flash Manufacturer ID Codes
  78  */
  79 enum {
  80         NAND_MFR_TOSHIBA = 0x98,
  81         NAND_MFR_SAMSUNG = 0xec,
  82         NAND_MFR_FUJITSU = 0x04,
  83         NAND_MFR_NATIONAL = 0x8f,
  84         NAND_MFR_RENESAS = 0x07,
  85         NAND_MFR_STMICRO = 0x20,
  86         NAND_MFR_HYNIX = 0xad,
  87         NAND_MFR_MICRON = 0x2c,
  88 };
  89
  90 struct nand_manufacturer {
  91         int id;
  92         const char *name;
  93 };
  94
  95 struct nand_info {
  96         int mfr_id;
  97         int id;
  98         int page_size;
  99         int chip_size;
 100         int erase_size;
 101         int options;
 102         const char *name;
 103 };
 104
 105 /* Option constants for bizarre disfunctionality and real features
 106  */
 107 enum {
 108         /* Chip can not auto increment pages */
 109         NAND_NO_AUTOINCR = 0x00000001,
 110
 111         /* Buswitdh is 16 bit */
 112         NAND_BUSWIDTH_16 = 0x00000002,
 113
 114         /* Device supports partial programming without padding */
 115         NAND_NO_PADDING = 0x00000004,
 116
 117         /* Chip has cache program function */
 118         NAND_CACHEPRG = 0x00000008,
 119
 120         /* Chip has copy back function */
 121         NAND_COPYBACK = 0x00000010,
 122
 123         /* AND Chip which has 4 banks and a confusing page / block
 124          * assignment. See Renesas datasheet for further information */
 125         NAND_IS_AND = 0x00000020,
 126
 127         /* Chip has a array of 4 pages which can be read without
 128          * additional ready /busy waits */
 129         NAND_4PAGE_ARRAY = 0x00000040,
 130
 131         /* Chip requires that BBT is periodically rewritten to prevent
 132          * bits from adjacent blocks from 'leaking' in altering data.
 133          * This happens with the Renesas AG-AND chips, possibly others.  */
 134         BBT_AUTO_REFRESH = 0x00000080,
 135
 136         /* Chip does not require ready check on read. True
 137          * for all large page devices, as they do not support
 138          * autoincrement.*/
 139         NAND_NO_READRDY = 0x00000100,
 140
 141         /* Options valid for Samsung large page devices */
 142         NAND_SAMSUNG_LP_OPTIONS = (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK),
 143
 144         /* Options for new chips with large page size. The pagesize and the
 145          * erasesize is determined from the extended id bytes
 146          */
 147         LP_OPTIONS = (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR),
 148         LP_OPTIONS16 = (LP_OPTIONS | NAND_BUSWIDTH_16),
 149 };
 150
 151 enum {
 152         /* Standard NAND flash commands */
 153         NAND_CMD_READ0 = 0x0,
 154         NAND_CMD_READ1 = 0x1,
 155         NAND_CMD_RNDOUT = 0x5,
 156         NAND_CMD_PAGEPROG = 0x10,
 157         NAND_CMD_READOOB = 0x50,
 158         NAND_CMD_ERASE1 = 0x60,
 159         NAND_CMD_STATUS = 0x70,
 160         NAND_CMD_STATUS_MULTI = 0x71,
 161         NAND_CMD_SEQIN = 0x80,
 162         NAND_CMD_RNDIN = 0x85,
 163         NAND_CMD_READID = 0x90,
 164         NAND_CMD_ERASE2 = 0xd0,
 165         NAND_CMD_RESET = 0xff,
 166
 167         /* Extended commands for large page devices */
 168         NAND_CMD_READSTART = 0x30,
 169         NAND_CMD_RNDOUTSTART = 0xE0,
 170         NAND_CMD_CACHEDPROG = 0x15,
 171 };
 172
 173 /* Status bits */
 174 enum {
 175         NAND_STATUS_FAIL = 0x01,
 176         NAND_STATUS_FAIL_N1 = 0x02,
 177         NAND_STATUS_TRUE_READY = 0x20,
 178         NAND_STATUS_READY = 0x40,
 179         NAND_STATUS_WP = 0x80,
 180 };
 181
 182 /* OOB (spare) data formats */
 183 enum oob_formats {
 184         NAND_OOB_NONE = 0x0,    /* no OOB data at all */
 185         NAND_OOB_RAW = 0x1,             /* raw OOB data (16 bytes for 512b page sizes, 64 bytes for
 186                                          *2048b page sizes) */
 187         NAND_OOB_ONLY = 0x2,    /* only OOB data */
 188         NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
 189         NAND_OOB_HW_ECC = 0x20, /* when writing, use HW ECC (as opposed to no ECC) */
 190         NAND_OOB_SW_ECC_KW = 0x40,      /* when writing, use Marvell's Kirkwood bootrom format */
 191         NAND_OOB_JFFS2 = 0x100, /* when writing, use JFFS2 OOB layout */
 192         NAND_OOB_YAFFS2 = 0x100,/* when writing, use YAFFS2 OOB layout */
 193 };
 194
 195
 196 struct nand_device *get_nand_device_by_num(int num);
 197
 198 int nand_page_command(struct nand_device *nand, uint32_t page,
 199                       uint8_t cmd, bool oob_only);
 200
 201 int nand_read_data_page(struct nand_device *nand, uint8_t *data, uint32_t size);
 202 int nand_write_data_page(struct nand_device *nand,
 203                          uint8_t *data, uint32_t size);
 204
 205 int nand_write_finish(struct nand_device *nand);
 206
 207 int nand_read_page_raw(struct nand_device *nand, uint32_t page,
 208                        uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
 209 int nand_write_page_raw(struct nand_device *nand, uint32_t page,
 210                         uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
 211
 212 int nand_read_status(struct nand_device *nand, uint8_t *status);
 213
 214 int nand_calculate_ecc(struct nand_device *nand,
 215                        const uint8_t *dat, uint8_t *ecc_code);
 216 int nand_calculate_ecc_kw(struct nand_device *nand,
 217                           const uint8_t *dat, uint8_t *ecc_code);
 218
 219 int nand_register_commands(struct command_context *cmd_ctx);
 220
 221 /** helper for parsing a nand device command argument string */
 222 COMMAND_HELPER(nand_command_get_device, unsigned name_index,
 223         struct nand_device **nand);
 224
 225
 226 #define         ERROR_NAND_DEVICE_INVALID               (-1100)
 227 #define         ERROR_NAND_OPERATION_FAILED             (-1101)
 228 #define         ERROR_NAND_OPERATION_TIMEOUT    (-1102)
 229 #define         ERROR_NAND_OPERATION_NOT_SUPPORTED      (-1103)
 230 #define         ERROR_NAND_DEVICE_NOT_PROBED    (-1104)
 231 #define         ERROR_NAND_ERROR_CORRECTION_FAILED      (-1105)
 232 #define         ERROR_NAND_NO_BUFFER                    (-1106)
 233
 234 #endif  /* FLASH_NAND_CORE_H */