815c7661fda3d26131a7da67cecb8ae7f395060a
[openocd.git] / src / flash / nand / core.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath <Dominic.Rath@gmx.de> *
3 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
4 * Copyright (C) 2009 Zachary T Welch <zw@superlucidity.net> *
5 * *
6 * Partially based on drivers/mtd/nand_ids.c from Linux. *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
22 ***************************************************************************/
23
24 #ifdef HAVE_CONFIG_H
25 #include "config.h"
26 #endif
27
28 #include "imp.h"
29
30 /* configured NAND devices and NAND Flash command handler */
31 struct nand_device *nand_devices;
32
33 void nand_device_add(struct nand_device *c)
34 {
35 if (nand_devices) {
36 struct nand_device *p = nand_devices;
37 while (p && p->next)
38 p = p->next;
39 p->next = c;
40 } else
41 nand_devices = c;
42 }
43
44
45 /* Chip ID list
46 *
47 * Manufacturer, ID code, pagesize, chipsize in MegaByte, eraseblock size,
48 * options, name
49 *
50 * Pagesize; 0, 256, 512
51 * 0 get this information from the extended chip ID
52 * 256 256 Byte page size
53 * 512 512 Byte page size
54 */
55 static struct nand_info nand_flash_ids[] = {
56 /* Vendor Specific Entries */
57 { NAND_MFR_SAMSUNG, 0xD5, 8192, 2048, 0x100000, LP_OPTIONS,
58 "K9GAG08 2GB NAND 3.3V x8 MLC 2b/cell"},
59 { NAND_MFR_SAMSUNG, 0xD7, 8192, 4096, 0x100000, LP_OPTIONS,
60 "K9LBG08 4GB NAND 3.3V x8 MLC 2b/cell"},
61
62 /* start "museum" IDs */
63 { 0x0, 0x6e, 256, 1, 0x1000, 0, "NAND 1MiB 5V 8-bit"},
64 { 0x0, 0x64, 256, 2, 0x1000, 0, "NAND 2MiB 5V 8-bit"},
65 { 0x0, 0x6b, 512, 4, 0x2000, 0, "NAND 4MiB 5V 8-bit"},
66 { 0x0, 0xe8, 256, 1, 0x1000, 0, "NAND 1MiB 3.3V 8-bit"},
67 { 0x0, 0xec, 256, 1, 0x1000, 0, "NAND 1MiB 3.3V 8-bit"},
68 { 0x0, 0xea, 256, 2, 0x1000, 0, "NAND 2MiB 3.3V 8-bit"},
69 { 0x0, 0xd5, 512, 4, 0x2000, 0, "NAND 4MiB 3.3V 8-bit"},
70 { 0x0, 0xe3, 512, 4, 0x2000, 0, "NAND 4MiB 3.3V 8-bit"},
71 { 0x0, 0xe5, 512, 4, 0x2000, 0, "NAND 4MiB 3.3V 8-bit"},
72 { 0x0, 0xd6, 512, 8, 0x2000, 0, "NAND 8MiB 3.3V 8-bit"},
73
74 { 0x0, 0x39, 512, 8, 0x2000, 0, "NAND 8MiB 1.8V 8-bit"},
75 { 0x0, 0xe6, 512, 8, 0x2000, 0, "NAND 8MiB 3.3V 8-bit"},
76 { 0x0, 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16, "NAND 8MiB 1.8V 16-bit"},
77 { 0x0, 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16, "NAND 8MiB 3.3V 16-bit"},
78 /* end "museum" IDs */
79
80 { 0x0, 0x33, 512, 16, 0x4000, 0, "NAND 16MiB 1.8V 8-bit"},
81 { 0x0, 0x73, 512, 16, 0x4000, 0, "NAND 16MiB 3.3V 8-bit"},
82 { 0x0, 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16, "NAND 16MiB 1.8V 16-bit"},
83 { 0x0, 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16, "NAND 16MiB 3.3V 16-bit"},
84
85 { 0x0, 0x35, 512, 32, 0x4000, 0, "NAND 32MiB 1.8V 8-bit"},
86 { 0x0, 0x75, 512, 32, 0x4000, 0, "NAND 32MiB 3.3V 8-bit"},
87 { 0x0, 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16, "NAND 32MiB 1.8V 16-bit"},
88 { 0x0, 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16, "NAND 32MiB 3.3V 16-bit"},
89
90 { 0x0, 0x36, 512, 64, 0x4000, 0, "NAND 64MiB 1.8V 8-bit"},
91 { 0x0, 0x76, 512, 64, 0x4000, 0, "NAND 64MiB 3.3V 8-bit"},
92 { 0x0, 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16, "NAND 64MiB 1.8V 16-bit"},
93 { 0x0, 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16, "NAND 64MiB 3.3V 16-bit"},
94
95 { 0x0, 0x78, 512, 128, 0x4000, 0, "NAND 128MiB 1.8V 8-bit"},
96 { 0x0, 0x39, 512, 128, 0x4000, 0, "NAND 128MiB 1.8V 8-bit"},
97 { 0x0, 0x79, 512, 128, 0x4000, 0, "NAND 128MiB 3.3V 8-bit"},
98 { 0x0, 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16, "NAND 128MiB 1.8V 16-bit"},
99 { 0x0, 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16, "NAND 128MiB 1.8V 16-bit"},
100 { 0x0, 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16, "NAND 128MiB 3.3V 16-bit"},
101 { 0x0, 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16, "NAND 128MiB 3.3V 16-bit"},
102
103 { 0x0, 0x71, 512, 256, 0x4000, 0, "NAND 256MiB 3.3V 8-bit"},
104
105 { 0x0, 0xA2, 0, 64, 0, LP_OPTIONS, "NAND 64MiB 1.8V 8-bit"},
106 { 0x0, 0xF2, 0, 64, 0, LP_OPTIONS, "NAND 64MiB 3.3V 8-bit"},
107 { 0x0, 0xB2, 0, 64, 0, LP_OPTIONS16, "NAND 64MiB 1.8V 16-bit"},
108 { 0x0, 0xC2, 0, 64, 0, LP_OPTIONS16, "NAND 64MiB 3.3V 16-bit"},
109
110 { 0x0, 0xA1, 0, 128, 0, LP_OPTIONS, "NAND 128MiB 1.8V 8-bit"},
111 { 0x0, 0xF1, 0, 128, 0, LP_OPTIONS, "NAND 128MiB 3.3V 8-bit"},
112 { 0x0, 0xB1, 0, 128, 0, LP_OPTIONS16, "NAND 128MiB 1.8V 16-bit"},
113 { 0x0, 0xC1, 0, 128, 0, LP_OPTIONS16, "NAND 128MiB 3.3V 16-bit"},
114
115 { 0x0, 0xAA, 0, 256, 0, LP_OPTIONS, "NAND 256MiB 1.8V 8-bit"},
116 { 0x0, 0xDA, 0, 256, 0, LP_OPTIONS, "NAND 256MiB 3.3V 8-bit"},
117 { 0x0, 0xBA, 0, 256, 0, LP_OPTIONS16, "NAND 256MiB 1.8V 16-bit"},
118 { 0x0, 0xCA, 0, 256, 0, LP_OPTIONS16, "NAND 256MiB 3.3V 16-bit"},
119
120 { 0x0, 0xAC, 0, 512, 0, LP_OPTIONS, "NAND 512MiB 1.8V 8-bit"},
121 { 0x0, 0xDC, 0, 512, 0, LP_OPTIONS, "NAND 512MiB 3.3V 8-bit"},
122 { 0x0, 0xBC, 0, 512, 0, LP_OPTIONS16, "NAND 512MiB 1.8V 16-bit"},
123 { 0x0, 0xCC, 0, 512, 0, LP_OPTIONS16, "NAND 512MiB 3.3V 16-bit"},
124
125 { 0x0, 0xA3, 0, 1024, 0, LP_OPTIONS, "NAND 1GiB 1.8V 8-bit"},
126 { 0x0, 0xD3, 0, 1024, 0, LP_OPTIONS, "NAND 1GiB 3.3V 8-bit"},
127 { 0x0, 0xB3, 0, 1024, 0, LP_OPTIONS16, "NAND 1GiB 1.8V 16-bit"},
128 { 0x0, 0xC3, 0, 1024, 0, LP_OPTIONS16, "NAND 1GiB 3.3V 16-bit"},
129
130 { 0x0, 0xA5, 0, 2048, 0, LP_OPTIONS, "NAND 2GiB 1.8V 8-bit"},
131 { 0x0, 0xD5, 0, 8192, 0, LP_OPTIONS, "NAND 2GiB 3.3V 8-bit"},
132 { 0x0, 0xB5, 0, 2048, 0, LP_OPTIONS16, "NAND 2GiB 1.8V 16-bit"},
133 { 0x0, 0xC5, 0, 2048, 0, LP_OPTIONS16, "NAND 2GiB 3.3V 16-bit"},
134
135 { 0x0, 0x48, 0, 2048, 0, LP_OPTIONS, "NAND 2GiB 3.3V 8-bit"},
136
137 {0, 0, 0, 0, 0, 0, NULL}
138 };
139
140 /* Manufacturer ID list
141 */
142 static struct nand_manufacturer nand_manuf_ids[] = {
143 {0x0, "unknown"},
144 {NAND_MFR_TOSHIBA, "Toshiba"},
145 {NAND_MFR_SAMSUNG, "Samsung"},
146 {NAND_MFR_FUJITSU, "Fujitsu"},
147 {NAND_MFR_NATIONAL, "National"},
148 {NAND_MFR_RENESAS, "Renesas"},
149 {NAND_MFR_STMICRO, "ST Micro"},
150 {NAND_MFR_HYNIX, "Hynix"},
151 {NAND_MFR_MICRON, "Micron"},
152 {0x0, NULL},
153 };
154
155 /*
156 * Define default oob placement schemes for large and small page devices
157 */
158
159 #if 0
160 static struct nand_ecclayout nand_oob_8 = {
161 .eccbytes = 3,
162 .eccpos = {0, 1, 2},
163 .oobfree = {
164 {.offset = 3,
165 .length = 2},
166 {.offset = 6,
167 .length = 2}
168 }
169 };
170 #endif
171
172 /**
173 * Returns the flash bank specified by @a name, which matches the
174 * driver name and a suffix (option) specify the driver-specific
175 * bank number. The suffix consists of the '.' and the driver-specific
176 * bank number: when two davinci banks are defined, then 'davinci.1' refers
177 * to the second (e.g. DM355EVM).
178 */
179 static struct nand_device *get_nand_device_by_name(const char *name)
180 {
181 unsigned requested = get_flash_name_index(name);
182 unsigned found = 0;
183
184 struct nand_device *nand;
185 for (nand = nand_devices; NULL != nand; nand = nand->next) {
186 if (strcmp(nand->name, name) == 0)
187 return nand;
188 if (!flash_driver_name_matches(nand->controller->name, name))
189 continue;
190 if (++found < requested)
191 continue;
192 return nand;
193 }
194 return NULL;
195 }
196
197 struct nand_device *get_nand_device_by_num(int num)
198 {
199 struct nand_device *p;
200 int i = 0;
201
202 for (p = nand_devices; p; p = p->next) {
203 if (i++ == num)
204 return p;
205 }
206
207 return NULL;
208 }
209
210 COMMAND_HELPER(nand_command_get_device, unsigned name_index,
211 struct nand_device **nand)
212 {
213 const char *str = CMD_ARGV[name_index];
214 *nand = get_nand_device_by_name(str);
215 if (*nand)
216 return ERROR_OK;
217
218 unsigned num;
219 COMMAND_PARSE_NUMBER(uint, str, num);
220 *nand = get_nand_device_by_num(num);
221 if (!*nand) {
222 command_print(CMD_CTX, "NAND flash device '%s' not found", str);
223 return ERROR_COMMAND_SYNTAX_ERROR;
224 }
225 return ERROR_OK;
226 }
227
228 int nand_build_bbt(struct nand_device *nand, int first, int last)
229 {
230 uint32_t page;
231 int i;
232 int pages_per_block = (nand->erase_size / nand->page_size);
233 uint8_t oob[6];
234 int ret;
235
236 if ((first < 0) || (first >= nand->num_blocks))
237 first = 0;
238
239 if ((last >= nand->num_blocks) || (last == -1))
240 last = nand->num_blocks - 1;
241
242 page = first * pages_per_block;
243 for (i = first; i <= last; i++) {
244 ret = nand_read_page(nand, page, NULL, 0, oob, 6);
245 if (ret != ERROR_OK)
246 return ret;
247
248 if (((nand->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
249 || (((nand->page_size == 512) && (oob[5] != 0xff)) ||
250 ((nand->page_size == 2048) && (oob[0] != 0xff)))) {
251 LOG_WARNING("bad block: %i", i);
252 nand->blocks[i].is_bad = 1;
253 } else
254 nand->blocks[i].is_bad = 0;
255
256 page += pages_per_block;
257 }
258
259 return ERROR_OK;
260 }
261
262 int nand_read_status(struct nand_device *nand, uint8_t *status)
263 {
264 if (!nand->device)
265 return ERROR_NAND_DEVICE_NOT_PROBED;
266
267 /* Send read status command */
268 nand->controller->command(nand, NAND_CMD_STATUS);
269
270 alive_sleep(1);
271
272 /* read status */
273 if (nand->device->options & NAND_BUSWIDTH_16) {
274 uint16_t data;
275 nand->controller->read_data(nand, &data);
276 *status = data & 0xff;
277 } else
278 nand->controller->read_data(nand, status);
279
280 return ERROR_OK;
281 }
282
283 static int nand_poll_ready(struct nand_device *nand, int timeout)
284 {
285 uint8_t status;
286
287 nand->controller->command(nand, NAND_CMD_STATUS);
288 do {
289 if (nand->device->options & NAND_BUSWIDTH_16) {
290 uint16_t data;
291 nand->controller->read_data(nand, &data);
292 status = data & 0xff;
293 } else
294 nand->controller->read_data(nand, &status);
295 if (status & NAND_STATUS_READY)
296 break;
297 alive_sleep(1);
298 } while (timeout--);
299
300 return (status & NAND_STATUS_READY) != 0;
301 }
302
303 int nand_probe(struct nand_device *nand)
304 {
305 uint8_t manufacturer_id, device_id;
306 uint8_t id_buff[6];
307 int retval;
308 int i;
309
310 /* clear device data */
311 nand->device = NULL;
312 nand->manufacturer = NULL;
313
314 /* clear device parameters */
315 nand->bus_width = 0;
316 nand->address_cycles = 0;
317 nand->page_size = 0;
318 nand->erase_size = 0;
319
320 /* initialize controller (device parameters are zero, use controller default) */
321 retval = nand->controller->init(nand);
322 if (retval != ERROR_OK) {
323 switch (retval) {
324 case ERROR_NAND_OPERATION_FAILED:
325 LOG_DEBUG("controller initialization failed");
326 return ERROR_NAND_OPERATION_FAILED;
327 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
328 LOG_ERROR(
329 "BUG: controller reported that it doesn't support default parameters");
330 return ERROR_NAND_OPERATION_FAILED;
331 default:
332 LOG_ERROR("BUG: unknown controller initialization failure");
333 return ERROR_NAND_OPERATION_FAILED;
334 }
335 }
336
337 nand->controller->command(nand, NAND_CMD_RESET);
338 nand->controller->reset(nand);
339
340 nand->controller->command(nand, NAND_CMD_READID);
341 nand->controller->address(nand, 0x0);
342
343 if (nand->bus_width == 8) {
344 nand->controller->read_data(nand, &manufacturer_id);
345 nand->controller->read_data(nand, &device_id);
346 } else {
347 uint16_t data_buf;
348 nand->controller->read_data(nand, &data_buf);
349 manufacturer_id = data_buf & 0xff;
350 nand->controller->read_data(nand, &data_buf);
351 device_id = data_buf & 0xff;
352 }
353
354 for (i = 0; nand_flash_ids[i].name; i++) {
355 if (nand_flash_ids[i].id == device_id &&
356 (nand_flash_ids[i].mfr_id == manufacturer_id ||
357 nand_flash_ids[i].mfr_id == 0)) {
358 nand->device = &nand_flash_ids[i];
359 break;
360 }
361 }
362
363 for (i = 0; nand_manuf_ids[i].name; i++) {
364 if (nand_manuf_ids[i].id == manufacturer_id) {
365 nand->manufacturer = &nand_manuf_ids[i];
366 break;
367 }
368 }
369
370 if (!nand->manufacturer) {
371 nand->manufacturer = &nand_manuf_ids[0];
372 nand->manufacturer->id = manufacturer_id;
373 }
374
375 if (!nand->device) {
376 LOG_ERROR(
377 "unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
378 manufacturer_id,
379 device_id);
380 return ERROR_NAND_OPERATION_FAILED;
381 }
382
383 LOG_DEBUG("found %s (%s)", nand->device->name, nand->manufacturer->name);
384
385 /* initialize device parameters */
386
387 /* bus width */
388 if (nand->device->options & NAND_BUSWIDTH_16)
389 nand->bus_width = 16;
390 else
391 nand->bus_width = 8;
392
393 /* Do we need extended device probe information? */
394 if (nand->device->page_size == 0 ||
395 nand->device->erase_size == 0) {
396 if (nand->bus_width == 8) {
397 nand->controller->read_data(nand, id_buff + 3);
398 nand->controller->read_data(nand, id_buff + 4);
399 nand->controller->read_data(nand, id_buff + 5);
400 } else {
401 uint16_t data_buf;
402
403 nand->controller->read_data(nand, &data_buf);
404 id_buff[3] = data_buf;
405
406 nand->controller->read_data(nand, &data_buf);
407 id_buff[4] = data_buf;
408
409 nand->controller->read_data(nand, &data_buf);
410 id_buff[5] = data_buf >> 8;
411 }
412 }
413
414 /* page size */
415 if (nand->device->page_size == 0)
416 nand->page_size = 1 << (10 + (id_buff[4] & 3));
417 else if (nand->device->page_size == 256) {
418 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
419 return ERROR_NAND_OPERATION_FAILED;
420 } else
421 nand->page_size = nand->device->page_size;
422
423 /* number of address cycles */
424 if (nand->page_size <= 512) {
425 /* small page devices */
426 if (nand->device->chip_size <= 32)
427 nand->address_cycles = 3;
428 else if (nand->device->chip_size <= 8*1024)
429 nand->address_cycles = 4;
430 else {
431 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
432 nand->address_cycles = 5;
433 }
434 } else {
435 /* large page devices */
436 if (nand->device->chip_size <= 128)
437 nand->address_cycles = 4;
438 else if (nand->device->chip_size <= 32*1024)
439 nand->address_cycles = 5;
440 else {
441 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
442 nand->address_cycles = 6;
443 }
444 }
445
446 /* erase size */
447 if (nand->device->erase_size == 0) {
448 switch ((id_buff[4] >> 4) & 3) {
449 case 0:
450 nand->erase_size = 64 << 10;
451 break;
452 case 1:
453 nand->erase_size = 128 << 10;
454 break;
455 case 2:
456 nand->erase_size = 256 << 10;
457 break;
458 case 3:
459 nand->erase_size = 512 << 10;
460 break;
461 }
462 } else
463 nand->erase_size = nand->device->erase_size;
464
465 /* initialize controller, but leave parameters at the controllers default */
466 retval = nand->controller->init(nand);
467 if (retval != ERROR_OK) {
468 switch (retval) {
469 case ERROR_NAND_OPERATION_FAILED:
470 LOG_DEBUG("controller initialization failed");
471 return ERROR_NAND_OPERATION_FAILED;
472 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
473 LOG_ERROR(
474 "controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
475 nand->bus_width,
476 nand->address_cycles,
477 nand->page_size);
478 return ERROR_NAND_OPERATION_FAILED;
479 default:
480 LOG_ERROR("BUG: unknown controller initialization failure");
481 return ERROR_NAND_OPERATION_FAILED;
482 }
483 }
484
485 nand->num_blocks = (nand->device->chip_size * 1024) / (nand->erase_size / 1024);
486 nand->blocks = malloc(sizeof(struct nand_block) * nand->num_blocks);
487
488 for (i = 0; i < nand->num_blocks; i++) {
489 nand->blocks[i].size = nand->erase_size;
490 nand->blocks[i].offset = i * nand->erase_size;
491 nand->blocks[i].is_erased = -1;
492 nand->blocks[i].is_bad = -1;
493 }
494
495 return ERROR_OK;
496 }
497
498 int nand_erase(struct nand_device *nand, int first_block, int last_block)
499 {
500 int i;
501 uint32_t page;
502 uint8_t status;
503 int retval;
504
505 if (!nand->device)
506 return ERROR_NAND_DEVICE_NOT_PROBED;
507
508 if ((first_block < 0) || (last_block >= nand->num_blocks))
509 return ERROR_COMMAND_SYNTAX_ERROR;
510
511 /* make sure we know if a block is bad before erasing it */
512 for (i = first_block; i <= last_block; i++) {
513 if (nand->blocks[i].is_bad == -1) {
514 nand_build_bbt(nand, i, last_block);
515 break;
516 }
517 }
518
519 for (i = first_block; i <= last_block; i++) {
520 /* Send erase setup command */
521 nand->controller->command(nand, NAND_CMD_ERASE1);
522
523 page = i * (nand->erase_size / nand->page_size);
524
525 /* Send page address */
526 if (nand->page_size <= 512) {
527 /* row */
528 nand->controller->address(nand, page & 0xff);
529 nand->controller->address(nand, (page >> 8) & 0xff);
530
531 /* 3rd cycle only on devices with more than 32 MiB */
532 if (nand->address_cycles >= 4)
533 nand->controller->address(nand, (page >> 16) & 0xff);
534
535 /* 4th cycle only on devices with more than 8 GiB */
536 if (nand->address_cycles >= 5)
537 nand->controller->address(nand, (page >> 24) & 0xff);
538 } else {
539 /* row */
540 nand->controller->address(nand, page & 0xff);
541 nand->controller->address(nand, (page >> 8) & 0xff);
542
543 /* 3rd cycle only on devices with more than 128 MiB */
544 if (nand->address_cycles >= 5)
545 nand->controller->address(nand, (page >> 16) & 0xff);
546 }
547
548 /* Send erase confirm command */
549 nand->controller->command(nand, NAND_CMD_ERASE2);
550
551 retval = nand->controller->nand_ready ?
552 nand->controller->nand_ready(nand, 1000) :
553 nand_poll_ready(nand, 1000);
554 if (!retval) {
555 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
556 return ERROR_NAND_OPERATION_TIMEOUT;
557 }
558
559 retval = nand_read_status(nand, &status);
560 if (retval != ERROR_OK) {
561 LOG_ERROR("couldn't read status");
562 return ERROR_NAND_OPERATION_FAILED;
563 }
564
565 if (status & 0x1) {
566 LOG_ERROR("didn't erase %sblock %d; status: 0x%2.2x",
567 (nand->blocks[i].is_bad == 1)
568 ? "bad " : "",
569 i, status);
570 /* continue; other blocks might still be erasable */
571 }
572
573 nand->blocks[i].is_erased = 1;
574 }
575
576 return ERROR_OK;
577 }
578
579 #if 0
580 static int nand_read_plain(struct nand_device *nand,
581 uint32_t address,
582 uint8_t *data,
583 uint32_t data_size)
584 {
585 uint8_t *page;
586
587 if (!nand->device)
588 return ERROR_NAND_DEVICE_NOT_PROBED;
589
590 if (address % nand->page_size) {
591 LOG_ERROR("reads need to be page aligned");
592 return ERROR_NAND_OPERATION_FAILED;
593 }
594
595 page = malloc(nand->page_size);
596
597 while (data_size > 0) {
598 uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
599 uint32_t page_address;
600
601
602 page_address = address / nand->page_size;
603
604 nand_read_page(nand, page_address, page, nand->page_size, NULL, 0);
605
606 memcpy(data, page, thisrun_size);
607
608 address += thisrun_size;
609 data += thisrun_size;
610 data_size -= thisrun_size;
611 }
612
613 free(page);
614
615 return ERROR_OK;
616 }
617
618 static int nand_write_plain(struct nand_device *nand,
619 uint32_t address,
620 uint8_t *data,
621 uint32_t data_size)
622 {
623 uint8_t *page;
624
625 if (!nand->device)
626 return ERROR_NAND_DEVICE_NOT_PROBED;
627
628 if (address % nand->page_size) {
629 LOG_ERROR("writes need to be page aligned");
630 return ERROR_NAND_OPERATION_FAILED;
631 }
632
633 page = malloc(nand->page_size);
634
635 while (data_size > 0) {
636 uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
637 uint32_t page_address;
638
639 memset(page, 0xff, nand->page_size);
640 memcpy(page, data, thisrun_size);
641
642 page_address = address / nand->page_size;
643
644 nand_write_page(nand, page_address, page, nand->page_size, NULL, 0);
645
646 address += thisrun_size;
647 data += thisrun_size;
648 data_size -= thisrun_size;
649 }
650
651 free(page);
652
653 return ERROR_OK;
654 }
655 #endif
656
657 int nand_write_page(struct nand_device *nand, uint32_t page,
658 uint8_t *data, uint32_t data_size,
659 uint8_t *oob, uint32_t oob_size)
660 {
661 uint32_t block;
662
663 if (!nand->device)
664 return ERROR_NAND_DEVICE_NOT_PROBED;
665
666 block = page / (nand->erase_size / nand->page_size);
667 if (nand->blocks[block].is_erased == 1)
668 nand->blocks[block].is_erased = 0;
669
670 if (nand->use_raw || nand->controller->write_page == NULL)
671 return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
672 else
673 return nand->controller->write_page(nand, page, data, data_size, oob, oob_size);
674 }
675
676 int nand_read_page(struct nand_device *nand, uint32_t page,
677 uint8_t *data, uint32_t data_size,
678 uint8_t *oob, uint32_t oob_size)
679 {
680 if (!nand->device)
681 return ERROR_NAND_DEVICE_NOT_PROBED;
682
683 if (nand->use_raw || nand->controller->read_page == NULL)
684 return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
685 else
686 return nand->controller->read_page(nand, page, data, data_size, oob, oob_size);
687 }
688
689 int nand_page_command(struct nand_device *nand, uint32_t page,
690 uint8_t cmd, bool oob_only)
691 {
692 if (!nand->device)
693 return ERROR_NAND_DEVICE_NOT_PROBED;
694
695 if (oob_only && NAND_CMD_READ0 == cmd && nand->page_size <= 512)
696 cmd = NAND_CMD_READOOB;
697
698 nand->controller->command(nand, cmd);
699
700 if (nand->page_size <= 512) {
701 /* small page device */
702
703 /* column (always 0, we start at the beginning of a page/OOB area) */
704 nand->controller->address(nand, 0x0);
705
706 /* row */
707 nand->controller->address(nand, page & 0xff);
708 nand->controller->address(nand, (page >> 8) & 0xff);
709
710 /* 4th cycle only on devices with more than 32 MiB */
711 if (nand->address_cycles >= 4)
712 nand->controller->address(nand, (page >> 16) & 0xff);
713
714 /* 5th cycle only on devices with more than 8 GiB */
715 if (nand->address_cycles >= 5)
716 nand->controller->address(nand, (page >> 24) & 0xff);
717 } else {
718 /* large page device */
719
720 /* column (0 when we start at the beginning of a page,
721 * or 2048 for the beginning of OOB area)
722 */
723 nand->controller->address(nand, 0x0);
724 if (oob_only)
725 nand->controller->address(nand, 0x8);
726 else
727 nand->controller->address(nand, 0x0);
728
729 /* row */
730 nand->controller->address(nand, page & 0xff);
731 nand->controller->address(nand, (page >> 8) & 0xff);
732
733 /* 5th cycle only on devices with more than 128 MiB */
734 if (nand->address_cycles >= 5)
735 nand->controller->address(nand, (page >> 16) & 0xff);
736
737 /* large page devices need a start command if reading */
738 if (NAND_CMD_READ0 == cmd)
739 nand->controller->command(nand, NAND_CMD_READSTART);
740 }
741
742 if (nand->controller->nand_ready) {
743 if (!nand->controller->nand_ready(nand, 100))
744 return ERROR_NAND_OPERATION_TIMEOUT;
745 } else {
746 /* nand_poll_read() cannot be used during nand read */
747 alive_sleep(1);
748 }
749
750 return ERROR_OK;
751 }
752
753 int nand_read_data_page(struct nand_device *nand, uint8_t *data, uint32_t size)
754 {
755 int retval = ERROR_NAND_NO_BUFFER;
756
757 if (nand->controller->read_block_data != NULL)
758 retval = (nand->controller->read_block_data)(nand, data, size);
759
760 if (ERROR_NAND_NO_BUFFER == retval) {
761 uint32_t i;
762 int incr = (nand->device->options & NAND_BUSWIDTH_16) ? 2 : 1;
763
764 retval = ERROR_OK;
765 for (i = 0; retval == ERROR_OK && i < size; i += incr) {
766 retval = nand->controller->read_data(nand, data);
767 data += incr;
768 }
769 }
770
771 return retval;
772 }
773
774 int nand_read_page_raw(struct nand_device *nand, uint32_t page,
775 uint8_t *data, uint32_t data_size,
776 uint8_t *oob, uint32_t oob_size)
777 {
778 int retval;
779
780 retval = nand_page_command(nand, page, NAND_CMD_READ0, !data);
781 if (ERROR_OK != retval)
782 return retval;
783
784 if (data)
785 nand_read_data_page(nand, data, data_size);
786
787 if (oob)
788 nand_read_data_page(nand, oob, oob_size);
789
790 return ERROR_OK;
791 }
792
793 int nand_write_data_page(struct nand_device *nand, uint8_t *data, uint32_t size)
794 {
795 int retval = ERROR_NAND_NO_BUFFER;
796
797 if (nand->controller->write_block_data != NULL)
798 retval = (nand->controller->write_block_data)(nand, data, size);
799
800 if (ERROR_NAND_NO_BUFFER == retval) {
801 bool is16bit = nand->device->options & NAND_BUSWIDTH_16;
802 uint32_t incr = is16bit ? 2 : 1;
803 uint16_t write_data;
804 uint32_t i;
805
806 for (i = 0; i < size; i += incr) {
807 if (is16bit)
808 write_data = le_to_h_u16(data);
809 else
810 write_data = *data;
811
812 retval = nand->controller->write_data(nand, write_data);
813 if (ERROR_OK != retval)
814 break;
815
816 data += incr;
817 }
818 }
819
820 return retval;
821 }
822
823 int nand_write_finish(struct nand_device *nand)
824 {
825 int retval;
826 uint8_t status;
827
828 nand->controller->command(nand, NAND_CMD_PAGEPROG);
829
830 retval = nand->controller->nand_ready ?
831 nand->controller->nand_ready(nand, 100) :
832 nand_poll_ready(nand, 100);
833 if (!retval)
834 return ERROR_NAND_OPERATION_TIMEOUT;
835
836 retval = nand_read_status(nand, &status);
837 if (ERROR_OK != retval) {
838 LOG_ERROR("couldn't read status");
839 return ERROR_NAND_OPERATION_FAILED;
840 }
841
842 if (status & NAND_STATUS_FAIL) {
843 LOG_ERROR("write operation didn't pass, status: 0x%2.2x",
844 status);
845 return ERROR_NAND_OPERATION_FAILED;
846 }
847
848 return ERROR_OK;
849 }
850
851 int nand_write_page_raw(struct nand_device *nand, uint32_t page,
852 uint8_t *data, uint32_t data_size,
853 uint8_t *oob, uint32_t oob_size)
854 {
855 int retval;
856
857 retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
858 if (ERROR_OK != retval)
859 return retval;
860
861 if (data) {
862 retval = nand_write_data_page(nand, data, data_size);
863 if (ERROR_OK != retval) {
864 LOG_ERROR("Unable to write data to NAND device");
865 return retval;
866 }
867 }
868
869 if (oob) {
870 retval = nand_write_data_page(nand, oob, oob_size);
871 if (ERROR_OK != retval) {
872 LOG_ERROR("Unable to write OOB data to NAND device");
873 return retval;
874 }
875 }
876
877 return nand_write_finish(nand);
878 }