2 * Copyright (C) 2009 by Dean Glazeski
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the
17 * Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 #include <target/arm.h>
25 #include <helper/log.h>
29 #define AT91C_PIOx_SODR (0x30) /**< Offset to PIO SODR. */
30 #define AT91C_PIOx_CODR (0x34) /**< Offset to PIO CODR. */
31 #define AT91C_PIOx_PDSR (0x3C) /**< Offset to PIO PDSR. */
32 #define AT91C_ECCx_CR (0x00) /**< Offset to ECC CR. */
33 #define AT91C_ECCx_SR (0x08) /**< Offset to ECC SR. */
34 #define AT91C_ECCx_PR (0x0C) /**< Offset to ECC PR. */
35 #define AT91C_ECCx_NPR (0x10) /**< Offset to ECC NPR. */
38 * Representation of a pin on an AT91SAM9 chip.
41 /** Target this pin is on. */
42 struct target
*target
;
44 /** Address of the PIO controller. */
52 * Private data for the controller that is stored in the NAND device structure.
54 struct at91sam9_nand
{
55 /** Target the NAND is attached to. */
56 struct target
*target
;
58 /** Address of the ECC controller for NAND. */
61 /** Address data is written to. */
64 /** Address commands are written to. */
67 /** Address addresses are written to. */
70 /** I/O structure for hosted reads/writes. */
71 struct arm_nand_data io
;
73 /** Pin representing the ready/~busy line. */
74 struct at91sam9_pin busy
;
76 /** Pin representing the chip enable. */
77 struct at91sam9_pin ce
;
81 * Checks if the target is halted and prints an error message if it isn't.
83 * @param target Target to be checked.
84 * @param label String label for where function is called from.
85 * @return True if the target is halted.
87 static int at91sam9_halted(struct target
*target
, const char *label
)
89 if (target
->state
== TARGET_HALTED
)
92 LOG_ERROR("Target must be halted to use NAND controller (%s)", label
);
97 * Initialize the AT91SAM9 NAND controller.
99 * @param nand NAND device the controller is attached to.
100 * @return Success or failure of initialization.
102 static int at91sam9_init(struct nand_device
*nand
)
104 struct at91sam9_nand
*info
= nand
->controller_priv
;
105 struct target
*target
= info
->target
;
107 if (!at91sam9_halted(target
, "init")) {
108 return ERROR_NAND_OPERATION_FAILED
;
115 * Enable NAND device attached to a controller.
117 * @param info NAND controller information for controlling NAND device.
118 * @return Success or failure of the enabling.
120 static int at91sam9_enable(struct at91sam9_nand
*info
)
122 struct target
*target
= info
->target
;
124 return target_write_u32(target
, info
->ce
.pioc
+ AT91C_PIOx_CODR
, 1 << info
->ce
.num
);
128 * Disable NAND device attached to a controller.
130 * @param info NAND controller information for controlling NAND device.
131 * @return Success or failure of the disabling.
133 static int at91sam9_disable(struct at91sam9_nand
*info
)
135 struct target
*target
= info
->target
;
137 return target_write_u32(target
, info
->ce
.pioc
+ AT91C_PIOx_SODR
, 1 << info
->ce
.num
);
141 * Send a command to the NAND device.
143 * @param nand NAND device to write the command to.
144 * @param command Command to be written.
145 * @return Success or failure of writing the command.
147 static int at91sam9_command(struct nand_device
*nand
, uint8_t command
)
149 struct at91sam9_nand
*info
= nand
->controller_priv
;
150 struct target
*target
= info
->target
;
152 if (!at91sam9_halted(target
, "command")) {
153 return ERROR_NAND_OPERATION_FAILED
;
156 at91sam9_enable(info
);
158 return target_write_u8(target
, info
->cmd
, command
);
162 * Reset the AT91SAM9 NAND controller.
164 * @param nand NAND device to be reset.
165 * @return Success or failure of reset.
167 static int at91sam9_reset(struct nand_device
*nand
)
169 struct at91sam9_nand
*info
= nand
->controller_priv
;
171 if (!at91sam9_halted(info
->target
, "reset")) {
172 return ERROR_NAND_OPERATION_FAILED
;
175 return at91sam9_disable(info
);
179 * Send an address to the NAND device attached to an AT91SAM9 NAND controller.
181 * @param nand NAND device to send the address to.
182 * @param address Address to be sent.
183 * @return Success or failure of sending the address.
185 static int at91sam9_address(struct nand_device
*nand
, uint8_t address
)
187 struct at91sam9_nand
*info
= nand
->controller_priv
;
188 struct target
*target
= info
->target
;
190 if (!at91sam9_halted(info
->target
, "address")) {
191 return ERROR_NAND_OPERATION_FAILED
;
194 return target_write_u8(target
, info
->addr
, address
);
198 * Read data directly from the NAND device attached to an AT91SAM9 NAND
201 * @param nand NAND device to read from.
202 * @param data Pointer to where the data should be put.
203 * @return Success or failure of reading the data.
205 static int at91sam9_read_data(struct nand_device
*nand
, void *data
)
207 struct at91sam9_nand
*info
= nand
->controller_priv
;
208 struct target
*target
= info
->target
;
210 if (!at91sam9_halted(info
->target
, "read data")) {
211 return ERROR_NAND_OPERATION_FAILED
;
214 return target_read_u8(target
, info
->data
, data
);
218 * Write data directly to the NAND device attached to an AT91SAM9 NAND
221 * @param nand NAND device to be written to.
222 * @param data Data to be written.
223 * @return Success or failure of the data write.
225 static int at91sam9_write_data(struct nand_device
*nand
, uint16_t data
)
227 struct at91sam9_nand
*info
= nand
->controller_priv
;
228 struct target
*target
= info
->target
;
230 if (!at91sam9_halted(target
, "write data")) {
231 return ERROR_NAND_OPERATION_FAILED
;
234 return target_write_u8(target
, info
->data
, data
);
238 * Determine if the NAND device is ready by looking at the ready/~busy pin.
240 * @param nand NAND device to check.
241 * @param timeout Time in milliseconds to wait for NAND to be ready.
242 * @return True if the NAND is ready in the timeout period.
244 static int at91sam9_nand_ready(struct nand_device
*nand
, int timeout
)
246 struct at91sam9_nand
*info
= nand
->controller_priv
;
247 struct target
*target
= info
->target
;
250 if (!at91sam9_halted(target
, "nand ready")) {
255 target_read_u32(target
, info
->busy
.pioc
+ AT91C_PIOx_PDSR
, &status
);
257 if (status
& (1 << info
->busy
.num
)) {
262 } while (timeout
-- > 0);
268 * Read a block of data from the NAND device attached to an AT91SAM9. This
269 * utilizes the ARM hosted NAND read function.
271 * @param nand NAND device to read from.
272 * @param data Pointer to where the read data should be placed.
273 * @param size Size of the data being read.
274 * @return Success or failure of the hosted read.
276 static int at91sam9_read_block_data(struct nand_device
*nand
, uint8_t *data
, int size
)
278 struct at91sam9_nand
*info
= nand
->controller_priv
;
279 struct arm_nand_data
*io
= &info
->io
;
282 if (!at91sam9_halted(info
->target
, "read block")) {
283 return ERROR_NAND_OPERATION_FAILED
;
286 io
->chunk_size
= nand
->page_size
;
287 status
= arm_nandread(io
, data
, size
);
293 * Write a block of data to a NAND device attached to an AT91SAM9. This uses
294 * the ARM hosted write function to write the data.
296 * @param nand NAND device to write to.
297 * @param data Data to be written to device.
298 * @param size Size of the data being written.
299 * @return Success or failure of the hosted write.
301 static int at91sam9_write_block_data(struct nand_device
*nand
, uint8_t *data
, int size
)
303 struct at91sam9_nand
*info
= nand
->controller_priv
;
304 struct arm_nand_data
*io
= &info
->io
;
307 if (!at91sam9_halted(info
->target
, "write block")) {
308 return ERROR_NAND_OPERATION_FAILED
;
311 io
->chunk_size
= nand
->page_size
;
312 status
= arm_nandwrite(io
, data
, size
);
318 * Initialize the ECC controller on the AT91SAM9.
320 * @param target Target to configure ECC on.
321 * @param info NAND controller information for where the ECC is.
322 * @return Success or failure of initialization.
324 static int at91sam9_ecc_init(struct target
*target
, struct at91sam9_nand
*info
)
327 LOG_ERROR("ECC controller address must be set when not reading raw NAND data");
328 return ERROR_NAND_OPERATION_FAILED
;
331 // reset ECC parity registers
332 return target_write_u32(target
, info
->ecc
+ AT91C_ECCx_CR
, 1);
336 * Initialize an area for the OOB based on whether a user is requesting the OOB
337 * data. This determines the size of the OOB and allocates the space in case
338 * the user has not requested the OOB data.
340 * @param nand NAND device we are creating an OOB for.
341 * @param oob Pointer to the user supplied OOB area.
342 * @param size Size of the OOB.
343 * @return Pointer to an area to store OOB data.
345 static uint8_t * at91sam9_oob_init(struct nand_device
*nand
, uint8_t *oob
, uint32_t *size
)
348 // user doesn't want OOB, allocate it
349 if (nand
->page_size
== 512) {
351 } else if (nand
->page_size
== 2048) {
357 LOG_ERROR("Unable to allocate space for OOB");
360 memset(oob
, 0xFF, *size
);
367 * Reads a page from an AT91SAM9 NAND controller and verifies using 1-bit ECC
368 * controller on chip. This makes an attempt to correct any errors that are
369 * encountered while reading the page of data.
371 * @param nand NAND device to read from
372 * @param page Page to be read.
373 * @param data Pointer to where data should be read to.
374 * @param data_size Size of the data to be read.
375 * @param oob Pointer to where OOB data should be read to.
376 * @param oob_size Size of the OOB data to be read.
377 * @return Success or failure of reading the NAND page.
379 static int at91sam9_read_page(struct nand_device
*nand
, uint32_t page
,
380 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
)
383 struct at91sam9_nand
*info
= nand
->controller_priv
;
384 struct target
*target
= info
->target
;
388 retval
= at91sam9_ecc_init(target
, info
);
389 if (ERROR_OK
!= retval
) {
393 retval
= nand_page_command(nand
, page
, NAND_CMD_READ0
, !data
);
394 if (ERROR_OK
!= retval
) {
399 retval
= nand_read_data_page(nand
, data
, data_size
);
400 if (ERROR_OK
!= retval
) {
405 oob_data
= at91sam9_oob_init(nand
, oob
, &oob_size
);
406 retval
= nand_read_data_page(nand
, oob_data
, oob_size
);
407 if (ERROR_OK
== retval
&& data
) {
408 target_read_u32(target
, info
->ecc
+ AT91C_ECCx_SR
, &status
);
410 LOG_ERROR("Error detected!");
412 LOG_ERROR("Multiple errors encountered; unrecoverable!");
417 target_read_u32(target
, info
->ecc
+ AT91C_ECCx_PR
, &parity
);
418 uint32_t word
= (parity
& 0x0000FFF0) >> 4;
419 uint32_t bit
= parity
& 0x0F;
421 data
[word
] ^= (0x1) << bit
;
422 LOG_INFO("Data word %d, bit %d corrected.", word
, bit
);
427 // we could write back correct ECC data
428 LOG_ERROR("Error in ECC bytes detected");
433 // if it wasn't asked for, free it
441 * Write a page of data including 1-bit ECC information to a NAND device
442 * attached to an AT91SAM9 controller. If there is OOB data to be written,
443 * this will ignore the computed ECC from the ECC controller.
445 * @param nand NAND device to write to.
446 * @param page Page to write.
447 * @param data Pointer to data being written.
448 * @param data_size Size of the data being written.
449 * @param oob Pointer to OOB data being written.
450 * @param oob_size Size of the OOB data.
451 * @return Success or failure of the page write.
453 static int at91sam9_write_page(struct nand_device
*nand
, uint32_t page
,
454 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
)
456 struct at91sam9_nand
*info
= nand
->controller_priv
;
457 struct target
*target
= info
->target
;
459 uint8_t *oob_data
= oob
;
460 uint32_t parity
, nparity
;
462 retval
= at91sam9_ecc_init(target
, info
);
463 if (ERROR_OK
!= retval
) {
467 retval
= nand_page_command(nand
, page
, NAND_CMD_SEQIN
, !data
);
468 if (ERROR_OK
!= retval
) {
473 retval
= nand_write_data_page(nand
, data
, data_size
);
474 if (ERROR_OK
!= retval
) {
475 LOG_ERROR("Unable to write data to NAND device");
480 oob_data
= at91sam9_oob_init(nand
, oob
, &oob_size
);
483 // no OOB given, so read in the ECC parity from the ECC controller
484 target_read_u32(target
, info
->ecc
+ AT91C_ECCx_PR
, &parity
);
485 target_read_u32(target
, info
->ecc
+ AT91C_ECCx_NPR
, &nparity
);
487 oob_data
[0] = (uint8_t) parity
;
488 oob_data
[1] = (uint8_t) (parity
>> 8);
489 oob_data
[2] = (uint8_t) nparity
;
490 oob_data
[3] = (uint8_t) (nparity
>> 8);
493 retval
= nand_write_data_page(nand
, oob_data
, oob_size
);
499 if (ERROR_OK
!= retval
) {
500 LOG_ERROR("Unable to write OOB data to NAND");
504 retval
= nand_write_finish(nand
);
510 * Handle the initial NAND device command for AT91SAM9 controllers. This
511 * initializes much of the controller information struct to be ready for future
514 NAND_DEVICE_COMMAND_HANDLER(at91sam9_nand_device_command
)
516 struct target
*target
= NULL
;
517 unsigned long chip
= 0, ecc
= 0;
518 struct at91sam9_nand
*info
= NULL
;
520 LOG_DEBUG("AT91SAM9 NAND Device Command\n");
522 if (CMD_ARGC
< 3 || CMD_ARGC
> 4) {
523 LOG_ERROR("parameters: %s target chip_addr", CMD_ARGV
[0]);
524 return ERROR_NAND_OPERATION_FAILED
;
527 target
= get_target(CMD_ARGV
[1]);
529 LOG_ERROR("invalid target: %s", CMD_ARGV
[1]);
530 return ERROR_NAND_OPERATION_FAILED
;
533 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[2], chip
);
535 LOG_ERROR("invalid NAND chip address: %s", CMD_ARGV
[2]);
536 return ERROR_NAND_OPERATION_FAILED
;
540 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[3], ecc
);
542 LOG_ERROR("invalid ECC controller address: %s", CMD_ARGV
[3]);
543 return ERROR_NAND_OPERATION_FAILED
;
547 info
= calloc(1, sizeof(*info
));
549 LOG_ERROR("unable to allocate space for controller private data");
550 return ERROR_NAND_OPERATION_FAILED
;
553 info
->target
= target
;
555 info
->cmd
= chip
| (1 << 22);
556 info
->addr
= chip
| (1 << 21);
559 nand
->controller_priv
= info
;
560 info
->io
.target
= target
;
561 info
->io
.data
= info
->data
;
562 info
->io
.op
= ARM_NAND_NONE
;
568 * Handle the AT91SAM9 CLE command for specifying the address line to use for
569 * writing commands to a NAND device.
571 COMMAND_HANDLER(handle_at91sam9_cle_command
)
573 struct nand_device
*nand
= NULL
;
574 struct at91sam9_nand
*info
= NULL
;
575 unsigned num
, address_line
;
578 command_print(CMD_CTX
, "incorrect number of arguments for 'at91sam9 cle' command");
582 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], num
);
583 nand
= get_nand_device_by_num(num
);
585 command_print(CMD_CTX
, "invalid nand device number: %s", CMD_ARGV
[0]);
589 info
= nand
->controller_priv
;
591 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[1], address_line
);
592 info
->cmd
= info
->data
| (1 << address_line
);
598 * Handle the AT91SAM9 ALE command for specifying the address line to use for
599 * writing addresses to the NAND device.
601 COMMAND_HANDLER(handle_at91sam9_ale_command
)
603 struct nand_device
*nand
= NULL
;
604 struct at91sam9_nand
*info
= NULL
;
605 unsigned num
, address_line
;
608 return ERROR_COMMAND_SYNTAX_ERROR
;
611 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], num
);
612 nand
= get_nand_device_by_num(num
);
614 command_print(CMD_CTX
, "invalid nand device number: %s", CMD_ARGV
[0]);
615 return ERROR_COMMAND_ARGUMENT_INVALID
;
618 info
= nand
->controller_priv
;
620 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[1], address_line
);
621 info
->addr
= info
->data
| (1 << address_line
);
627 * Handle the AT91SAM9 RDY/~BUSY command for specifying the pin that watches the
628 * RDY/~BUSY line from the NAND device.
630 COMMAND_HANDLER(handle_at91sam9_rdy_busy_command
)
632 struct nand_device
*nand
= NULL
;
633 struct at91sam9_nand
*info
= NULL
;
634 unsigned num
, base_pioc
, pin_num
;
637 return ERROR_COMMAND_SYNTAX_ERROR
;
640 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], num
);
641 nand
= get_nand_device_by_num(num
);
643 command_print(CMD_CTX
, "invalid nand device number: %s", CMD_ARGV
[0]);
644 return ERROR_COMMAND_ARGUMENT_INVALID
;
647 info
= nand
->controller_priv
;
649 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[1], base_pioc
);
650 info
->busy
.pioc
= base_pioc
;
652 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[2], pin_num
);
653 info
->busy
.num
= pin_num
;
659 * Handle the AT91SAM9 CE command for specifying the pin that is used to enable
660 * or disable the NAND device.
662 COMMAND_HANDLER(handle_at91sam9_ce_command
)
664 struct nand_device
*nand
= NULL
;
665 struct at91sam9_nand
*info
= NULL
;
666 unsigned num
, base_pioc
, pin_num
;
669 return ERROR_COMMAND_SYNTAX_ERROR
;
672 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], num
);
673 nand
= get_nand_device_by_num(num
);
675 command_print(CMD_CTX
, "invalid nand device number: %s", CMD_ARGV
[0]);
676 return ERROR_COMMAND_ARGUMENT_INVALID
;
679 info
= nand
->controller_priv
;
681 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[1], base_pioc
);
682 info
->ce
.pioc
= base_pioc
;
684 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[2], pin_num
);
685 info
->ce
.num
= pin_num
;
690 static const struct command_registration at91sam9_sub_command_handlers
[] = {
693 .handler
= handle_at91sam9_cle_command
,
694 .mode
= COMMAND_CONFIG
,
695 .help
= "set command latch enable address line (default is 22)",
696 .usage
= "<device_id> <address_line>",
700 .handler
= handle_at91sam9_ale_command
,
701 .mode
= COMMAND_CONFIG
,
702 .help
= "set address latch enable address line (default is 21)",
703 .usage
= "<device_id> <address_line>",
707 .handler
= handle_at91sam9_rdy_busy_command
,
708 .mode
= COMMAND_CONFIG
,
709 .help
= "set the input pin connected to RDY/~BUSY signal (no default)",
710 .usage
= "<device_id> <base_pioc> <pin_num>",
714 .handler
= handle_at91sam9_ce_command
,
715 .mode
= COMMAND_CONFIG
,
716 .help
= "set the output pin connected to chip enable signal (no default)",
717 .usage
= "<device_id> <base_pioc> <pin_num>",
719 COMMAND_REGISTRATION_DONE
722 static const struct command_registration at91sam9_command_handler
[] = {
726 .help
= "AT91SAM9 NAND flash controller commands",
727 .chain
= at91sam9_sub_command_handlers
,
729 COMMAND_REGISTRATION_DONE
733 * Structure representing the AT91SAM9 NAND controller.
735 struct nand_flash_controller at91sam9_nand_controller
= {
737 .nand_device_command
= at91sam9_nand_device_command
,
738 .commands
= at91sam9_command_handler
,
739 .init
= at91sam9_init
,
740 .command
= at91sam9_command
,
741 .reset
= at91sam9_reset
,
742 .address
= at91sam9_address
,
743 .read_data
= at91sam9_read_data
,
744 .write_data
= at91sam9_write_data
,
745 .nand_ready
= at91sam9_nand_ready
,
746 .read_block_data
= at91sam9_read_block_data
,
747 .write_block_data
= at91sam9_write_block_data
,
748 .read_page
= at91sam9_read_page
,
749 .write_page
= at91sam9_write_page
,
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+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)