2 * Copyright (C) 2009 by Dean Glazeski
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the
17 * Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 #include <target/arm.h>
25 #include <helper/log.h>
29 #define AT91C_PIOx_SODR (0x30) /**< Offset to PIO SODR. */
30 #define AT91C_PIOx_CODR (0x34) /**< Offset to PIO CODR. */
31 #define AT91C_PIOx_PDSR (0x3C) /**< Offset to PIO PDSR. */
32 #define AT91C_ECCx_CR (0x00) /**< Offset to ECC CR. */
33 #define AT91C_ECCx_SR (0x08) /**< Offset to ECC SR. */
34 #define AT91C_ECCx_PR (0x0C) /**< Offset to ECC PR. */
35 #define AT91C_ECCx_NPR (0x10) /**< Offset to ECC NPR. */
38 * Representation of a pin on an AT91SAM9 chip.
41 /** Address of the PIO controller. */
49 * Private data for the controller that is stored in the NAND device structure.
51 struct at91sam9_nand
{
52 /** Address of the ECC controller for NAND. */
55 /** Address data is written to. */
58 /** Address commands are written to. */
61 /** Address addresses are written to. */
64 /** I/O structure for hosted reads/writes. */
65 struct arm_nand_data io
;
67 /** Pin representing the ready/~busy line. */
68 struct at91sam9_pin busy
;
70 /** Pin representing the chip enable. */
71 struct at91sam9_pin ce
;
75 * Checks if the target is halted and prints an error message if it isn't.
77 * @param target Target to be checked.
78 * @param label String label for where function is called from.
79 * @return True if the target is halted.
81 static int at91sam9_halted(struct target
*target
, const char *label
)
83 if (target
->state
== TARGET_HALTED
)
86 LOG_ERROR("Target must be halted to use NAND controller (%s)", label
);
91 * Initialize the AT91SAM9 NAND controller.
93 * @param nand NAND device the controller is attached to.
94 * @return Success or failure of initialization.
96 static int at91sam9_init(struct nand_device
*nand
)
98 struct target
*target
= nand
->target
;
100 if (!at91sam9_halted(target
, "init")) {
101 return ERROR_NAND_OPERATION_FAILED
;
108 * Enable NAND device attached to a controller.
110 * @param info NAND controller information for controlling NAND device.
111 * @return Success or failure of the enabling.
113 static int at91sam9_enable(struct nand_device
*nand
)
115 struct at91sam9_nand
*info
= nand
->controller_priv
;
116 struct target
*target
= nand
->target
;
118 return target_write_u32(target
, info
->ce
.pioc
+ AT91C_PIOx_CODR
, 1 << info
->ce
.num
);
122 * Disable NAND device attached to a controller.
124 * @param info NAND controller information for controlling NAND device.
125 * @return Success or failure of the disabling.
127 static int at91sam9_disable(struct nand_device
*nand
)
129 struct at91sam9_nand
*info
= nand
->controller_priv
;
130 struct target
*target
= nand
->target
;
132 return target_write_u32(target
, info
->ce
.pioc
+ AT91C_PIOx_SODR
, 1 << info
->ce
.num
);
136 * Send a command to the NAND device.
138 * @param nand NAND device to write the command to.
139 * @param command Command to be written.
140 * @return Success or failure of writing the command.
142 static int at91sam9_command(struct nand_device
*nand
, uint8_t command
)
144 struct at91sam9_nand
*info
= nand
->controller_priv
;
145 struct target
*target
= nand
->target
;
147 if (!at91sam9_halted(target
, "command")) {
148 return ERROR_NAND_OPERATION_FAILED
;
151 at91sam9_enable(nand
);
153 return target_write_u8(target
, info
->cmd
, command
);
157 * Reset the AT91SAM9 NAND controller.
159 * @param nand NAND device to be reset.
160 * @return Success or failure of reset.
162 static int at91sam9_reset(struct nand_device
*nand
)
164 if (!at91sam9_halted(nand
->target
, "reset")) {
165 return ERROR_NAND_OPERATION_FAILED
;
168 return at91sam9_disable(nand
);
172 * Send an address to the NAND device attached to an AT91SAM9 NAND controller.
174 * @param nand NAND device to send the address to.
175 * @param address Address to be sent.
176 * @return Success or failure of sending the address.
178 static int at91sam9_address(struct nand_device
*nand
, uint8_t address
)
180 struct at91sam9_nand
*info
= nand
->controller_priv
;
181 struct target
*target
= nand
->target
;
183 if (!at91sam9_halted(nand
->target
, "address")) {
184 return ERROR_NAND_OPERATION_FAILED
;
187 return target_write_u8(target
, info
->addr
, address
);
191 * Read data directly from the NAND device attached to an AT91SAM9 NAND
194 * @param nand NAND device to read from.
195 * @param data Pointer to where the data should be put.
196 * @return Success or failure of reading the data.
198 static int at91sam9_read_data(struct nand_device
*nand
, void *data
)
200 struct at91sam9_nand
*info
= nand
->controller_priv
;
201 struct target
*target
= nand
->target
;
203 if (!at91sam9_halted(nand
->target
, "read data")) {
204 return ERROR_NAND_OPERATION_FAILED
;
207 return target_read_u8(target
, info
->data
, data
);
211 * Write data directly to the NAND device attached to an AT91SAM9 NAND
214 * @param nand NAND device to be written to.
215 * @param data Data to be written.
216 * @return Success or failure of the data write.
218 static int at91sam9_write_data(struct nand_device
*nand
, uint16_t data
)
220 struct at91sam9_nand
*info
= nand
->controller_priv
;
221 struct target
*target
= nand
->target
;
223 if (!at91sam9_halted(target
, "write data")) {
224 return ERROR_NAND_OPERATION_FAILED
;
227 return target_write_u8(target
, info
->data
, data
);
231 * Determine if the NAND device is ready by looking at the ready/~busy pin.
233 * @param nand NAND device to check.
234 * @param timeout Time in milliseconds to wait for NAND to be ready.
235 * @return True if the NAND is ready in the timeout period.
237 static int at91sam9_nand_ready(struct nand_device
*nand
, int timeout
)
239 struct at91sam9_nand
*info
= nand
->controller_priv
;
240 struct target
*target
= nand
->target
;
243 if (!at91sam9_halted(target
, "nand ready")) {
248 target_read_u32(target
, info
->busy
.pioc
+ AT91C_PIOx_PDSR
, &status
);
250 if (status
& (1 << info
->busy
.num
)) {
255 } while (timeout
-- > 0);
261 * Read a block of data from the NAND device attached to an AT91SAM9. This
262 * utilizes the ARM hosted NAND read function.
264 * @param nand NAND device to read from.
265 * @param data Pointer to where the read data should be placed.
266 * @param size Size of the data being read.
267 * @return Success or failure of the hosted read.
269 static int at91sam9_read_block_data(struct nand_device
*nand
, uint8_t *data
, int size
)
271 struct at91sam9_nand
*info
= nand
->controller_priv
;
272 struct arm_nand_data
*io
= &info
->io
;
275 if (!at91sam9_halted(nand
->target
, "read block")) {
276 return ERROR_NAND_OPERATION_FAILED
;
279 io
->chunk_size
= nand
->page_size
;
280 status
= arm_nandread(io
, data
, size
);
286 * Write a block of data to a NAND device attached to an AT91SAM9. This uses
287 * the ARM hosted write function to write the data.
289 * @param nand NAND device to write to.
290 * @param data Data to be written to device.
291 * @param size Size of the data being written.
292 * @return Success or failure of the hosted write.
294 static int at91sam9_write_block_data(struct nand_device
*nand
, uint8_t *data
, int size
)
296 struct at91sam9_nand
*info
= nand
->controller_priv
;
297 struct arm_nand_data
*io
= &info
->io
;
300 if (!at91sam9_halted(nand
->target
, "write block")) {
301 return ERROR_NAND_OPERATION_FAILED
;
304 io
->chunk_size
= nand
->page_size
;
305 status
= arm_nandwrite(io
, data
, size
);
311 * Initialize the ECC controller on the AT91SAM9.
313 * @param target Target to configure ECC on.
314 * @param info NAND controller information for where the ECC is.
315 * @return Success or failure of initialization.
317 static int at91sam9_ecc_init(struct target
*target
, struct at91sam9_nand
*info
)
320 LOG_ERROR("ECC controller address must be set when not reading raw NAND data");
321 return ERROR_NAND_OPERATION_FAILED
;
324 // reset ECC parity registers
325 return target_write_u32(target
, info
->ecc
+ AT91C_ECCx_CR
, 1);
329 * Initialize an area for the OOB based on whether a user is requesting the OOB
330 * data. This determines the size of the OOB and allocates the space in case
331 * the user has not requested the OOB data.
333 * @param nand NAND device we are creating an OOB for.
334 * @param oob Pointer to the user supplied OOB area.
335 * @param size Size of the OOB.
336 * @return Pointer to an area to store OOB data.
338 static uint8_t * at91sam9_oob_init(struct nand_device
*nand
, uint8_t *oob
, uint32_t *size
)
341 // user doesn't want OOB, allocate it
342 if (nand
->page_size
== 512) {
344 } else if (nand
->page_size
== 2048) {
350 LOG_ERROR("Unable to allocate space for OOB");
353 memset(oob
, 0xFF, *size
);
360 * Reads a page from an AT91SAM9 NAND controller and verifies using 1-bit ECC
361 * controller on chip. This makes an attempt to correct any errors that are
362 * encountered while reading the page of data.
364 * @param nand NAND device to read from
365 * @param page Page to be read.
366 * @param data Pointer to where data should be read to.
367 * @param data_size Size of the data to be read.
368 * @param oob Pointer to where OOB data should be read to.
369 * @param oob_size Size of the OOB data to be read.
370 * @return Success or failure of reading the NAND page.
372 static int at91sam9_read_page(struct nand_device
*nand
, uint32_t page
,
373 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
)
376 struct at91sam9_nand
*info
= nand
->controller_priv
;
377 struct target
*target
= nand
->target
;
381 retval
= at91sam9_ecc_init(target
, info
);
382 if (ERROR_OK
!= retval
) {
386 retval
= nand_page_command(nand
, page
, NAND_CMD_READ0
, !data
);
387 if (ERROR_OK
!= retval
) {
392 retval
= nand_read_data_page(nand
, data
, data_size
);
393 if (ERROR_OK
!= retval
) {
398 oob_data
= at91sam9_oob_init(nand
, oob
, &oob_size
);
399 retval
= nand_read_data_page(nand
, oob_data
, oob_size
);
400 if (ERROR_OK
== retval
&& data
) {
401 target_read_u32(target
, info
->ecc
+ AT91C_ECCx_SR
, &status
);
403 LOG_ERROR("Error detected!");
405 LOG_ERROR("Multiple errors encountered; unrecoverable!");
410 target_read_u32(target
,
411 info
->ecc
+ AT91C_ECCx_PR
,
413 uint32_t word
= (parity
& 0x0000FFF0) >> 4;
414 uint32_t bit
= parity
& 0x0F;
416 data
[word
] ^= (0x1) << bit
;
417 LOG_INFO("Data word %d, bit %d corrected.",
424 // we could write back correct ECC data
425 LOG_ERROR("Error in ECC bytes detected");
430 // if it wasn't asked for, free it
438 * Write a page of data including 1-bit ECC information to a NAND device
439 * attached to an AT91SAM9 controller. If there is OOB data to be written,
440 * this will ignore the computed ECC from the ECC controller.
442 * @param nand NAND device to write to.
443 * @param page Page to write.
444 * @param data Pointer to data being written.
445 * @param data_size Size of the data being written.
446 * @param oob Pointer to OOB data being written.
447 * @param oob_size Size of the OOB data.
448 * @return Success or failure of the page write.
450 static int at91sam9_write_page(struct nand_device
*nand
, uint32_t page
,
451 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
)
453 struct at91sam9_nand
*info
= nand
->controller_priv
;
454 struct target
*target
= nand
->target
;
456 uint8_t *oob_data
= oob
;
457 uint32_t parity
, nparity
;
459 retval
= at91sam9_ecc_init(target
, info
);
460 if (ERROR_OK
!= retval
) {
464 retval
= nand_page_command(nand
, page
, NAND_CMD_SEQIN
, !data
);
465 if (ERROR_OK
!= retval
) {
470 retval
= nand_write_data_page(nand
, data
, data_size
);
471 if (ERROR_OK
!= retval
) {
472 LOG_ERROR("Unable to write data to NAND device");
477 oob_data
= at91sam9_oob_init(nand
, oob
, &oob_size
);
480 // no OOB given, so read in the ECC parity from the ECC controller
481 target_read_u32(target
, info
->ecc
+ AT91C_ECCx_PR
, &parity
);
482 target_read_u32(target
, info
->ecc
+ AT91C_ECCx_NPR
, &nparity
);
484 oob_data
[0] = (uint8_t) parity
;
485 oob_data
[1] = (uint8_t) (parity
>> 8);
486 oob_data
[2] = (uint8_t) nparity
;
487 oob_data
[3] = (uint8_t) (nparity
>> 8);
490 retval
= nand_write_data_page(nand
, oob_data
, oob_size
);
496 if (ERROR_OK
!= retval
) {
497 LOG_ERROR("Unable to write OOB data to NAND");
501 retval
= nand_write_finish(nand
);
507 * Handle the initial NAND device command for AT91SAM9 controllers. This
508 * initializes much of the controller information struct to be ready for future
511 NAND_DEVICE_COMMAND_HANDLER(at91sam9_nand_device_command
)
513 unsigned long chip
= 0, ecc
= 0;
514 struct at91sam9_nand
*info
= NULL
;
516 LOG_DEBUG("AT91SAM9 NAND Device Command");
518 if (CMD_ARGC
< 3 || CMD_ARGC
> 4) {
519 LOG_ERROR("parameters: %s target chip_addr", CMD_ARGV
[0]);
520 return ERROR_NAND_OPERATION_FAILED
;
523 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[2], chip
);
525 LOG_ERROR("invalid NAND chip address: %s", CMD_ARGV
[2]);
526 return ERROR_NAND_OPERATION_FAILED
;
530 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[3], ecc
);
532 LOG_ERROR("invalid ECC controller address: %s", CMD_ARGV
[3]);
533 return ERROR_NAND_OPERATION_FAILED
;
537 info
= calloc(1, sizeof(*info
));
539 LOG_ERROR("unable to allocate space for controller private data");
540 return ERROR_NAND_OPERATION_FAILED
;
544 info
->cmd
= chip
| (1 << 22);
545 info
->addr
= chip
| (1 << 21);
548 nand
->controller_priv
= info
;
549 info
->io
.target
= nand
->target
;
550 info
->io
.data
= info
->data
;
551 info
->io
.op
= ARM_NAND_NONE
;
557 * Handle the AT91SAM9 CLE command for specifying the address line to use for
558 * writing commands to a NAND device.
560 COMMAND_HANDLER(handle_at91sam9_cle_command
)
562 struct nand_device
*nand
= NULL
;
563 struct at91sam9_nand
*info
= NULL
;
564 unsigned num
, address_line
;
567 command_print(CMD_CTX
, "incorrect number of arguments for 'at91sam9 cle' command");
571 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], num
);
572 nand
= get_nand_device_by_num(num
);
574 command_print(CMD_CTX
, "invalid nand device number: %s", CMD_ARGV
[0]);
578 info
= nand
->controller_priv
;
580 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[1], address_line
);
581 info
->cmd
= info
->data
| (1 << address_line
);
587 * Handle the AT91SAM9 ALE command for specifying the address line to use for
588 * writing addresses to the NAND device.
590 COMMAND_HANDLER(handle_at91sam9_ale_command
)
592 struct nand_device
*nand
= NULL
;
593 struct at91sam9_nand
*info
= NULL
;
594 unsigned num
, address_line
;
597 return ERROR_COMMAND_SYNTAX_ERROR
;
600 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], num
);
601 nand
= get_nand_device_by_num(num
);
603 command_print(CMD_CTX
, "invalid nand device number: %s", CMD_ARGV
[0]);
604 return ERROR_COMMAND_ARGUMENT_INVALID
;
607 info
= nand
->controller_priv
;
609 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[1], address_line
);
610 info
->addr
= info
->data
| (1 << address_line
);
616 * Handle the AT91SAM9 RDY/~BUSY command for specifying the pin that watches the
617 * RDY/~BUSY line from the NAND device.
619 COMMAND_HANDLER(handle_at91sam9_rdy_busy_command
)
621 struct nand_device
*nand
= NULL
;
622 struct at91sam9_nand
*info
= NULL
;
623 unsigned num
, base_pioc
, pin_num
;
626 return ERROR_COMMAND_SYNTAX_ERROR
;
629 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], num
);
630 nand
= get_nand_device_by_num(num
);
632 command_print(CMD_CTX
, "invalid nand device number: %s", CMD_ARGV
[0]);
633 return ERROR_COMMAND_ARGUMENT_INVALID
;
636 info
= nand
->controller_priv
;
638 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[1], base_pioc
);
639 info
->busy
.pioc
= base_pioc
;
641 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[2], pin_num
);
642 info
->busy
.num
= pin_num
;
648 * Handle the AT91SAM9 CE command for specifying the pin that is used to enable
649 * or disable the NAND device.
651 COMMAND_HANDLER(handle_at91sam9_ce_command
)
653 struct nand_device
*nand
= NULL
;
654 struct at91sam9_nand
*info
= NULL
;
655 unsigned num
, base_pioc
, pin_num
;
658 return ERROR_COMMAND_SYNTAX_ERROR
;
661 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], num
);
662 nand
= get_nand_device_by_num(num
);
664 command_print(CMD_CTX
, "invalid nand device number: %s", CMD_ARGV
[0]);
665 return ERROR_COMMAND_ARGUMENT_INVALID
;
668 info
= nand
->controller_priv
;
670 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[1], base_pioc
);
671 info
->ce
.pioc
= base_pioc
;
673 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[2], pin_num
);
674 info
->ce
.num
= pin_num
;
679 static const struct command_registration at91sam9_sub_command_handlers
[] = {
682 .handler
= handle_at91sam9_cle_command
,
683 .mode
= COMMAND_CONFIG
,
684 .help
= "set command latch enable address line (default is 22)",
685 .usage
= "bank_id address_line",
689 .handler
= handle_at91sam9_ale_command
,
690 .mode
= COMMAND_CONFIG
,
691 .help
= "set address latch enable address line (default is 21)",
692 .usage
= "bank_id address_line",
696 .handler
= handle_at91sam9_rdy_busy_command
,
697 .mode
= COMMAND_CONFIG
,
698 .help
= "set the GPIO input pin connected to "
699 "the RDY/~BUSY signal (no default)",
700 .usage
= "bank_id pio_base_addr pin_num",
704 .handler
= handle_at91sam9_ce_command
,
705 .mode
= COMMAND_CONFIG
,
706 .help
= "set the GPIO output pin connected to "
707 "the chip enable signal (no default)",
708 .usage
= "bank_id pio_base_addr pin_num",
710 COMMAND_REGISTRATION_DONE
713 static const struct command_registration at91sam9_command_handler
[] = {
717 .help
= "AT91SAM9 NAND flash controller commands",
718 .chain
= at91sam9_sub_command_handlers
,
720 COMMAND_REGISTRATION_DONE
724 * Structure representing the AT91SAM9 NAND controller.
726 struct nand_flash_controller at91sam9_nand_controller
= {
728 .nand_device_command
= at91sam9_nand_device_command
,
729 .commands
= at91sam9_command_handler
,
730 .init
= at91sam9_init
,
731 .command
= at91sam9_command
,
732 .reset
= at91sam9_reset
,
733 .address
= at91sam9_address
,
734 .read_data
= at91sam9_read_data
,
735 .write_data
= at91sam9_write_data
,
736 .nand_ready
= at91sam9_nand_ready
,
737 .read_block_data
= at91sam9_read_block_data
,
738 .write_block_data
= at91sam9_write_block_data
,
739 .read_page
= at91sam9_read_page
,
740 .write_page
= at91sam9_write_page
,
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|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)