cygwin build fixes
[openocd.git] / src / flash / nand / at91sam9.c
1 /*
2 * Copyright (C) 2009 by Dean Glazeski
3 * dnglaze@gmail.com
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the
17 * Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include <target/arm.h>
25 #include <helper/log.h>
26 #include "imp.h"
27 #include "arm_io.h"
28
29 #define AT91C_PIOx_SODR (0x30) /**< Offset to PIO SODR. */
30 #define AT91C_PIOx_CODR (0x34) /**< Offset to PIO CODR. */
31 #define AT91C_PIOx_PDSR (0x3C) /**< Offset to PIO PDSR. */
32 #define AT91C_ECCx_CR (0x00) /**< Offset to ECC CR. */
33 #define AT91C_ECCx_SR (0x08) /**< Offset to ECC SR. */
34 #define AT91C_ECCx_PR (0x0C) /**< Offset to ECC PR. */
35 #define AT91C_ECCx_NPR (0x10) /**< Offset to ECC NPR. */
36
37 /**
38 * Representation of a pin on an AT91SAM9 chip.
39 */
40 struct at91sam9_pin {
41 /** Target this pin is on. */
42 struct target *target;
43
44 /** Address of the PIO controller. */
45 uint32_t pioc;
46
47 /** Pin number. */
48 uint32_t num;
49 };
50
51 /**
52 * Private data for the controller that is stored in the NAND device structure.
53 */
54 struct at91sam9_nand {
55 /** Target the NAND is attached to. */
56 struct target *target;
57
58 /** Address of the ECC controller for NAND. */
59 uint32_t ecc;
60
61 /** Address data is written to. */
62 uint32_t data;
63
64 /** Address commands are written to. */
65 uint32_t cmd;
66
67 /** Address addresses are written to. */
68 uint32_t addr;
69
70 /** I/O structure for hosted reads/writes. */
71 struct arm_nand_data io;
72
73 /** Pin representing the ready/~busy line. */
74 struct at91sam9_pin busy;
75
76 /** Pin representing the chip enable. */
77 struct at91sam9_pin ce;
78 };
79
80 /**
81 * Checks if the target is halted and prints an error message if it isn't.
82 *
83 * @param target Target to be checked.
84 * @param label String label for where function is called from.
85 * @return True if the target is halted.
86 */
87 static int at91sam9_halted(struct target *target, const char *label)
88 {
89 if (target->state == TARGET_HALTED)
90 return true;
91
92 LOG_ERROR("Target must be halted to use NAND controller (%s)", label);
93 return false;
94 }
95
96 /**
97 * Initialize the AT91SAM9 NAND controller.
98 *
99 * @param nand NAND device the controller is attached to.
100 * @return Success or failure of initialization.
101 */
102 static int at91sam9_init(struct nand_device *nand)
103 {
104 struct at91sam9_nand *info = nand->controller_priv;
105 struct target *target = info->target;
106
107 if (!at91sam9_halted(target, "init")) {
108 return ERROR_NAND_OPERATION_FAILED;
109 }
110
111 return ERROR_OK;
112 }
113
114 /**
115 * Enable NAND device attached to a controller.
116 *
117 * @param info NAND controller information for controlling NAND device.
118 * @return Success or failure of the enabling.
119 */
120 static int at91sam9_enable(struct at91sam9_nand *info)
121 {
122 struct target *target = info->target;
123
124 return target_write_u32(target, info->ce.pioc + AT91C_PIOx_CODR, 1 << info->ce.num);
125 }
126
127 /**
128 * Disable NAND device attached to a controller.
129 *
130 * @param info NAND controller information for controlling NAND device.
131 * @return Success or failure of the disabling.
132 */
133 static int at91sam9_disable(struct at91sam9_nand *info)
134 {
135 struct target *target = info->target;
136
137 return target_write_u32(target, info->ce.pioc + AT91C_PIOx_SODR, 1 << info->ce.num);
138 }
139
140 /**
141 * Send a command to the NAND device.
142 *
143 * @param nand NAND device to write the command to.
144 * @param command Command to be written.
145 * @return Success or failure of writing the command.
146 */
147 static int at91sam9_command(struct nand_device *nand, uint8_t command)
148 {
149 struct at91sam9_nand *info = nand->controller_priv;
150 struct target *target = info->target;
151
152 if (!at91sam9_halted(target, "command")) {
153 return ERROR_NAND_OPERATION_FAILED;
154 }
155
156 at91sam9_enable(info);
157
158 return target_write_u8(target, info->cmd, command);
159 }
160
161 /**
162 * Reset the AT91SAM9 NAND controller.
163 *
164 * @param nand NAND device to be reset.
165 * @return Success or failure of reset.
166 */
167 static int at91sam9_reset(struct nand_device *nand)
168 {
169 struct at91sam9_nand *info = nand->controller_priv;
170
171 if (!at91sam9_halted(info->target, "reset")) {
172 return ERROR_NAND_OPERATION_FAILED;
173 }
174
175 return at91sam9_disable(info);
176 }
177
178 /**
179 * Send an address to the NAND device attached to an AT91SAM9 NAND controller.
180 *
181 * @param nand NAND device to send the address to.
182 * @param address Address to be sent.
183 * @return Success or failure of sending the address.
184 */
185 static int at91sam9_address(struct nand_device *nand, uint8_t address)
186 {
187 struct at91sam9_nand *info = nand->controller_priv;
188 struct target *target = info->target;
189
190 if (!at91sam9_halted(info->target, "address")) {
191 return ERROR_NAND_OPERATION_FAILED;
192 }
193
194 return target_write_u8(target, info->addr, address);
195 }
196
197 /**
198 * Read data directly from the NAND device attached to an AT91SAM9 NAND
199 * controller.
200 *
201 * @param nand NAND device to read from.
202 * @param data Pointer to where the data should be put.
203 * @return Success or failure of reading the data.
204 */
205 static int at91sam9_read_data(struct nand_device *nand, void *data)
206 {
207 struct at91sam9_nand *info = nand->controller_priv;
208 struct target *target = info->target;
209
210 if (!at91sam9_halted(info->target, "read data")) {
211 return ERROR_NAND_OPERATION_FAILED;
212 }
213
214 return target_read_u8(target, info->data, data);
215 }
216
217 /**
218 * Write data directly to the NAND device attached to an AT91SAM9 NAND
219 * controller.
220 *
221 * @param nand NAND device to be written to.
222 * @param data Data to be written.
223 * @return Success or failure of the data write.
224 */
225 static int at91sam9_write_data(struct nand_device *nand, uint16_t data)
226 {
227 struct at91sam9_nand *info = nand->controller_priv;
228 struct target *target = info->target;
229
230 if (!at91sam9_halted(target, "write data")) {
231 return ERROR_NAND_OPERATION_FAILED;
232 }
233
234 return target_write_u8(target, info->data, data);
235 }
236
237 /**
238 * Determine if the NAND device is ready by looking at the ready/~busy pin.
239 *
240 * @param nand NAND device to check.
241 * @param timeout Time in milliseconds to wait for NAND to be ready.
242 * @return True if the NAND is ready in the timeout period.
243 */
244 static int at91sam9_nand_ready(struct nand_device *nand, int timeout)
245 {
246 struct at91sam9_nand *info = nand->controller_priv;
247 struct target *target = info->target;
248 uint32_t status;
249
250 if (!at91sam9_halted(target, "nand ready")) {
251 return 0;
252 }
253
254 do {
255 target_read_u32(target, info->busy.pioc + AT91C_PIOx_PDSR, &status);
256
257 if (status & (1 << info->busy.num)) {
258 return 1;
259 }
260
261 alive_sleep(1);
262 } while (timeout-- > 0);
263
264 return 0;
265 }
266
267 /**
268 * Read a block of data from the NAND device attached to an AT91SAM9. This
269 * utilizes the ARM hosted NAND read function.
270 *
271 * @param nand NAND device to read from.
272 * @param data Pointer to where the read data should be placed.
273 * @param size Size of the data being read.
274 * @return Success or failure of the hosted read.
275 */
276 static int at91sam9_read_block_data(struct nand_device *nand, uint8_t *data, int size)
277 {
278 struct at91sam9_nand *info = nand->controller_priv;
279 struct arm_nand_data *io = &info->io;
280 int status;
281
282 if (!at91sam9_halted(info->target, "read block")) {
283 return ERROR_NAND_OPERATION_FAILED;
284 }
285
286 io->chunk_size = nand->page_size;
287 status = arm_nandread(io, data, size);
288
289 return status;
290 }
291
292 /**
293 * Write a block of data to a NAND device attached to an AT91SAM9. This uses
294 * the ARM hosted write function to write the data.
295 *
296 * @param nand NAND device to write to.
297 * @param data Data to be written to device.
298 * @param size Size of the data being written.
299 * @return Success or failure of the hosted write.
300 */
301 static int at91sam9_write_block_data(struct nand_device *nand, uint8_t *data, int size)
302 {
303 struct at91sam9_nand *info = nand->controller_priv;
304 struct arm_nand_data *io = &info->io;
305 int status;
306
307 if (!at91sam9_halted(info->target, "write block")) {
308 return ERROR_NAND_OPERATION_FAILED;
309 }
310
311 io->chunk_size = nand->page_size;
312 status = arm_nandwrite(io, data, size);
313
314 return status;
315 }
316
317 /**
318 * Initialize the ECC controller on the AT91SAM9.
319 *
320 * @param target Target to configure ECC on.
321 * @param info NAND controller information for where the ECC is.
322 * @return Success or failure of initialization.
323 */
324 static int at91sam9_ecc_init(struct target *target, struct at91sam9_nand *info)
325 {
326 if (!info->ecc) {
327 LOG_ERROR("ECC controller address must be set when not reading raw NAND data");
328 return ERROR_NAND_OPERATION_FAILED;
329 }
330
331 // reset ECC parity registers
332 return target_write_u32(target, info->ecc + AT91C_ECCx_CR, 1);
333 }
334
335 /**
336 * Initialize an area for the OOB based on whether a user is requesting the OOB
337 * data. This determines the size of the OOB and allocates the space in case
338 * the user has not requested the OOB data.
339 *
340 * @param nand NAND device we are creating an OOB for.
341 * @param oob Pointer to the user supplied OOB area.
342 * @param size Size of the OOB.
343 * @return Pointer to an area to store OOB data.
344 */
345 static uint8_t * at91sam9_oob_init(struct nand_device *nand, uint8_t *oob, uint32_t *size)
346 {
347 if (!oob) {
348 // user doesn't want OOB, allocate it
349 if (nand->page_size == 512) {
350 *size = 16;
351 } else if (nand->page_size == 2048) {
352 *size = 64;
353 }
354
355 oob = malloc(*size);
356 if (!oob) {
357 LOG_ERROR("Unable to allocate space for OOB");
358 }
359
360 memset(oob, 0xFF, *size);
361 }
362
363 return oob;
364 }
365
366 /**
367 * Reads a page from an AT91SAM9 NAND controller and verifies using 1-bit ECC
368 * controller on chip. This makes an attempt to correct any errors that are
369 * encountered while reading the page of data.
370 *
371 * @param nand NAND device to read from
372 * @param page Page to be read.
373 * @param data Pointer to where data should be read to.
374 * @param data_size Size of the data to be read.
375 * @param oob Pointer to where OOB data should be read to.
376 * @param oob_size Size of the OOB data to be read.
377 * @return Success or failure of reading the NAND page.
378 */
379 static int at91sam9_read_page(struct nand_device *nand, uint32_t page,
380 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
381 {
382 int retval;
383 struct at91sam9_nand *info = nand->controller_priv;
384 struct target *target = info->target;
385 uint8_t *oob_data;
386 uint32_t status;
387
388 retval = at91sam9_ecc_init(target, info);
389 if (ERROR_OK != retval) {
390 return retval;
391 }
392
393 retval = nand_page_command(nand, page, NAND_CMD_READ0, !data);
394 if (ERROR_OK != retval) {
395 return retval;
396 }
397
398 if (data) {
399 retval = nand_read_data_page(nand, data, data_size);
400 if (ERROR_OK != retval) {
401 return retval;
402 }
403 }
404
405 oob_data = at91sam9_oob_init(nand, oob, &oob_size);
406 retval = nand_read_data_page(nand, oob_data, oob_size);
407 if (ERROR_OK == retval && data) {
408 target_read_u32(target, info->ecc + AT91C_ECCx_SR, &status);
409 if (status & 1) {
410 LOG_ERROR("Error detected!");
411 if (status & 4) {
412 LOG_ERROR("Multiple errors encountered; unrecoverable!");
413 } else {
414 // attempt recovery
415 uint32_t parity;
416
417 target_read_u32(target,
418 info->ecc + AT91C_ECCx_PR,
419 &parity);
420 uint32_t word = (parity & 0x0000FFF0) >> 4;
421 uint32_t bit = parity & 0x0F;
422
423 data[word] ^= (0x1) << bit;
424 LOG_INFO("Data word %d, bit %d corrected.",
425 (unsigned) word,
426 (unsigned) bit);
427 }
428 }
429
430 if (status & 2) {
431 // we could write back correct ECC data
432 LOG_ERROR("Error in ECC bytes detected");
433 }
434 }
435
436 if (!oob) {
437 // if it wasn't asked for, free it
438 free(oob_data);
439 }
440
441 return retval;
442 }
443
444 /**
445 * Write a page of data including 1-bit ECC information to a NAND device
446 * attached to an AT91SAM9 controller. If there is OOB data to be written,
447 * this will ignore the computed ECC from the ECC controller.
448 *
449 * @param nand NAND device to write to.
450 * @param page Page to write.
451 * @param data Pointer to data being written.
452 * @param data_size Size of the data being written.
453 * @param oob Pointer to OOB data being written.
454 * @param oob_size Size of the OOB data.
455 * @return Success or failure of the page write.
456 */
457 static int at91sam9_write_page(struct nand_device *nand, uint32_t page,
458 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
459 {
460 struct at91sam9_nand *info = nand->controller_priv;
461 struct target *target = info->target;
462 int retval;
463 uint8_t *oob_data = oob;
464 uint32_t parity, nparity;
465
466 retval = at91sam9_ecc_init(target, info);
467 if (ERROR_OK != retval) {
468 return retval;
469 }
470
471 retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
472 if (ERROR_OK != retval) {
473 return retval;
474 }
475
476 if (data) {
477 retval = nand_write_data_page(nand, data, data_size);
478 if (ERROR_OK != retval) {
479 LOG_ERROR("Unable to write data to NAND device");
480 return retval;
481 }
482 }
483
484 oob_data = at91sam9_oob_init(nand, oob, &oob_size);
485
486 if (!oob) {
487 // no OOB given, so read in the ECC parity from the ECC controller
488 target_read_u32(target, info->ecc + AT91C_ECCx_PR, &parity);
489 target_read_u32(target, info->ecc + AT91C_ECCx_NPR, &nparity);
490
491 oob_data[0] = (uint8_t) parity;
492 oob_data[1] = (uint8_t) (parity >> 8);
493 oob_data[2] = (uint8_t) nparity;
494 oob_data[3] = (uint8_t) (nparity >> 8);
495 }
496
497 retval = nand_write_data_page(nand, oob_data, oob_size);
498
499 if (!oob) {
500 free(oob_data);
501 }
502
503 if (ERROR_OK != retval) {
504 LOG_ERROR("Unable to write OOB data to NAND");
505 return retval;
506 }
507
508 retval = nand_write_finish(nand);
509
510 return retval;
511 }
512
513 /**
514 * Handle the initial NAND device command for AT91SAM9 controllers. This
515 * initializes much of the controller information struct to be ready for future
516 * reads and writes.
517 */
518 NAND_DEVICE_COMMAND_HANDLER(at91sam9_nand_device_command)
519 {
520 struct target *target = NULL;
521 unsigned long chip = 0, ecc = 0;
522 struct at91sam9_nand *info = NULL;
523
524 LOG_DEBUG("AT91SAM9 NAND Device Command\n");
525
526 if (CMD_ARGC < 3 || CMD_ARGC > 4) {
527 LOG_ERROR("parameters: %s target chip_addr", CMD_ARGV[0]);
528 return ERROR_NAND_OPERATION_FAILED;
529 }
530
531 target = get_target(CMD_ARGV[1]);
532 if (!target) {
533 LOG_ERROR("invalid target: %s", CMD_ARGV[1]);
534 return ERROR_NAND_OPERATION_FAILED;
535 }
536
537 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], chip);
538 if (chip == 0) {
539 LOG_ERROR("invalid NAND chip address: %s", CMD_ARGV[2]);
540 return ERROR_NAND_OPERATION_FAILED;
541 }
542
543 if (CMD_ARGC == 4) {
544 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[3], ecc);
545 if (ecc == 0) {
546 LOG_ERROR("invalid ECC controller address: %s", CMD_ARGV[3]);
547 return ERROR_NAND_OPERATION_FAILED;
548 }
549 }
550
551 info = calloc(1, sizeof(*info));
552 if (!info) {
553 LOG_ERROR("unable to allocate space for controller private data");
554 return ERROR_NAND_OPERATION_FAILED;
555 }
556
557 info->target = target;
558 info->data = chip;
559 info->cmd = chip | (1 << 22);
560 info->addr = chip | (1 << 21);
561 info->ecc = ecc;
562
563 nand->controller_priv = info;
564 info->io.target = target;
565 info->io.data = info->data;
566 info->io.op = ARM_NAND_NONE;
567
568 return ERROR_OK;
569 }
570
571 /**
572 * Handle the AT91SAM9 CLE command for specifying the address line to use for
573 * writing commands to a NAND device.
574 */
575 COMMAND_HANDLER(handle_at91sam9_cle_command)
576 {
577 struct nand_device *nand = NULL;
578 struct at91sam9_nand *info = NULL;
579 unsigned num, address_line;
580
581 if (CMD_ARGC != 2) {
582 command_print(CMD_CTX, "incorrect number of arguments for 'at91sam9 cle' command");
583 return ERROR_OK;
584 }
585
586 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
587 nand = get_nand_device_by_num(num);
588 if (!nand) {
589 command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
590 return ERROR_OK;
591 }
592
593 info = nand->controller_priv;
594
595 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], address_line);
596 info->cmd = info->data | (1 << address_line);
597
598 return ERROR_OK;
599 }
600
601 /**
602 * Handle the AT91SAM9 ALE command for specifying the address line to use for
603 * writing addresses to the NAND device.
604 */
605 COMMAND_HANDLER(handle_at91sam9_ale_command)
606 {
607 struct nand_device *nand = NULL;
608 struct at91sam9_nand *info = NULL;
609 unsigned num, address_line;
610
611 if (CMD_ARGC != 2) {
612 return ERROR_COMMAND_SYNTAX_ERROR;
613 }
614
615 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
616 nand = get_nand_device_by_num(num);
617 if (!nand) {
618 command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
619 return ERROR_COMMAND_ARGUMENT_INVALID;
620 }
621
622 info = nand->controller_priv;
623
624 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], address_line);
625 info->addr = info->data | (1 << address_line);
626
627 return ERROR_OK;
628 }
629
630 /**
631 * Handle the AT91SAM9 RDY/~BUSY command for specifying the pin that watches the
632 * RDY/~BUSY line from the NAND device.
633 */
634 COMMAND_HANDLER(handle_at91sam9_rdy_busy_command)
635 {
636 struct nand_device *nand = NULL;
637 struct at91sam9_nand *info = NULL;
638 unsigned num, base_pioc, pin_num;
639
640 if (CMD_ARGC != 3) {
641 return ERROR_COMMAND_SYNTAX_ERROR;
642 }
643
644 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
645 nand = get_nand_device_by_num(num);
646 if (!nand) {
647 command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
648 return ERROR_COMMAND_ARGUMENT_INVALID;
649 }
650
651 info = nand->controller_priv;
652
653 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], base_pioc);
654 info->busy.pioc = base_pioc;
655
656 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], pin_num);
657 info->busy.num = pin_num;
658
659 return ERROR_OK;
660 }
661
662 /**
663 * Handle the AT91SAM9 CE command for specifying the pin that is used to enable
664 * or disable the NAND device.
665 */
666 COMMAND_HANDLER(handle_at91sam9_ce_command)
667 {
668 struct nand_device *nand = NULL;
669 struct at91sam9_nand *info = NULL;
670 unsigned num, base_pioc, pin_num;
671
672 if (CMD_ARGC != 3) {
673 return ERROR_COMMAND_SYNTAX_ERROR;
674 }
675
676 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
677 nand = get_nand_device_by_num(num);
678 if (!nand) {
679 command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
680 return ERROR_COMMAND_ARGUMENT_INVALID;
681 }
682
683 info = nand->controller_priv;
684
685 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], base_pioc);
686 info->ce.pioc = base_pioc;
687
688 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], pin_num);
689 info->ce.num = pin_num;
690
691 return ERROR_OK;
692 }
693
694 static const struct command_registration at91sam9_sub_command_handlers[] = {
695 {
696 .name = "cle",
697 .handler = handle_at91sam9_cle_command,
698 .mode = COMMAND_CONFIG,
699 .help = "set command latch enable address line (default is 22)",
700 .usage = "<device_id> <address_line>",
701 },
702 {
703 .name = "ale",
704 .handler = handle_at91sam9_ale_command,
705 .mode = COMMAND_CONFIG,
706 .help = "set address latch enable address line (default is 21)",
707 .usage = "<device_id> <address_line>",
708 },
709 {
710 .name = "rdy_busy",
711 .handler = handle_at91sam9_rdy_busy_command,
712 .mode = COMMAND_CONFIG,
713 .help = "set the input pin connected to RDY/~BUSY signal (no default)",
714 .usage = "<device_id> <base_pioc> <pin_num>",
715 },
716 {
717 .name = "ce",
718 .handler = handle_at91sam9_ce_command,
719 .mode = COMMAND_CONFIG,
720 .help = "set the output pin connected to chip enable signal (no default)",
721 .usage = "<device_id> <base_pioc> <pin_num>",
722 },
723 COMMAND_REGISTRATION_DONE
724 };
725
726 static const struct command_registration at91sam9_command_handler[] = {
727 {
728 .name = "at91sam9",
729 .mode = COMMAND_ANY,
730 .help = "AT91SAM9 NAND flash controller commands",
731 .chain = at91sam9_sub_command_handlers,
732 },
733 COMMAND_REGISTRATION_DONE
734 };
735
736 /**
737 * Structure representing the AT91SAM9 NAND controller.
738 */
739 struct nand_flash_controller at91sam9_nand_controller = {
740 .name = "at91sam9",
741 .nand_device_command = at91sam9_nand_device_command,
742 .commands = at91sam9_command_handler,
743 .init = at91sam9_init,
744 .command = at91sam9_command,
745 .reset = at91sam9_reset,
746 .address = at91sam9_address,
747 .read_data = at91sam9_read_data,
748 .write_data = at91sam9_write_data,
749 .nand_ready = at91sam9_nand_ready,
750 .read_block_data = at91sam9_read_block_data,
751 .write_block_data = at91sam9_write_block_data,
752 .read_page = at91sam9_read_page,
753 .write_page = at91sam9_write_page,
754 };