src/flash/nand/arm_io.c

   1 /*
   2  * Copyright (C) 2009 by Marvell Semiconductors, Inc.
   3  * Written by Nicolas Pitre <nico at marvell.com>
   4  *
   5  * Copyright (C) 2009 by David Brownell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the
  19  * Free Software Foundation, Inc.,
  20  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  21  */
  22
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "core.h"
  28 #include "arm_io.h"
  29 #include <helper/binarybuffer.h>
  30 #include <target/arm.h>
  31 #include <target/algorithm.h>
  32
  33 /**
  34  * Copies code to a working area.  This will allocate room for the code plus the
  35  * additional amount requested if the working area pointer is null.
  36  *
  37  * @param target Pointer to the target to copy code to
  38  * @param code Pointer to the code area to be copied
  39  * @param code_size Size of the code being copied
  40  * @param additional Size of the additional area to be allocated in addition to
  41  *                   code
  42  * @param area Pointer to a pointer to a working area to copy code to
  43  * @return Success or failure of the operation
  44  */
  45 static int arm_code_to_working_area(struct target *target,
  46         const uint32_t *code, unsigned code_size,
  47         unsigned additional, struct working_area **area)
  48 {
  49         uint8_t code_buf[code_size];
  50         unsigned i;
  51         int retval;
  52         unsigned size = code_size + additional;
  53
  54         /* REVISIT this assumes size doesn't ever change.
  55          * That's usually correct; but there are boards with
  56          * both large and small page chips, where it won't be...
  57          */
  58
  59         /* make sure we have a working area */
  60         if (NULL == *area) {
  61                 retval = target_alloc_working_area(target, size, area);
  62                 if (retval != ERROR_OK) {
  63                         LOG_DEBUG("%s: no %d byte buffer", __func__, (int) size);
  64                         return ERROR_NAND_NO_BUFFER;
  65                 }
  66         }
  67
  68         /* buffer code in target endianness */
  69         for (i = 0; i < code_size / 4; i++)
  70                 target_buffer_set_u32(target, code_buf + i * 4, code[i]);
  71
  72         /* copy code to work area */
  73         retval = target_write_memory(target, (*area)->address,
  74                         4, code_size / 4, code_buf);
  75
  76         return retval;
  77 }
  78
  79 /**
  80  * ARM-specific bulk write from buffer to address of 8-bit wide NAND.
  81  * For now this only supports ARMv4 and ARMv5 cores.
  82  *
  83  * Enhancements to target_run_algorithm() could enable:
  84  *   - ARMv6 and ARMv7 cores in ARM mode
  85  *
  86  * Different code fragments could handle:
  87  *   - Thumb2 cores like Cortex-M (needs different byteswapping)
  88  *   - 16-bit wide data (needs different setup too)
  89  *
  90  * @param nand Pointer to the arm_nand_data struct that defines the I/O
  91  * @param data Pointer to the data to be copied to flash
  92  * @param size Size of the data being copied
  93  * @return Success or failure of the operation
  94  */
  95 int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
  96 {
  97         struct target *target = nand->target;
  98         struct arm_algorithm algo;
  99         struct arm *arm = target->arch_info;
 100         struct reg_param reg_params[3];
 101         uint32_t target_buf;
 102         uint32_t exit_var = 0;
 103         int retval;
 104
 105         /* Inputs:
 106          *  r0  NAND data address (byte wide)
 107          *  r1  buffer address
 108          *  r2  buffer length
 109          */
 110         static const uint32_t code[] = {
 111                 0xe4d13001,     /* s: ldrb  r3, [r1], #1 */
 112                 0xe5c03000,     /*    strb  r3, [r0]     */
 113                 0xe2522001,     /*    subs  r2, r2, #1   */
 114                 0x1afffffb,     /*    bne   s            */
 115
 116                 /* exit: ARMv4 needs hardware breakpoint */
 117                 0xe1200070,     /* e: bkpt  #0           */
 118         };
 119
 120         if (nand->op != ARM_NAND_WRITE || !nand->copy_area) {
 121                 retval = arm_code_to_working_area(target, code, sizeof(code),
 122                                 nand->chunk_size, &nand->copy_area);
 123                 if (retval != ERROR_OK)
 124                         return retval;
 125         }
 126
 127         nand->op = ARM_NAND_WRITE;
 128
 129         /* copy data to work area */
 130         target_buf = nand->copy_area->address + sizeof(code);
 131         retval = target_write_buffer(target, target_buf, size, data);
 132         if (retval != ERROR_OK)
 133                 return retval;
 134
 135         /* set up algorithm and parameters */
 136         algo.common_magic = ARM_COMMON_MAGIC;
 137         algo.core_mode = ARM_MODE_SVC;
 138         algo.core_state = ARM_STATE_ARM;
 139
 140         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN);
 141         init_reg_param(&reg_params[1], "r1", 32, PARAM_IN);
 142         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN);
 143
 144         buf_set_u32(reg_params[0].value, 0, 32, nand->data);
 145         buf_set_u32(reg_params[1].value, 0, 32, target_buf);
 146         buf_set_u32(reg_params[2].value, 0, 32, size);
 147
 148         /* armv4 must exit using a hardware breakpoint */
 149         if (arm->is_armv4)
 150                 exit_var = nand->copy_area->address + sizeof(code) - 4;
 151
 152         /* use alg to write data from work area to NAND chip */
 153         retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
 154                         nand->copy_area->address, exit_var, 1000, &algo);
 155         if (retval != ERROR_OK)
 156                 LOG_ERROR("error executing hosted NAND write");
 157
 158         destroy_reg_param(&reg_params[0]);
 159         destroy_reg_param(&reg_params[1]);
 160         destroy_reg_param(&reg_params[2]);
 161
 162         return retval;
 163 }
 164
 165 /**
 166  * Uses an on-chip algorithm for an ARM device to read from a NAND device and
 167  * store the data into the host machine's memory.
 168  *
 169  * @param nand Pointer to the arm_nand_data struct that defines the I/O
 170  * @param data Pointer to the data buffer to store the read data
 171  * @param size Amount of data to be stored to the buffer.
 172  * @return Success or failure of the operation
 173  */
 174 int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
 175 {
 176         struct target *target = nand->target;
 177         struct arm_algorithm algo;
 178         struct arm *arm = target->arch_info;
 179         struct reg_param reg_params[3];
 180         uint32_t target_buf;
 181         uint32_t exit_var = 0;
 182         int retval;
 183
 184         /* Inputs:
 185          *  r0  buffer address
 186          *  r1  NAND data address (byte wide)
 187          *  r2  buffer length
 188          */
 189         static const uint32_t code[] = {
 190                 0xe5d13000,     /* s: ldrb  r3, [r1]     */
 191                 0xe4c03001,     /*    strb  r3, [r0], #1 */
 192                 0xe2522001,     /*    subs  r2, r2, #1   */
 193                 0x1afffffb,     /*    bne   s            */
 194
 195                 /* exit: ARMv4 needs hardware breakpoint */
 196                 0xe1200070,     /* e: bkpt  #0           */
 197         };
 198
 199         /* create the copy area if not yet available */
 200         if (nand->op != ARM_NAND_READ || !nand->copy_area) {
 201                 retval = arm_code_to_working_area(target, code, sizeof(code),
 202                                 nand->chunk_size, &nand->copy_area);
 203                 if (retval != ERROR_OK)
 204                         return retval;
 205         }
 206
 207         nand->op = ARM_NAND_READ;
 208         target_buf = nand->copy_area->address + sizeof(code);
 209
 210         /* set up algorithm and parameters */
 211         algo.common_magic = ARM_COMMON_MAGIC;
 212         algo.core_mode = ARM_MODE_SVC;
 213         algo.core_state = ARM_STATE_ARM;
 214
 215         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN);
 216         init_reg_param(&reg_params[1], "r1", 32, PARAM_IN);
 217         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN);
 218
 219         buf_set_u32(reg_params[0].value, 0, 32, target_buf);
 220         buf_set_u32(reg_params[1].value, 0, 32, nand->data);
 221         buf_set_u32(reg_params[2].value, 0, 32, size);
 222
 223         /* armv4 must exit using a hardware breakpoint */
 224         if (arm->is_armv4)
 225                 exit_var = nand->copy_area->address + sizeof(code) - 4;
 226
 227         /* use alg to write data from NAND chip to work area */
 228         retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
 229                         nand->copy_area->address, exit_var, 1000, &algo);
 230         if (retval != ERROR_OK)
 231                 LOG_ERROR("error executing hosted NAND read");
 232
 233         destroy_reg_param(&reg_params[0]);
 234         destroy_reg_param(&reg_params[1]);
 235         destroy_reg_param(&reg_params[2]);
 236
 237         /* read from work area to the host's memory */
 238         retval = target_read_buffer(target, target_buf, size, data);
 239
 240         return retval;
 241 }