bd9554c344c4e8ac027189858c9a08792866d588
[openocd.git] / src / flash / nand.h
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Partially based on linux/include/linux/mtd/nand.h *
6 * Copyright (C) 2000 David Woodhouse <dwmw2@mvhi.com> *
7 * Copyright (C) 2000 Steven J. Hill <sjhill@realitydiluted.com> *
8 * Copyright (C) 2000 Thomas Gleixner <tglx@linutronix.de> *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
25 #ifndef NAND_H
26 #define NAND_H
27
28 #include "flash.h"
29
30 struct nand_device_s;
31
32 typedef struct nand_flash_controller_s
33 {
34 char *name;
35 int (*nand_device_command)(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
36 int (*register_commands)(struct command_context_s *cmd_ctx);
37 int (*init)(struct nand_device_s *device);
38 int (*reset)(struct nand_device_s *device);
39 int (*command)(struct nand_device_s *device, u8 command);
40 int (*address)(struct nand_device_s *device, u8 address);
41 int (*write_data)(struct nand_device_s *device, u16 data);
42 int (*read_data)(struct nand_device_s *device, void *data);
43 int (*write_block_data)(struct nand_device_s *device, u8 *data, int size);
44 int (*read_block_data)(struct nand_device_s *device, u8 *data, int size);
45 int (*write_page)(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
46 int (*read_page)(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
47 int (*controller_ready)(struct nand_device_s *device, int timeout);
48 int (*nand_ready)(struct nand_device_s *device, int timeout);
49 } nand_flash_controller_t;
50
51 typedef struct nand_block_s
52 {
53 u32 offset;
54 u32 size;
55 int is_erased;
56 int is_bad;
57 } nand_block_t;
58
59 struct nand_oobfree {
60 int offset;
61 int length;
62 };
63
64 typedef struct nand_ecclayout_s {
65 int eccbytes;
66 int eccpos[64];
67 int oobavail;
68 struct nand_oobfree oobfree[2];
69 } nand_ecclayout_t;
70
71 typedef struct nand_device_s
72 {
73 nand_flash_controller_t *controller;
74 void *controller_priv;
75 struct nand_manufacturer_s *manufacturer;
76 struct nand_info_s *device;
77 int bus_width;
78 int address_cycles;
79 int page_size;
80 int erase_size;
81 int use_raw;
82 int num_blocks;
83 nand_block_t *blocks;
84 struct nand_device_s *next;
85 } nand_device_t;
86
87 /* NAND Flash Manufacturer ID Codes
88 */
89 enum
90 {
91 NAND_MFR_TOSHIBA = 0x98,
92 NAND_MFR_SAMSUNG = 0xec,
93 NAND_MFR_FUJITSU = 0x04,
94 NAND_MFR_NATIONAL = 0x8f,
95 NAND_MFR_RENESAS = 0x07,
96 NAND_MFR_STMICRO = 0x20,
97 NAND_MFR_HYNIX = 0xad,
98 };
99
100 typedef struct nand_manufacturer_s
101 {
102 int id;
103 char *name;
104 } nand_manufacturer_t;
105
106 typedef struct nand_info_s
107 {
108 char *name;
109 int id;
110 int page_size;
111 int chip_size;
112 int erase_size;
113 int options;
114 } nand_info_t;
115
116 /* Option constants for bizarre disfunctionality and real features
117 */
118 enum {
119 /* Chip can not auto increment pages */
120 NAND_NO_AUTOINCR = 0x00000001,
121
122 /* Buswitdh is 16 bit */
123 NAND_BUSWIDTH_16 = 0x00000002,
124
125 /* Device supports partial programming without padding */
126 NAND_NO_PADDING = 0x00000004,
127
128 /* Chip has cache program function */
129 NAND_CACHEPRG = 0x00000008,
130
131 /* Chip has copy back function */
132 NAND_COPYBACK = 0x00000010,
133
134 /* AND Chip which has 4 banks and a confusing page / block
135 * assignment. See Renesas datasheet for further information */
136 NAND_IS_AND = 0x00000020,
137
138 /* Chip has a array of 4 pages which can be read without
139 * additional ready /busy waits */
140 NAND_4PAGE_ARRAY = 0x00000040,
141
142 /* Chip requires that BBT is periodically rewritten to prevent
143 * bits from adjacent blocks from 'leaking' in altering data.
144 * This happens with the Renesas AG-AND chips, possibly others. */
145 BBT_AUTO_REFRESH = 0x00000080,
146
147 /* Chip does not require ready check on read. True
148 * for all large page devices, as they do not support
149 * autoincrement.*/
150 NAND_NO_READRDY = 0x00000100,
151
152 /* Options valid for Samsung large page devices */
153 NAND_SAMSUNG_LP_OPTIONS = (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK),
154
155 /* Options for new chips with large page size. The pagesize and the
156 * erasesize is determined from the extended id bytes
157 */
158 LP_OPTIONS = (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR),
159 LP_OPTIONS16 = (LP_OPTIONS | NAND_BUSWIDTH_16),
160 };
161
162 enum
163 {
164 /* Standard NAND flash commands */
165 NAND_CMD_READ0 = 0x0,
166 NAND_CMD_READ1 = 0x1,
167 NAND_CMD_RNDOUT = 0x5,
168 NAND_CMD_PAGEPROG = 0x10,
169 NAND_CMD_READOOB = 0x50,
170 NAND_CMD_ERASE1 = 0x60,
171 NAND_CMD_STATUS = 0x70,
172 NAND_CMD_STATUS_MULTI = 0x71,
173 NAND_CMD_SEQIN = 0x80,
174 NAND_CMD_RNDIN = 0x85,
175 NAND_CMD_READID = 0x90,
176 NAND_CMD_ERASE2 = 0xd0,
177 NAND_CMD_RESET = 0xff,
178
179 /* Extended commands for large page devices */
180 NAND_CMD_READSTART = 0x30,
181 NAND_CMD_RNDOUTSTART = 0xE0,
182 NAND_CMD_CACHEDPROG = 0x15,
183 };
184
185 /* Status bits */
186 enum
187 {
188 NAND_STATUS_FAIL = 0x01,
189 NAND_STATUS_FAIL_N1 = 0x02,
190 NAND_STATUS_TRUE_READY = 0x20,
191 NAND_STATUS_READY = 0x40,
192 NAND_STATUS_WP = 0x80,
193 };
194
195 /* OOB (spare) data formats */
196 enum oob_formats
197 {
198 NAND_OOB_NONE = 0x0, /* no OOB data at all */
199 NAND_OOB_RAW = 0x1, /* raw OOB data (16 bytes for 512b page sizes, 64 bytes for 2048b page sizes) */
200 NAND_OOB_ONLY = 0x2, /* only OOB data */
201 NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
202 NAND_OOB_HW_ECC = 0x20, /* when writing, use HW ECC (as opposed to no ECC) */
203 NAND_OOB_JFFS2 = 0x100, /* when writing, use JFFS2 OOB layout */
204 NAND_OOB_YAFFS2 = 0x100,/* when writing, use YAFFS2 OOB layout */
205 };
206
207 /* Function prototypes */
208 extern nand_device_t *get_nand_device_by_num(int num);
209 extern int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
210 extern int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
211 extern int nand_read_status(struct nand_device_s *device, u8 *status);
212 extern int nand_calculate_ecc(struct nand_device_s *device, const u8 *dat, u8 *ecc_code);
213
214 extern int nand_register_commands(struct command_context_s *cmd_ctx);
215 extern int nand_init(struct command_context_s *cmd_ctx);
216
217 #define ERROR_NAND_DEVICE_INVALID (-1100)
218 #define ERROR_NAND_OPERATION_FAILED (-1101)
219 #define ERROR_NAND_OPERATION_TIMEOUT (-1102)
220 #define ERROR_NAND_OPERATION_NOT_SUPPORTED (-1103)
221 #define ERROR_NAND_DEVICE_NOT_PROBED (-1104)
222 #define ERROR_NAND_ERROR_CORRECTION_FAILED (-1105)
223
224 #endif /* NAND_H */