5b19d5a95056ee209e94e214f7d9f7c1171d55a6
[openocd.git] / src / flash / nand.h
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Partially based on linux/include/linux/mtd/nand.h *
6 * Copyright (C) 2000 David Woodhouse <dwmw2@mvhi.com> *
7 * Copyright (C) 2000 Steven J. Hill <sjhill@realitydiluted.com> *
8 * Copyright (C) 2000 Thomas Gleixner <tglx@linutronix.de> *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
25 #ifndef NAND_H
26 #define NAND_H
27
28 #include "flash.h"
29
30 struct nand_device_s;
31
32 typedef struct nand_flash_controller_s
33 {
34 char *name;
35 int (*nand_device_command)(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
36 int (*register_commands)(struct command_context_s *cmd_ctx);
37 int (*init)(struct nand_device_s *device);
38 int (*reset)(struct nand_device_s *device);
39 int (*command)(struct nand_device_s *device, uint8_t command);
40 int (*address)(struct nand_device_s *device, uint8_t address);
41 int (*write_data)(struct nand_device_s *device, uint16_t data);
42 int (*read_data)(struct nand_device_s *device, void *data);
43 int (*write_block_data)(struct nand_device_s *device, uint8_t *data, int size);
44 int (*read_block_data)(struct nand_device_s *device, uint8_t *data, int size);
45 int (*write_page)(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
46 int (*read_page)(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
47 int (*controller_ready)(struct nand_device_s *device, int timeout);
48 int (*nand_ready)(struct nand_device_s *device, int timeout);
49 } nand_flash_controller_t;
50
51 typedef struct nand_block_s
52 {
53 uint32_t offset;
54 uint32_t size;
55 int is_erased;
56 int is_bad;
57 } nand_block_t;
58
59 struct nand_oobfree {
60 int offset;
61 int length;
62 };
63
64 typedef struct nand_ecclayout_s {
65 int eccbytes;
66 int eccpos[64];
67 int oobavail;
68 struct nand_oobfree oobfree[2];
69 } nand_ecclayout_t;
70
71 typedef struct nand_device_s
72 {
73 nand_flash_controller_t *controller;
74 void *controller_priv;
75 struct nand_manufacturer_s *manufacturer;
76 struct nand_info_s *device;
77 int bus_width;
78 int address_cycles;
79 int page_size;
80 int erase_size;
81 int use_raw;
82 int num_blocks;
83 nand_block_t *blocks;
84 struct nand_device_s *next;
85 } nand_device_t;
86
87 /* NAND Flash Manufacturer ID Codes
88 */
89 enum
90 {
91 NAND_MFR_TOSHIBA = 0x98,
92 NAND_MFR_SAMSUNG = 0xec,
93 NAND_MFR_FUJITSU = 0x04,
94 NAND_MFR_NATIONAL = 0x8f,
95 NAND_MFR_RENESAS = 0x07,
96 NAND_MFR_STMICRO = 0x20,
97 NAND_MFR_HYNIX = 0xad,
98 NAND_MFR_MICRON = 0x2c,
99 };
100
101 typedef struct nand_manufacturer_s
102 {
103 int id;
104 char *name;
105 } nand_manufacturer_t;
106
107 typedef struct nand_info_s
108 {
109 char *name;
110 int id;
111 int page_size;
112 int chip_size;
113 int erase_size;
114 int options;
115 } nand_info_t;
116
117 /* Option constants for bizarre disfunctionality and real features
118 */
119 enum {
120 /* Chip can not auto increment pages */
121 NAND_NO_AUTOINCR = 0x00000001,
122
123 /* Buswitdh is 16 bit */
124 NAND_BUSWIDTH_16 = 0x00000002,
125
126 /* Device supports partial programming without padding */
127 NAND_NO_PADDING = 0x00000004,
128
129 /* Chip has cache program function */
130 NAND_CACHEPRG = 0x00000008,
131
132 /* Chip has copy back function */
133 NAND_COPYBACK = 0x00000010,
134
135 /* AND Chip which has 4 banks and a confusing page / block
136 * assignment. See Renesas datasheet for further information */
137 NAND_IS_AND = 0x00000020,
138
139 /* Chip has a array of 4 pages which can be read without
140 * additional ready /busy waits */
141 NAND_4PAGE_ARRAY = 0x00000040,
142
143 /* Chip requires that BBT is periodically rewritten to prevent
144 * bits from adjacent blocks from 'leaking' in altering data.
145 * This happens with the Renesas AG-AND chips, possibly others. */
146 BBT_AUTO_REFRESH = 0x00000080,
147
148 /* Chip does not require ready check on read. True
149 * for all large page devices, as they do not support
150 * autoincrement.*/
151 NAND_NO_READRDY = 0x00000100,
152
153 /* Options valid for Samsung large page devices */
154 NAND_SAMSUNG_LP_OPTIONS = (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK),
155
156 /* Options for new chips with large page size. The pagesize and the
157 * erasesize is determined from the extended id bytes
158 */
159 LP_OPTIONS = (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR),
160 LP_OPTIONS16 = (LP_OPTIONS | NAND_BUSWIDTH_16),
161 };
162
163 enum
164 {
165 /* Standard NAND flash commands */
166 NAND_CMD_READ0 = 0x0,
167 NAND_CMD_READ1 = 0x1,
168 NAND_CMD_RNDOUT = 0x5,
169 NAND_CMD_PAGEPROG = 0x10,
170 NAND_CMD_READOOB = 0x50,
171 NAND_CMD_ERASE1 = 0x60,
172 NAND_CMD_STATUS = 0x70,
173 NAND_CMD_STATUS_MULTI = 0x71,
174 NAND_CMD_SEQIN = 0x80,
175 NAND_CMD_RNDIN = 0x85,
176 NAND_CMD_READID = 0x90,
177 NAND_CMD_ERASE2 = 0xd0,
178 NAND_CMD_RESET = 0xff,
179
180 /* Extended commands for large page devices */
181 NAND_CMD_READSTART = 0x30,
182 NAND_CMD_RNDOUTSTART = 0xE0,
183 NAND_CMD_CACHEDPROG = 0x15,
184 };
185
186 /* Status bits */
187 enum
188 {
189 NAND_STATUS_FAIL = 0x01,
190 NAND_STATUS_FAIL_N1 = 0x02,
191 NAND_STATUS_TRUE_READY = 0x20,
192 NAND_STATUS_READY = 0x40,
193 NAND_STATUS_WP = 0x80,
194 };
195
196 /* OOB (spare) data formats */
197 enum oob_formats
198 {
199 NAND_OOB_NONE = 0x0, /* no OOB data at all */
200 NAND_OOB_RAW = 0x1, /* raw OOB data (16 bytes for 512b page sizes, 64 bytes for 2048b page sizes) */
201 NAND_OOB_ONLY = 0x2, /* only OOB data */
202 NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
203 NAND_OOB_HW_ECC = 0x20, /* when writing, use HW ECC (as opposed to no ECC) */
204 NAND_OOB_SW_ECC_KW = 0x40, /* when writing, use Marvell's Kirkwood bootrom format */
205 NAND_OOB_JFFS2 = 0x100, /* when writing, use JFFS2 OOB layout */
206 NAND_OOB_YAFFS2 = 0x100,/* when writing, use YAFFS2 OOB layout */
207 };
208
209
210 nand_device_t *get_nand_device_by_num(int num);
211
212 int nand_read_page_raw(struct nand_device_s *device, uint32_t page,
213 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
214 int nand_write_page_raw(struct nand_device_s *device, uint32_t page,
215 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
216
217 int nand_read_status(struct nand_device_s *device, uint8_t *status);
218
219 int nand_calculate_ecc(struct nand_device_s *device,
220 const uint8_t *dat, uint8_t *ecc_code);
221 int nand_calculate_ecc_kw(struct nand_device_s *device,
222 const uint8_t *dat, uint8_t *ecc_code);
223
224 int nand_register_commands(struct command_context_s *cmd_ctx);
225 int nand_init(struct command_context_s *cmd_ctx);
226
227 /// helper for parsing a nand device command argument string
228 int nand_command_get_device_by_num(struct command_context_s *cmd_ctx,
229 const char *str, nand_device_t **device);
230
231
232 #define ERROR_NAND_DEVICE_INVALID (-1100)
233 #define ERROR_NAND_OPERATION_FAILED (-1101)
234 #define ERROR_NAND_OPERATION_TIMEOUT (-1102)
235 #define ERROR_NAND_OPERATION_NOT_SUPPORTED (-1103)
236 #define ERROR_NAND_DEVICE_NOT_PROBED (-1104)
237 #define ERROR_NAND_ERROR_CORRECTION_FAILED (-1105)
238 #define ERROR_NAND_NO_BUFFER (-1106)
239
240 #endif /* NAND_H */