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nand: factor init to 'nand init'
[openocd.git] / src / flash / nand.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "nand.h"
28 #include "common.h"
29 #include "time_support.h"
30 #include "fileio.h"
31
32 static int nand_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
33 //static int nand_read_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size);
34
35 static int nand_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
36
37 /* NAND flash controller
38 */
39 extern struct nand_flash_controller nonce_nand_controller;
40 extern struct nand_flash_controller davinci_nand_controller;
41 extern struct nand_flash_controller lpc3180_nand_controller;
42 extern struct nand_flash_controller orion_nand_controller;
43 extern struct nand_flash_controller s3c2410_nand_controller;
44 extern struct nand_flash_controller s3c2412_nand_controller;
45 extern struct nand_flash_controller s3c2440_nand_controller;
46 extern struct nand_flash_controller s3c2443_nand_controller;
47 extern struct nand_flash_controller imx31_nand_flash_controller;
48
49 /* extern struct nand_flash_controller boundary_scan_nand_controller; */
50
51 static struct nand_flash_controller *nand_flash_controllers[] =
52 {
53 &nonce_nand_controller,
54 &davinci_nand_controller,
55 &lpc3180_nand_controller,
56 &orion_nand_controller,
57 &s3c2410_nand_controller,
58 &s3c2412_nand_controller,
59 &s3c2440_nand_controller,
60 &s3c2443_nand_controller,
61 &imx31_nand_flash_controller,
62 /* &boundary_scan_nand_controller, */
63 NULL
64 };
65
66 /* configured NAND devices and NAND Flash command handler */
67 static struct nand_device *nand_devices = NULL;
68
69 /* Chip ID list
70 *
71 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
72 * options
73 *
74 * Pagesize; 0, 256, 512
75 * 0 get this information from the extended chip ID
76 * 256 256 Byte page size
77 * 512 512 Byte page size
78 */
79 static struct nand_info nand_flash_ids[] =
80 {
81 /* start "museum" IDs */
82 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
83 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
84 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
85 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
86 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
87 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
88 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
89 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
90 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
91 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
92
93 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
94 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
95 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
96 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
97 /* end "museum" IDs */
98
99 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
100 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
101 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
102 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
103
104 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
105 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
106 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
107 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
108
109 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
110 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
111 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
112 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
113
114 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
115 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
116 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
117 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
118 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
119 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
120 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
121
122 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
123
124 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
125 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
126 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
127 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
128
129 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
130 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
131 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
132 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
133
134 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
135 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
136 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
137 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
138
139 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
140 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
141 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
142 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
143
144 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
145 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
146 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
147 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
148
149 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
150 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
151 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
152 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
153
154 {NULL, 0, 0, 0, 0, 0 }
155 };
156
157 /* Manufacturer ID list
158 */
159 static struct nand_manufacturer nand_manuf_ids[] =
160 {
161 {0x0, "unknown"},
162 {NAND_MFR_TOSHIBA, "Toshiba"},
163 {NAND_MFR_SAMSUNG, "Samsung"},
164 {NAND_MFR_FUJITSU, "Fujitsu"},
165 {NAND_MFR_NATIONAL, "National"},
166 {NAND_MFR_RENESAS, "Renesas"},
167 {NAND_MFR_STMICRO, "ST Micro"},
168 {NAND_MFR_HYNIX, "Hynix"},
169 {NAND_MFR_MICRON, "Micron"},
170 {0x0, NULL},
171 };
172
173 /*
174 * Define default oob placement schemes for large and small page devices
175 */
176
177 #if 0
178 static struct nand_ecclayout nand_oob_8 = {
179 .eccbytes = 3,
180 .eccpos = {0, 1, 2},
181 .oobfree = {
182 {.offset = 3,
183 .length = 2},
184 {.offset = 6,
185 .length = 2}}
186 };
187 #endif
188
189 static struct nand_ecclayout nand_oob_16 = {
190 .eccbytes = 6,
191 .eccpos = {0, 1, 2, 3, 6, 7},
192 .oobfree = {
193 {.offset = 8,
194 . length = 8}}
195 };
196
197 static struct nand_ecclayout nand_oob_64 = {
198 .eccbytes = 24,
199 .eccpos = {
200 40, 41, 42, 43, 44, 45, 46, 47,
201 48, 49, 50, 51, 52, 53, 54, 55,
202 56, 57, 58, 59, 60, 61, 62, 63},
203 .oobfree = {
204 {.offset = 2,
205 .length = 38}}
206 };
207
208 COMMAND_HANDLER(handle_nand_list_drivers)
209 {
210 command_print(CMD_CTX, "Available NAND flash controller drivers:");
211 for (unsigned i = 0; nand_flash_controllers[i]; i++)
212 command_print(CMD_CTX, " %s", nand_flash_controllers[i]->name);
213 return ERROR_OK;
214 }
215
216 static COMMAND_HELPER(create_nand_device, const char *bank_name,
217 struct nand_flash_controller *controller)
218 {
219 if (NULL != controller->commands)
220 {
221 int retval = register_commands(CMD_CTX, NULL,
222 controller->commands);
223 if (ERROR_OK != retval)
224 return retval;
225 }
226 struct nand_device *c = malloc(sizeof(struct nand_device));
227
228 c->name = strdup(bank_name);
229 c->controller = controller;
230 c->controller_priv = NULL;
231 c->manufacturer = NULL;
232 c->device = NULL;
233 c->bus_width = 0;
234 c->address_cycles = 0;
235 c->page_size = 0;
236 c->use_raw = 0;
237 c->next = NULL;
238
239 int retval = CALL_COMMAND_HANDLER(controller->nand_device_command, c);
240 if (ERROR_OK != retval)
241 {
242 LOG_ERROR("'%s' driver rejected nand flash", controller->name);
243 free(c);
244 return ERROR_OK;
245 }
246
247 if (nand_devices) {
248 struct nand_device *p = nand_devices;
249 while (p && p->next) p = p->next;
250 p->next = c;
251 } else
252 nand_devices = c;
253
254 return ERROR_OK;
255 }
256
257 COMMAND_HANDLER(handle_nand_device_command)
258 {
259 if (CMD_ARGC < 1)
260 {
261 LOG_ERROR("incomplete nand device configuration");
262 return ERROR_FLASH_BANK_INVALID;
263 }
264
265 // save name and increment (for compatibility) with drivers
266 const char *bank_name = *CMD_ARGV++;
267 CMD_ARGC--;
268
269 const char *driver_name = CMD_ARGV[0];
270 for (unsigned i = 0; nand_flash_controllers[i]; i++)
271 {
272 struct nand_flash_controller *controller = nand_flash_controllers[i];
273 if (strcmp(driver_name, controller->name) != 0)
274 continue;
275
276 return CALL_COMMAND_HANDLER(create_nand_device,
277 bank_name, controller);
278 }
279
280 LOG_ERROR("No valid NAND flash driver found (%s)", driver_name);
281 return CALL_COMMAND_HANDLER(handle_nand_list_drivers);
282 }
283
284
285 COMMAND_HANDLER(handle_nand_init_command);
286
287 static const struct command_registration nand_config_command_handlers[] = {
288 {
289 .name = "device",
290 .handler = &handle_nand_device_command,
291 .mode = COMMAND_CONFIG,
292 .help = "defines a new NAND bank",
293 },
294 {
295 .name = "drivers",
296 .handler = &handle_nand_list_drivers,
297 .mode = COMMAND_ANY,
298 .help = "lists available NAND drivers",
299 },
300 {
301 .name = "init",
302 .mode = COMMAND_CONFIG,
303 .handler = &handle_nand_init_command,
304 .help = "initialize NAND devices",
305 },
306 COMMAND_REGISTRATION_DONE
307 };
308 static const struct command_registration nand_command_handlers[] = {
309 {
310 .name = "nand",
311 .mode = COMMAND_ANY,
312 .help = "NAND flash command group",
313 .chain = nand_config_command_handlers,
314 },
315 COMMAND_REGISTRATION_DONE
316 };
317
318 int nand_register_commands(struct command_context *cmd_ctx)
319 {
320 return register_commands(cmd_ctx, NULL, nand_command_handlers);
321 }
322
323 struct nand_device *get_nand_device_by_name(const char *name)
324 {
325 unsigned requested = get_flash_name_index(name);
326 unsigned found = 0;
327
328 struct nand_device *nand;
329 for (nand = nand_devices; NULL != nand; nand = nand->next)
330 {
331 if (strcmp(nand->name, name) == 0)
332 return nand;
333 if (!flash_driver_name_matches(nand->controller->name, name))
334 continue;
335 if (++found < requested)
336 continue;
337 return nand;
338 }
339 return NULL;
340 }
341
342 struct nand_device *get_nand_device_by_num(int num)
343 {
344 struct nand_device *p;
345 int i = 0;
346
347 for (p = nand_devices; p; p = p->next)
348 {
349 if (i++ == num)
350 {
351 return p;
352 }
353 }
354
355 return NULL;
356 }
357
358 COMMAND_HELPER(nand_command_get_device, unsigned name_index,
359 struct nand_device **nand)
360 {
361 const char *str = CMD_ARGV[name_index];
362 *nand = get_nand_device_by_name(str);
363 if (*nand)
364 return ERROR_OK;
365
366 unsigned num;
367 COMMAND_PARSE_NUMBER(uint, str, num);
368 *nand = get_nand_device_by_num(num);
369 if (!*nand) {
370 command_print(CMD_CTX, "NAND flash device '%s' not found", str);
371 return ERROR_INVALID_ARGUMENTS;
372 }
373 return ERROR_OK;
374 }
375
376 static int nand_build_bbt(struct nand_device *nand, int first, int last)
377 {
378 uint32_t page = 0x0;
379 int i;
380 uint8_t oob[6];
381
382 if ((first < 0) || (first >= nand->num_blocks))
383 first = 0;
384
385 if ((last >= nand->num_blocks) || (last == -1))
386 last = nand->num_blocks - 1;
387
388 for (i = first; i < last; i++)
389 {
390 nand_read_page(nand, page, NULL, 0, oob, 6);
391
392 if (((nand->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
393 || (((nand->page_size == 512) && (oob[5] != 0xff)) ||
394 ((nand->page_size == 2048) && (oob[0] != 0xff))))
395 {
396 LOG_WARNING("bad block: %i", i);
397 nand->blocks[i].is_bad = 1;
398 }
399 else
400 {
401 nand->blocks[i].is_bad = 0;
402 }
403
404 page += (nand->erase_size / nand->page_size);
405 }
406
407 return ERROR_OK;
408 }
409
410 int nand_read_status(struct nand_device *nand, uint8_t *status)
411 {
412 if (!nand->device)
413 return ERROR_NAND_DEVICE_NOT_PROBED;
414
415 /* Send read status command */
416 nand->controller->command(nand, NAND_CMD_STATUS);
417
418 alive_sleep(1);
419
420 /* read status */
421 if (nand->device->options & NAND_BUSWIDTH_16)
422 {
423 uint16_t data;
424 nand->controller->read_data(nand, &data);
425 *status = data & 0xff;
426 }
427 else
428 {
429 nand->controller->read_data(nand, status);
430 }
431
432 return ERROR_OK;
433 }
434
435 static int nand_poll_ready(struct nand_device *nand, int timeout)
436 {
437 uint8_t status;
438
439 nand->controller->command(nand, NAND_CMD_STATUS);
440 do {
441 if (nand->device->options & NAND_BUSWIDTH_16) {
442 uint16_t data;
443 nand->controller->read_data(nand, &data);
444 status = data & 0xff;
445 } else {
446 nand->controller->read_data(nand, &status);
447 }
448 if (status & NAND_STATUS_READY)
449 break;
450 alive_sleep(1);
451 } while (timeout--);
452
453 return (status & NAND_STATUS_READY) != 0;
454 }
455
456 int nand_probe(struct nand_device *nand)
457 {
458 uint8_t manufacturer_id, device_id;
459 uint8_t id_buff[6];
460 int retval;
461 int i;
462
463 /* clear device data */
464 nand->device = NULL;
465 nand->manufacturer = NULL;
466
467 /* clear device parameters */
468 nand->bus_width = 0;
469 nand->address_cycles = 0;
470 nand->page_size = 0;
471 nand->erase_size = 0;
472
473 /* initialize controller (device parameters are zero, use controller default) */
474 if ((retval = nand->controller->init(nand) != ERROR_OK))
475 {
476 switch (retval)
477 {
478 case ERROR_NAND_OPERATION_FAILED:
479 LOG_DEBUG("controller initialization failed");
480 return ERROR_NAND_OPERATION_FAILED;
481 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
482 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
483 return ERROR_NAND_OPERATION_FAILED;
484 default:
485 LOG_ERROR("BUG: unknown controller initialization failure");
486 return ERROR_NAND_OPERATION_FAILED;
487 }
488 }
489
490 nand->controller->command(nand, NAND_CMD_RESET);
491 nand->controller->reset(nand);
492
493 nand->controller->command(nand, NAND_CMD_READID);
494 nand->controller->address(nand, 0x0);
495
496 if (nand->bus_width == 8)
497 {
498 nand->controller->read_data(nand, &manufacturer_id);
499 nand->controller->read_data(nand, &device_id);
500 }
501 else
502 {
503 uint16_t data_buf;
504 nand->controller->read_data(nand, &data_buf);
505 manufacturer_id = data_buf & 0xff;
506 nand->controller->read_data(nand, &data_buf);
507 device_id = data_buf & 0xff;
508 }
509
510 for (i = 0; nand_flash_ids[i].name; i++)
511 {
512 if (nand_flash_ids[i].id == device_id)
513 {
514 nand->device = &nand_flash_ids[i];
515 break;
516 }
517 }
518
519 for (i = 0; nand_manuf_ids[i].name; i++)
520 {
521 if (nand_manuf_ids[i].id == manufacturer_id)
522 {
523 nand->manufacturer = &nand_manuf_ids[i];
524 break;
525 }
526 }
527
528 if (!nand->manufacturer)
529 {
530 nand->manufacturer = &nand_manuf_ids[0];
531 nand->manufacturer->id = manufacturer_id;
532 }
533
534 if (!nand->device)
535 {
536 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
537 manufacturer_id, device_id);
538 return ERROR_NAND_OPERATION_FAILED;
539 }
540
541 LOG_DEBUG("found %s (%s)", nand->device->name, nand->manufacturer->name);
542
543 /* initialize device parameters */
544
545 /* bus width */
546 if (nand->device->options & NAND_BUSWIDTH_16)
547 nand->bus_width = 16;
548 else
549 nand->bus_width = 8;
550
551 /* Do we need extended device probe information? */
552 if (nand->device->page_size == 0 ||
553 nand->device->erase_size == 0)
554 {
555 if (nand->bus_width == 8)
556 {
557 nand->controller->read_data(nand, id_buff + 3);
558 nand->controller->read_data(nand, id_buff + 4);
559 nand->controller->read_data(nand, id_buff + 5);
560 }
561 else
562 {
563 uint16_t data_buf;
564
565 nand->controller->read_data(nand, &data_buf);
566 id_buff[3] = data_buf;
567
568 nand->controller->read_data(nand, &data_buf);
569 id_buff[4] = data_buf;
570
571 nand->controller->read_data(nand, &data_buf);
572 id_buff[5] = data_buf >> 8;
573 }
574 }
575
576 /* page size */
577 if (nand->device->page_size == 0)
578 {
579 nand->page_size = 1 << (10 + (id_buff[4] & 3));
580 }
581 else if (nand->device->page_size == 256)
582 {
583 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
584 return ERROR_NAND_OPERATION_FAILED;
585 }
586 else
587 {
588 nand->page_size = nand->device->page_size;
589 }
590
591 /* number of address cycles */
592 if (nand->page_size <= 512)
593 {
594 /* small page devices */
595 if (nand->device->chip_size <= 32)
596 nand->address_cycles = 3;
597 else if (nand->device->chip_size <= 8*1024)
598 nand->address_cycles = 4;
599 else
600 {
601 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
602 nand->address_cycles = 5;
603 }
604 }
605 else
606 {
607 /* large page devices */
608 if (nand->device->chip_size <= 128)
609 nand->address_cycles = 4;
610 else if (nand->device->chip_size <= 32*1024)
611 nand->address_cycles = 5;
612 else
613 {
614 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
615 nand->address_cycles = 6;
616 }
617 }
618
619 /* erase size */
620 if (nand->device->erase_size == 0)
621 {
622 switch ((id_buff[4] >> 4) & 3) {
623 case 0:
624 nand->erase_size = 64 << 10;
625 break;
626 case 1:
627 nand->erase_size = 128 << 10;
628 break;
629 case 2:
630 nand->erase_size = 256 << 10;
631 break;
632 case 3:
633 nand->erase_size =512 << 10;
634 break;
635 }
636 }
637 else
638 {
639 nand->erase_size = nand->device->erase_size;
640 }
641
642 /* initialize controller, but leave parameters at the controllers default */
643 if ((retval = nand->controller->init(nand) != ERROR_OK))
644 {
645 switch (retval)
646 {
647 case ERROR_NAND_OPERATION_FAILED:
648 LOG_DEBUG("controller initialization failed");
649 return ERROR_NAND_OPERATION_FAILED;
650 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
651 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
652 nand->bus_width, nand->address_cycles, nand->page_size);
653 return ERROR_NAND_OPERATION_FAILED;
654 default:
655 LOG_ERROR("BUG: unknown controller initialization failure");
656 return ERROR_NAND_OPERATION_FAILED;
657 }
658 }
659
660 nand->num_blocks = (nand->device->chip_size * 1024) / (nand->erase_size / 1024);
661 nand->blocks = malloc(sizeof(struct nand_block) * nand->num_blocks);
662
663 for (i = 0; i < nand->num_blocks; i++)
664 {
665 nand->blocks[i].size = nand->erase_size;
666 nand->blocks[i].offset = i * nand->erase_size;
667 nand->blocks[i].is_erased = -1;
668 nand->blocks[i].is_bad = -1;
669 }
670
671 return ERROR_OK;
672 }
673
674 static int nand_erase(struct nand_device *nand, int first_block, int last_block)
675 {
676 int i;
677 uint32_t page;
678 uint8_t status;
679 int retval;
680
681 if (!nand->device)
682 return ERROR_NAND_DEVICE_NOT_PROBED;
683
684 if ((first_block < 0) || (last_block > nand->num_blocks))
685 return ERROR_INVALID_ARGUMENTS;
686
687 /* make sure we know if a block is bad before erasing it */
688 for (i = first_block; i <= last_block; i++)
689 {
690 if (nand->blocks[i].is_bad == -1)
691 {
692 nand_build_bbt(nand, i, last_block);
693 break;
694 }
695 }
696
697 for (i = first_block; i <= last_block; i++)
698 {
699 /* Send erase setup command */
700 nand->controller->command(nand, NAND_CMD_ERASE1);
701
702 page = i * (nand->erase_size / nand->page_size);
703
704 /* Send page address */
705 if (nand->page_size <= 512)
706 {
707 /* row */
708 nand->controller->address(nand, page & 0xff);
709 nand->controller->address(nand, (page >> 8) & 0xff);
710
711 /* 3rd cycle only on devices with more than 32 MiB */
712 if (nand->address_cycles >= 4)
713 nand->controller->address(nand, (page >> 16) & 0xff);
714
715 /* 4th cycle only on devices with more than 8 GiB */
716 if (nand->address_cycles >= 5)
717 nand->controller->address(nand, (page >> 24) & 0xff);
718 }
719 else
720 {
721 /* row */
722 nand->controller->address(nand, page & 0xff);
723 nand->controller->address(nand, (page >> 8) & 0xff);
724
725 /* 3rd cycle only on devices with more than 128 MiB */
726 if (nand->address_cycles >= 5)
727 nand->controller->address(nand, (page >> 16) & 0xff);
728 }
729
730 /* Send erase confirm command */
731 nand->controller->command(nand, NAND_CMD_ERASE2);
732
733 retval = nand->controller->nand_ready ?
734 nand->controller->nand_ready(nand, 1000) :
735 nand_poll_ready(nand, 1000);
736 if (!retval) {
737 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
738 return ERROR_NAND_OPERATION_TIMEOUT;
739 }
740
741 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
742 {
743 LOG_ERROR("couldn't read status");
744 return ERROR_NAND_OPERATION_FAILED;
745 }
746
747 if (status & 0x1)
748 {
749 LOG_ERROR("didn't erase %sblock %d; status: 0x%2.2x",
750 (nand->blocks[i].is_bad == 1)
751 ? "bad " : "",
752 i, status);
753 /* continue; other blocks might still be erasable */
754 }
755
756 nand->blocks[i].is_erased = 1;
757 }
758
759 return ERROR_OK;
760 }
761
762 #if 0
763 static int nand_read_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size)
764 {
765 uint8_t *page;
766
767 if (!nand->device)
768 return ERROR_NAND_DEVICE_NOT_PROBED;
769
770 if (address % nand->page_size)
771 {
772 LOG_ERROR("reads need to be page aligned");
773 return ERROR_NAND_OPERATION_FAILED;
774 }
775
776 page = malloc(nand->page_size);
777
778 while (data_size > 0)
779 {
780 uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
781 uint32_t page_address;
782
783
784 page_address = address / nand->page_size;
785
786 nand_read_page(nand, page_address, page, nand->page_size, NULL, 0);
787
788 memcpy(data, page, thisrun_size);
789
790 address += thisrun_size;
791 data += thisrun_size;
792 data_size -= thisrun_size;
793 }
794
795 free(page);
796
797 return ERROR_OK;
798 }
799
800 static int nand_write_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size)
801 {
802 uint8_t *page;
803
804 if (!nand->device)
805 return ERROR_NAND_DEVICE_NOT_PROBED;
806
807 if (address % nand->page_size)
808 {
809 LOG_ERROR("writes need to be page aligned");
810 return ERROR_NAND_OPERATION_FAILED;
811 }
812
813 page = malloc(nand->page_size);
814
815 while (data_size > 0)
816 {
817 uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
818 uint32_t page_address;
819
820 memset(page, 0xff, nand->page_size);
821 memcpy(page, data, thisrun_size);
822
823 page_address = address / nand->page_size;
824
825 nand_write_page(nand, page_address, page, nand->page_size, NULL, 0);
826
827 address += thisrun_size;
828 data += thisrun_size;
829 data_size -= thisrun_size;
830 }
831
832 free(page);
833
834 return ERROR_OK;
835 }
836 #endif
837
838 int nand_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
839 {
840 uint32_t block;
841
842 if (!nand->device)
843 return ERROR_NAND_DEVICE_NOT_PROBED;
844
845 block = page / (nand->erase_size / nand->page_size);
846 if (nand->blocks[block].is_erased == 1)
847 nand->blocks[block].is_erased = 0;
848
849 if (nand->use_raw || nand->controller->write_page == NULL)
850 return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
851 else
852 return nand->controller->write_page(nand, page, data, data_size, oob, oob_size);
853 }
854
855 static int nand_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
856 {
857 if (!nand->device)
858 return ERROR_NAND_DEVICE_NOT_PROBED;
859
860 if (nand->use_raw || nand->controller->read_page == NULL)
861 return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
862 else
863 return nand->controller->read_page(nand, page, data, data_size, oob, oob_size);
864 }
865
866 int nand_read_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
867 {
868 uint32_t i;
869
870 if (!nand->device)
871 return ERROR_NAND_DEVICE_NOT_PROBED;
872
873 if (nand->page_size <= 512)
874 {
875 /* small page device */
876 if (data)
877 nand->controller->command(nand, NAND_CMD_READ0);
878 else
879 nand->controller->command(nand, NAND_CMD_READOOB);
880
881 /* column (always 0, we start at the beginning of a page/OOB area) */
882 nand->controller->address(nand, 0x0);
883
884 /* row */
885 nand->controller->address(nand, page & 0xff);
886 nand->controller->address(nand, (page >> 8) & 0xff);
887
888 /* 4th cycle only on devices with more than 32 MiB */
889 if (nand->address_cycles >= 4)
890 nand->controller->address(nand, (page >> 16) & 0xff);
891
892 /* 5th cycle only on devices with more than 8 GiB */
893 if (nand->address_cycles >= 5)
894 nand->controller->address(nand, (page >> 24) & 0xff);
895 }
896 else
897 {
898 /* large page device */
899 nand->controller->command(nand, NAND_CMD_READ0);
900
901 /* column (0 when we start at the beginning of a page,
902 * or 2048 for the beginning of OOB area)
903 */
904 nand->controller->address(nand, 0x0);
905 if (data)
906 nand->controller->address(nand, 0x0);
907 else
908 nand->controller->address(nand, 0x8);
909
910 /* row */
911 nand->controller->address(nand, page & 0xff);
912 nand->controller->address(nand, (page >> 8) & 0xff);
913
914 /* 5th cycle only on devices with more than 128 MiB */
915 if (nand->address_cycles >= 5)
916 nand->controller->address(nand, (page >> 16) & 0xff);
917
918 /* large page devices need a start command */
919 nand->controller->command(nand, NAND_CMD_READSTART);
920 }
921
922 if (nand->controller->nand_ready) {
923 if (!nand->controller->nand_ready(nand, 100))
924 return ERROR_NAND_OPERATION_TIMEOUT;
925 } else {
926 alive_sleep(1);
927 }
928
929 if (data)
930 {
931 if (nand->controller->read_block_data != NULL)
932 (nand->controller->read_block_data)(nand, data, data_size);
933 else
934 {
935 for (i = 0; i < data_size;)
936 {
937 if (nand->device->options & NAND_BUSWIDTH_16)
938 {
939 nand->controller->read_data(nand, data);
940 data += 2;
941 i += 2;
942 }
943 else
944 {
945 nand->controller->read_data(nand, data);
946 data += 1;
947 i += 1;
948 }
949 }
950 }
951 }
952
953 if (oob)
954 {
955 if (nand->controller->read_block_data != NULL)
956 (nand->controller->read_block_data)(nand, oob, oob_size);
957 else
958 {
959 for (i = 0; i < oob_size;)
960 {
961 if (nand->device->options & NAND_BUSWIDTH_16)
962 {
963 nand->controller->read_data(nand, oob);
964 oob += 2;
965 i += 2;
966 }
967 else
968 {
969 nand->controller->read_data(nand, oob);
970 oob += 1;
971 i += 1;
972 }
973 }
974 }
975 }
976
977 return ERROR_OK;
978 }
979
980 int nand_write_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
981 {
982 uint32_t i;
983 int retval;
984 uint8_t status;
985
986 if (!nand->device)
987 return ERROR_NAND_DEVICE_NOT_PROBED;
988
989 nand->controller->command(nand, NAND_CMD_SEQIN);
990
991 if (nand->page_size <= 512)
992 {
993 /* column (always 0, we start at the beginning of a page/OOB area) */
994 nand->controller->address(nand, 0x0);
995
996 /* row */
997 nand->controller->address(nand, page & 0xff);
998 nand->controller->address(nand, (page >> 8) & 0xff);
999
1000 /* 4th cycle only on devices with more than 32 MiB */
1001 if (nand->address_cycles >= 4)
1002 nand->controller->address(nand, (page >> 16) & 0xff);
1003
1004 /* 5th cycle only on devices with more than 8 GiB */
1005 if (nand->address_cycles >= 5)
1006 nand->controller->address(nand, (page >> 24) & 0xff);
1007 }
1008 else
1009 {
1010 /* column (0 when we start at the beginning of a page,
1011 * or 2048 for the beginning of OOB area)
1012 */
1013 nand->controller->address(nand, 0x0);
1014 if (data)
1015 nand->controller->address(nand, 0x0);
1016 else
1017 nand->controller->address(nand, 0x8);
1018
1019 /* row */
1020 nand->controller->address(nand, page & 0xff);
1021 nand->controller->address(nand, (page >> 8) & 0xff);
1022
1023 /* 5th cycle only on devices with more than 128 MiB */
1024 if (nand->address_cycles >= 5)
1025 nand->controller->address(nand, (page >> 16) & 0xff);
1026 }
1027
1028 if (data)
1029 {
1030 if (nand->controller->write_block_data != NULL)
1031 (nand->controller->write_block_data)(nand, data, data_size);
1032 else
1033 {
1034 for (i = 0; i < data_size;)
1035 {
1036 if (nand->device->options & NAND_BUSWIDTH_16)
1037 {
1038 uint16_t data_buf = le_to_h_u16(data);
1039 nand->controller->write_data(nand, data_buf);
1040 data += 2;
1041 i += 2;
1042 }
1043 else
1044 {
1045 nand->controller->write_data(nand, *data);
1046 data += 1;
1047 i += 1;
1048 }
1049 }
1050 }
1051 }
1052
1053 if (oob)
1054 {
1055 if (nand->controller->write_block_data != NULL)
1056 (nand->controller->write_block_data)(nand, oob, oob_size);
1057 else
1058 {
1059 for (i = 0; i < oob_size;)
1060 {
1061 if (nand->device->options & NAND_BUSWIDTH_16)
1062 {
1063 uint16_t oob_buf = le_to_h_u16(data);
1064 nand->controller->write_data(nand, oob_buf);
1065 oob += 2;
1066 i += 2;
1067 }
1068 else
1069 {
1070 nand->controller->write_data(nand, *oob);
1071 oob += 1;
1072 i += 1;
1073 }
1074 }
1075 }
1076 }
1077
1078 nand->controller->command(nand, NAND_CMD_PAGEPROG);
1079
1080 retval = nand->controller->nand_ready ?
1081 nand->controller->nand_ready(nand, 100) :
1082 nand_poll_ready(nand, 100);
1083 if (!retval)
1084 return ERROR_NAND_OPERATION_TIMEOUT;
1085
1086 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
1087 {
1088 LOG_ERROR("couldn't read status");
1089 return ERROR_NAND_OPERATION_FAILED;
1090 }
1091
1092 if (status & NAND_STATUS_FAIL)
1093 {
1094 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1095 return ERROR_NAND_OPERATION_FAILED;
1096 }
1097
1098 return ERROR_OK;
1099 }
1100
1101 COMMAND_HANDLER(handle_nand_list_command)
1102 {
1103 struct nand_device *p;
1104 int i;
1105
1106 if (!nand_devices)
1107 {
1108 command_print(CMD_CTX, "no NAND flash devices configured");
1109 return ERROR_OK;
1110 }
1111
1112 for (p = nand_devices, i = 0; p; p = p->next, i++)
1113 {
1114 if (p->device)
1115 command_print(CMD_CTX, "#%i: %s (%s) "
1116 "pagesize: %i, buswidth: %i,\n\t"
1117 "blocksize: %i, blocks: %i",
1118 i, p->device->name, p->manufacturer->name,
1119 p->page_size, p->bus_width,
1120 p->erase_size, p->num_blocks);
1121 else
1122 command_print(CMD_CTX, "#%i: not probed", i);
1123 }
1124
1125 return ERROR_OK;
1126 }
1127
1128 COMMAND_HANDLER(handle_nand_info_command)
1129 {
1130 int i = 0;
1131 int j = 0;
1132 int first = -1;
1133 int last = -1;
1134
1135 switch (CMD_ARGC) {
1136 default:
1137 return ERROR_COMMAND_SYNTAX_ERROR;
1138 case 1:
1139 first = 0;
1140 last = INT32_MAX;
1141 break;
1142 case 2:
1143 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], i);
1144 first = last = i;
1145 i = 0;
1146 break;
1147 case 3:
1148 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], first);
1149 COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], last);
1150 break;
1151 }
1152
1153 struct nand_device *p;
1154 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1155 if (ERROR_OK != retval)
1156 return retval;
1157
1158 if (NULL == p->device)
1159 {
1160 command_print(CMD_CTX, "#%s: not probed", CMD_ARGV[0]);
1161 return ERROR_OK;
1162 }
1163
1164 if (first >= p->num_blocks)
1165 first = p->num_blocks - 1;
1166
1167 if (last >= p->num_blocks)
1168 last = p->num_blocks - 1;
1169
1170 command_print(CMD_CTX, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1171 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1172
1173 for (j = first; j <= last; j++)
1174 {
1175 char *erase_state, *bad_state;
1176
1177 if (p->blocks[j].is_erased == 0)
1178 erase_state = "not erased";
1179 else if (p->blocks[j].is_erased == 1)
1180 erase_state = "erased";
1181 else
1182 erase_state = "erase state unknown";
1183
1184 if (p->blocks[j].is_bad == 0)
1185 bad_state = "";
1186 else if (p->blocks[j].is_bad == 1)
1187 bad_state = " (marked bad)";
1188 else
1189 bad_state = " (block condition unknown)";
1190
1191 command_print(CMD_CTX,
1192 "\t#%i: 0x%8.8" PRIx32 " (%" PRId32 "kB) %s%s",
1193 j,
1194 p->blocks[j].offset,
1195 p->blocks[j].size / 1024,
1196 erase_state,
1197 bad_state);
1198 }
1199
1200 return ERROR_OK;
1201 }
1202
1203 COMMAND_HANDLER(handle_nand_probe_command)
1204 {
1205 if (CMD_ARGC != 1)
1206 {
1207 return ERROR_COMMAND_SYNTAX_ERROR;
1208 }
1209
1210 struct nand_device *p;
1211 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1212 if (ERROR_OK != retval)
1213 return retval;
1214
1215 if ((retval = nand_probe(p)) == ERROR_OK)
1216 {
1217 command_print(CMD_CTX, "NAND flash device '%s' found", p->device->name);
1218 }
1219 else if (retval == ERROR_NAND_OPERATION_FAILED)
1220 {
1221 command_print(CMD_CTX, "probing failed for NAND flash device");
1222 }
1223 else
1224 {
1225 command_print(CMD_CTX, "unknown error when probing NAND flash device");
1226 }
1227
1228 return ERROR_OK;
1229 }
1230
1231 COMMAND_HANDLER(handle_nand_erase_command)
1232 {
1233 if (CMD_ARGC != 1 && CMD_ARGC != 3)
1234 {
1235 return ERROR_COMMAND_SYNTAX_ERROR;
1236
1237 }
1238
1239 struct nand_device *p;
1240 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1241 if (ERROR_OK != retval)
1242 return retval;
1243
1244 unsigned long offset;
1245 unsigned long length;
1246
1247 /* erase specified part of the chip; or else everything */
1248 if (CMD_ARGC == 3) {
1249 unsigned long size = p->erase_size * p->num_blocks;
1250
1251 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], offset);
1252 if ((offset % p->erase_size) != 0 || offset >= size)
1253 return ERROR_INVALID_ARGUMENTS;
1254
1255 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], length);
1256 if ((length == 0) || (length % p->erase_size) != 0
1257 || (length + offset) > size)
1258 return ERROR_INVALID_ARGUMENTS;
1259
1260 offset /= p->erase_size;
1261 length /= p->erase_size;
1262 } else {
1263 offset = 0;
1264 length = p->num_blocks;
1265 }
1266
1267 retval = nand_erase(p, offset, offset + length - 1);
1268 if (retval == ERROR_OK)
1269 {
1270 command_print(CMD_CTX, "erased blocks %lu to %lu "
1271 "on NAND flash device #%s '%s'",
1272 offset, offset + length,
1273 CMD_ARGV[0], p->device->name);
1274 }
1275 else if (retval == ERROR_NAND_OPERATION_FAILED)
1276 {
1277 command_print(CMD_CTX, "erase failed");
1278 }
1279 else
1280 {
1281 command_print(CMD_CTX, "unknown error when erasing NAND flash device");
1282 }
1283
1284 return ERROR_OK;
1285 }
1286
1287 COMMAND_HANDLER(handle_nand_check_bad_blocks_command)
1288 {
1289 int first = -1;
1290 int last = -1;
1291
1292 if ((CMD_ARGC < 1) || (CMD_ARGC > 3) || (CMD_ARGC == 2))
1293 {
1294 return ERROR_COMMAND_SYNTAX_ERROR;
1295
1296 }
1297
1298 struct nand_device *p;
1299 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1300 if (ERROR_OK != retval)
1301 return retval;
1302
1303 if (CMD_ARGC == 3)
1304 {
1305 unsigned long offset;
1306 unsigned long length;
1307
1308 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], offset);
1309 if (offset % p->erase_size)
1310 return ERROR_INVALID_ARGUMENTS;
1311 offset /= p->erase_size;
1312
1313 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], length);
1314 if (length % p->erase_size)
1315 return ERROR_INVALID_ARGUMENTS;
1316
1317 length -= 1;
1318 length /= p->erase_size;
1319
1320 first = offset;
1321 last = offset + length;
1322 }
1323
1324 retval = nand_build_bbt(p, first, last);
1325 if (retval == ERROR_OK)
1326 {
1327 command_print(CMD_CTX, "checked NAND flash device for bad blocks, "
1328 "use \"nand info\" command to list blocks");
1329 }
1330 else if (retval == ERROR_NAND_OPERATION_FAILED)
1331 {
1332 command_print(CMD_CTX, "error when checking for bad blocks on "
1333 "NAND flash device");
1334 }
1335 else
1336 {
1337 command_print(CMD_CTX, "unknown error when checking for bad "
1338 "blocks on NAND flash device");
1339 }
1340
1341 return ERROR_OK;
1342 }
1343
1344 struct nand_fileio_state {
1345 uint32_t address;
1346 uint32_t size;
1347
1348 uint8_t *page;
1349 uint32_t page_size;
1350
1351 enum oob_formats oob_format;
1352 uint8_t *oob;
1353 uint32_t oob_size;
1354
1355 const int *eccpos;
1356
1357 bool file_opened;
1358 struct fileio fileio;
1359
1360 struct duration bench;
1361 };
1362
1363 static void nand_fileio_init(struct nand_fileio_state *state)
1364 {
1365 memset(state, 0, sizeof(*state));
1366 state->oob_format = NAND_OOB_NONE;
1367 }
1368
1369 static int nand_fileio_start(struct command_context *cmd_ctx,
1370 struct nand_device *nand, const char *filename, int filemode,
1371 struct nand_fileio_state *state)
1372 {
1373 if (state->address % nand->page_size)
1374 {
1375 command_print(cmd_ctx, "only page-aligned addresses are supported");
1376 return ERROR_COMMAND_SYNTAX_ERROR;
1377 }
1378
1379 duration_start(&state->bench);
1380
1381 if (NULL != filename)
1382 {
1383 int retval = fileio_open(&state->fileio, filename, filemode, FILEIO_BINARY);
1384 if (ERROR_OK != retval)
1385 {
1386 const char *msg = (FILEIO_READ == filemode) ? "read" : "write";
1387 command_print(cmd_ctx, "failed to open '%s' for %s access",
1388 filename, msg);
1389 return retval;
1390 }
1391 state->file_opened = true;
1392 }
1393
1394 if (!(state->oob_format & NAND_OOB_ONLY))
1395 {
1396 state->page_size = nand->page_size;
1397 state->page = malloc(nand->page_size);
1398 }
1399
1400 if (state->oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC | NAND_OOB_SW_ECC_KW))
1401 {
1402 if (nand->page_size == 512)
1403 {
1404 state->oob_size = 16;
1405 state->eccpos = nand_oob_16.eccpos;
1406 }
1407 else if (nand->page_size == 2048)
1408 {
1409 state->oob_size = 64;
1410 state->eccpos = nand_oob_64.eccpos;
1411 }
1412 state->oob = malloc(state->oob_size);
1413 }
1414
1415 return ERROR_OK;
1416 }
1417 static int nand_fileio_cleanup(struct nand_fileio_state *state)
1418 {
1419 if (state->file_opened)
1420 fileio_close(&state->fileio);
1421
1422 if (state->oob)
1423 {
1424 free(state->oob);
1425 state->oob = NULL;
1426 }
1427 if (state->page)
1428 {
1429 free(state->page);
1430 state->page = NULL;
1431 }
1432 return ERROR_OK;
1433 }
1434 static int nand_fileio_finish(struct nand_fileio_state *state)
1435 {
1436 nand_fileio_cleanup(state);
1437 return duration_measure(&state->bench);
1438 }
1439
1440 static COMMAND_HELPER(nand_fileio_parse_args, struct nand_fileio_state *state,
1441 struct nand_device **dev, enum fileio_access filemode,
1442 bool need_size, bool sw_ecc)
1443 {
1444 nand_fileio_init(state);
1445
1446 unsigned minargs = need_size ? 4 : 3;
1447 if (CMD_ARGC < minargs)
1448 return ERROR_COMMAND_SYNTAX_ERROR;
1449
1450 struct nand_device *nand;
1451 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
1452 if (ERROR_OK != retval)
1453 return retval;
1454
1455 if (NULL == nand->device)
1456 {
1457 command_print(CMD_CTX, "#%s: not probed", CMD_ARGV[0]);
1458 return ERROR_OK;
1459 }
1460
1461 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], state->address);
1462 if (need_size)
1463 {
1464 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], state->size);
1465 if (state->size % nand->page_size)
1466 {
1467 command_print(CMD_CTX, "only page-aligned sizes are supported");
1468 return ERROR_COMMAND_SYNTAX_ERROR;
1469 }
1470 }
1471
1472 if (CMD_ARGC > minargs)
1473 {
1474 for (unsigned i = minargs; i < CMD_ARGC; i++)
1475 {
1476 if (!strcmp(CMD_ARGV[i], "oob_raw"))
1477 state->oob_format |= NAND_OOB_RAW;
1478 else if (!strcmp(CMD_ARGV[i], "oob_only"))
1479 state->oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1480 else if (sw_ecc && !strcmp(CMD_ARGV[i], "oob_softecc"))
1481 state->oob_format |= NAND_OOB_SW_ECC;
1482 else if (sw_ecc && !strcmp(CMD_ARGV[i], "oob_softecc_kw"))
1483 state->oob_format |= NAND_OOB_SW_ECC_KW;
1484 else
1485 {
1486 command_print(CMD_CTX, "unknown option: %s", CMD_ARGV[i]);
1487 return ERROR_COMMAND_SYNTAX_ERROR;
1488 }
1489 }
1490 }
1491
1492 retval = nand_fileio_start(CMD_CTX, nand, CMD_ARGV[1], filemode, state);
1493 if (ERROR_OK != retval)
1494 return retval;
1495
1496 if (!need_size)
1497 state->size = state->fileio.size;
1498
1499 *dev = nand;
1500
1501 return ERROR_OK;
1502 }
1503
1504 /**
1505 * @returns If no error occurred, returns number of bytes consumed;
1506 * otherwise, returns a negative error code.)
1507 */
1508 static int nand_fileio_read(struct nand_device *nand,
1509 struct nand_fileio_state *s)
1510 {
1511 size_t total_read = 0;
1512 size_t one_read;
1513
1514 if (NULL != s->page)
1515 {
1516 fileio_read(&s->fileio, s->page_size, s->page, &one_read);
1517 if (one_read < s->page_size)
1518 memset(s->page + one_read, 0xff, s->page_size - one_read);
1519 total_read += one_read;
1520 }
1521
1522 if (s->oob_format & NAND_OOB_SW_ECC)
1523 {
1524 uint8_t ecc[3];
1525 memset(s->oob, 0xff, s->oob_size);
1526 for (uint32_t i = 0, j = 0; i < s->page_size; i += 256)
1527 {
1528 nand_calculate_ecc(nand, s->page + i, ecc);
1529 s->oob[s->eccpos[j++]] = ecc[0];
1530 s->oob[s->eccpos[j++]] = ecc[1];
1531 s->oob[s->eccpos[j++]] = ecc[2];
1532 }
1533 }
1534 else if (s->oob_format & NAND_OOB_SW_ECC_KW)
1535 {
1536 /*
1537 * In this case eccpos is not used as
1538 * the ECC data is always stored contigously
1539 * at the end of the OOB area. It consists
1540 * of 10 bytes per 512-byte data block.
1541 */
1542 uint8_t *ecc = s->oob + s->oob_size - s->page_size / 512 * 10;
1543 memset(s->oob, 0xff, s->oob_size);
1544 for (uint32_t i = 0; i < s->page_size; i += 512)
1545 {
1546 nand_calculate_ecc_kw(nand, s->page + i, ecc);
1547 ecc += 10;
1548 }
1549 }
1550 else if (NULL != s->oob)
1551 {
1552 fileio_read(&s->fileio, s->oob_size, s->oob, &one_read);
1553 if (one_read < s->oob_size)
1554 memset(s->oob + one_read, 0xff, s->oob_size - one_read);
1555 total_read += one_read;
1556 }
1557 return total_read;
1558 }
1559
1560 COMMAND_HANDLER(handle_nand_write_command)
1561 {
1562 struct nand_device *nand = NULL;
1563 struct nand_fileio_state s;
1564 int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
1565 &s, &nand, FILEIO_READ, false, true);
1566 if (ERROR_OK != retval)
1567 return retval;
1568
1569 uint32_t total_bytes = s.size;
1570 while (s.size > 0)
1571 {
1572 int bytes_read = nand_fileio_read(nand, &s);
1573 if (bytes_read <= 0)
1574 {
1575 command_print(CMD_CTX, "error while reading file");
1576 return nand_fileio_cleanup(&s);
1577 }
1578 s.size -= bytes_read;
1579
1580 retval = nand_write_page(nand, s.address / nand->page_size,
1581 s.page, s.page_size, s.oob, s.oob_size);
1582 if (ERROR_OK != retval)
1583 {
1584 command_print(CMD_CTX, "failed writing file %s "
1585 "to NAND flash %s at offset 0x%8.8" PRIx32,
1586 CMD_ARGV[1], CMD_ARGV[0], s.address);
1587 return nand_fileio_cleanup(&s);
1588 }
1589 s.address += s.page_size;
1590 }
1591
1592 if (nand_fileio_finish(&s))
1593 {
1594 command_print(CMD_CTX, "wrote file %s to NAND flash %s up to "
1595 "offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
1596 CMD_ARGV[1], CMD_ARGV[0], s.address, duration_elapsed(&s.bench),
1597 duration_kbps(&s.bench, total_bytes));
1598 }
1599 return ERROR_OK;
1600 }
1601
1602 COMMAND_HANDLER(handle_nand_verify_command)
1603 {
1604 struct nand_device *nand = NULL;
1605 struct nand_fileio_state file;
1606 int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
1607 &file, &nand, FILEIO_READ, false, true);
1608 if (ERROR_OK != retval)
1609 return retval;
1610
1611 struct nand_fileio_state dev;
1612 nand_fileio_init(&dev);
1613 dev.address = file.address;
1614 dev.size = file.size;
1615 dev.oob_format = file.oob_format;
1616 retval = nand_fileio_start(CMD_CTX, nand, NULL, FILEIO_NONE, &dev);
1617 if (ERROR_OK != retval)
1618 return retval;
1619
1620 while (file.size > 0)
1621 {
1622 int retval = nand_read_page(nand, dev.address / dev.page_size,
1623 dev.page, dev.page_size, dev.oob, dev.oob_size);
1624 if (ERROR_OK != retval)
1625 {
1626 command_print(CMD_CTX, "reading NAND flash page failed");
1627 nand_fileio_cleanup(&dev);
1628 return nand_fileio_cleanup(&file);
1629 }
1630
1631 int bytes_read = nand_fileio_read(nand, &file);
1632 if (bytes_read <= 0)
1633 {
1634 command_print(CMD_CTX, "error while reading file");
1635 nand_fileio_cleanup(&dev);
1636 return nand_fileio_cleanup(&file);
1637 }
1638
1639 if ((dev.page && memcmp(dev.page, file.page, dev.page_size)) ||
1640 (dev.oob && memcmp(dev.oob, file.oob, dev.oob_size)) )
1641 {
1642 command_print(CMD_CTX, "NAND flash contents differ "
1643 "at 0x%8.8" PRIx32, dev.address);
1644 nand_fileio_cleanup(&dev);
1645 return nand_fileio_cleanup(&file);
1646 }
1647
1648 file.size -= bytes_read;
1649 dev.address += nand->page_size;
1650 }
1651
1652 if (nand_fileio_finish(&file) == ERROR_OK)
1653 {
1654 command_print(CMD_CTX, "verified file %s in NAND flash %s "
1655 "up to offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
1656 CMD_ARGV[1], CMD_ARGV[0], dev.address, duration_elapsed(&file.bench),
1657 duration_kbps(&file.bench, dev.size));
1658 }
1659
1660 return nand_fileio_cleanup(&dev);
1661 }
1662
1663 COMMAND_HANDLER(handle_nand_dump_command)
1664 {
1665 struct nand_device *nand = NULL;
1666 struct nand_fileio_state s;
1667 int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
1668 &s, &nand, FILEIO_WRITE, true, false);
1669 if (ERROR_OK != retval)
1670 return retval;
1671
1672 while (s.size > 0)
1673 {
1674 size_t size_written;
1675 int retval = nand_read_page(nand, s.address / nand->page_size,
1676 s.page, s.page_size, s.oob, s.oob_size);
1677 if (ERROR_OK != retval)
1678 {
1679 command_print(CMD_CTX, "reading NAND flash page failed");
1680 return nand_fileio_cleanup(&s);
1681 }
1682
1683 if (NULL != s.page)
1684 fileio_write(&s.fileio, s.page_size, s.page, &size_written);
1685
1686 if (NULL != s.oob)
1687 fileio_write(&s.fileio, s.oob_size, s.oob, &size_written);
1688
1689 s.size -= nand->page_size;
1690 s.address += nand->page_size;
1691 }
1692
1693 if (nand_fileio_finish(&s) == ERROR_OK)
1694 {
1695 command_print(CMD_CTX, "dumped %zu bytes in %fs (%0.3f kb/s)",
1696 s.fileio.size, duration_elapsed(&s.bench),
1697 duration_kbps(&s.bench, s.fileio.size));
1698 }
1699 return ERROR_OK;
1700 }
1701
1702 COMMAND_HANDLER(handle_nand_raw_access_command)
1703 {
1704 if ((CMD_ARGC < 1) || (CMD_ARGC > 2))
1705 {
1706 return ERROR_COMMAND_SYNTAX_ERROR;
1707 }
1708
1709 struct nand_device *p;
1710 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1711 if (ERROR_OK != retval)
1712 return retval;
1713
1714 if (NULL == p->device)
1715 {
1716 command_print(CMD_CTX, "#%s: not probed", CMD_ARGV[0]);
1717 return ERROR_OK;
1718 }
1719
1720 if (CMD_ARGC == 2)
1721 COMMAND_PARSE_ENABLE(CMD_ARGV[1], p->use_raw);
1722
1723 const char *msg = p->use_raw ? "enabled" : "disabled";
1724 command_print(CMD_CTX, "raw access is %s", msg);
1725
1726 return ERROR_OK;
1727 }
1728
1729 static const struct command_registration nand_exec_command_handlers[] = {
1730 {
1731 .name = "list",
1732 .handler = &handle_nand_list_command,
1733 .mode = COMMAND_EXEC,
1734 .help = "list configured NAND flash devices",
1735 },
1736 {
1737 .name = "info",
1738 .handler = &handle_nand_info_command,
1739 .mode = COMMAND_EXEC,
1740 .usage = "<bank>",
1741 .help = "print info about a NAND flash device",
1742 },
1743 {
1744 .name = "probe",
1745 .handler = &handle_nand_probe_command,
1746 .mode = COMMAND_EXEC,
1747 .usage = "<bank>",
1748 .help = "identify NAND flash device <num>",
1749
1750 },
1751 {
1752 .name = "check_bad_blocks",
1753 .handler = &handle_nand_check_bad_blocks_command,
1754 .mode = COMMAND_EXEC,
1755 .usage = "<bank> [<offset> <length>]",
1756 .help = "check NAND flash device <num> for bad blocks",
1757 },
1758 {
1759 .name = "erase",
1760 .handler = &handle_nand_erase_command,
1761 .mode = COMMAND_EXEC,
1762 .usage = "<bank> [<offset> <length>]",
1763 .help = "erase blocks on NAND flash device",
1764 },
1765 {
1766 .name = "dump",
1767 .handler = &handle_nand_dump_command,
1768 .mode = COMMAND_EXEC,
1769 .usage = "<bank> <filename> <offset> <length> "
1770 "[oob_raw | oob_only]",
1771 .help = "dump from NAND flash device",
1772 },
1773 {
1774 .name = "verify",
1775 .handler = &handle_nand_verify_command,
1776 .mode = COMMAND_EXEC,
1777 .usage = "<bank> <filename> <offset> "
1778 "[oob_raw | oob_only | oob_softecc | oob_softecc_kw]",
1779 .help = "verify NAND flash device",
1780 },
1781 {
1782 .name = "write",
1783 .handler = &handle_nand_write_command,
1784 .mode = COMMAND_EXEC,
1785 .usage = "<bank> <filename> <offset> "
1786 "[oob_raw | oob_only | oob_softecc | oob_softecc_kw]",
1787 .help = "write to NAND flash device",
1788 },
1789 {
1790 .name = "raw_access",
1791 .handler = &handle_nand_raw_access_command,
1792 .mode = COMMAND_EXEC,
1793 .usage = "<num> ['enable'|'disable']",
1794 .help = "raw access to NAND flash device",
1795 },
1796 COMMAND_REGISTRATION_DONE
1797 };
1798
1799 int nand_init(struct command_context *cmd_ctx)
1800 {
1801 if (!nand_devices)
1802 return ERROR_OK;
1803 struct command *parent = command_find_in_context(cmd_ctx, "nand");
1804 return register_commands(cmd_ctx, parent, nand_exec_command_handlers);
1805 }
1806
1807 COMMAND_HANDLER(handle_nand_init_command)
1808 {
1809 if (CMD_ARGC != 0)
1810 return ERROR_COMMAND_SYNTAX_ERROR;
1811
1812 static bool nand_initialized = false;
1813 if (nand_initialized)
1814 {
1815 LOG_INFO("'nand init' has already been called");
1816 return ERROR_OK;
1817 }
1818 nand_initialized = true;
1819
1820 LOG_DEBUG("Initializing NAND devices...");
1821 return nand_init(CMD_CTX);
1822 }
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