e0dfa22ff9afb0d86bf1b031711f019a95f259b8
[openocd.git] / src / flash / nand.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * partially based on *
6 * drivers/mtd/nand_ids.c *
7 * *
8 * Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de) *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "replacements.h"
30 #include "log.h"
31
32 #include <stdlib.h>
33 #include <string.h>
34
35 #include <errno.h>
36
37 #include "nand.h"
38 #include "flash.h"
39 #include "time_support.h"
40 #include "fileio.h"
41
42 int nand_register_commands(struct command_context_s *cmd_ctx);
43 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44 int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46 int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47 int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48 int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51
52 int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53
54 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
55 int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
56 int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size);
57
58 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
59 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
60
61 /* NAND flash controller
62 */
63 extern nand_flash_controller_t lpc3180_nand_controller;
64 /* extern nand_flash_controller_t s3c2410_nand_controller; */
65 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
66
67 nand_flash_controller_t *nand_flash_controllers[] =
68 {
69 &lpc3180_nand_controller,
70 /* &s3c2410_nand_controller, */
71 /* &boundary_scan_nand_controller, */
72 NULL
73 };
74
75 /* configured NAND devices and NAND Flash command handler */
76 nand_device_t *nand_devices = NULL;
77 static command_t *nand_cmd;
78
79 /* Chip ID list
80 *
81 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
82 * options
83 *
84 * Pagesize; 0, 256, 512
85 * 0 get this information from the extended chip ID
86 * 256 256 Byte page size
87 * 512 512 Byte page size
88 */
89 nand_info_t nand_flash_ids[] =
90 {
91 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
92 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
93 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
94 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
95 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
96 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
97 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
98 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
99 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
100 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
101
102 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
103 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
104 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
105 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
106
107 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
108 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
109 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
110 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
111
112 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
113 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
114 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
115 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
116
117 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
118 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
119 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
120 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
121
122 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
123 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
124 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
125 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
126 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
127 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
128 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
129
130 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
131
132 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
133 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
134 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
135 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
136
137 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
138 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
139 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
140 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
141
142 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
143 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
144 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
145 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
146
147 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
148 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
149 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
150 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
151
152 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
153 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
154 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
155 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
156
157 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
158 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
159 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
160 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
161
162 {NULL, 0,}
163 };
164
165 /* Manufacturer ID list
166 */
167 nand_manufacturer_t nand_manuf_ids[] =
168 {
169 {0x0, "unknown"},
170 {NAND_MFR_TOSHIBA, "Toshiba"},
171 {NAND_MFR_SAMSUNG, "Samsung"},
172 {NAND_MFR_FUJITSU, "Fujitsu"},
173 {NAND_MFR_NATIONAL, "National"},
174 {NAND_MFR_RENESAS, "Renesas"},
175 {NAND_MFR_STMICRO, "ST Micro"},
176 {NAND_MFR_HYNIX, "Hynix"},
177 {0x0, NULL},
178 };
179
180 /* nand device <nand_controller> [controller options]
181 */
182 int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
183 {
184 int i;
185 int retval;
186
187 if (argc < 1)
188 {
189 WARNING("incomplete flash device nand configuration");
190 return ERROR_FLASH_BANK_INVALID;
191 }
192
193 for (i = 0; nand_flash_controllers[i]; i++)
194 {
195 nand_device_t *p, *c;
196
197 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
198 {
199 /* register flash specific commands */
200 if (nand_flash_controllers[i]->register_commands(cmd_ctx) != ERROR_OK)
201 {
202 ERROR("couldn't register '%s' commands", args[0]);
203 exit(-1);
204 }
205
206 c = malloc(sizeof(nand_device_t));
207
208 c->controller = nand_flash_controllers[i];
209 c->controller_priv = NULL;
210 c->manufacturer = NULL;
211 c->device = NULL;
212 c->bus_width = 0;
213 c->address_cycles = 0;
214 c->page_size = 0;
215 c->use_raw = 0;
216 c->next = NULL;
217
218 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
219 {
220 ERROR("'%s' driver rejected nand flash", c->controller->name);
221 free(c);
222 return ERROR_OK;
223 }
224
225 /* put NAND device in linked list */
226 if (nand_devices)
227 {
228 /* find last flash device */
229 for (p = nand_devices; p && p->next; p = p->next);
230 if (p)
231 p->next = c;
232 }
233 else
234 {
235 nand_devices = c;
236 }
237
238 return ERROR_OK;
239 }
240 }
241
242 /* no valid NAND controller was found (i.e. the configuration option,
243 * didn't match one of the compiled-in controllers)
244 */
245 ERROR("No valid NAND flash controller found (%s)", args[0]);
246 ERROR("compiled-in NAND flash controllers:");
247 for (i = 0; nand_flash_controllers[i]; i++)
248 {
249 ERROR("%i: %s", i, nand_flash_controllers[i]->name);
250 }
251
252 return ERROR_OK;
253 }
254
255 int nand_register_commands(struct command_context_s *cmd_ctx)
256 {
257 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, NULL);
258
259 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
260
261 return ERROR_OK;
262 }
263
264 int nand_init(struct command_context_s *cmd_ctx)
265 {
266 if (nand_devices)
267 {
268 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
269 "list configured NAND flash devices");
270 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
271 "print info about NAND flash device <num>");
272 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
273 "identify NAND flash device <num>");
274 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
275 "check NAND flash device <num> for bad blocks [<first> <last>]");
276 register_command(cmd_ctx, nand_cmd, "erase", handle_nand_erase_command, COMMAND_EXEC,
277 "erase blocks on NAND flash device <num> <first> <last>");
278 register_command(cmd_ctx, nand_cmd, "copy", handle_nand_copy_command, COMMAND_EXEC,
279 "copy from NAND flash device <num> <offset> <length> <ram-address>");
280 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
281 "dump from NAND flash device <num> <filename> <offset> <size> [options]");
282 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
283 "write to NAND flash device <num> <filename> <offset> [options]");
284 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
285 "raw access to NAND flash device <num> ['enable'|'disable']");
286 }
287
288 return ERROR_OK;
289 }
290
291 nand_device_t *get_nand_device_by_num(int num)
292 {
293 nand_device_t *p;
294 int i = 0;
295
296 for (p = nand_devices; p; p = p->next)
297 {
298 if (i++ == num)
299 {
300 return p;
301 }
302 }
303
304 return NULL;
305 }
306
307 int nand_build_bbt(struct nand_device_s *device, int first, int last)
308 {
309 u32 page = 0x0;
310 int i;
311 u8 *oob;
312
313 oob = malloc(6);
314
315 if ((first < 0) || (first >= device->num_blocks))
316 first = 0;
317
318 if ((last >= device->num_blocks) || (last == -1))
319 last = device->num_blocks - 1;
320
321 for (i = first; i < last; i++)
322 {
323 nand_read_page(device, page, NULL, 0, oob, 6);
324
325 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
326 || (((device->page_size == 512) && (oob[5] != 0xff)) ||
327 ((device->page_size == 2048) && (oob[0] != 0xff))))
328 {
329 WARNING("invalid block: %i", i);
330 device->blocks[i].is_bad = 1;
331 }
332 else
333 {
334 device->blocks[i].is_bad = 0;
335 }
336
337 page += (device->erase_size / device->page_size);
338 }
339
340 return ERROR_OK;
341 }
342
343 int nand_read_status(struct nand_device_s *device, u8 *status)
344 {
345 if (!device->device)
346 return ERROR_NAND_DEVICE_NOT_PROBED;
347
348 /* Send read status command */
349 device->controller->command(device, NAND_CMD_STATUS);
350
351 usleep(1000);
352
353 /* read status */
354 if (device->device->options & NAND_BUSWIDTH_16)
355 {
356 u16 data;
357 device->controller->read_data(device, &data);
358 *status = data & 0xff;
359 }
360 else
361 {
362 device->controller->read_data(device, status);
363 }
364
365 return ERROR_OK;
366 }
367
368 int nand_probe(struct nand_device_s *device)
369 {
370 u8 manufacturer_id, device_id;
371 int retval;
372 int i;
373
374 /* clear device data */
375 device->device = NULL;
376 device->manufacturer = NULL;
377
378 /* clear device parameters */
379 device->bus_width = 0;
380 device->address_cycles = 0;
381 device->page_size = 0;
382 device->erase_size = 0;
383
384 /* initialize controller (device parameters are zero, use controller default) */
385 if ((retval = device->controller->init(device) != ERROR_OK))
386 {
387 switch (retval)
388 {
389 case ERROR_NAND_OPERATION_FAILED:
390 DEBUG("controller initialization failed");
391 return ERROR_NAND_OPERATION_FAILED;
392 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
393 ERROR("BUG: controller reported that it doesn't support default parameters");
394 return ERROR_NAND_OPERATION_FAILED;
395 default:
396 ERROR("BUG: unknown controller initialization failure");
397 return ERROR_NAND_OPERATION_FAILED;
398 }
399 }
400
401 device->controller->command(device, NAND_CMD_RESET);
402 device->controller->reset(device);
403
404 device->controller->command(device, NAND_CMD_READID);
405 device->controller->address(device, 0x0);
406
407 if (device->bus_width == 8)
408 {
409 device->controller->read_data(device, &manufacturer_id);
410 device->controller->read_data(device, &device_id);
411 }
412 else
413 {
414 u16 data_buf;
415 device->controller->read_data(device, &data_buf);
416 manufacturer_id = data_buf & 0xff;
417 device->controller->read_data(device, &data_buf);
418 device_id = data_buf & 0xff;
419 }
420
421 for (i = 0; nand_flash_ids[i].name; i++)
422 {
423 if (nand_flash_ids[i].id == device_id)
424 {
425 device->device = &nand_flash_ids[i];
426 break;
427 }
428 }
429
430 for (i = 0; nand_manuf_ids[i].name; i++)
431 {
432 if (nand_manuf_ids[i].id == manufacturer_id)
433 {
434 device->manufacturer = &nand_manuf_ids[i];
435 break;
436 }
437 }
438
439 if (!device->manufacturer)
440 {
441 device->manufacturer = &nand_manuf_ids[0];
442 device->manufacturer->id = manufacturer_id;
443 }
444
445 if (!device->device)
446 {
447 ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
448 manufacturer_id, device_id);
449 return ERROR_NAND_OPERATION_FAILED;
450 }
451
452 DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
453
454 /* initialize device parameters */
455
456 /* bus width */
457 if (device->device->options & NAND_BUSWIDTH_16)
458 device->bus_width = 16;
459 else
460 device->bus_width = 8;
461
462 /* page size */
463 if (device->device->page_size == 0)
464 {
465 /* TODO: support reading extended chip id to determine page size */
466 return ERROR_NAND_OPERATION_FAILED;
467 }
468 else if (device->device->page_size == 256)
469 {
470 ERROR("NAND flashes with 256 byte pagesize are not supported");
471 return ERROR_NAND_OPERATION_FAILED;
472 }
473 else
474 {
475 device->page_size = device->device->page_size;
476 }
477
478 /* number of address cycles */
479 if (device->page_size <= 512)
480 {
481 /* small page devices */
482 if (device->device->chip_size <= 32)
483 device->address_cycles = 3;
484 else if (device->device->chip_size <= 8*1024)
485 device->address_cycles = 4;
486 else
487 {
488 ERROR("BUG: small page NAND device with more than 8 GiB encountered");
489 device->address_cycles = 5;
490 }
491 }
492 else
493 {
494 /* large page devices */
495 if (device->device->chip_size <= 128)
496 device->address_cycles = 4;
497 else if (device->device->chip_size <= 32*1024)
498 device->address_cycles = 5;
499 else
500 {
501 ERROR("BUG: small page NAND device with more than 32 GiB encountered");
502 device->address_cycles = 6;
503 }
504 }
505
506 /* erase size */
507 if (device->device->erase_size == 0)
508 {
509 /* TODO: support reading extended chip id to determine erase size */
510 }
511 else
512 {
513 device->erase_size = device->device->erase_size;
514 }
515
516 /* initialize controller, but leave parameters at the controllers default */
517 if ((retval = device->controller->init(device) != ERROR_OK))
518 {
519 switch (retval)
520 {
521 case ERROR_NAND_OPERATION_FAILED:
522 DEBUG("controller initialization failed");
523 return ERROR_NAND_OPERATION_FAILED;
524 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
525 ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
526 device->bus_width, device->address_cycles, device->page_size);
527 return ERROR_NAND_OPERATION_FAILED;
528 default:
529 ERROR("BUG: unknown controller initialization failure");
530 return ERROR_NAND_OPERATION_FAILED;
531 }
532 }
533
534 device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
535 device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
536
537 for (i = 0; i < device->num_blocks; i++)
538 {
539 device->blocks[i].size = device->erase_size;
540 device->blocks[i].offset = i * device->erase_size;
541 device->blocks[i].is_erased = -1;
542 device->blocks[i].is_bad = -1;
543 }
544
545 return ERROR_OK;
546 }
547
548 int nand_erase(struct nand_device_s *device, int first_block, int last_block)
549 {
550 int i;
551 u32 page;
552 u8 status;
553 int retval;
554
555 if (!device->device)
556 return ERROR_NAND_DEVICE_NOT_PROBED;
557
558 if ((first_block < 0) || (last_block > device->num_blocks))
559 return ERROR_INVALID_ARGUMENTS;
560
561 /* make sure we know if a block is bad before erasing it */
562 for (i = first_block; i <= last_block; i++)
563 {
564 if (device->blocks[i].is_bad == -1)
565 {
566 nand_build_bbt(device, i, last_block);
567 break;
568 }
569 }
570
571 for (i = first_block; i <= last_block; i++)
572 {
573 /* Send erase setup command */
574 device->controller->command(device, NAND_CMD_ERASE1);
575
576 page = i * (device->erase_size / device->page_size);
577
578 /* Send page address */
579 if (device->page_size <= 512)
580 {
581 /* row */
582 device->controller->address(device, page & 0xff);
583 device->controller->address(device, (page >> 8) & 0xff);
584
585 /* 3rd cycle only on devices with more than 32 MiB */
586 if (device->address_cycles >= 4)
587 device->controller->address(device, (page >> 16) & 0xff);
588
589 /* 4th cycle only on devices with more than 8 GiB */
590 if (device->address_cycles >= 5)
591 device->controller->address(device, (page >> 24) & 0xff);
592 }
593 else
594 {
595 /* row */
596 device->controller->address(device, page & 0xff);
597 device->controller->address(device, (page >> 8) & 0xff);
598
599 /* 3rd cycle only on devices with more than 128 MiB */
600 if (device->address_cycles >= 5)
601 device->controller->address(device, (page >> 16) & 0xff);
602 }
603
604 /* Send erase confirm command */
605 device->controller->command(device, NAND_CMD_ERASE2);
606
607 if (!device->controller->nand_ready(device, 1000))
608 {
609 ERROR("timeout waiting for NAND flash block erase to complete");
610 return ERROR_NAND_OPERATION_TIMEOUT;
611 }
612
613 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
614 {
615 ERROR("couldn't read status");
616 return ERROR_NAND_OPERATION_FAILED;
617 }
618
619 if (status & 0x1)
620 {
621 ERROR("erase operation didn't pass, status: 0x%2.2x", status);
622 return ERROR_NAND_OPERATION_FAILED;
623 }
624 }
625
626 return ERROR_OK;
627 }
628
629 int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
630 {
631 u8 *page;
632
633 if (!device->device)
634 return ERROR_NAND_DEVICE_NOT_PROBED;
635
636 if (address % device->page_size)
637 {
638 ERROR("reads need to be page aligned");
639 return ERROR_NAND_OPERATION_FAILED;
640 }
641
642 page = malloc(device->page_size);
643
644 while (data_size > 0 )
645 {
646 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
647 u32 page_address;
648
649
650 page_address = address / device->page_size;
651
652 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
653
654 memcpy(data, page, thisrun_size);
655
656 address += thisrun_size;
657 data += thisrun_size;
658 data_size -= thisrun_size;
659 }
660
661 free(page);
662
663 return ERROR_OK;
664 }
665
666 int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
667 {
668 u8 *page;
669
670 if (!device->device)
671 return ERROR_NAND_DEVICE_NOT_PROBED;
672
673 if (address % device->page_size)
674 {
675 ERROR("writes need to be page aligned");
676 return ERROR_NAND_OPERATION_FAILED;
677 }
678
679 page = malloc(device->page_size);
680
681 while (data_size > 0 )
682 {
683 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
684 u32 page_address;
685
686 memset(page, 0xff, device->page_size);
687 memcpy(page, data, thisrun_size);
688
689 page_address = address / device->page_size;
690
691 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
692
693 address += thisrun_size;
694 data += thisrun_size;
695 data_size -= thisrun_size;
696 }
697
698 free(page);
699
700 return ERROR_OK;
701 }
702
703 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
704 {
705 if (!device->device)
706 return ERROR_NAND_DEVICE_NOT_PROBED;
707
708 if (device->use_raw)
709 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
710 else
711 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
712 }
713
714 int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
715 {
716 if (!device->device)
717 return ERROR_NAND_DEVICE_NOT_PROBED;
718
719 if (device->use_raw)
720 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
721 else
722 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
723 }
724
725 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
726 {
727 int i;
728
729 if (!device->device)
730 return ERROR_NAND_DEVICE_NOT_PROBED;
731
732 if (device->page_size <= 512)
733 {
734 /* small page device */
735 if (data)
736 device->controller->command(device, NAND_CMD_READ0);
737 else
738 device->controller->command(device, NAND_CMD_READOOB);
739
740 /* column (always 0, we start at the beginning of a page/OOB area) */
741 device->controller->address(device, 0x0);
742
743 /* row */
744 device->controller->address(device, page & 0xff);
745 device->controller->address(device, (page >> 8) & 0xff);
746
747 /* 4th cycle only on devices with more than 32 MiB */
748 if (device->address_cycles >= 4)
749 device->controller->address(device, (page >> 16) & 0xff);
750
751 /* 5th cycle only on devices with more than 8 GiB */
752 if (device->address_cycles >= 5)
753 device->controller->address(device, (page >> 24) & 0xff);
754 }
755 else
756 {
757 /* large page device */
758 device->controller->command(device, NAND_CMD_READ0);
759
760 /* column (0 when we start at the beginning of a page,
761 * or 2048 for the beginning of OOB area)
762 */
763 device->controller->address(device, 0x0);
764 device->controller->address(device, 0x8);
765
766 /* row */
767 device->controller->address(device, page & 0xff);
768 device->controller->address(device, (page >> 8) & 0xff);
769
770 /* 5th cycle only on devices with more than 128 MiB */
771 if (device->address_cycles >= 5)
772 device->controller->address(device, (page >> 16) & 0xff);
773
774 /* large page devices need a start command */
775 device->controller->command(device, NAND_CMD_READSTART);
776 }
777
778 if (!device->controller->nand_ready(device, 100))
779 return ERROR_NAND_OPERATION_TIMEOUT;
780
781 if (data)
782 {
783 for (i = 0; i < data_size;)
784 {
785 if (device->device->options & NAND_BUSWIDTH_16)
786 {
787 device->controller->read_data(device, data);
788 data += 2;
789 i += 2;
790 }
791 else
792 {
793 device->controller->read_data(device, data);
794 data += 1;
795 i += 1;
796 }
797 }
798 }
799
800 if (oob)
801 {
802 for (i = 0; i < oob_size;)
803 {
804 if (device->device->options & NAND_BUSWIDTH_16)
805 {
806 device->controller->read_data(device, oob);
807 oob += 2;
808 i += 2;
809 }
810 else
811 {
812 device->controller->read_data(device, oob);
813 oob += 1;
814 i += 1;
815 }
816 }
817 }
818
819 return ERROR_OK;
820 }
821
822 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
823 {
824 int i;
825 int retval;
826 u8 status;
827
828 if (!device->device)
829 return ERROR_NAND_DEVICE_NOT_PROBED;
830
831 device->controller->command(device, NAND_CMD_SEQIN);
832
833 if (device->page_size <= 512)
834 {
835 /* column (always 0, we start at the beginning of a page/OOB area) */
836 device->controller->address(device, 0x0);
837
838 /* row */
839 device->controller->address(device, page & 0xff);
840 device->controller->address(device, (page >> 8) & 0xff);
841
842 /* 4th cycle only on devices with more than 32 MiB */
843 if (device->address_cycles >= 4)
844 device->controller->address(device, (page >> 16) & 0xff);
845
846 /* 5th cycle only on devices with more than 8 GiB */
847 if (device->address_cycles >= 5)
848 device->controller->address(device, (page >> 24) & 0xff);
849 }
850 else
851 {
852 /* column (0 when we start at the beginning of a page,
853 * or 2048 for the beginning of OOB area)
854 */
855 device->controller->address(device, 0x0);
856 device->controller->address(device, 0x8);
857
858 /* row */
859 device->controller->address(device, page & 0xff);
860 device->controller->address(device, (page >> 8) & 0xff);
861
862 /* 5th cycle only on devices with more than 128 MiB */
863 if (device->address_cycles >= 5)
864 device->controller->address(device, (page >> 16) & 0xff);
865 }
866
867 if (data)
868 {
869 for (i = 0; i < data_size;)
870 {
871 if (device->device->options & NAND_BUSWIDTH_16)
872 {
873 u16 data_buf = le_to_h_u16(data);
874 device->controller->write_data(device, data_buf);
875 data += 2;
876 i += 2;
877 }
878 else
879 {
880 device->controller->write_data(device, *data);
881 data += 1;
882 i += 1;
883 }
884 }
885 }
886
887 if (oob)
888 {
889 for (i = 0; i < oob_size;)
890 {
891 if (device->device->options & NAND_BUSWIDTH_16)
892 {
893 u16 oob_buf = le_to_h_u16(data);
894 device->controller->write_data(device, oob_buf);
895 oob += 2;
896 i += 2;
897 }
898 else
899 {
900 device->controller->write_data(device, *oob);
901 oob += 1;
902 i += 1;
903 }
904 }
905 }
906
907 device->controller->command(device, NAND_CMD_PAGEPROG);
908
909 if (!device->controller->nand_ready(device, 100))
910 return ERROR_NAND_OPERATION_TIMEOUT;
911
912 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
913 {
914 ERROR("couldn't read status");
915 return ERROR_NAND_OPERATION_FAILED;
916 }
917
918 if (status & NAND_STATUS_FAIL)
919 {
920 ERROR("write operation didn't pass, status: 0x%2.2x", status);
921 return ERROR_NAND_OPERATION_FAILED;
922 }
923
924 return ERROR_OK;
925 }
926
927 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
928 {
929 nand_device_t *p;
930 int i = 0;
931
932 if (!nand_devices)
933 {
934 command_print(cmd_ctx, "no NAND flash devices configured");
935 return ERROR_OK;
936 }
937
938 for (p = nand_devices; p; p = p->next)
939 {
940 if (p->device)
941 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
942 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
943 else
944 command_print(cmd_ctx, "#%i: not probed");
945 }
946
947 return ERROR_OK;
948 }
949
950 int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
951 {
952 nand_device_t *p;
953 int i = 0;
954 int j = 0;
955 int first = -1;
956 int last = -1;
957
958 if ((argc < 1) || (argc > 3))
959 {
960 command_print(cmd_ctx, "usage: nand info <num> [<first> <last>]");
961 return ERROR_OK;
962 }
963
964 if (argc == 2)
965 {
966 first = last = strtoul(args[1], NULL, 0);
967 }
968 else if (argc == 3)
969 {
970 first = strtoul(args[1], NULL, 0);
971 last = strtoul(args[2], NULL, 0);
972 }
973
974 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
975 if (p)
976 {
977 if (p->device)
978 {
979 if (first >= p->num_blocks)
980 first = p->num_blocks - 1;
981
982 if (last >= p->num_blocks)
983 last = p->num_blocks - 1;
984
985 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
986 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
987
988 for (j = first; j <= last; j++)
989 {
990 char *erase_state, *bad_state;
991
992 if (p->blocks[j].is_erased == 0)
993 erase_state = "not erased";
994 else if (p->blocks[j].is_erased == 1)
995 erase_state = "erased";
996 else
997 erase_state = "erase state unknown";
998
999 if (p->blocks[j].is_bad == 0)
1000 bad_state = "";
1001 else if (p->blocks[j].is_bad == 1)
1002 bad_state = " (marked bad)";
1003 else
1004 bad_state = " (block condition unknown)";
1005
1006 command_print(cmd_ctx, "\t#%i: 0x%8.8x (0x%xkB) %s%s",
1007 j, p->blocks[j].offset, p->blocks[j].size / 1024,
1008 erase_state, bad_state);
1009 }
1010 }
1011 else
1012 {
1013 command_print(cmd_ctx, "#%i: not probed");
1014 }
1015 }
1016
1017 return ERROR_OK;
1018 }
1019
1020 int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1021 {
1022 nand_device_t *p;
1023 int retval;
1024
1025 if (argc != 1)
1026 {
1027 command_print(cmd_ctx, "usage: nand probe <num>");
1028 return ERROR_OK;
1029 }
1030
1031 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1032 if (p)
1033 {
1034 if ((retval = nand_probe(p)) == ERROR_OK)
1035 {
1036 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1037 }
1038 else if (retval == ERROR_NAND_OPERATION_FAILED)
1039 {
1040 command_print(cmd_ctx, "probing failed for NAND flash device");
1041 }
1042 else
1043 {
1044 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1045 }
1046 }
1047 else
1048 {
1049 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1050 }
1051
1052 return ERROR_OK;
1053 }
1054
1055 int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1056 {
1057 nand_device_t *p;
1058 int retval;
1059
1060 if (argc != 3)
1061 {
1062 command_print(cmd_ctx, "usage: nand erase <num> <first> <last>");
1063 return ERROR_OK;
1064 }
1065
1066 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1067 if (p)
1068 {
1069 int first = strtoul(args[1], NULL, 0);
1070 int last = strtoul(args[2], NULL, 0);
1071
1072 if ((retval = nand_erase(p, first, last)) == ERROR_OK)
1073 {
1074 command_print(cmd_ctx, "successfully erased blocks %i to %i on NAND flash device '%s'", first, last, p->device->name);
1075 }
1076 else if (retval == ERROR_NAND_OPERATION_FAILED)
1077 {
1078 command_print(cmd_ctx, "erase failed");
1079 }
1080 else
1081 {
1082 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1083 }
1084 }
1085 else
1086 {
1087 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1088 }
1089
1090 return ERROR_OK;
1091 }
1092
1093 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1094 {
1095 nand_device_t *p;
1096 int retval;
1097 int first = -1;
1098 int last = -1;
1099
1100 if ((argc < 1) || (argc > 3) || (argc == 2))
1101 {
1102 command_print(cmd_ctx, "usage: nand check_bad_blocks <num> [<first> <last>]");
1103 return ERROR_OK;
1104 }
1105
1106 if (argc == 3)
1107 {
1108 first = strtoul(args[1], NULL, 0);
1109 last = strtoul(args[2], NULL, 0);
1110 }
1111
1112 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1113 if (p)
1114 {
1115 if ((retval = nand_build_bbt(p, first, last)) == ERROR_OK)
1116 {
1117 command_print(cmd_ctx, "checked NAND flash device for bad blocks, use \"nand info\" command to list blocks", p->device->name);
1118 }
1119 else if (retval == ERROR_NAND_OPERATION_FAILED)
1120 {
1121 command_print(cmd_ctx, "error when checking for bad blocks on NAND flash device");
1122 }
1123 else
1124 {
1125 command_print(cmd_ctx, "unknown error when checking for bad blocks on NAND flash device");
1126 }
1127 }
1128 else
1129 {
1130 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1131 }
1132
1133 return ERROR_OK;
1134 }
1135
1136 int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1137 {
1138 nand_device_t *p;
1139
1140 if (argc != 4)
1141 {
1142 command_print(cmd_ctx, "usage: nand copy <num> <offset> <length> <ram-address>");
1143 return ERROR_OK;
1144 }
1145
1146 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1147 if (p)
1148 {
1149
1150 }
1151 else
1152 {
1153 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1154 }
1155
1156 return ERROR_OK;
1157 }
1158
1159 int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1160 {
1161 u32 offset;
1162 u32 binary_size;
1163 u32 buf_cnt;
1164 enum oob_formats oob_format = NAND_OOB_NONE;
1165
1166 fileio_t file;
1167 fileio_image_t image_info;
1168 int sec_type_identified = 0;
1169 enum fileio_sec_type sec_type;
1170
1171 duration_t duration;
1172 char *duration_text;
1173
1174 nand_device_t *p;
1175
1176 if (argc < 3)
1177 {
1178 command_print(cmd_ctx, "usage: nand write <num> <file> <offset> [options]");
1179 return ERROR_OK;
1180 }
1181
1182 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1183 if (p)
1184 {
1185 u8 *page = NULL;
1186 u32 page_size = 0;
1187 u8 *oob = NULL;
1188 u32 oob_size = 0;
1189
1190 duration_start_measure(&duration);
1191 strtoul(args[2], NULL, 0);
1192
1193 if (argc > 3)
1194 {
1195 int i;
1196 for (i = 3; i < argc; i++)
1197 {
1198 if (!strcmp(args[i], "oob_raw"))
1199 oob_format |= NAND_OOB_RAW;
1200 else if (!strcmp(args[i], "oob_only"))
1201 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1202 else
1203 {
1204 if (fileio_identify_image_type(&sec_type, args[i]) == ERROR_OK)
1205 {
1206 sec_type_identified = 1;
1207 }
1208 else
1209 {
1210 command_print(cmd_ctx, "unknown option: %s", args[i]);
1211 }
1212 }
1213 }
1214 }
1215
1216 /* if no image type option was encountered, set the default */
1217 if (!sec_type_identified)
1218 {
1219
1220 fileio_identify_image_type(&sec_type, NULL);
1221 sec_type_identified = 1;
1222 }
1223
1224 image_info.base_address = strtoul(args[2], NULL, 0);
1225 image_info.has_start_address = 0;
1226
1227 if (fileio_open(&file, args[1], FILEIO_READ,
1228 FILEIO_IMAGE, &image_info, sec_type) != ERROR_OK)
1229 {
1230 command_print(cmd_ctx, "flash write error: %s", file.error_str);
1231 return ERROR_OK;
1232 }
1233
1234 /* the offset might have been overwritten by the image base address */
1235 offset = image_info.base_address;
1236
1237 buf_cnt = binary_size = file.size;
1238
1239 if (!(oob_format & NAND_OOB_ONLY))
1240 {
1241 page_size = p->page_size;
1242 page = malloc(p->page_size);
1243 }
1244
1245 if (oob_format & NAND_OOB_RAW)
1246 {
1247 if (p->page_size == 512)
1248 oob_size = 16;
1249 else if (p->page_size == 2048)
1250 oob_size = 64;
1251 oob = malloc(oob_size);
1252 }
1253
1254 if (offset % p->page_size)
1255 {
1256 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1257 return ERROR_OK;
1258 }
1259
1260 while (buf_cnt > 0)
1261 {
1262 u32 size_read;
1263
1264 if (page)
1265 {
1266 fileio_read(&file, page_size, page, &size_read);
1267 buf_cnt -= size_read;
1268 if (size_read < page_size)
1269 {
1270 memset(page + size_read, 0xff, page_size - size_read);
1271 }
1272 }
1273
1274 if (oob)
1275 {
1276 fileio_read(&file, oob_size, oob, &size_read);
1277 buf_cnt -= size_read;
1278 if (size_read < oob_size)
1279 {
1280 memset(oob + size_read, 0xff, oob_size - size_read);
1281 }
1282 }
1283
1284 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1285 {
1286 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8x",
1287 file.url, args[0], offset);
1288 return ERROR_OK;
1289 }
1290 offset += page_size;
1291 }
1292
1293 duration_stop_measure(&duration, &duration_text);
1294 command_print(cmd_ctx, "wrote file %s to NAND flash %s at offset 0x%8.8x in %s",
1295 file.url, args[0], image_info.base_address, duration_text);
1296 free(duration_text);
1297 }
1298 else
1299 {
1300 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1301 }
1302
1303 return ERROR_OK;
1304 }
1305
1306 int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1307 {
1308 nand_device_t *p;
1309
1310 if (argc < 4)
1311 {
1312 command_print(cmd_ctx, "usage: nand dump <num> <filename> <address> <size> [options]");
1313 return ERROR_OK;
1314 }
1315
1316 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1317 if (p)
1318 {
1319 if (p->device)
1320 {
1321 fileio_t file;
1322 fileio_image_t image_info;
1323 duration_t duration;
1324 char *duration_text;
1325 int retval;
1326
1327 u8 *page = NULL;
1328 u32 page_size = 0;
1329 u8 *oob = NULL;
1330 u32 oob_size = 0;
1331 u32 address = strtoul(args[2], NULL, 0);
1332 u32 size = strtoul(args[3], NULL, 0);
1333 u32 bytes_done = 0;
1334 enum oob_formats oob_format = NAND_OOB_NONE;
1335
1336 if (argc > 4)
1337 {
1338 int i;
1339 for (i = 4; i < argc; i++)
1340 {
1341 if (!strcmp(args[i], "oob_raw"))
1342 oob_format |= NAND_OOB_RAW;
1343 else if (!strcmp(args[i], "oob_only"))
1344 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1345 else
1346 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1347 }
1348 }
1349
1350 if ((address % p->page_size) || (size % p->page_size))
1351 {
1352 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1353 return ERROR_OK;
1354 }
1355
1356 if (!(oob_format & NAND_OOB_ONLY))
1357 {
1358 page_size = p->page_size;
1359 page = malloc(p->page_size);
1360 }
1361
1362 if (oob_format & NAND_OOB_RAW)
1363 {
1364 if (p->page_size == 512)
1365 oob_size = 16;
1366 else if (p->page_size == 2048)
1367 oob_size = 64;
1368 oob = malloc(oob_size);
1369 }
1370
1371 image_info.base_address = address;
1372 image_info.has_start_address = 0;
1373
1374 if (fileio_open(&file, args[1], FILEIO_WRITE,
1375 FILEIO_IMAGE, &image_info, FILEIO_PLAIN) != ERROR_OK)
1376 {
1377 command_print(cmd_ctx, "dump_image error: %s", file.error_str);
1378 return ERROR_OK;
1379 }
1380
1381 duration_start_measure(&duration);
1382
1383 while (size > 0)
1384 {
1385 u32 size_written;
1386 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1387 {
1388 command_print(cmd_ctx, "reading NAND flash page failed");
1389 return ERROR_OK;
1390 }
1391
1392 if (page)
1393 {
1394 fileio_write(&file, page_size, page, &size_written);
1395 bytes_done += page_size;
1396 }
1397
1398 if (oob)
1399 {
1400 fileio_write(&file, oob_size, oob, &size_written);
1401 bytes_done += oob_size;
1402 }
1403
1404 size -= p->page_size;
1405 address += p->page_size;
1406 }
1407
1408 if (page)
1409 free(page);
1410
1411 if (oob)
1412 free(oob);
1413
1414 fileio_close(&file);
1415
1416 duration_stop_measure(&duration, &duration_text);
1417 command_print(cmd_ctx, "dumped %lli byte in %s", file.size, duration_text);
1418 free(duration_text);
1419 }
1420 else
1421 {
1422 command_print(cmd_ctx, "#%i: not probed");
1423 }
1424 }
1425 else
1426 {
1427 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1428 }
1429
1430 return ERROR_OK;
1431 }
1432
1433 int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1434 {
1435 nand_device_t *p;
1436
1437 if ((argc < 1) || (argc > 2))
1438 {
1439 command_print(cmd_ctx, "usage: nand raw_access <num> ['enable'|'disable']");
1440 return ERROR_OK;
1441 }
1442
1443 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1444 if (p)
1445 {
1446 if (p->device)
1447 {
1448 if (argc == 2)
1449 {
1450 if (strcmp("enable", args[1]) == 0)
1451 {
1452 p->use_raw = 1;
1453 }
1454 else if (strcmp("disable", args[1]) == 0)
1455 {
1456 p->use_raw = 0;
1457 }
1458 else
1459 {
1460 command_print(cmd_ctx, "usage: nand raw_access ['enable'|disable']");
1461 }
1462 }
1463
1464 command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
1465 }
1466 else
1467 {
1468 command_print(cmd_ctx, "#%i: not probed");
1469 }
1470 }
1471 else
1472 {
1473 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1474 }
1475
1476 return ERROR_OK;
1477 }
1478