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- "flash write_binary" is now "flash write_bank" to clarify the focus of the
[openocd.git] / src / flash / nand.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * partially based on *
6 * drivers/mtd/nand_ids.c *
7 * *
8 * Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de) *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "replacements.h"
30 #include "log.h"
31
32 #include <stdlib.h>
33 #include <string.h>
34 #include <inttypes.h>
35
36 #include <errno.h>
37
38 #include "nand.h"
39 #include "flash.h"
40 #include "time_support.h"
41 #include "fileio.h"
42 #include "image.h"
43
44 int nand_register_commands(struct command_context_s *cmd_ctx);
45 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46 int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48 int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53
54 int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55
56 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
57 int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
58 int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size);
59
60 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
61 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
62
63 /* NAND flash controller
64 */
65 extern nand_flash_controller_t lpc3180_nand_controller;
66 extern nand_flash_controller_t s3c2410_nand_controller;
67 extern nand_flash_controller_t s3c2412_nand_controller;
68 extern nand_flash_controller_t s3c2440_nand_controller;
69 extern nand_flash_controller_t s3c2443_nand_controller;
70
71 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
72
73 nand_flash_controller_t *nand_flash_controllers[] =
74 {
75 &lpc3180_nand_controller,
76 &s3c2410_nand_controller,
77 &s3c2412_nand_controller,
78 &s3c2440_nand_controller,
79 &s3c2443_nand_controller,
80 /* &boundary_scan_nand_controller, */
81 NULL
82 };
83
84 /* configured NAND devices and NAND Flash command handler */
85 nand_device_t *nand_devices = NULL;
86 static command_t *nand_cmd;
87
88 /* Chip ID list
89 *
90 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
91 * options
92 *
93 * Pagesize; 0, 256, 512
94 * 0 get this information from the extended chip ID
95 * 256 256 Byte page size
96 * 512 512 Byte page size
97 */
98 nand_info_t nand_flash_ids[] =
99 {
100 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
101 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
102 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
103 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
104 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
105 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
106 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
107 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
108 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
109 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
110
111 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
112 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
113 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
114 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
115
116 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
117 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
118 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
119 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
120
121 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
122 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
123 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
124 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
125
126 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
127 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
128 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
129 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
130
131 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
132 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
133 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
134 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
135 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
136 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
137 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
138
139 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
140
141 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
142 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
143 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
144 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
145
146 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
147 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
148 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
149 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
150
151 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
152 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
153 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
154 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
155
156 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
157 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
158 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
159 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
160
161 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
162 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
163 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
164 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
165
166 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
167 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
168 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
169 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
170
171 {NULL, 0,}
172 };
173
174 /* Manufacturer ID list
175 */
176 nand_manufacturer_t nand_manuf_ids[] =
177 {
178 {0x0, "unknown"},
179 {NAND_MFR_TOSHIBA, "Toshiba"},
180 {NAND_MFR_SAMSUNG, "Samsung"},
181 {NAND_MFR_FUJITSU, "Fujitsu"},
182 {NAND_MFR_NATIONAL, "National"},
183 {NAND_MFR_RENESAS, "Renesas"},
184 {NAND_MFR_STMICRO, "ST Micro"},
185 {NAND_MFR_HYNIX, "Hynix"},
186 {0x0, NULL},
187 };
188
189 /* nand device <nand_controller> [controller options]
190 */
191 int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
192 {
193 int i;
194 int retval;
195
196 if (argc < 1)
197 {
198 WARNING("incomplete flash device nand configuration");
199 return ERROR_FLASH_BANK_INVALID;
200 }
201
202 for (i = 0; nand_flash_controllers[i]; i++)
203 {
204 nand_device_t *p, *c;
205
206 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
207 {
208 /* register flash specific commands */
209 if (nand_flash_controllers[i]->register_commands(cmd_ctx) != ERROR_OK)
210 {
211 ERROR("couldn't register '%s' commands", args[0]);
212 exit(-1);
213 }
214
215 c = malloc(sizeof(nand_device_t));
216
217 c->controller = nand_flash_controllers[i];
218 c->controller_priv = NULL;
219 c->manufacturer = NULL;
220 c->device = NULL;
221 c->bus_width = 0;
222 c->address_cycles = 0;
223 c->page_size = 0;
224 c->use_raw = 0;
225 c->next = NULL;
226
227 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
228 {
229 ERROR("'%s' driver rejected nand flash", c->controller->name);
230 free(c);
231 return ERROR_OK;
232 }
233
234 /* put NAND device in linked list */
235 if (nand_devices)
236 {
237 /* find last flash device */
238 for (p = nand_devices; p && p->next; p = p->next);
239 if (p)
240 p->next = c;
241 }
242 else
243 {
244 nand_devices = c;
245 }
246
247 return ERROR_OK;
248 }
249 }
250
251 /* no valid NAND controller was found (i.e. the configuration option,
252 * didn't match one of the compiled-in controllers)
253 */
254 ERROR("No valid NAND flash controller found (%s)", args[0]);
255 ERROR("compiled-in NAND flash controllers:");
256 for (i = 0; nand_flash_controllers[i]; i++)
257 {
258 ERROR("%i: %s", i, nand_flash_controllers[i]->name);
259 }
260
261 return ERROR_OK;
262 }
263
264 int nand_register_commands(struct command_context_s *cmd_ctx)
265 {
266 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
267
268 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
269
270 return ERROR_OK;
271 }
272
273 int nand_init(struct command_context_s *cmd_ctx)
274 {
275 if (nand_devices)
276 {
277 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
278 "list configured NAND flash devices");
279 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
280 "print info about NAND flash device <num>");
281 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
282 "identify NAND flash device <num>");
283 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
284 "check NAND flash device <num> for bad blocks [<first> <last>]");
285 register_command(cmd_ctx, nand_cmd, "erase", handle_nand_erase_command, COMMAND_EXEC,
286 "erase blocks on NAND flash device <num> <first> <last>");
287 register_command(cmd_ctx, nand_cmd, "copy", handle_nand_copy_command, COMMAND_EXEC,
288 "copy from NAND flash device <num> <offset> <length> <ram-address>");
289 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
290 "dump from NAND flash device <num> <filename> <offset> <size> [options]");
291 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
292 "write to NAND flash device <num> <filename> <offset> [options]");
293 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
294 "raw access to NAND flash device <num> ['enable'|'disable']");
295 }
296
297 return ERROR_OK;
298 }
299
300 nand_device_t *get_nand_device_by_num(int num)
301 {
302 nand_device_t *p;
303 int i = 0;
304
305 for (p = nand_devices; p; p = p->next)
306 {
307 if (i++ == num)
308 {
309 return p;
310 }
311 }
312
313 return NULL;
314 }
315
316 int nand_build_bbt(struct nand_device_s *device, int first, int last)
317 {
318 u32 page = 0x0;
319 int i;
320 u8 *oob;
321
322 oob = malloc(6);
323
324 if ((first < 0) || (first >= device->num_blocks))
325 first = 0;
326
327 if ((last >= device->num_blocks) || (last == -1))
328 last = device->num_blocks - 1;
329
330 for (i = first; i < last; i++)
331 {
332 nand_read_page(device, page, NULL, 0, oob, 6);
333
334 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
335 || (((device->page_size == 512) && (oob[5] != 0xff)) ||
336 ((device->page_size == 2048) && (oob[0] != 0xff))))
337 {
338 WARNING("invalid block: %i", i);
339 device->blocks[i].is_bad = 1;
340 }
341 else
342 {
343 device->blocks[i].is_bad = 0;
344 }
345
346 page += (device->erase_size / device->page_size);
347 }
348
349 return ERROR_OK;
350 }
351
352 int nand_read_status(struct nand_device_s *device, u8 *status)
353 {
354 if (!device->device)
355 return ERROR_NAND_DEVICE_NOT_PROBED;
356
357 /* Send read status command */
358 device->controller->command(device, NAND_CMD_STATUS);
359
360 usleep(1000);
361
362 /* read status */
363 if (device->device->options & NAND_BUSWIDTH_16)
364 {
365 u16 data;
366 device->controller->read_data(device, &data);
367 *status = data & 0xff;
368 }
369 else
370 {
371 device->controller->read_data(device, status);
372 }
373
374 return ERROR_OK;
375 }
376
377 int nand_probe(struct nand_device_s *device)
378 {
379 u8 manufacturer_id, device_id;
380 u8 id_buff[5];
381 int retval;
382 int i;
383
384 /* clear device data */
385 device->device = NULL;
386 device->manufacturer = NULL;
387
388 /* clear device parameters */
389 device->bus_width = 0;
390 device->address_cycles = 0;
391 device->page_size = 0;
392 device->erase_size = 0;
393
394 /* initialize controller (device parameters are zero, use controller default) */
395 if ((retval = device->controller->init(device) != ERROR_OK))
396 {
397 switch (retval)
398 {
399 case ERROR_NAND_OPERATION_FAILED:
400 DEBUG("controller initialization failed");
401 return ERROR_NAND_OPERATION_FAILED;
402 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
403 ERROR("BUG: controller reported that it doesn't support default parameters");
404 return ERROR_NAND_OPERATION_FAILED;
405 default:
406 ERROR("BUG: unknown controller initialization failure");
407 return ERROR_NAND_OPERATION_FAILED;
408 }
409 }
410
411 device->controller->command(device, NAND_CMD_RESET);
412 device->controller->reset(device);
413
414 device->controller->command(device, NAND_CMD_READID);
415 device->controller->address(device, 0x0);
416
417 if (device->bus_width == 8)
418 {
419 device->controller->read_data(device, &manufacturer_id);
420 device->controller->read_data(device, &device_id);
421 }
422 else
423 {
424 u16 data_buf;
425 device->controller->read_data(device, &data_buf);
426 manufacturer_id = data_buf & 0xff;
427 device->controller->read_data(device, &data_buf);
428 device_id = data_buf & 0xff;
429 }
430
431 for (i = 0; nand_flash_ids[i].name; i++)
432 {
433 if (nand_flash_ids[i].id == device_id)
434 {
435 device->device = &nand_flash_ids[i];
436 break;
437 }
438 }
439
440 for (i = 0; nand_manuf_ids[i].name; i++)
441 {
442 if (nand_manuf_ids[i].id == manufacturer_id)
443 {
444 device->manufacturer = &nand_manuf_ids[i];
445 break;
446 }
447 }
448
449 if (!device->manufacturer)
450 {
451 device->manufacturer = &nand_manuf_ids[0];
452 device->manufacturer->id = manufacturer_id;
453 }
454
455 if (!device->device)
456 {
457 ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
458 manufacturer_id, device_id);
459 return ERROR_NAND_OPERATION_FAILED;
460 }
461
462 DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
463
464 /* initialize device parameters */
465
466 /* bus width */
467 if (device->device->options & NAND_BUSWIDTH_16)
468 device->bus_width = 16;
469 else
470 device->bus_width = 8;
471
472 /* Do we need extended device probe information? */
473 if (device->device->page_size == 0 ||
474 device->device->erase_size == 0)
475 {
476 if (device->bus_width == 8)
477 {
478 device->controller->read_data(device, id_buff+3);
479 device->controller->read_data(device, id_buff+4);
480 device->controller->read_data(device, id_buff+5);
481 }
482 else
483 {
484 u16 data_buf;
485
486 device->controller->read_data(device, &data_buf);
487 id_buff[3] = data_buf;
488
489 device->controller->read_data(device, &data_buf);
490 id_buff[4] = data_buf;
491
492 device->controller->read_data(device, &data_buf);
493 id_buff[5] = data_buf >> 8;
494 }
495 }
496
497 /* page size */
498 if (device->device->page_size == 0)
499 {
500 device->page_size = 1 << (10 + (id_buff[4] & 3));
501 }
502 else if (device->device->page_size == 256)
503 {
504 ERROR("NAND flashes with 256 byte pagesize are not supported");
505 return ERROR_NAND_OPERATION_FAILED;
506 }
507 else
508 {
509 device->page_size = device->device->page_size;
510 }
511
512 /* number of address cycles */
513 if (device->page_size <= 512)
514 {
515 /* small page devices */
516 if (device->device->chip_size <= 32)
517 device->address_cycles = 3;
518 else if (device->device->chip_size <= 8*1024)
519 device->address_cycles = 4;
520 else
521 {
522 ERROR("BUG: small page NAND device with more than 8 GiB encountered");
523 device->address_cycles = 5;
524 }
525 }
526 else
527 {
528 /* large page devices */
529 if (device->device->chip_size <= 128)
530 device->address_cycles = 4;
531 else if (device->device->chip_size <= 32*1024)
532 device->address_cycles = 5;
533 else
534 {
535 ERROR("BUG: small page NAND device with more than 32 GiB encountered");
536 device->address_cycles = 6;
537 }
538 }
539
540 /* erase size */
541 if (device->device->erase_size == 0)
542 {
543 switch ((id_buff[4] >> 4) & 3) {
544 case 0:
545 device->erase_size = 64 << 10;
546 break;
547 case 1:
548 device->erase_size = 128 << 10;
549 break;
550 case 2:
551 device->erase_size = 256 << 10;
552 break;
553 case 3:
554 device->erase_size =512 << 10;
555 break;
556 }
557 }
558 else
559 {
560 device->erase_size = device->device->erase_size;
561 }
562
563 /* initialize controller, but leave parameters at the controllers default */
564 if ((retval = device->controller->init(device) != ERROR_OK))
565 {
566 switch (retval)
567 {
568 case ERROR_NAND_OPERATION_FAILED:
569 DEBUG("controller initialization failed");
570 return ERROR_NAND_OPERATION_FAILED;
571 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
572 ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
573 device->bus_width, device->address_cycles, device->page_size);
574 return ERROR_NAND_OPERATION_FAILED;
575 default:
576 ERROR("BUG: unknown controller initialization failure");
577 return ERROR_NAND_OPERATION_FAILED;
578 }
579 }
580
581 device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
582 device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
583
584 for (i = 0; i < device->num_blocks; i++)
585 {
586 device->blocks[i].size = device->erase_size;
587 device->blocks[i].offset = i * device->erase_size;
588 device->blocks[i].is_erased = -1;
589 device->blocks[i].is_bad = -1;
590 }
591
592 return ERROR_OK;
593 }
594
595 int nand_erase(struct nand_device_s *device, int first_block, int last_block)
596 {
597 int i;
598 u32 page;
599 u8 status;
600 int retval;
601
602 if (!device->device)
603 return ERROR_NAND_DEVICE_NOT_PROBED;
604
605 if ((first_block < 0) || (last_block > device->num_blocks))
606 return ERROR_INVALID_ARGUMENTS;
607
608 /* make sure we know if a block is bad before erasing it */
609 for (i = first_block; i <= last_block; i++)
610 {
611 if (device->blocks[i].is_bad == -1)
612 {
613 nand_build_bbt(device, i, last_block);
614 break;
615 }
616 }
617
618 for (i = first_block; i <= last_block; i++)
619 {
620 /* Send erase setup command */
621 device->controller->command(device, NAND_CMD_ERASE1);
622
623 page = i * (device->erase_size / device->page_size);
624
625 /* Send page address */
626 if (device->page_size <= 512)
627 {
628 /* row */
629 device->controller->address(device, page & 0xff);
630 device->controller->address(device, (page >> 8) & 0xff);
631
632 /* 3rd cycle only on devices with more than 32 MiB */
633 if (device->address_cycles >= 4)
634 device->controller->address(device, (page >> 16) & 0xff);
635
636 /* 4th cycle only on devices with more than 8 GiB */
637 if (device->address_cycles >= 5)
638 device->controller->address(device, (page >> 24) & 0xff);
639 }
640 else
641 {
642 /* row */
643 device->controller->address(device, page & 0xff);
644 device->controller->address(device, (page >> 8) & 0xff);
645
646 /* 3rd cycle only on devices with more than 128 MiB */
647 if (device->address_cycles >= 5)
648 device->controller->address(device, (page >> 16) & 0xff);
649 }
650
651 /* Send erase confirm command */
652 device->controller->command(device, NAND_CMD_ERASE2);
653
654 if (!device->controller->nand_ready(device, 1000))
655 {
656 ERROR("timeout waiting for NAND flash block erase to complete");
657 return ERROR_NAND_OPERATION_TIMEOUT;
658 }
659
660 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
661 {
662 ERROR("couldn't read status");
663 return ERROR_NAND_OPERATION_FAILED;
664 }
665
666 if (status & 0x1)
667 {
668 ERROR("erase operation didn't pass, status: 0x%2.2x", status);
669 return ERROR_NAND_OPERATION_FAILED;
670 }
671 }
672
673 return ERROR_OK;
674 }
675
676 int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
677 {
678 u8 *page;
679
680 if (!device->device)
681 return ERROR_NAND_DEVICE_NOT_PROBED;
682
683 if (address % device->page_size)
684 {
685 ERROR("reads need to be page aligned");
686 return ERROR_NAND_OPERATION_FAILED;
687 }
688
689 page = malloc(device->page_size);
690
691 while (data_size > 0 )
692 {
693 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
694 u32 page_address;
695
696
697 page_address = address / device->page_size;
698
699 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
700
701 memcpy(data, page, thisrun_size);
702
703 address += thisrun_size;
704 data += thisrun_size;
705 data_size -= thisrun_size;
706 }
707
708 free(page);
709
710 return ERROR_OK;
711 }
712
713 int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
714 {
715 u8 *page;
716
717 if (!device->device)
718 return ERROR_NAND_DEVICE_NOT_PROBED;
719
720 if (address % device->page_size)
721 {
722 ERROR("writes need to be page aligned");
723 return ERROR_NAND_OPERATION_FAILED;
724 }
725
726 page = malloc(device->page_size);
727
728 while (data_size > 0 )
729 {
730 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
731 u32 page_address;
732
733 memset(page, 0xff, device->page_size);
734 memcpy(page, data, thisrun_size);
735
736 page_address = address / device->page_size;
737
738 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
739
740 address += thisrun_size;
741 data += thisrun_size;
742 data_size -= thisrun_size;
743 }
744
745 free(page);
746
747 return ERROR_OK;
748 }
749
750 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
751 {
752 if (!device->device)
753 return ERROR_NAND_DEVICE_NOT_PROBED;
754
755 if (device->use_raw || device->controller->write_page == NULL)
756 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
757 else
758 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
759 }
760
761 int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
762 {
763 if (!device->device)
764 return ERROR_NAND_DEVICE_NOT_PROBED;
765
766 if (device->use_raw || device->controller->read_page == NULL)
767 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
768 else
769 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
770 }
771
772 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
773 {
774 int i;
775
776 if (!device->device)
777 return ERROR_NAND_DEVICE_NOT_PROBED;
778
779 if (device->page_size <= 512)
780 {
781 /* small page device */
782 if (data)
783 device->controller->command(device, NAND_CMD_READ0);
784 else
785 device->controller->command(device, NAND_CMD_READOOB);
786
787 /* column (always 0, we start at the beginning of a page/OOB area) */
788 device->controller->address(device, 0x0);
789
790 /* row */
791 device->controller->address(device, page & 0xff);
792 device->controller->address(device, (page >> 8) & 0xff);
793
794 /* 4th cycle only on devices with more than 32 MiB */
795 if (device->address_cycles >= 4)
796 device->controller->address(device, (page >> 16) & 0xff);
797
798 /* 5th cycle only on devices with more than 8 GiB */
799 if (device->address_cycles >= 5)
800 device->controller->address(device, (page >> 24) & 0xff);
801 }
802 else
803 {
804 /* large page device */
805 device->controller->command(device, NAND_CMD_READ0);
806
807 /* column (0 when we start at the beginning of a page,
808 * or 2048 for the beginning of OOB area)
809 */
810 device->controller->address(device, 0x0);
811 device->controller->address(device, 0x8);
812
813 /* row */
814 device->controller->address(device, page & 0xff);
815 device->controller->address(device, (page >> 8) & 0xff);
816
817 /* 5th cycle only on devices with more than 128 MiB */
818 if (device->address_cycles >= 5)
819 device->controller->address(device, (page >> 16) & 0xff);
820
821 /* large page devices need a start command */
822 device->controller->command(device, NAND_CMD_READSTART);
823 }
824
825 if (!device->controller->nand_ready(device, 100))
826 return ERROR_NAND_OPERATION_TIMEOUT;
827
828 if (data)
829 {
830 if (device->controller->read_block_data != NULL)
831 (device->controller->read_block_data)(device, data, data_size);
832 else
833 {
834 for (i = 0; i < data_size;)
835 {
836 if (device->device->options & NAND_BUSWIDTH_16)
837 {
838 device->controller->read_data(device, data);
839 data += 2;
840 i += 2;
841 }
842 else
843 {
844 device->controller->read_data(device, data);
845 data += 1;
846 i += 1;
847 }
848 }
849 }
850 }
851
852 if (oob)
853 {
854 if (device->controller->read_block_data != NULL)
855 (device->controller->read_block_data)(device, oob, oob_size);
856 else
857 {
858 for (i = 0; i < oob_size;)
859 {
860 if (device->device->options & NAND_BUSWIDTH_16)
861 {
862 device->controller->read_data(device, oob);
863 oob += 2;
864 i += 2;
865 }
866 else
867 {
868 device->controller->read_data(device, oob);
869 oob += 1;
870 i += 1;
871 }
872 }
873 }
874 }
875
876 return ERROR_OK;
877 }
878
879 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
880 {
881 int i;
882 int retval;
883 u8 status;
884
885 if (!device->device)
886 return ERROR_NAND_DEVICE_NOT_PROBED;
887
888 device->controller->command(device, NAND_CMD_SEQIN);
889
890 if (device->page_size <= 512)
891 {
892 /* column (always 0, we start at the beginning of a page/OOB area) */
893 device->controller->address(device, 0x0);
894
895 /* row */
896 device->controller->address(device, page & 0xff);
897 device->controller->address(device, (page >> 8) & 0xff);
898
899 /* 4th cycle only on devices with more than 32 MiB */
900 if (device->address_cycles >= 4)
901 device->controller->address(device, (page >> 16) & 0xff);
902
903 /* 5th cycle only on devices with more than 8 GiB */
904 if (device->address_cycles >= 5)
905 device->controller->address(device, (page >> 24) & 0xff);
906 }
907 else
908 {
909 /* column (0 when we start at the beginning of a page,
910 * or 2048 for the beginning of OOB area)
911 */
912 device->controller->address(device, 0x0);
913 device->controller->address(device, 0x8);
914
915 /* row */
916 device->controller->address(device, page & 0xff);
917 device->controller->address(device, (page >> 8) & 0xff);
918
919 /* 5th cycle only on devices with more than 128 MiB */
920 if (device->address_cycles >= 5)
921 device->controller->address(device, (page >> 16) & 0xff);
922 }
923
924 if (data)
925 {
926 if (device->controller->write_block_data != NULL)
927 (device->controller->write_block_data)(device, data, data_size);
928 else
929 {
930 for (i = 0; i < data_size;)
931 {
932 if (device->device->options & NAND_BUSWIDTH_16)
933 {
934 u16 data_buf = le_to_h_u16(data);
935 device->controller->write_data(device, data_buf);
936 data += 2;
937 i += 2;
938 }
939 else
940 {
941 device->controller->write_data(device, *data);
942 data += 1;
943 i += 1;
944 }
945 }
946 }
947 }
948
949 if (oob)
950 {
951 if (device->controller->write_block_data != NULL)
952 (device->controller->write_block_data)(device, oob, oob_size);
953 else
954 {
955 for (i = 0; i < oob_size;)
956 {
957 if (device->device->options & NAND_BUSWIDTH_16)
958 {
959 u16 oob_buf = le_to_h_u16(data);
960 device->controller->write_data(device, oob_buf);
961 oob += 2;
962 i += 2;
963 }
964 else
965 {
966 device->controller->write_data(device, *oob);
967 oob += 1;
968 i += 1;
969 }
970 }
971 }
972 }
973
974 device->controller->command(device, NAND_CMD_PAGEPROG);
975
976 if (!device->controller->nand_ready(device, 100))
977 return ERROR_NAND_OPERATION_TIMEOUT;
978
979 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
980 {
981 ERROR("couldn't read status");
982 return ERROR_NAND_OPERATION_FAILED;
983 }
984
985 if (status & NAND_STATUS_FAIL)
986 {
987 ERROR("write operation didn't pass, status: 0x%2.2x", status);
988 return ERROR_NAND_OPERATION_FAILED;
989 }
990
991 return ERROR_OK;
992 }
993
994 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
995 {
996 nand_device_t *p;
997 int i = 0;
998
999 if (!nand_devices)
1000 {
1001 command_print(cmd_ctx, "no NAND flash devices configured");
1002 return ERROR_OK;
1003 }
1004
1005 for (p = nand_devices; p; p = p->next)
1006 {
1007 if (p->device)
1008 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1009 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1010 else
1011 command_print(cmd_ctx, "#%i: not probed");
1012 }
1013
1014 return ERROR_OK;
1015 }
1016
1017 int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1018 {
1019 nand_device_t *p;
1020 int i = 0;
1021 int j = 0;
1022 int first = -1;
1023 int last = -1;
1024
1025 if ((argc < 1) || (argc > 3))
1026 {
1027 return ERROR_COMMAND_SYNTAX_ERROR;
1028
1029 }
1030
1031 if (argc == 2)
1032 {
1033 first = last = strtoul(args[1], NULL, 0);
1034 }
1035 else if (argc == 3)
1036 {
1037 first = strtoul(args[1], NULL, 0);
1038 last = strtoul(args[2], NULL, 0);
1039 }
1040
1041 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1042 if (p)
1043 {
1044 if (p->device)
1045 {
1046 if (first >= p->num_blocks)
1047 first = p->num_blocks - 1;
1048
1049 if (last >= p->num_blocks)
1050 last = p->num_blocks - 1;
1051
1052 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1053 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1054
1055 for (j = first; j <= last; j++)
1056 {
1057 char *erase_state, *bad_state;
1058
1059 if (p->blocks[j].is_erased == 0)
1060 erase_state = "not erased";
1061 else if (p->blocks[j].is_erased == 1)
1062 erase_state = "erased";
1063 else
1064 erase_state = "erase state unknown";
1065
1066 if (p->blocks[j].is_bad == 0)
1067 bad_state = "";
1068 else if (p->blocks[j].is_bad == 1)
1069 bad_state = " (marked bad)";
1070 else
1071 bad_state = " (block condition unknown)";
1072
1073 command_print(cmd_ctx, "\t#%i: 0x%8.8x (0x%xkB) %s%s",
1074 j, p->blocks[j].offset, p->blocks[j].size / 1024,
1075 erase_state, bad_state);
1076 }
1077 }
1078 else
1079 {
1080 command_print(cmd_ctx, "#%i: not probed");
1081 }
1082 }
1083
1084 return ERROR_OK;
1085 }
1086
1087 int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1088 {
1089 nand_device_t *p;
1090 int retval;
1091
1092 if (argc != 1)
1093 {
1094 return ERROR_COMMAND_SYNTAX_ERROR;
1095 }
1096
1097 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1098 if (p)
1099 {
1100 if ((retval = nand_probe(p)) == ERROR_OK)
1101 {
1102 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1103 }
1104 else if (retval == ERROR_NAND_OPERATION_FAILED)
1105 {
1106 command_print(cmd_ctx, "probing failed for NAND flash device");
1107 }
1108 else
1109 {
1110 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1111 }
1112 }
1113 else
1114 {
1115 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1116 }
1117
1118 return ERROR_OK;
1119 }
1120
1121 int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1122 {
1123 nand_device_t *p;
1124 int retval;
1125
1126 if (argc != 3)
1127 {
1128 return ERROR_COMMAND_SYNTAX_ERROR;
1129
1130 }
1131
1132 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1133 if (p)
1134 {
1135 int first = strtoul(args[1], NULL, 0);
1136 int last = strtoul(args[2], NULL, 0);
1137
1138 if ((retval = nand_erase(p, first, last)) == ERROR_OK)
1139 {
1140 command_print(cmd_ctx, "successfully erased blocks %i to %i on NAND flash device '%s'", first, last, p->device->name);
1141 }
1142 else if (retval == ERROR_NAND_OPERATION_FAILED)
1143 {
1144 command_print(cmd_ctx, "erase failed");
1145 }
1146 else
1147 {
1148 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1149 }
1150 }
1151 else
1152 {
1153 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1154 }
1155
1156 return ERROR_OK;
1157 }
1158
1159 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1160 {
1161 nand_device_t *p;
1162 int retval;
1163 int first = -1;
1164 int last = -1;
1165
1166 if ((argc < 1) || (argc > 3) || (argc == 2))
1167 {
1168 return ERROR_COMMAND_SYNTAX_ERROR;
1169
1170 }
1171
1172 if (argc == 3)
1173 {
1174 first = strtoul(args[1], NULL, 0);
1175 last = strtoul(args[2], NULL, 0);
1176 }
1177
1178 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1179 if (p)
1180 {
1181 if ((retval = nand_build_bbt(p, first, last)) == ERROR_OK)
1182 {
1183 command_print(cmd_ctx, "checked NAND flash device for bad blocks, use \"nand info\" command to list blocks", p->device->name);
1184 }
1185 else if (retval == ERROR_NAND_OPERATION_FAILED)
1186 {
1187 command_print(cmd_ctx, "error when checking for bad blocks on NAND flash device");
1188 }
1189 else
1190 {
1191 command_print(cmd_ctx, "unknown error when checking for bad blocks on NAND flash device");
1192 }
1193 }
1194 else
1195 {
1196 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1197 }
1198
1199 return ERROR_OK;
1200 }
1201
1202 int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1203 {
1204 nand_device_t *p;
1205
1206 if (argc != 4)
1207 {
1208 return ERROR_COMMAND_SYNTAX_ERROR;
1209
1210 }
1211
1212 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1213 if (p)
1214 {
1215
1216 }
1217 else
1218 {
1219 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1220 }
1221
1222 return ERROR_OK;
1223 }
1224
1225 int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1226 {
1227 u32 offset;
1228 u32 binary_size;
1229 u32 buf_cnt;
1230 enum oob_formats oob_format = NAND_OOB_NONE;
1231
1232 fileio_t fileio;
1233
1234 duration_t duration;
1235 char *duration_text;
1236
1237 nand_device_t *p;
1238
1239 if (argc < 3)
1240 {
1241 return ERROR_COMMAND_SYNTAX_ERROR;
1242
1243 }
1244
1245 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1246 if (p)
1247 {
1248 u8 *page = NULL;
1249 u32 page_size = 0;
1250 u8 *oob = NULL;
1251 u32 oob_size = 0;
1252
1253 duration_start_measure(&duration);
1254 offset = strtoul(args[2], NULL, 0);
1255
1256 if (argc > 3)
1257 {
1258 int i;
1259 for (i = 3; i < argc; i++)
1260 {
1261 if (!strcmp(args[i], "oob_raw"))
1262 oob_format |= NAND_OOB_RAW;
1263 else if (!strcmp(args[i], "oob_only"))
1264 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1265 else
1266 {
1267 command_print(cmd_ctx, "unknown option: %s", args[i]);
1268 }
1269 }
1270 }
1271
1272 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1273 {
1274 command_print(cmd_ctx, "file open error: %s", fileio.error_str);
1275 return ERROR_OK;
1276 }
1277
1278 buf_cnt = binary_size = fileio.size;
1279
1280 if (!(oob_format & NAND_OOB_ONLY))
1281 {
1282 page_size = p->page_size;
1283 page = malloc(p->page_size);
1284 }
1285
1286 if (oob_format & NAND_OOB_RAW)
1287 {
1288 if (p->page_size == 512)
1289 oob_size = 16;
1290 else if (p->page_size == 2048)
1291 oob_size = 64;
1292 oob = malloc(oob_size);
1293 }
1294
1295 if (offset % p->page_size)
1296 {
1297 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1298 return ERROR_OK;
1299 }
1300
1301 while (buf_cnt > 0)
1302 {
1303 u32 size_read;
1304
1305 if (page)
1306 {
1307 fileio_read(&fileio, page_size, page, &size_read);
1308 buf_cnt -= size_read;
1309 if (size_read < page_size)
1310 {
1311 memset(page + size_read, 0xff, page_size - size_read);
1312 }
1313 }
1314
1315 if (oob)
1316 {
1317 fileio_read(&fileio, oob_size, oob, &size_read);
1318 buf_cnt -= size_read;
1319 if (size_read < oob_size)
1320 {
1321 memset(oob + size_read, 0xff, oob_size - size_read);
1322 }
1323 }
1324
1325 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1326 {
1327 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8x",
1328 args[1], args[0], offset);
1329 return ERROR_OK;
1330 }
1331 offset += page_size;
1332 }
1333
1334 fileio_close(&fileio);
1335
1336 duration_stop_measure(&duration, &duration_text);
1337 command_print(cmd_ctx, "wrote file %s to NAND flash %s at offset 0x%8.8x in %s",
1338 args[1], args[0], offset, duration_text);
1339 free(duration_text);
1340 }
1341 else
1342 {
1343 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1344 }
1345
1346 return ERROR_OK;
1347 }
1348
1349 int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1350 {
1351 nand_device_t *p;
1352
1353 if (argc < 4)
1354 {
1355 return ERROR_COMMAND_SYNTAX_ERROR;
1356 }
1357
1358 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1359 if (p)
1360 {
1361 if (p->device)
1362 {
1363 fileio_t fileio;
1364 duration_t duration;
1365 char *duration_text;
1366 int retval;
1367
1368 u8 *page = NULL;
1369 u32 page_size = 0;
1370 u8 *oob = NULL;
1371 u32 oob_size = 0;
1372 u32 address = strtoul(args[2], NULL, 0);
1373 u32 size = strtoul(args[3], NULL, 0);
1374 u32 bytes_done = 0;
1375 enum oob_formats oob_format = NAND_OOB_NONE;
1376
1377 if (argc > 4)
1378 {
1379 int i;
1380 for (i = 4; i < argc; i++)
1381 {
1382 if (!strcmp(args[i], "oob_raw"))
1383 oob_format |= NAND_OOB_RAW;
1384 else if (!strcmp(args[i], "oob_only"))
1385 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1386 else
1387 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1388 }
1389 }
1390
1391 if ((address % p->page_size) || (size % p->page_size))
1392 {
1393 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1394 return ERROR_OK;
1395 }
1396
1397 if (!(oob_format & NAND_OOB_ONLY))
1398 {
1399 page_size = p->page_size;
1400 page = malloc(p->page_size);
1401 }
1402
1403 if (oob_format & NAND_OOB_RAW)
1404 {
1405 if (p->page_size == 512)
1406 oob_size = 16;
1407 else if (p->page_size == 2048)
1408 oob_size = 64;
1409 oob = malloc(oob_size);
1410 }
1411
1412 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1413 {
1414 command_print(cmd_ctx, "dump_image error: %s", fileio.error_str);
1415 return ERROR_OK;
1416 }
1417
1418 duration_start_measure(&duration);
1419
1420 while (size > 0)
1421 {
1422 u32 size_written;
1423 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1424 {
1425 command_print(cmd_ctx, "reading NAND flash page failed");
1426 return ERROR_OK;
1427 }
1428
1429 if (page)
1430 {
1431 fileio_write(&fileio, page_size, page, &size_written);
1432 bytes_done += page_size;
1433 }
1434
1435 if (oob)
1436 {
1437 fileio_write(&fileio, oob_size, oob, &size_written);
1438 bytes_done += oob_size;
1439 }
1440
1441 size -= p->page_size;
1442 address += p->page_size;
1443 }
1444
1445 if (page)
1446 free(page);
1447
1448 if (oob)
1449 free(oob);
1450
1451 fileio_close(&fileio);
1452
1453 duration_stop_measure(&duration, &duration_text);
1454 command_print(cmd_ctx, "dumped %"PRIi64" byte in %s", fileio.size, duration_text);
1455 free(duration_text);
1456 }
1457 else
1458 {
1459 command_print(cmd_ctx, "#%i: not probed");
1460 }
1461 }
1462 else
1463 {
1464 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1465 }
1466
1467 return ERROR_OK;
1468 }
1469
1470 int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1471 {
1472 nand_device_t *p;
1473
1474 if ((argc < 1) || (argc > 2))
1475 {
1476 return ERROR_COMMAND_SYNTAX_ERROR;
1477 }
1478
1479 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1480 if (p)
1481 {
1482 if (p->device)
1483 {
1484 if (argc == 2)
1485 {
1486 if (strcmp("enable", args[1]) == 0)
1487 {
1488 p->use_raw = 1;
1489 }
1490 else if (strcmp("disable", args[1]) == 0)
1491 {
1492 p->use_raw = 0;
1493 }
1494 else
1495 {
1496 return ERROR_COMMAND_SYNTAX_ERROR;
1497 }
1498 }
1499
1500 command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
1501 }
1502 else
1503 {
1504 command_print(cmd_ctx, "#%i: not probed");
1505 }
1506 }
1507 else
1508 {
1509 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1510 }
1511
1512 return ERROR_OK;
1513 }
1514
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