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pld: factor init to 'pld init'
[openocd.git] / src / flash / nand.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "nand.h"
28 #include "common.h"
29 #include "time_support.h"
30 #include "fileio.h"
31
32 static int nand_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
33 //static int nand_read_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size);
34
35 static int nand_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
36
37 /* NAND flash controller
38 */
39 extern struct nand_flash_controller nonce_nand_controller;
40 extern struct nand_flash_controller davinci_nand_controller;
41 extern struct nand_flash_controller lpc3180_nand_controller;
42 extern struct nand_flash_controller orion_nand_controller;
43 extern struct nand_flash_controller s3c2410_nand_controller;
44 extern struct nand_flash_controller s3c2412_nand_controller;
45 extern struct nand_flash_controller s3c2440_nand_controller;
46 extern struct nand_flash_controller s3c2443_nand_controller;
47 extern struct nand_flash_controller imx31_nand_flash_controller;
48
49 /* extern struct nand_flash_controller boundary_scan_nand_controller; */
50
51 static struct nand_flash_controller *nand_flash_controllers[] =
52 {
53 &nonce_nand_controller,
54 &davinci_nand_controller,
55 &lpc3180_nand_controller,
56 &orion_nand_controller,
57 &s3c2410_nand_controller,
58 &s3c2412_nand_controller,
59 &s3c2440_nand_controller,
60 &s3c2443_nand_controller,
61 &imx31_nand_flash_controller,
62 /* &boundary_scan_nand_controller, */
63 NULL
64 };
65
66 /* configured NAND devices and NAND Flash command handler */
67 static struct nand_device *nand_devices = NULL;
68
69 /* Chip ID list
70 *
71 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
72 * options
73 *
74 * Pagesize; 0, 256, 512
75 * 0 get this information from the extended chip ID
76 * 256 256 Byte page size
77 * 512 512 Byte page size
78 */
79 static struct nand_info nand_flash_ids[] =
80 {
81 /* start "museum" IDs */
82 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
83 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
84 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
85 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
86 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
87 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
88 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
89 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
90 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
91 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
92
93 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
94 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
95 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
96 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
97 /* end "museum" IDs */
98
99 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
100 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
101 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
102 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
103
104 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
105 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
106 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
107 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
108
109 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
110 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
111 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
112 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
113
114 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
115 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
116 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
117 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
118 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
119 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
120 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
121
122 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
123
124 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
125 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
126 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
127 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
128
129 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
130 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
131 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
132 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
133
134 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
135 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
136 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
137 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
138
139 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
140 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
141 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
142 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
143
144 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
145 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
146 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
147 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
148
149 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
150 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
151 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
152 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
153
154 {NULL, 0, 0, 0, 0, 0 }
155 };
156
157 /* Manufacturer ID list
158 */
159 static struct nand_manufacturer nand_manuf_ids[] =
160 {
161 {0x0, "unknown"},
162 {NAND_MFR_TOSHIBA, "Toshiba"},
163 {NAND_MFR_SAMSUNG, "Samsung"},
164 {NAND_MFR_FUJITSU, "Fujitsu"},
165 {NAND_MFR_NATIONAL, "National"},
166 {NAND_MFR_RENESAS, "Renesas"},
167 {NAND_MFR_STMICRO, "ST Micro"},
168 {NAND_MFR_HYNIX, "Hynix"},
169 {NAND_MFR_MICRON, "Micron"},
170 {0x0, NULL},
171 };
172
173 /*
174 * Define default oob placement schemes for large and small page devices
175 */
176
177 #if 0
178 static struct nand_ecclayout nand_oob_8 = {
179 .eccbytes = 3,
180 .eccpos = {0, 1, 2},
181 .oobfree = {
182 {.offset = 3,
183 .length = 2},
184 {.offset = 6,
185 .length = 2}}
186 };
187 #endif
188
189 static struct nand_ecclayout nand_oob_16 = {
190 .eccbytes = 6,
191 .eccpos = {0, 1, 2, 3, 6, 7},
192 .oobfree = {
193 {.offset = 8,
194 . length = 8}}
195 };
196
197 static struct nand_ecclayout nand_oob_64 = {
198 .eccbytes = 24,
199 .eccpos = {
200 40, 41, 42, 43, 44, 45, 46, 47,
201 48, 49, 50, 51, 52, 53, 54, 55,
202 56, 57, 58, 59, 60, 61, 62, 63},
203 .oobfree = {
204 {.offset = 2,
205 .length = 38}}
206 };
207
208 COMMAND_HANDLER(handle_nand_list_drivers)
209 {
210 command_print(CMD_CTX, "Available NAND flash controller drivers:");
211 for (unsigned i = 0; nand_flash_controllers[i]; i++)
212 command_print(CMD_CTX, " %s", nand_flash_controllers[i]->name);
213 return ERROR_OK;
214 }
215
216 static COMMAND_HELPER(create_nand_device, const char *bank_name,
217 struct nand_flash_controller *controller)
218 {
219 if (NULL != controller->commands)
220 {
221 int retval = register_commands(CMD_CTX, NULL,
222 controller->commands);
223 if (ERROR_OK != retval)
224 return retval;
225 }
226 struct nand_device *c = malloc(sizeof(struct nand_device));
227
228 c->name = strdup(bank_name);
229 c->controller = controller;
230 c->controller_priv = NULL;
231 c->manufacturer = NULL;
232 c->device = NULL;
233 c->bus_width = 0;
234 c->address_cycles = 0;
235 c->page_size = 0;
236 c->use_raw = 0;
237 c->next = NULL;
238
239 int retval = CALL_COMMAND_HANDLER(controller->nand_device_command, c);
240 if (ERROR_OK != retval)
241 {
242 LOG_ERROR("'%s' driver rejected nand flash", controller->name);
243 free(c);
244 return ERROR_OK;
245 }
246
247 if (nand_devices) {
248 struct nand_device *p = nand_devices;
249 while (p && p->next) p = p->next;
250 p->next = c;
251 } else
252 nand_devices = c;
253
254 return ERROR_OK;
255 }
256
257 COMMAND_HANDLER(handle_nand_device_command)
258 {
259 if (CMD_ARGC < 1)
260 {
261 LOG_ERROR("incomplete nand device configuration");
262 return ERROR_FLASH_BANK_INVALID;
263 }
264
265 // save name and increment (for compatibility) with drivers
266 const char *bank_name = *CMD_ARGV++;
267 CMD_ARGC--;
268
269 const char *driver_name = CMD_ARGV[0];
270 for (unsigned i = 0; nand_flash_controllers[i]; i++)
271 {
272 struct nand_flash_controller *controller = nand_flash_controllers[i];
273 if (strcmp(driver_name, controller->name) != 0)
274 continue;
275
276 return CALL_COMMAND_HANDLER(create_nand_device,
277 bank_name, controller);
278 }
279
280 LOG_ERROR("No valid NAND flash driver found (%s)", driver_name);
281 return CALL_COMMAND_HANDLER(handle_nand_list_drivers);
282 }
283
284 static const struct command_registration nand_config_command_handlers[] = {
285 {
286 .name = "device",
287 .handler = &handle_nand_device_command,
288 .mode = COMMAND_CONFIG,
289 .help = "defines a new NAND bank",
290 },
291 {
292 .name = "drivers",
293 .handler = &handle_nand_list_drivers,
294 .mode = COMMAND_ANY,
295 .help = "lists available NAND drivers",
296 },
297 COMMAND_REGISTRATION_DONE
298 };
299 static const struct command_registration nand_command_handlers[] = {
300 {
301 .name = "nand",
302 .mode = COMMAND_ANY,
303 .help = "NAND flash command group",
304 .chain = nand_config_command_handlers,
305 },
306 COMMAND_REGISTRATION_DONE
307 };
308
309 int nand_register_commands(struct command_context *cmd_ctx)
310 {
311 return register_commands(cmd_ctx, NULL, nand_command_handlers);
312 }
313
314 struct nand_device *get_nand_device_by_name(const char *name)
315 {
316 unsigned requested = get_flash_name_index(name);
317 unsigned found = 0;
318
319 struct nand_device *nand;
320 for (nand = nand_devices; NULL != nand; nand = nand->next)
321 {
322 if (strcmp(nand->name, name) == 0)
323 return nand;
324 if (!flash_driver_name_matches(nand->controller->name, name))
325 continue;
326 if (++found < requested)
327 continue;
328 return nand;
329 }
330 return NULL;
331 }
332
333 struct nand_device *get_nand_device_by_num(int num)
334 {
335 struct nand_device *p;
336 int i = 0;
337
338 for (p = nand_devices; p; p = p->next)
339 {
340 if (i++ == num)
341 {
342 return p;
343 }
344 }
345
346 return NULL;
347 }
348
349 COMMAND_HELPER(nand_command_get_device, unsigned name_index,
350 struct nand_device **nand)
351 {
352 const char *str = CMD_ARGV[name_index];
353 *nand = get_nand_device_by_name(str);
354 if (*nand)
355 return ERROR_OK;
356
357 unsigned num;
358 COMMAND_PARSE_NUMBER(uint, str, num);
359 *nand = get_nand_device_by_num(num);
360 if (!*nand) {
361 command_print(CMD_CTX, "NAND flash device '%s' not found", str);
362 return ERROR_INVALID_ARGUMENTS;
363 }
364 return ERROR_OK;
365 }
366
367 static int nand_build_bbt(struct nand_device *nand, int first, int last)
368 {
369 uint32_t page = 0x0;
370 int i;
371 uint8_t oob[6];
372
373 if ((first < 0) || (first >= nand->num_blocks))
374 first = 0;
375
376 if ((last >= nand->num_blocks) || (last == -1))
377 last = nand->num_blocks - 1;
378
379 for (i = first; i < last; i++)
380 {
381 nand_read_page(nand, page, NULL, 0, oob, 6);
382
383 if (((nand->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
384 || (((nand->page_size == 512) && (oob[5] != 0xff)) ||
385 ((nand->page_size == 2048) && (oob[0] != 0xff))))
386 {
387 LOG_WARNING("bad block: %i", i);
388 nand->blocks[i].is_bad = 1;
389 }
390 else
391 {
392 nand->blocks[i].is_bad = 0;
393 }
394
395 page += (nand->erase_size / nand->page_size);
396 }
397
398 return ERROR_OK;
399 }
400
401 int nand_read_status(struct nand_device *nand, uint8_t *status)
402 {
403 if (!nand->device)
404 return ERROR_NAND_DEVICE_NOT_PROBED;
405
406 /* Send read status command */
407 nand->controller->command(nand, NAND_CMD_STATUS);
408
409 alive_sleep(1);
410
411 /* read status */
412 if (nand->device->options & NAND_BUSWIDTH_16)
413 {
414 uint16_t data;
415 nand->controller->read_data(nand, &data);
416 *status = data & 0xff;
417 }
418 else
419 {
420 nand->controller->read_data(nand, status);
421 }
422
423 return ERROR_OK;
424 }
425
426 static int nand_poll_ready(struct nand_device *nand, int timeout)
427 {
428 uint8_t status;
429
430 nand->controller->command(nand, NAND_CMD_STATUS);
431 do {
432 if (nand->device->options & NAND_BUSWIDTH_16) {
433 uint16_t data;
434 nand->controller->read_data(nand, &data);
435 status = data & 0xff;
436 } else {
437 nand->controller->read_data(nand, &status);
438 }
439 if (status & NAND_STATUS_READY)
440 break;
441 alive_sleep(1);
442 } while (timeout--);
443
444 return (status & NAND_STATUS_READY) != 0;
445 }
446
447 int nand_probe(struct nand_device *nand)
448 {
449 uint8_t manufacturer_id, device_id;
450 uint8_t id_buff[6];
451 int retval;
452 int i;
453
454 /* clear device data */
455 nand->device = NULL;
456 nand->manufacturer = NULL;
457
458 /* clear device parameters */
459 nand->bus_width = 0;
460 nand->address_cycles = 0;
461 nand->page_size = 0;
462 nand->erase_size = 0;
463
464 /* initialize controller (device parameters are zero, use controller default) */
465 if ((retval = nand->controller->init(nand) != ERROR_OK))
466 {
467 switch (retval)
468 {
469 case ERROR_NAND_OPERATION_FAILED:
470 LOG_DEBUG("controller initialization failed");
471 return ERROR_NAND_OPERATION_FAILED;
472 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
473 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
474 return ERROR_NAND_OPERATION_FAILED;
475 default:
476 LOG_ERROR("BUG: unknown controller initialization failure");
477 return ERROR_NAND_OPERATION_FAILED;
478 }
479 }
480
481 nand->controller->command(nand, NAND_CMD_RESET);
482 nand->controller->reset(nand);
483
484 nand->controller->command(nand, NAND_CMD_READID);
485 nand->controller->address(nand, 0x0);
486
487 if (nand->bus_width == 8)
488 {
489 nand->controller->read_data(nand, &manufacturer_id);
490 nand->controller->read_data(nand, &device_id);
491 }
492 else
493 {
494 uint16_t data_buf;
495 nand->controller->read_data(nand, &data_buf);
496 manufacturer_id = data_buf & 0xff;
497 nand->controller->read_data(nand, &data_buf);
498 device_id = data_buf & 0xff;
499 }
500
501 for (i = 0; nand_flash_ids[i].name; i++)
502 {
503 if (nand_flash_ids[i].id == device_id)
504 {
505 nand->device = &nand_flash_ids[i];
506 break;
507 }
508 }
509
510 for (i = 0; nand_manuf_ids[i].name; i++)
511 {
512 if (nand_manuf_ids[i].id == manufacturer_id)
513 {
514 nand->manufacturer = &nand_manuf_ids[i];
515 break;
516 }
517 }
518
519 if (!nand->manufacturer)
520 {
521 nand->manufacturer = &nand_manuf_ids[0];
522 nand->manufacturer->id = manufacturer_id;
523 }
524
525 if (!nand->device)
526 {
527 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
528 manufacturer_id, device_id);
529 return ERROR_NAND_OPERATION_FAILED;
530 }
531
532 LOG_DEBUG("found %s (%s)", nand->device->name, nand->manufacturer->name);
533
534 /* initialize device parameters */
535
536 /* bus width */
537 if (nand->device->options & NAND_BUSWIDTH_16)
538 nand->bus_width = 16;
539 else
540 nand->bus_width = 8;
541
542 /* Do we need extended device probe information? */
543 if (nand->device->page_size == 0 ||
544 nand->device->erase_size == 0)
545 {
546 if (nand->bus_width == 8)
547 {
548 nand->controller->read_data(nand, id_buff + 3);
549 nand->controller->read_data(nand, id_buff + 4);
550 nand->controller->read_data(nand, id_buff + 5);
551 }
552 else
553 {
554 uint16_t data_buf;
555
556 nand->controller->read_data(nand, &data_buf);
557 id_buff[3] = data_buf;
558
559 nand->controller->read_data(nand, &data_buf);
560 id_buff[4] = data_buf;
561
562 nand->controller->read_data(nand, &data_buf);
563 id_buff[5] = data_buf >> 8;
564 }
565 }
566
567 /* page size */
568 if (nand->device->page_size == 0)
569 {
570 nand->page_size = 1 << (10 + (id_buff[4] & 3));
571 }
572 else if (nand->device->page_size == 256)
573 {
574 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
575 return ERROR_NAND_OPERATION_FAILED;
576 }
577 else
578 {
579 nand->page_size = nand->device->page_size;
580 }
581
582 /* number of address cycles */
583 if (nand->page_size <= 512)
584 {
585 /* small page devices */
586 if (nand->device->chip_size <= 32)
587 nand->address_cycles = 3;
588 else if (nand->device->chip_size <= 8*1024)
589 nand->address_cycles = 4;
590 else
591 {
592 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
593 nand->address_cycles = 5;
594 }
595 }
596 else
597 {
598 /* large page devices */
599 if (nand->device->chip_size <= 128)
600 nand->address_cycles = 4;
601 else if (nand->device->chip_size <= 32*1024)
602 nand->address_cycles = 5;
603 else
604 {
605 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
606 nand->address_cycles = 6;
607 }
608 }
609
610 /* erase size */
611 if (nand->device->erase_size == 0)
612 {
613 switch ((id_buff[4] >> 4) & 3) {
614 case 0:
615 nand->erase_size = 64 << 10;
616 break;
617 case 1:
618 nand->erase_size = 128 << 10;
619 break;
620 case 2:
621 nand->erase_size = 256 << 10;
622 break;
623 case 3:
624 nand->erase_size =512 << 10;
625 break;
626 }
627 }
628 else
629 {
630 nand->erase_size = nand->device->erase_size;
631 }
632
633 /* initialize controller, but leave parameters at the controllers default */
634 if ((retval = nand->controller->init(nand) != ERROR_OK))
635 {
636 switch (retval)
637 {
638 case ERROR_NAND_OPERATION_FAILED:
639 LOG_DEBUG("controller initialization failed");
640 return ERROR_NAND_OPERATION_FAILED;
641 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
642 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
643 nand->bus_width, nand->address_cycles, nand->page_size);
644 return ERROR_NAND_OPERATION_FAILED;
645 default:
646 LOG_ERROR("BUG: unknown controller initialization failure");
647 return ERROR_NAND_OPERATION_FAILED;
648 }
649 }
650
651 nand->num_blocks = (nand->device->chip_size * 1024) / (nand->erase_size / 1024);
652 nand->blocks = malloc(sizeof(struct nand_block) * nand->num_blocks);
653
654 for (i = 0; i < nand->num_blocks; i++)
655 {
656 nand->blocks[i].size = nand->erase_size;
657 nand->blocks[i].offset = i * nand->erase_size;
658 nand->blocks[i].is_erased = -1;
659 nand->blocks[i].is_bad = -1;
660 }
661
662 return ERROR_OK;
663 }
664
665 static int nand_erase(struct nand_device *nand, int first_block, int last_block)
666 {
667 int i;
668 uint32_t page;
669 uint8_t status;
670 int retval;
671
672 if (!nand->device)
673 return ERROR_NAND_DEVICE_NOT_PROBED;
674
675 if ((first_block < 0) || (last_block > nand->num_blocks))
676 return ERROR_INVALID_ARGUMENTS;
677
678 /* make sure we know if a block is bad before erasing it */
679 for (i = first_block; i <= last_block; i++)
680 {
681 if (nand->blocks[i].is_bad == -1)
682 {
683 nand_build_bbt(nand, i, last_block);
684 break;
685 }
686 }
687
688 for (i = first_block; i <= last_block; i++)
689 {
690 /* Send erase setup command */
691 nand->controller->command(nand, NAND_CMD_ERASE1);
692
693 page = i * (nand->erase_size / nand->page_size);
694
695 /* Send page address */
696 if (nand->page_size <= 512)
697 {
698 /* row */
699 nand->controller->address(nand, page & 0xff);
700 nand->controller->address(nand, (page >> 8) & 0xff);
701
702 /* 3rd cycle only on devices with more than 32 MiB */
703 if (nand->address_cycles >= 4)
704 nand->controller->address(nand, (page >> 16) & 0xff);
705
706 /* 4th cycle only on devices with more than 8 GiB */
707 if (nand->address_cycles >= 5)
708 nand->controller->address(nand, (page >> 24) & 0xff);
709 }
710 else
711 {
712 /* row */
713 nand->controller->address(nand, page & 0xff);
714 nand->controller->address(nand, (page >> 8) & 0xff);
715
716 /* 3rd cycle only on devices with more than 128 MiB */
717 if (nand->address_cycles >= 5)
718 nand->controller->address(nand, (page >> 16) & 0xff);
719 }
720
721 /* Send erase confirm command */
722 nand->controller->command(nand, NAND_CMD_ERASE2);
723
724 retval = nand->controller->nand_ready ?
725 nand->controller->nand_ready(nand, 1000) :
726 nand_poll_ready(nand, 1000);
727 if (!retval) {
728 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
729 return ERROR_NAND_OPERATION_TIMEOUT;
730 }
731
732 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
733 {
734 LOG_ERROR("couldn't read status");
735 return ERROR_NAND_OPERATION_FAILED;
736 }
737
738 if (status & 0x1)
739 {
740 LOG_ERROR("didn't erase %sblock %d; status: 0x%2.2x",
741 (nand->blocks[i].is_bad == 1)
742 ? "bad " : "",
743 i, status);
744 /* continue; other blocks might still be erasable */
745 }
746
747 nand->blocks[i].is_erased = 1;
748 }
749
750 return ERROR_OK;
751 }
752
753 #if 0
754 static int nand_read_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size)
755 {
756 uint8_t *page;
757
758 if (!nand->device)
759 return ERROR_NAND_DEVICE_NOT_PROBED;
760
761 if (address % nand->page_size)
762 {
763 LOG_ERROR("reads need to be page aligned");
764 return ERROR_NAND_OPERATION_FAILED;
765 }
766
767 page = malloc(nand->page_size);
768
769 while (data_size > 0)
770 {
771 uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
772 uint32_t page_address;
773
774
775 page_address = address / nand->page_size;
776
777 nand_read_page(nand, page_address, page, nand->page_size, NULL, 0);
778
779 memcpy(data, page, thisrun_size);
780
781 address += thisrun_size;
782 data += thisrun_size;
783 data_size -= thisrun_size;
784 }
785
786 free(page);
787
788 return ERROR_OK;
789 }
790
791 static int nand_write_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size)
792 {
793 uint8_t *page;
794
795 if (!nand->device)
796 return ERROR_NAND_DEVICE_NOT_PROBED;
797
798 if (address % nand->page_size)
799 {
800 LOG_ERROR("writes need to be page aligned");
801 return ERROR_NAND_OPERATION_FAILED;
802 }
803
804 page = malloc(nand->page_size);
805
806 while (data_size > 0)
807 {
808 uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
809 uint32_t page_address;
810
811 memset(page, 0xff, nand->page_size);
812 memcpy(page, data, thisrun_size);
813
814 page_address = address / nand->page_size;
815
816 nand_write_page(nand, page_address, page, nand->page_size, NULL, 0);
817
818 address += thisrun_size;
819 data += thisrun_size;
820 data_size -= thisrun_size;
821 }
822
823 free(page);
824
825 return ERROR_OK;
826 }
827 #endif
828
829 int nand_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
830 {
831 uint32_t block;
832
833 if (!nand->device)
834 return ERROR_NAND_DEVICE_NOT_PROBED;
835
836 block = page / (nand->erase_size / nand->page_size);
837 if (nand->blocks[block].is_erased == 1)
838 nand->blocks[block].is_erased = 0;
839
840 if (nand->use_raw || nand->controller->write_page == NULL)
841 return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
842 else
843 return nand->controller->write_page(nand, page, data, data_size, oob, oob_size);
844 }
845
846 static int nand_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
847 {
848 if (!nand->device)
849 return ERROR_NAND_DEVICE_NOT_PROBED;
850
851 if (nand->use_raw || nand->controller->read_page == NULL)
852 return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
853 else
854 return nand->controller->read_page(nand, page, data, data_size, oob, oob_size);
855 }
856
857 int nand_read_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
858 {
859 uint32_t i;
860
861 if (!nand->device)
862 return ERROR_NAND_DEVICE_NOT_PROBED;
863
864 if (nand->page_size <= 512)
865 {
866 /* small page device */
867 if (data)
868 nand->controller->command(nand, NAND_CMD_READ0);
869 else
870 nand->controller->command(nand, NAND_CMD_READOOB);
871
872 /* column (always 0, we start at the beginning of a page/OOB area) */
873 nand->controller->address(nand, 0x0);
874
875 /* row */
876 nand->controller->address(nand, page & 0xff);
877 nand->controller->address(nand, (page >> 8) & 0xff);
878
879 /* 4th cycle only on devices with more than 32 MiB */
880 if (nand->address_cycles >= 4)
881 nand->controller->address(nand, (page >> 16) & 0xff);
882
883 /* 5th cycle only on devices with more than 8 GiB */
884 if (nand->address_cycles >= 5)
885 nand->controller->address(nand, (page >> 24) & 0xff);
886 }
887 else
888 {
889 /* large page device */
890 nand->controller->command(nand, NAND_CMD_READ0);
891
892 /* column (0 when we start at the beginning of a page,
893 * or 2048 for the beginning of OOB area)
894 */
895 nand->controller->address(nand, 0x0);
896 if (data)
897 nand->controller->address(nand, 0x0);
898 else
899 nand->controller->address(nand, 0x8);
900
901 /* row */
902 nand->controller->address(nand, page & 0xff);
903 nand->controller->address(nand, (page >> 8) & 0xff);
904
905 /* 5th cycle only on devices with more than 128 MiB */
906 if (nand->address_cycles >= 5)
907 nand->controller->address(nand, (page >> 16) & 0xff);
908
909 /* large page devices need a start command */
910 nand->controller->command(nand, NAND_CMD_READSTART);
911 }
912
913 if (nand->controller->nand_ready) {
914 if (!nand->controller->nand_ready(nand, 100))
915 return ERROR_NAND_OPERATION_TIMEOUT;
916 } else {
917 alive_sleep(1);
918 }
919
920 if (data)
921 {
922 if (nand->controller->read_block_data != NULL)
923 (nand->controller->read_block_data)(nand, data, data_size);
924 else
925 {
926 for (i = 0; i < data_size;)
927 {
928 if (nand->device->options & NAND_BUSWIDTH_16)
929 {
930 nand->controller->read_data(nand, data);
931 data += 2;
932 i += 2;
933 }
934 else
935 {
936 nand->controller->read_data(nand, data);
937 data += 1;
938 i += 1;
939 }
940 }
941 }
942 }
943
944 if (oob)
945 {
946 if (nand->controller->read_block_data != NULL)
947 (nand->controller->read_block_data)(nand, oob, oob_size);
948 else
949 {
950 for (i = 0; i < oob_size;)
951 {
952 if (nand->device->options & NAND_BUSWIDTH_16)
953 {
954 nand->controller->read_data(nand, oob);
955 oob += 2;
956 i += 2;
957 }
958 else
959 {
960 nand->controller->read_data(nand, oob);
961 oob += 1;
962 i += 1;
963 }
964 }
965 }
966 }
967
968 return ERROR_OK;
969 }
970
971 int nand_write_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
972 {
973 uint32_t i;
974 int retval;
975 uint8_t status;
976
977 if (!nand->device)
978 return ERROR_NAND_DEVICE_NOT_PROBED;
979
980 nand->controller->command(nand, NAND_CMD_SEQIN);
981
982 if (nand->page_size <= 512)
983 {
984 /* column (always 0, we start at the beginning of a page/OOB area) */
985 nand->controller->address(nand, 0x0);
986
987 /* row */
988 nand->controller->address(nand, page & 0xff);
989 nand->controller->address(nand, (page >> 8) & 0xff);
990
991 /* 4th cycle only on devices with more than 32 MiB */
992 if (nand->address_cycles >= 4)
993 nand->controller->address(nand, (page >> 16) & 0xff);
994
995 /* 5th cycle only on devices with more than 8 GiB */
996 if (nand->address_cycles >= 5)
997 nand->controller->address(nand, (page >> 24) & 0xff);
998 }
999 else
1000 {
1001 /* column (0 when we start at the beginning of a page,
1002 * or 2048 for the beginning of OOB area)
1003 */
1004 nand->controller->address(nand, 0x0);
1005 if (data)
1006 nand->controller->address(nand, 0x0);
1007 else
1008 nand->controller->address(nand, 0x8);
1009
1010 /* row */
1011 nand->controller->address(nand, page & 0xff);
1012 nand->controller->address(nand, (page >> 8) & 0xff);
1013
1014 /* 5th cycle only on devices with more than 128 MiB */
1015 if (nand->address_cycles >= 5)
1016 nand->controller->address(nand, (page >> 16) & 0xff);
1017 }
1018
1019 if (data)
1020 {
1021 if (nand->controller->write_block_data != NULL)
1022 (nand->controller->write_block_data)(nand, data, data_size);
1023 else
1024 {
1025 for (i = 0; i < data_size;)
1026 {
1027 if (nand->device->options & NAND_BUSWIDTH_16)
1028 {
1029 uint16_t data_buf = le_to_h_u16(data);
1030 nand->controller->write_data(nand, data_buf);
1031 data += 2;
1032 i += 2;
1033 }
1034 else
1035 {
1036 nand->controller->write_data(nand, *data);
1037 data += 1;
1038 i += 1;
1039 }
1040 }
1041 }
1042 }
1043
1044 if (oob)
1045 {
1046 if (nand->controller->write_block_data != NULL)
1047 (nand->controller->write_block_data)(nand, oob, oob_size);
1048 else
1049 {
1050 for (i = 0; i < oob_size;)
1051 {
1052 if (nand->device->options & NAND_BUSWIDTH_16)
1053 {
1054 uint16_t oob_buf = le_to_h_u16(data);
1055 nand->controller->write_data(nand, oob_buf);
1056 oob += 2;
1057 i += 2;
1058 }
1059 else
1060 {
1061 nand->controller->write_data(nand, *oob);
1062 oob += 1;
1063 i += 1;
1064 }
1065 }
1066 }
1067 }
1068
1069 nand->controller->command(nand, NAND_CMD_PAGEPROG);
1070
1071 retval = nand->controller->nand_ready ?
1072 nand->controller->nand_ready(nand, 100) :
1073 nand_poll_ready(nand, 100);
1074 if (!retval)
1075 return ERROR_NAND_OPERATION_TIMEOUT;
1076
1077 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
1078 {
1079 LOG_ERROR("couldn't read status");
1080 return ERROR_NAND_OPERATION_FAILED;
1081 }
1082
1083 if (status & NAND_STATUS_FAIL)
1084 {
1085 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1086 return ERROR_NAND_OPERATION_FAILED;
1087 }
1088
1089 return ERROR_OK;
1090 }
1091
1092 COMMAND_HANDLER(handle_nand_list_command)
1093 {
1094 struct nand_device *p;
1095 int i;
1096
1097 if (!nand_devices)
1098 {
1099 command_print(CMD_CTX, "no NAND flash devices configured");
1100 return ERROR_OK;
1101 }
1102
1103 for (p = nand_devices, i = 0; p; p = p->next, i++)
1104 {
1105 if (p->device)
1106 command_print(CMD_CTX, "#%i: %s (%s) "
1107 "pagesize: %i, buswidth: %i,\n\t"
1108 "blocksize: %i, blocks: %i",
1109 i, p->device->name, p->manufacturer->name,
1110 p->page_size, p->bus_width,
1111 p->erase_size, p->num_blocks);
1112 else
1113 command_print(CMD_CTX, "#%i: not probed", i);
1114 }
1115
1116 return ERROR_OK;
1117 }
1118
1119 COMMAND_HANDLER(handle_nand_info_command)
1120 {
1121 int i = 0;
1122 int j = 0;
1123 int first = -1;
1124 int last = -1;
1125
1126 switch (CMD_ARGC) {
1127 default:
1128 return ERROR_COMMAND_SYNTAX_ERROR;
1129 case 1:
1130 first = 0;
1131 last = INT32_MAX;
1132 break;
1133 case 2:
1134 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], i);
1135 first = last = i;
1136 i = 0;
1137 break;
1138 case 3:
1139 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], first);
1140 COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], last);
1141 break;
1142 }
1143
1144 struct nand_device *p;
1145 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1146 if (ERROR_OK != retval)
1147 return retval;
1148
1149 if (NULL == p->device)
1150 {
1151 command_print(CMD_CTX, "#%s: not probed", CMD_ARGV[0]);
1152 return ERROR_OK;
1153 }
1154
1155 if (first >= p->num_blocks)
1156 first = p->num_blocks - 1;
1157
1158 if (last >= p->num_blocks)
1159 last = p->num_blocks - 1;
1160
1161 command_print(CMD_CTX, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1162 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1163
1164 for (j = first; j <= last; j++)
1165 {
1166 char *erase_state, *bad_state;
1167
1168 if (p->blocks[j].is_erased == 0)
1169 erase_state = "not erased";
1170 else if (p->blocks[j].is_erased == 1)
1171 erase_state = "erased";
1172 else
1173 erase_state = "erase state unknown";
1174
1175 if (p->blocks[j].is_bad == 0)
1176 bad_state = "";
1177 else if (p->blocks[j].is_bad == 1)
1178 bad_state = " (marked bad)";
1179 else
1180 bad_state = " (block condition unknown)";
1181
1182 command_print(CMD_CTX,
1183 "\t#%i: 0x%8.8" PRIx32 " (%" PRId32 "kB) %s%s",
1184 j,
1185 p->blocks[j].offset,
1186 p->blocks[j].size / 1024,
1187 erase_state,
1188 bad_state);
1189 }
1190
1191 return ERROR_OK;
1192 }
1193
1194 COMMAND_HANDLER(handle_nand_probe_command)
1195 {
1196 if (CMD_ARGC != 1)
1197 {
1198 return ERROR_COMMAND_SYNTAX_ERROR;
1199 }
1200
1201 struct nand_device *p;
1202 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1203 if (ERROR_OK != retval)
1204 return retval;
1205
1206 if ((retval = nand_probe(p)) == ERROR_OK)
1207 {
1208 command_print(CMD_CTX, "NAND flash device '%s' found", p->device->name);
1209 }
1210 else if (retval == ERROR_NAND_OPERATION_FAILED)
1211 {
1212 command_print(CMD_CTX, "probing failed for NAND flash device");
1213 }
1214 else
1215 {
1216 command_print(CMD_CTX, "unknown error when probing NAND flash device");
1217 }
1218
1219 return ERROR_OK;
1220 }
1221
1222 COMMAND_HANDLER(handle_nand_erase_command)
1223 {
1224 if (CMD_ARGC != 1 && CMD_ARGC != 3)
1225 {
1226 return ERROR_COMMAND_SYNTAX_ERROR;
1227
1228 }
1229
1230 struct nand_device *p;
1231 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1232 if (ERROR_OK != retval)
1233 return retval;
1234
1235 unsigned long offset;
1236 unsigned long length;
1237
1238 /* erase specified part of the chip; or else everything */
1239 if (CMD_ARGC == 3) {
1240 unsigned long size = p->erase_size * p->num_blocks;
1241
1242 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], offset);
1243 if ((offset % p->erase_size) != 0 || offset >= size)
1244 return ERROR_INVALID_ARGUMENTS;
1245
1246 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], length);
1247 if ((length == 0) || (length % p->erase_size) != 0
1248 || (length + offset) > size)
1249 return ERROR_INVALID_ARGUMENTS;
1250
1251 offset /= p->erase_size;
1252 length /= p->erase_size;
1253 } else {
1254 offset = 0;
1255 length = p->num_blocks;
1256 }
1257
1258 retval = nand_erase(p, offset, offset + length - 1);
1259 if (retval == ERROR_OK)
1260 {
1261 command_print(CMD_CTX, "erased blocks %lu to %lu "
1262 "on NAND flash device #%s '%s'",
1263 offset, offset + length,
1264 CMD_ARGV[0], p->device->name);
1265 }
1266 else if (retval == ERROR_NAND_OPERATION_FAILED)
1267 {
1268 command_print(CMD_CTX, "erase failed");
1269 }
1270 else
1271 {
1272 command_print(CMD_CTX, "unknown error when erasing NAND flash device");
1273 }
1274
1275 return ERROR_OK;
1276 }
1277
1278 COMMAND_HANDLER(handle_nand_check_bad_blocks_command)
1279 {
1280 int first = -1;
1281 int last = -1;
1282
1283 if ((CMD_ARGC < 1) || (CMD_ARGC > 3) || (CMD_ARGC == 2))
1284 {
1285 return ERROR_COMMAND_SYNTAX_ERROR;
1286
1287 }
1288
1289 struct nand_device *p;
1290 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1291 if (ERROR_OK != retval)
1292 return retval;
1293
1294 if (CMD_ARGC == 3)
1295 {
1296 unsigned long offset;
1297 unsigned long length;
1298
1299 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], offset);
1300 if (offset % p->erase_size)
1301 return ERROR_INVALID_ARGUMENTS;
1302 offset /= p->erase_size;
1303
1304 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], length);
1305 if (length % p->erase_size)
1306 return ERROR_INVALID_ARGUMENTS;
1307
1308 length -= 1;
1309 length /= p->erase_size;
1310
1311 first = offset;
1312 last = offset + length;
1313 }
1314
1315 retval = nand_build_bbt(p, first, last);
1316 if (retval == ERROR_OK)
1317 {
1318 command_print(CMD_CTX, "checked NAND flash device for bad blocks, "
1319 "use \"nand info\" command to list blocks");
1320 }
1321 else if (retval == ERROR_NAND_OPERATION_FAILED)
1322 {
1323 command_print(CMD_CTX, "error when checking for bad blocks on "
1324 "NAND flash device");
1325 }
1326 else
1327 {
1328 command_print(CMD_CTX, "unknown error when checking for bad "
1329 "blocks on NAND flash device");
1330 }
1331
1332 return ERROR_OK;
1333 }
1334
1335 struct nand_fileio_state {
1336 uint32_t address;
1337 uint32_t size;
1338
1339 uint8_t *page;
1340 uint32_t page_size;
1341
1342 enum oob_formats oob_format;
1343 uint8_t *oob;
1344 uint32_t oob_size;
1345
1346 const int *eccpos;
1347
1348 bool file_opened;
1349 struct fileio fileio;
1350
1351 struct duration bench;
1352 };
1353
1354 static void nand_fileio_init(struct nand_fileio_state *state)
1355 {
1356 memset(state, 0, sizeof(*state));
1357 state->oob_format = NAND_OOB_NONE;
1358 }
1359
1360 static int nand_fileio_start(struct command_context *cmd_ctx,
1361 struct nand_device *nand, const char *filename, int filemode,
1362 struct nand_fileio_state *state)
1363 {
1364 if (state->address % nand->page_size)
1365 {
1366 command_print(cmd_ctx, "only page-aligned addresses are supported");
1367 return ERROR_COMMAND_SYNTAX_ERROR;
1368 }
1369
1370 duration_start(&state->bench);
1371
1372 if (NULL != filename)
1373 {
1374 int retval = fileio_open(&state->fileio, filename, filemode, FILEIO_BINARY);
1375 if (ERROR_OK != retval)
1376 {
1377 const char *msg = (FILEIO_READ == filemode) ? "read" : "write";
1378 command_print(cmd_ctx, "failed to open '%s' for %s access",
1379 filename, msg);
1380 return retval;
1381 }
1382 state->file_opened = true;
1383 }
1384
1385 if (!(state->oob_format & NAND_OOB_ONLY))
1386 {
1387 state->page_size = nand->page_size;
1388 state->page = malloc(nand->page_size);
1389 }
1390
1391 if (state->oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC | NAND_OOB_SW_ECC_KW))
1392 {
1393 if (nand->page_size == 512)
1394 {
1395 state->oob_size = 16;
1396 state->eccpos = nand_oob_16.eccpos;
1397 }
1398 else if (nand->page_size == 2048)
1399 {
1400 state->oob_size = 64;
1401 state->eccpos = nand_oob_64.eccpos;
1402 }
1403 state->oob = malloc(state->oob_size);
1404 }
1405
1406 return ERROR_OK;
1407 }
1408 static int nand_fileio_cleanup(struct nand_fileio_state *state)
1409 {
1410 if (state->file_opened)
1411 fileio_close(&state->fileio);
1412
1413 if (state->oob)
1414 {
1415 free(state->oob);
1416 state->oob = NULL;
1417 }
1418 if (state->page)
1419 {
1420 free(state->page);
1421 state->page = NULL;
1422 }
1423 return ERROR_OK;
1424 }
1425 static int nand_fileio_finish(struct nand_fileio_state *state)
1426 {
1427 nand_fileio_cleanup(state);
1428 return duration_measure(&state->bench);
1429 }
1430
1431 static COMMAND_HELPER(nand_fileio_parse_args, struct nand_fileio_state *state,
1432 struct nand_device **dev, enum fileio_access filemode,
1433 bool need_size, bool sw_ecc)
1434 {
1435 nand_fileio_init(state);
1436
1437 unsigned minargs = need_size ? 4 : 3;
1438 if (CMD_ARGC < minargs)
1439 return ERROR_COMMAND_SYNTAX_ERROR;
1440
1441 struct nand_device *nand;
1442 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
1443 if (ERROR_OK != retval)
1444 return retval;
1445
1446 if (NULL == nand->device)
1447 {
1448 command_print(CMD_CTX, "#%s: not probed", CMD_ARGV[0]);
1449 return ERROR_OK;
1450 }
1451
1452 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], state->address);
1453 if (need_size)
1454 {
1455 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], state->size);
1456 if (state->size % nand->page_size)
1457 {
1458 command_print(CMD_CTX, "only page-aligned sizes are supported");
1459 return ERROR_COMMAND_SYNTAX_ERROR;
1460 }
1461 }
1462
1463 if (CMD_ARGC > minargs)
1464 {
1465 for (unsigned i = minargs; i < CMD_ARGC; i++)
1466 {
1467 if (!strcmp(CMD_ARGV[i], "oob_raw"))
1468 state->oob_format |= NAND_OOB_RAW;
1469 else if (!strcmp(CMD_ARGV[i], "oob_only"))
1470 state->oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1471 else if (sw_ecc && !strcmp(CMD_ARGV[i], "oob_softecc"))
1472 state->oob_format |= NAND_OOB_SW_ECC;
1473 else if (sw_ecc && !strcmp(CMD_ARGV[i], "oob_softecc_kw"))
1474 state->oob_format |= NAND_OOB_SW_ECC_KW;
1475 else
1476 {
1477 command_print(CMD_CTX, "unknown option: %s", CMD_ARGV[i]);
1478 return ERROR_COMMAND_SYNTAX_ERROR;
1479 }
1480 }
1481 }
1482
1483 retval = nand_fileio_start(CMD_CTX, nand, CMD_ARGV[1], filemode, state);
1484 if (ERROR_OK != retval)
1485 return retval;
1486
1487 if (!need_size)
1488 state->size = state->fileio.size;
1489
1490 *dev = nand;
1491
1492 return ERROR_OK;
1493 }
1494
1495 /**
1496 * @returns If no error occurred, returns number of bytes consumed;
1497 * otherwise, returns a negative error code.)
1498 */
1499 static int nand_fileio_read(struct nand_device *nand,
1500 struct nand_fileio_state *s)
1501 {
1502 size_t total_read = 0;
1503 size_t one_read;
1504
1505 if (NULL != s->page)
1506 {
1507 fileio_read(&s->fileio, s->page_size, s->page, &one_read);
1508 if (one_read < s->page_size)
1509 memset(s->page + one_read, 0xff, s->page_size - one_read);
1510 total_read += one_read;
1511 }
1512
1513 if (s->oob_format & NAND_OOB_SW_ECC)
1514 {
1515 uint8_t ecc[3];
1516 memset(s->oob, 0xff, s->oob_size);
1517 for (uint32_t i = 0, j = 0; i < s->page_size; i += 256)
1518 {
1519 nand_calculate_ecc(nand, s->page + i, ecc);
1520 s->oob[s->eccpos[j++]] = ecc[0];
1521 s->oob[s->eccpos[j++]] = ecc[1];
1522 s->oob[s->eccpos[j++]] = ecc[2];
1523 }
1524 }
1525 else if (s->oob_format & NAND_OOB_SW_ECC_KW)
1526 {
1527 /*
1528 * In this case eccpos is not used as
1529 * the ECC data is always stored contigously
1530 * at the end of the OOB area. It consists
1531 * of 10 bytes per 512-byte data block.
1532 */
1533 uint8_t *ecc = s->oob + s->oob_size - s->page_size / 512 * 10;
1534 memset(s->oob, 0xff, s->oob_size);
1535 for (uint32_t i = 0; i < s->page_size; i += 512)
1536 {
1537 nand_calculate_ecc_kw(nand, s->page + i, ecc);
1538 ecc += 10;
1539 }
1540 }
1541 else if (NULL != s->oob)
1542 {
1543 fileio_read(&s->fileio, s->oob_size, s->oob, &one_read);
1544 if (one_read < s->oob_size)
1545 memset(s->oob + one_read, 0xff, s->oob_size - one_read);
1546 total_read += one_read;
1547 }
1548 return total_read;
1549 }
1550
1551 COMMAND_HANDLER(handle_nand_write_command)
1552 {
1553 struct nand_device *nand = NULL;
1554 struct nand_fileio_state s;
1555 int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
1556 &s, &nand, FILEIO_READ, false, true);
1557 if (ERROR_OK != retval)
1558 return retval;
1559
1560 uint32_t total_bytes = s.size;
1561 while (s.size > 0)
1562 {
1563 int bytes_read = nand_fileio_read(nand, &s);
1564 if (bytes_read <= 0)
1565 {
1566 command_print(CMD_CTX, "error while reading file");
1567 return nand_fileio_cleanup(&s);
1568 }
1569 s.size -= bytes_read;
1570
1571 retval = nand_write_page(nand, s.address / nand->page_size,
1572 s.page, s.page_size, s.oob, s.oob_size);
1573 if (ERROR_OK != retval)
1574 {
1575 command_print(CMD_CTX, "failed writing file %s "
1576 "to NAND flash %s at offset 0x%8.8" PRIx32,
1577 CMD_ARGV[1], CMD_ARGV[0], s.address);
1578 return nand_fileio_cleanup(&s);
1579 }
1580 s.address += s.page_size;
1581 }
1582
1583 if (nand_fileio_finish(&s))
1584 {
1585 command_print(CMD_CTX, "wrote file %s to NAND flash %s up to "
1586 "offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
1587 CMD_ARGV[1], CMD_ARGV[0], s.address, duration_elapsed(&s.bench),
1588 duration_kbps(&s.bench, total_bytes));
1589 }
1590 return ERROR_OK;
1591 }
1592
1593 COMMAND_HANDLER(handle_nand_verify_command)
1594 {
1595 struct nand_device *nand = NULL;
1596 struct nand_fileio_state file;
1597 int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
1598 &file, &nand, FILEIO_READ, false, true);
1599 if (ERROR_OK != retval)
1600 return retval;
1601
1602 struct nand_fileio_state dev;
1603 nand_fileio_init(&dev);
1604 dev.address = file.address;
1605 dev.size = file.size;
1606 dev.oob_format = file.oob_format;
1607 retval = nand_fileio_start(CMD_CTX, nand, NULL, FILEIO_NONE, &dev);
1608 if (ERROR_OK != retval)
1609 return retval;
1610
1611 while (file.size > 0)
1612 {
1613 int retval = nand_read_page(nand, dev.address / dev.page_size,
1614 dev.page, dev.page_size, dev.oob, dev.oob_size);
1615 if (ERROR_OK != retval)
1616 {
1617 command_print(CMD_CTX, "reading NAND flash page failed");
1618 nand_fileio_cleanup(&dev);
1619 return nand_fileio_cleanup(&file);
1620 }
1621
1622 int bytes_read = nand_fileio_read(nand, &file);
1623 if (bytes_read <= 0)
1624 {
1625 command_print(CMD_CTX, "error while reading file");
1626 nand_fileio_cleanup(&dev);
1627 return nand_fileio_cleanup(&file);
1628 }
1629
1630 if ((dev.page && memcmp(dev.page, file.page, dev.page_size)) ||
1631 (dev.oob && memcmp(dev.oob, file.oob, dev.oob_size)) )
1632 {
1633 command_print(CMD_CTX, "NAND flash contents differ "
1634 "at 0x%8.8" PRIx32, dev.address);
1635 nand_fileio_cleanup(&dev);
1636 return nand_fileio_cleanup(&file);
1637 }
1638
1639 file.size -= bytes_read;
1640 dev.address += nand->page_size;
1641 }
1642
1643 if (nand_fileio_finish(&file) == ERROR_OK)
1644 {
1645 command_print(CMD_CTX, "verified file %s in NAND flash %s "
1646 "up to offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
1647 CMD_ARGV[1], CMD_ARGV[0], dev.address, duration_elapsed(&file.bench),
1648 duration_kbps(&file.bench, dev.size));
1649 }
1650
1651 return nand_fileio_cleanup(&dev);
1652 }
1653
1654 COMMAND_HANDLER(handle_nand_dump_command)
1655 {
1656 struct nand_device *nand = NULL;
1657 struct nand_fileio_state s;
1658 int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
1659 &s, &nand, FILEIO_WRITE, true, false);
1660 if (ERROR_OK != retval)
1661 return retval;
1662
1663 while (s.size > 0)
1664 {
1665 size_t size_written;
1666 int retval = nand_read_page(nand, s.address / nand->page_size,
1667 s.page, s.page_size, s.oob, s.oob_size);
1668 if (ERROR_OK != retval)
1669 {
1670 command_print(CMD_CTX, "reading NAND flash page failed");
1671 return nand_fileio_cleanup(&s);
1672 }
1673
1674 if (NULL != s.page)
1675 fileio_write(&s.fileio, s.page_size, s.page, &size_written);
1676
1677 if (NULL != s.oob)
1678 fileio_write(&s.fileio, s.oob_size, s.oob, &size_written);
1679
1680 s.size -= nand->page_size;
1681 s.address += nand->page_size;
1682 }
1683
1684 if (nand_fileio_finish(&s) == ERROR_OK)
1685 {
1686 command_print(CMD_CTX, "dumped %zu bytes in %fs (%0.3f kb/s)",
1687 s.fileio.size, duration_elapsed(&s.bench),
1688 duration_kbps(&s.bench, s.fileio.size));
1689 }
1690 return ERROR_OK;
1691 }
1692
1693 COMMAND_HANDLER(handle_nand_raw_access_command)
1694 {
1695 if ((CMD_ARGC < 1) || (CMD_ARGC > 2))
1696 {
1697 return ERROR_COMMAND_SYNTAX_ERROR;
1698 }
1699
1700 struct nand_device *p;
1701 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1702 if (ERROR_OK != retval)
1703 return retval;
1704
1705 if (NULL == p->device)
1706 {
1707 command_print(CMD_CTX, "#%s: not probed", CMD_ARGV[0]);
1708 return ERROR_OK;
1709 }
1710
1711 if (CMD_ARGC == 2)
1712 COMMAND_PARSE_ENABLE(CMD_ARGV[1], p->use_raw);
1713
1714 const char *msg = p->use_raw ? "enabled" : "disabled";
1715 command_print(CMD_CTX, "raw access is %s", msg);
1716
1717 return ERROR_OK;
1718 }
1719
1720 static const struct command_registration nand_exec_command_handlers[] = {
1721 {
1722 .name = "list",
1723 .handler = &handle_nand_list_command,
1724 .mode = COMMAND_EXEC,
1725 .help = "list configured NAND flash devices",
1726 },
1727 {
1728 .name = "info",
1729 .handler = &handle_nand_info_command,
1730 .mode = COMMAND_EXEC,
1731 .usage = "<bank>",
1732 .help = "print info about a NAND flash device",
1733 },
1734 {
1735 .name = "probe",
1736 .handler = &handle_nand_probe_command,
1737 .mode = COMMAND_EXEC,
1738 .usage = "<bank>",
1739 .help = "identify NAND flash device <num>",
1740
1741 },
1742 {
1743 .name = "check_bad_blocks",
1744 .handler = &handle_nand_check_bad_blocks_command,
1745 .mode = COMMAND_EXEC,
1746 .usage = "<bank> [<offset> <length>]",
1747 .help = "check NAND flash device <num> for bad blocks",
1748 },
1749 {
1750 .name = "erase",
1751 .handler = &handle_nand_erase_command,
1752 .mode = COMMAND_EXEC,
1753 .usage = "<bank> [<offset> <length>]",
1754 .help = "erase blocks on NAND flash device",
1755 },
1756 {
1757 .name = "dump",
1758 .handler = &handle_nand_dump_command,
1759 .mode = COMMAND_EXEC,
1760 .usage = "<bank> <filename> <offset> <length> "
1761 "[oob_raw | oob_only]",
1762 .help = "dump from NAND flash device",
1763 },
1764 {
1765 .name = "verify",
1766 .handler = &handle_nand_verify_command,
1767 .mode = COMMAND_EXEC,
1768 .usage = "<bank> <filename> <offset> "
1769 "[oob_raw | oob_only | oob_softecc | oob_softecc_kw]",
1770 .help = "verify NAND flash device",
1771 },
1772 {
1773 .name = "write",
1774 .handler = &handle_nand_write_command,
1775 .mode = COMMAND_EXEC,
1776 .usage = "<bank> <filename> <offset> "
1777 "[oob_raw | oob_only | oob_softecc | oob_softecc_kw]",
1778 .help = "write to NAND flash device",
1779 },
1780 {
1781 .name = "raw_access",
1782 .handler = &handle_nand_raw_access_command,
1783 .mode = COMMAND_EXEC,
1784 .usage = "<num> ['enable'|'disable']",
1785 .help = "raw access to NAND flash device",
1786 },
1787 COMMAND_REGISTRATION_DONE
1788 };
1789
1790 int nand_init(struct command_context *cmd_ctx)
1791 {
1792 if (!nand_devices)
1793 return ERROR_OK;
1794 struct command *parent = command_find_in_context(cmd_ctx, "nand");
1795 return register_commands(cmd_ctx, parent, nand_exec_command_handlers);
1796 }
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