Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
split jim_jtag_command into multiple handlers
[openocd.git] / src / flash / nand.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "nand.h"
28 #include "common.h"
29 #include "time_support.h"
30 #include "fileio.h"
31
32 static int nand_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
33 //static int nand_read_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size);
34
35 static int nand_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
36
37 /* NAND flash controller
38 */
39 extern struct nand_flash_controller davinci_nand_controller;
40 extern struct nand_flash_controller lpc3180_nand_controller;
41 extern struct nand_flash_controller orion_nand_controller;
42 extern struct nand_flash_controller s3c2410_nand_controller;
43 extern struct nand_flash_controller s3c2412_nand_controller;
44 extern struct nand_flash_controller s3c2440_nand_controller;
45 extern struct nand_flash_controller s3c2443_nand_controller;
46 extern struct nand_flash_controller imx31_nand_flash_controller;
47
48 /* extern struct nand_flash_controller boundary_scan_nand_controller; */
49
50 static struct nand_flash_controller *nand_flash_controllers[] =
51 {
52 &davinci_nand_controller,
53 &lpc3180_nand_controller,
54 &orion_nand_controller,
55 &s3c2410_nand_controller,
56 &s3c2412_nand_controller,
57 &s3c2440_nand_controller,
58 &s3c2443_nand_controller,
59 &imx31_nand_flash_controller,
60 /* &boundary_scan_nand_controller, */
61 NULL
62 };
63
64 /* configured NAND devices and NAND Flash command handler */
65 static struct nand_device *nand_devices = NULL;
66
67 /* Chip ID list
68 *
69 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
70 * options
71 *
72 * Pagesize; 0, 256, 512
73 * 0 get this information from the extended chip ID
74 * 256 256 Byte page size
75 * 512 512 Byte page size
76 */
77 static struct nand_info nand_flash_ids[] =
78 {
79 /* start "museum" IDs */
80 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
81 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
82 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
83 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
84 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
85 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
86 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
87 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
88 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
89 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
90
91 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
92 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
93 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
94 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
95 /* end "museum" IDs */
96
97 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
98 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
99 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
100 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
101
102 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
103 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
104 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
105 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
106
107 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
108 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
109 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
110 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
111
112 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
113 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
114 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
115 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
116 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
117 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
118 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
119
120 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
121
122 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
123 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
124 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
125 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
126
127 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
128 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
129 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
130 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
131
132 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
133 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
134 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
135 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
136
137 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
138 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
139 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
140 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
141
142 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
143 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
144 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
145 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
146
147 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
148 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
149 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
150 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
151
152 {NULL, 0, 0, 0, 0, 0 }
153 };
154
155 /* Manufacturer ID list
156 */
157 static struct nand_manufacturer nand_manuf_ids[] =
158 {
159 {0x0, "unknown"},
160 {NAND_MFR_TOSHIBA, "Toshiba"},
161 {NAND_MFR_SAMSUNG, "Samsung"},
162 {NAND_MFR_FUJITSU, "Fujitsu"},
163 {NAND_MFR_NATIONAL, "National"},
164 {NAND_MFR_RENESAS, "Renesas"},
165 {NAND_MFR_STMICRO, "ST Micro"},
166 {NAND_MFR_HYNIX, "Hynix"},
167 {NAND_MFR_MICRON, "Micron"},
168 {0x0, NULL},
169 };
170
171 /*
172 * Define default oob placement schemes for large and small page devices
173 */
174
175 #if 0
176 static struct nand_ecclayout nand_oob_8 = {
177 .eccbytes = 3,
178 .eccpos = {0, 1, 2},
179 .oobfree = {
180 {.offset = 3,
181 .length = 2},
182 {.offset = 6,
183 .length = 2}}
184 };
185 #endif
186
187 static struct nand_ecclayout nand_oob_16 = {
188 .eccbytes = 6,
189 .eccpos = {0, 1, 2, 3, 6, 7},
190 .oobfree = {
191 {.offset = 8,
192 . length = 8}}
193 };
194
195 static struct nand_ecclayout nand_oob_64 = {
196 .eccbytes = 24,
197 .eccpos = {
198 40, 41, 42, 43, 44, 45, 46, 47,
199 48, 49, 50, 51, 52, 53, 54, 55,
200 56, 57, 58, 59, 60, 61, 62, 63},
201 .oobfree = {
202 {.offset = 2,
203 .length = 38}}
204 };
205
206 COMMAND_HANDLER(handle_nand_list_drivers)
207 {
208 command_print(CMD_CTX, "Available NAND flash controller drivers:");
209 for (unsigned i = 0; nand_flash_controllers[i]; i++)
210 command_print(CMD_CTX, " %s", nand_flash_controllers[i]->name);
211 return ERROR_OK;
212 }
213
214 static COMMAND_HELPER(create_nand_device, const char *bank_name,
215 struct nand_flash_controller *controller)
216 {
217 if (NULL != controller->commands)
218 {
219 int retval = register_commands(CMD_CTX, NULL,
220 controller->commands);
221 if (ERROR_OK != retval)
222 return retval;
223 }
224 struct nand_device *c = malloc(sizeof(struct nand_device));
225
226 c->name = strdup(bank_name);
227 c->controller = controller;
228 c->controller_priv = NULL;
229 c->manufacturer = NULL;
230 c->device = NULL;
231 c->bus_width = 0;
232 c->address_cycles = 0;
233 c->page_size = 0;
234 c->use_raw = 0;
235 c->next = NULL;
236
237 int retval = CALL_COMMAND_HANDLER(controller->nand_device_command, c);
238 if (ERROR_OK != retval)
239 {
240 LOG_ERROR("'%s' driver rejected nand flash", controller->name);
241 free(c);
242 return ERROR_OK;
243 }
244
245 if (nand_devices) {
246 struct nand_device *p = nand_devices;
247 while (p && p->next) p = p->next;
248 p->next = c;
249 } else
250 nand_devices = c;
251
252 return ERROR_OK;
253 }
254
255 COMMAND_HANDLER(handle_nand_device_command)
256 {
257 if (CMD_ARGC < 1)
258 {
259 LOG_ERROR("incomplete nand device configuration");
260 return ERROR_FLASH_BANK_INVALID;
261 }
262
263 // save name and increment (for compatibility) with drivers
264 const char *bank_name = *CMD_ARGV++;
265 CMD_ARGC--;
266
267 const char *driver_name = CMD_ARGV[0];
268 for (unsigned i = 0; nand_flash_controllers[i]; i++)
269 {
270 struct nand_flash_controller *controller = nand_flash_controllers[i];
271 if (strcmp(driver_name, controller->name) != 0)
272 continue;
273
274 return CALL_COMMAND_HANDLER(create_nand_device,
275 bank_name, controller);
276 }
277
278 LOG_ERROR("No valid NAND flash driver found (%s)", driver_name);
279 return CALL_COMMAND_HANDLER(handle_nand_list_drivers);
280 }
281
282 static const struct command_registration nand_config_command_handlers[] = {
283 {
284 .name = "device",
285 .handler = &handle_nand_device_command,
286 .mode = COMMAND_CONFIG,
287 .help = "defines a new NAND bank",
288 },
289 {
290 .name = "drivers",
291 .handler = &handle_nand_list_drivers,
292 .mode = COMMAND_ANY,
293 .help = "lists available NAND drivers",
294 },
295 COMMAND_REGISTRATION_DONE
296 };
297 static const struct command_registration nand_command_handlers[] = {
298 {
299 .name = "nand",
300 .mode = COMMAND_ANY,
301 .help = "NAND flash command group",
302 .chain = nand_config_command_handlers,
303 },
304 COMMAND_REGISTRATION_DONE
305 };
306
307 int nand_register_commands(struct command_context *cmd_ctx)
308 {
309 return register_commands(cmd_ctx, NULL, nand_command_handlers);
310 }
311
312 struct nand_device *get_nand_device_by_name(const char *name)
313 {
314 unsigned requested = get_flash_name_index(name);
315 unsigned found = 0;
316
317 struct nand_device *nand;
318 for (nand = nand_devices; NULL != nand; nand = nand->next)
319 {
320 if (strcmp(nand->name, name) == 0)
321 return nand;
322 if (!flash_driver_name_matches(nand->controller->name, name))
323 continue;
324 if (++found < requested)
325 continue;
326 return nand;
327 }
328 return NULL;
329 }
330
331 struct nand_device *get_nand_device_by_num(int num)
332 {
333 struct nand_device *p;
334 int i = 0;
335
336 for (p = nand_devices; p; p = p->next)
337 {
338 if (i++ == num)
339 {
340 return p;
341 }
342 }
343
344 return NULL;
345 }
346
347 COMMAND_HELPER(nand_command_get_device, unsigned name_index,
348 struct nand_device **nand)
349 {
350 const char *str = CMD_ARGV[name_index];
351 *nand = get_nand_device_by_name(str);
352 if (*nand)
353 return ERROR_OK;
354
355 unsigned num;
356 COMMAND_PARSE_NUMBER(uint, str, num);
357 *nand = get_nand_device_by_num(num);
358 if (!*nand) {
359 command_print(CMD_CTX, "NAND flash device '%s' not found", str);
360 return ERROR_INVALID_ARGUMENTS;
361 }
362 return ERROR_OK;
363 }
364
365 static int nand_build_bbt(struct nand_device *nand, int first, int last)
366 {
367 uint32_t page = 0x0;
368 int i;
369 uint8_t oob[6];
370
371 if ((first < 0) || (first >= nand->num_blocks))
372 first = 0;
373
374 if ((last >= nand->num_blocks) || (last == -1))
375 last = nand->num_blocks - 1;
376
377 for (i = first; i < last; i++)
378 {
379 nand_read_page(nand, page, NULL, 0, oob, 6);
380
381 if (((nand->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
382 || (((nand->page_size == 512) && (oob[5] != 0xff)) ||
383 ((nand->page_size == 2048) && (oob[0] != 0xff))))
384 {
385 LOG_WARNING("bad block: %i", i);
386 nand->blocks[i].is_bad = 1;
387 }
388 else
389 {
390 nand->blocks[i].is_bad = 0;
391 }
392
393 page += (nand->erase_size / nand->page_size);
394 }
395
396 return ERROR_OK;
397 }
398
399 int nand_read_status(struct nand_device *nand, uint8_t *status)
400 {
401 if (!nand->device)
402 return ERROR_NAND_DEVICE_NOT_PROBED;
403
404 /* Send read status command */
405 nand->controller->command(nand, NAND_CMD_STATUS);
406
407 alive_sleep(1);
408
409 /* read status */
410 if (nand->device->options & NAND_BUSWIDTH_16)
411 {
412 uint16_t data;
413 nand->controller->read_data(nand, &data);
414 *status = data & 0xff;
415 }
416 else
417 {
418 nand->controller->read_data(nand, status);
419 }
420
421 return ERROR_OK;
422 }
423
424 static int nand_poll_ready(struct nand_device *nand, int timeout)
425 {
426 uint8_t status;
427
428 nand->controller->command(nand, NAND_CMD_STATUS);
429 do {
430 if (nand->device->options & NAND_BUSWIDTH_16) {
431 uint16_t data;
432 nand->controller->read_data(nand, &data);
433 status = data & 0xff;
434 } else {
435 nand->controller->read_data(nand, &status);
436 }
437 if (status & NAND_STATUS_READY)
438 break;
439 alive_sleep(1);
440 } while (timeout--);
441
442 return (status & NAND_STATUS_READY) != 0;
443 }
444
445 int nand_probe(struct nand_device *nand)
446 {
447 uint8_t manufacturer_id, device_id;
448 uint8_t id_buff[6];
449 int retval;
450 int i;
451
452 /* clear device data */
453 nand->device = NULL;
454 nand->manufacturer = NULL;
455
456 /* clear device parameters */
457 nand->bus_width = 0;
458 nand->address_cycles = 0;
459 nand->page_size = 0;
460 nand->erase_size = 0;
461
462 /* initialize controller (device parameters are zero, use controller default) */
463 if ((retval = nand->controller->init(nand) != ERROR_OK))
464 {
465 switch (retval)
466 {
467 case ERROR_NAND_OPERATION_FAILED:
468 LOG_DEBUG("controller initialization failed");
469 return ERROR_NAND_OPERATION_FAILED;
470 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
471 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
472 return ERROR_NAND_OPERATION_FAILED;
473 default:
474 LOG_ERROR("BUG: unknown controller initialization failure");
475 return ERROR_NAND_OPERATION_FAILED;
476 }
477 }
478
479 nand->controller->command(nand, NAND_CMD_RESET);
480 nand->controller->reset(nand);
481
482 nand->controller->command(nand, NAND_CMD_READID);
483 nand->controller->address(nand, 0x0);
484
485 if (nand->bus_width == 8)
486 {
487 nand->controller->read_data(nand, &manufacturer_id);
488 nand->controller->read_data(nand, &device_id);
489 }
490 else
491 {
492 uint16_t data_buf;
493 nand->controller->read_data(nand, &data_buf);
494 manufacturer_id = data_buf & 0xff;
495 nand->controller->read_data(nand, &data_buf);
496 device_id = data_buf & 0xff;
497 }
498
499 for (i = 0; nand_flash_ids[i].name; i++)
500 {
501 if (nand_flash_ids[i].id == device_id)
502 {
503 nand->device = &nand_flash_ids[i];
504 break;
505 }
506 }
507
508 for (i = 0; nand_manuf_ids[i].name; i++)
509 {
510 if (nand_manuf_ids[i].id == manufacturer_id)
511 {
512 nand->manufacturer = &nand_manuf_ids[i];
513 break;
514 }
515 }
516
517 if (!nand->manufacturer)
518 {
519 nand->manufacturer = &nand_manuf_ids[0];
520 nand->manufacturer->id = manufacturer_id;
521 }
522
523 if (!nand->device)
524 {
525 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
526 manufacturer_id, device_id);
527 return ERROR_NAND_OPERATION_FAILED;
528 }
529
530 LOG_DEBUG("found %s (%s)", nand->device->name, nand->manufacturer->name);
531
532 /* initialize device parameters */
533
534 /* bus width */
535 if (nand->device->options & NAND_BUSWIDTH_16)
536 nand->bus_width = 16;
537 else
538 nand->bus_width = 8;
539
540 /* Do we need extended device probe information? */
541 if (nand->device->page_size == 0 ||
542 nand->device->erase_size == 0)
543 {
544 if (nand->bus_width == 8)
545 {
546 nand->controller->read_data(nand, id_buff + 3);
547 nand->controller->read_data(nand, id_buff + 4);
548 nand->controller->read_data(nand, id_buff + 5);
549 }
550 else
551 {
552 uint16_t data_buf;
553
554 nand->controller->read_data(nand, &data_buf);
555 id_buff[3] = data_buf;
556
557 nand->controller->read_data(nand, &data_buf);
558 id_buff[4] = data_buf;
559
560 nand->controller->read_data(nand, &data_buf);
561 id_buff[5] = data_buf >> 8;
562 }
563 }
564
565 /* page size */
566 if (nand->device->page_size == 0)
567 {
568 nand->page_size = 1 << (10 + (id_buff[4] & 3));
569 }
570 else if (nand->device->page_size == 256)
571 {
572 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
573 return ERROR_NAND_OPERATION_FAILED;
574 }
575 else
576 {
577 nand->page_size = nand->device->page_size;
578 }
579
580 /* number of address cycles */
581 if (nand->page_size <= 512)
582 {
583 /* small page devices */
584 if (nand->device->chip_size <= 32)
585 nand->address_cycles = 3;
586 else if (nand->device->chip_size <= 8*1024)
587 nand->address_cycles = 4;
588 else
589 {
590 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
591 nand->address_cycles = 5;
592 }
593 }
594 else
595 {
596 /* large page devices */
597 if (nand->device->chip_size <= 128)
598 nand->address_cycles = 4;
599 else if (nand->device->chip_size <= 32*1024)
600 nand->address_cycles = 5;
601 else
602 {
603 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
604 nand->address_cycles = 6;
605 }
606 }
607
608 /* erase size */
609 if (nand->device->erase_size == 0)
610 {
611 switch ((id_buff[4] >> 4) & 3) {
612 case 0:
613 nand->erase_size = 64 << 10;
614 break;
615 case 1:
616 nand->erase_size = 128 << 10;
617 break;
618 case 2:
619 nand->erase_size = 256 << 10;
620 break;
621 case 3:
622 nand->erase_size =512 << 10;
623 break;
624 }
625 }
626 else
627 {
628 nand->erase_size = nand->device->erase_size;
629 }
630
631 /* initialize controller, but leave parameters at the controllers default */
632 if ((retval = nand->controller->init(nand) != ERROR_OK))
633 {
634 switch (retval)
635 {
636 case ERROR_NAND_OPERATION_FAILED:
637 LOG_DEBUG("controller initialization failed");
638 return ERROR_NAND_OPERATION_FAILED;
639 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
640 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
641 nand->bus_width, nand->address_cycles, nand->page_size);
642 return ERROR_NAND_OPERATION_FAILED;
643 default:
644 LOG_ERROR("BUG: unknown controller initialization failure");
645 return ERROR_NAND_OPERATION_FAILED;
646 }
647 }
648
649 nand->num_blocks = (nand->device->chip_size * 1024) / (nand->erase_size / 1024);
650 nand->blocks = malloc(sizeof(struct nand_block) * nand->num_blocks);
651
652 for (i = 0; i < nand->num_blocks; i++)
653 {
654 nand->blocks[i].size = nand->erase_size;
655 nand->blocks[i].offset = i * nand->erase_size;
656 nand->blocks[i].is_erased = -1;
657 nand->blocks[i].is_bad = -1;
658 }
659
660 return ERROR_OK;
661 }
662
663 static int nand_erase(struct nand_device *nand, int first_block, int last_block)
664 {
665 int i;
666 uint32_t page;
667 uint8_t status;
668 int retval;
669
670 if (!nand->device)
671 return ERROR_NAND_DEVICE_NOT_PROBED;
672
673 if ((first_block < 0) || (last_block > nand->num_blocks))
674 return ERROR_INVALID_ARGUMENTS;
675
676 /* make sure we know if a block is bad before erasing it */
677 for (i = first_block; i <= last_block; i++)
678 {
679 if (nand->blocks[i].is_bad == -1)
680 {
681 nand_build_bbt(nand, i, last_block);
682 break;
683 }
684 }
685
686 for (i = first_block; i <= last_block; i++)
687 {
688 /* Send erase setup command */
689 nand->controller->command(nand, NAND_CMD_ERASE1);
690
691 page = i * (nand->erase_size / nand->page_size);
692
693 /* Send page address */
694 if (nand->page_size <= 512)
695 {
696 /* row */
697 nand->controller->address(nand, page & 0xff);
698 nand->controller->address(nand, (page >> 8) & 0xff);
699
700 /* 3rd cycle only on devices with more than 32 MiB */
701 if (nand->address_cycles >= 4)
702 nand->controller->address(nand, (page >> 16) & 0xff);
703
704 /* 4th cycle only on devices with more than 8 GiB */
705 if (nand->address_cycles >= 5)
706 nand->controller->address(nand, (page >> 24) & 0xff);
707 }
708 else
709 {
710 /* row */
711 nand->controller->address(nand, page & 0xff);
712 nand->controller->address(nand, (page >> 8) & 0xff);
713
714 /* 3rd cycle only on devices with more than 128 MiB */
715 if (nand->address_cycles >= 5)
716 nand->controller->address(nand, (page >> 16) & 0xff);
717 }
718
719 /* Send erase confirm command */
720 nand->controller->command(nand, NAND_CMD_ERASE2);
721
722 retval = nand->controller->nand_ready ?
723 nand->controller->nand_ready(nand, 1000) :
724 nand_poll_ready(nand, 1000);
725 if (!retval) {
726 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
727 return ERROR_NAND_OPERATION_TIMEOUT;
728 }
729
730 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
731 {
732 LOG_ERROR("couldn't read status");
733 return ERROR_NAND_OPERATION_FAILED;
734 }
735
736 if (status & 0x1)
737 {
738 LOG_ERROR("didn't erase %sblock %d; status: 0x%2.2x",
739 (nand->blocks[i].is_bad == 1)
740 ? "bad " : "",
741 i, status);
742 /* continue; other blocks might still be erasable */
743 }
744
745 nand->blocks[i].is_erased = 1;
746 }
747
748 return ERROR_OK;
749 }
750
751 #if 0
752 static int nand_read_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size)
753 {
754 uint8_t *page;
755
756 if (!nand->device)
757 return ERROR_NAND_DEVICE_NOT_PROBED;
758
759 if (address % nand->page_size)
760 {
761 LOG_ERROR("reads need to be page aligned");
762 return ERROR_NAND_OPERATION_FAILED;
763 }
764
765 page = malloc(nand->page_size);
766
767 while (data_size > 0)
768 {
769 uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
770 uint32_t page_address;
771
772
773 page_address = address / nand->page_size;
774
775 nand_read_page(nand, page_address, page, nand->page_size, NULL, 0);
776
777 memcpy(data, page, thisrun_size);
778
779 address += thisrun_size;
780 data += thisrun_size;
781 data_size -= thisrun_size;
782 }
783
784 free(page);
785
786 return ERROR_OK;
787 }
788
789 static int nand_write_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size)
790 {
791 uint8_t *page;
792
793 if (!nand->device)
794 return ERROR_NAND_DEVICE_NOT_PROBED;
795
796 if (address % nand->page_size)
797 {
798 LOG_ERROR("writes need to be page aligned");
799 return ERROR_NAND_OPERATION_FAILED;
800 }
801
802 page = malloc(nand->page_size);
803
804 while (data_size > 0)
805 {
806 uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
807 uint32_t page_address;
808
809 memset(page, 0xff, nand->page_size);
810 memcpy(page, data, thisrun_size);
811
812 page_address = address / nand->page_size;
813
814 nand_write_page(nand, page_address, page, nand->page_size, NULL, 0);
815
816 address += thisrun_size;
817 data += thisrun_size;
818 data_size -= thisrun_size;
819 }
820
821 free(page);
822
823 return ERROR_OK;
824 }
825 #endif
826
827 int nand_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
828 {
829 uint32_t block;
830
831 if (!nand->device)
832 return ERROR_NAND_DEVICE_NOT_PROBED;
833
834 block = page / (nand->erase_size / nand->page_size);
835 if (nand->blocks[block].is_erased == 1)
836 nand->blocks[block].is_erased = 0;
837
838 if (nand->use_raw || nand->controller->write_page == NULL)
839 return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
840 else
841 return nand->controller->write_page(nand, page, data, data_size, oob, oob_size);
842 }
843
844 static int nand_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
845 {
846 if (!nand->device)
847 return ERROR_NAND_DEVICE_NOT_PROBED;
848
849 if (nand->use_raw || nand->controller->read_page == NULL)
850 return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
851 else
852 return nand->controller->read_page(nand, page, data, data_size, oob, oob_size);
853 }
854
855 int nand_read_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
856 {
857 uint32_t i;
858
859 if (!nand->device)
860 return ERROR_NAND_DEVICE_NOT_PROBED;
861
862 if (nand->page_size <= 512)
863 {
864 /* small page device */
865 if (data)
866 nand->controller->command(nand, NAND_CMD_READ0);
867 else
868 nand->controller->command(nand, NAND_CMD_READOOB);
869
870 /* column (always 0, we start at the beginning of a page/OOB area) */
871 nand->controller->address(nand, 0x0);
872
873 /* row */
874 nand->controller->address(nand, page & 0xff);
875 nand->controller->address(nand, (page >> 8) & 0xff);
876
877 /* 4th cycle only on devices with more than 32 MiB */
878 if (nand->address_cycles >= 4)
879 nand->controller->address(nand, (page >> 16) & 0xff);
880
881 /* 5th cycle only on devices with more than 8 GiB */
882 if (nand->address_cycles >= 5)
883 nand->controller->address(nand, (page >> 24) & 0xff);
884 }
885 else
886 {
887 /* large page device */
888 nand->controller->command(nand, NAND_CMD_READ0);
889
890 /* column (0 when we start at the beginning of a page,
891 * or 2048 for the beginning of OOB area)
892 */
893 nand->controller->address(nand, 0x0);
894 if (data)
895 nand->controller->address(nand, 0x0);
896 else
897 nand->controller->address(nand, 0x8);
898
899 /* row */
900 nand->controller->address(nand, page & 0xff);
901 nand->controller->address(nand, (page >> 8) & 0xff);
902
903 /* 5th cycle only on devices with more than 128 MiB */
904 if (nand->address_cycles >= 5)
905 nand->controller->address(nand, (page >> 16) & 0xff);
906
907 /* large page devices need a start command */
908 nand->controller->command(nand, NAND_CMD_READSTART);
909 }
910
911 if (nand->controller->nand_ready) {
912 if (!nand->controller->nand_ready(nand, 100))
913 return ERROR_NAND_OPERATION_TIMEOUT;
914 } else {
915 alive_sleep(1);
916 }
917
918 if (data)
919 {
920 if (nand->controller->read_block_data != NULL)
921 (nand->controller->read_block_data)(nand, data, data_size);
922 else
923 {
924 for (i = 0; i < data_size;)
925 {
926 if (nand->device->options & NAND_BUSWIDTH_16)
927 {
928 nand->controller->read_data(nand, data);
929 data += 2;
930 i += 2;
931 }
932 else
933 {
934 nand->controller->read_data(nand, data);
935 data += 1;
936 i += 1;
937 }
938 }
939 }
940 }
941
942 if (oob)
943 {
944 if (nand->controller->read_block_data != NULL)
945 (nand->controller->read_block_data)(nand, oob, oob_size);
946 else
947 {
948 for (i = 0; i < oob_size;)
949 {
950 if (nand->device->options & NAND_BUSWIDTH_16)
951 {
952 nand->controller->read_data(nand, oob);
953 oob += 2;
954 i += 2;
955 }
956 else
957 {
958 nand->controller->read_data(nand, oob);
959 oob += 1;
960 i += 1;
961 }
962 }
963 }
964 }
965
966 return ERROR_OK;
967 }
968
969 int nand_write_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
970 {
971 uint32_t i;
972 int retval;
973 uint8_t status;
974
975 if (!nand->device)
976 return ERROR_NAND_DEVICE_NOT_PROBED;
977
978 nand->controller->command(nand, NAND_CMD_SEQIN);
979
980 if (nand->page_size <= 512)
981 {
982 /* column (always 0, we start at the beginning of a page/OOB area) */
983 nand->controller->address(nand, 0x0);
984
985 /* row */
986 nand->controller->address(nand, page & 0xff);
987 nand->controller->address(nand, (page >> 8) & 0xff);
988
989 /* 4th cycle only on devices with more than 32 MiB */
990 if (nand->address_cycles >= 4)
991 nand->controller->address(nand, (page >> 16) & 0xff);
992
993 /* 5th cycle only on devices with more than 8 GiB */
994 if (nand->address_cycles >= 5)
995 nand->controller->address(nand, (page >> 24) & 0xff);
996 }
997 else
998 {
999 /* column (0 when we start at the beginning of a page,
1000 * or 2048 for the beginning of OOB area)
1001 */
1002 nand->controller->address(nand, 0x0);
1003 if (data)
1004 nand->controller->address(nand, 0x0);
1005 else
1006 nand->controller->address(nand, 0x8);
1007
1008 /* row */
1009 nand->controller->address(nand, page & 0xff);
1010 nand->controller->address(nand, (page >> 8) & 0xff);
1011
1012 /* 5th cycle only on devices with more than 128 MiB */
1013 if (nand->address_cycles >= 5)
1014 nand->controller->address(nand, (page >> 16) & 0xff);
1015 }
1016
1017 if (data)
1018 {
1019 if (nand->controller->write_block_data != NULL)
1020 (nand->controller->write_block_data)(nand, data, data_size);
1021 else
1022 {
1023 for (i = 0; i < data_size;)
1024 {
1025 if (nand->device->options & NAND_BUSWIDTH_16)
1026 {
1027 uint16_t data_buf = le_to_h_u16(data);
1028 nand->controller->write_data(nand, data_buf);
1029 data += 2;
1030 i += 2;
1031 }
1032 else
1033 {
1034 nand->controller->write_data(nand, *data);
1035 data += 1;
1036 i += 1;
1037 }
1038 }
1039 }
1040 }
1041
1042 if (oob)
1043 {
1044 if (nand->controller->write_block_data != NULL)
1045 (nand->controller->write_block_data)(nand, oob, oob_size);
1046 else
1047 {
1048 for (i = 0; i < oob_size;)
1049 {
1050 if (nand->device->options & NAND_BUSWIDTH_16)
1051 {
1052 uint16_t oob_buf = le_to_h_u16(data);
1053 nand->controller->write_data(nand, oob_buf);
1054 oob += 2;
1055 i += 2;
1056 }
1057 else
1058 {
1059 nand->controller->write_data(nand, *oob);
1060 oob += 1;
1061 i += 1;
1062 }
1063 }
1064 }
1065 }
1066
1067 nand->controller->command(nand, NAND_CMD_PAGEPROG);
1068
1069 retval = nand->controller->nand_ready ?
1070 nand->controller->nand_ready(nand, 100) :
1071 nand_poll_ready(nand, 100);
1072 if (!retval)
1073 return ERROR_NAND_OPERATION_TIMEOUT;
1074
1075 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
1076 {
1077 LOG_ERROR("couldn't read status");
1078 return ERROR_NAND_OPERATION_FAILED;
1079 }
1080
1081 if (status & NAND_STATUS_FAIL)
1082 {
1083 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1084 return ERROR_NAND_OPERATION_FAILED;
1085 }
1086
1087 return ERROR_OK;
1088 }
1089
1090 COMMAND_HANDLER(handle_nand_list_command)
1091 {
1092 struct nand_device *p;
1093 int i;
1094
1095 if (!nand_devices)
1096 {
1097 command_print(CMD_CTX, "no NAND flash devices configured");
1098 return ERROR_OK;
1099 }
1100
1101 for (p = nand_devices, i = 0; p; p = p->next, i++)
1102 {
1103 if (p->device)
1104 command_print(CMD_CTX, "#%i: %s (%s) "
1105 "pagesize: %i, buswidth: %i,\n\t"
1106 "blocksize: %i, blocks: %i",
1107 i, p->device->name, p->manufacturer->name,
1108 p->page_size, p->bus_width,
1109 p->erase_size, p->num_blocks);
1110 else
1111 command_print(CMD_CTX, "#%i: not probed", i);
1112 }
1113
1114 return ERROR_OK;
1115 }
1116
1117 COMMAND_HANDLER(handle_nand_info_command)
1118 {
1119 int i = 0;
1120 int j = 0;
1121 int first = -1;
1122 int last = -1;
1123
1124 switch (CMD_ARGC) {
1125 default:
1126 return ERROR_COMMAND_SYNTAX_ERROR;
1127 case 1:
1128 first = 0;
1129 last = INT32_MAX;
1130 break;
1131 case 2:
1132 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], i);
1133 first = last = i;
1134 i = 0;
1135 break;
1136 case 3:
1137 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], first);
1138 COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], last);
1139 break;
1140 }
1141
1142 struct nand_device *p;
1143 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1144 if (ERROR_OK != retval)
1145 return retval;
1146
1147 if (NULL == p->device)
1148 {
1149 command_print(CMD_CTX, "#%s: not probed", CMD_ARGV[0]);
1150 return ERROR_OK;
1151 }
1152
1153 if (first >= p->num_blocks)
1154 first = p->num_blocks - 1;
1155
1156 if (last >= p->num_blocks)
1157 last = p->num_blocks - 1;
1158
1159 command_print(CMD_CTX, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1160 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1161
1162 for (j = first; j <= last; j++)
1163 {
1164 char *erase_state, *bad_state;
1165
1166 if (p->blocks[j].is_erased == 0)
1167 erase_state = "not erased";
1168 else if (p->blocks[j].is_erased == 1)
1169 erase_state = "erased";
1170 else
1171 erase_state = "erase state unknown";
1172
1173 if (p->blocks[j].is_bad == 0)
1174 bad_state = "";
1175 else if (p->blocks[j].is_bad == 1)
1176 bad_state = " (marked bad)";
1177 else
1178 bad_state = " (block condition unknown)";
1179
1180 command_print(CMD_CTX,
1181 "\t#%i: 0x%8.8" PRIx32 " (%" PRId32 "kB) %s%s",
1182 j,
1183 p->blocks[j].offset,
1184 p->blocks[j].size / 1024,
1185 erase_state,
1186 bad_state);
1187 }
1188
1189 return ERROR_OK;
1190 }
1191
1192 COMMAND_HANDLER(handle_nand_probe_command)
1193 {
1194 if (CMD_ARGC != 1)
1195 {
1196 return ERROR_COMMAND_SYNTAX_ERROR;
1197 }
1198
1199 struct nand_device *p;
1200 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1201 if (ERROR_OK != retval)
1202 return retval;
1203
1204 if ((retval = nand_probe(p)) == ERROR_OK)
1205 {
1206 command_print(CMD_CTX, "NAND flash device '%s' found", p->device->name);
1207 }
1208 else if (retval == ERROR_NAND_OPERATION_FAILED)
1209 {
1210 command_print(CMD_CTX, "probing failed for NAND flash device");
1211 }
1212 else
1213 {
1214 command_print(CMD_CTX, "unknown error when probing NAND flash device");
1215 }
1216
1217 return ERROR_OK;
1218 }
1219
1220 COMMAND_HANDLER(handle_nand_erase_command)
1221 {
1222 if (CMD_ARGC != 1 && CMD_ARGC != 3)
1223 {
1224 return ERROR_COMMAND_SYNTAX_ERROR;
1225
1226 }
1227
1228 struct nand_device *p;
1229 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1230 if (ERROR_OK != retval)
1231 return retval;
1232
1233 unsigned long offset;
1234 unsigned long length;
1235
1236 /* erase specified part of the chip; or else everything */
1237 if (CMD_ARGC == 3) {
1238 unsigned long size = p->erase_size * p->num_blocks;
1239
1240 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], offset);
1241 if ((offset % p->erase_size) != 0 || offset >= size)
1242 return ERROR_INVALID_ARGUMENTS;
1243
1244 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], length);
1245 if ((length == 0) || (length % p->erase_size) != 0
1246 || (length + offset) > size)
1247 return ERROR_INVALID_ARGUMENTS;
1248
1249 offset /= p->erase_size;
1250 length /= p->erase_size;
1251 } else {
1252 offset = 0;
1253 length = p->num_blocks;
1254 }
1255
1256 retval = nand_erase(p, offset, offset + length - 1);
1257 if (retval == ERROR_OK)
1258 {
1259 command_print(CMD_CTX, "erased blocks %lu to %lu "
1260 "on NAND flash device #%s '%s'",
1261 offset, offset + length,
1262 CMD_ARGV[0], p->device->name);
1263 }
1264 else if (retval == ERROR_NAND_OPERATION_FAILED)
1265 {
1266 command_print(CMD_CTX, "erase failed");
1267 }
1268 else
1269 {
1270 command_print(CMD_CTX, "unknown error when erasing NAND flash device");
1271 }
1272
1273 return ERROR_OK;
1274 }
1275
1276 COMMAND_HANDLER(handle_nand_check_bad_blocks_command)
1277 {
1278 int first = -1;
1279 int last = -1;
1280
1281 if ((CMD_ARGC < 1) || (CMD_ARGC > 3) || (CMD_ARGC == 2))
1282 {
1283 return ERROR_COMMAND_SYNTAX_ERROR;
1284
1285 }
1286
1287 struct nand_device *p;
1288 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1289 if (ERROR_OK != retval)
1290 return retval;
1291
1292 if (CMD_ARGC == 3)
1293 {
1294 unsigned long offset;
1295 unsigned long length;
1296
1297 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], offset);
1298 if (offset % p->erase_size)
1299 return ERROR_INVALID_ARGUMENTS;
1300 offset /= p->erase_size;
1301
1302 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], length);
1303 if (length % p->erase_size)
1304 return ERROR_INVALID_ARGUMENTS;
1305
1306 length -= 1;
1307 length /= p->erase_size;
1308
1309 first = offset;
1310 last = offset + length;
1311 }
1312
1313 retval = nand_build_bbt(p, first, last);
1314 if (retval == ERROR_OK)
1315 {
1316 command_print(CMD_CTX, "checked NAND flash device for bad blocks, "
1317 "use \"nand info\" command to list blocks");
1318 }
1319 else if (retval == ERROR_NAND_OPERATION_FAILED)
1320 {
1321 command_print(CMD_CTX, "error when checking for bad blocks on "
1322 "NAND flash device");
1323 }
1324 else
1325 {
1326 command_print(CMD_CTX, "unknown error when checking for bad "
1327 "blocks on NAND flash device");
1328 }
1329
1330 return ERROR_OK;
1331 }
1332
1333 struct nand_fileio_state {
1334 uint32_t address;
1335 uint32_t size;
1336
1337 uint8_t *page;
1338 uint32_t page_size;
1339
1340 enum oob_formats oob_format;
1341 uint8_t *oob;
1342 uint32_t oob_size;
1343
1344 const int *eccpos;
1345
1346 bool file_opened;
1347 struct fileio fileio;
1348
1349 struct duration bench;
1350 };
1351
1352 static void nand_fileio_init(struct nand_fileio_state *state)
1353 {
1354 memset(state, 0, sizeof(*state));
1355 state->oob_format = NAND_OOB_NONE;
1356 }
1357
1358 static int nand_fileio_start(struct command_context *cmd_ctx,
1359 struct nand_device *nand, const char *filename, int filemode,
1360 struct nand_fileio_state *state)
1361 {
1362 if (state->address % nand->page_size)
1363 {
1364 command_print(cmd_ctx, "only page-aligned addresses are supported");
1365 return ERROR_COMMAND_SYNTAX_ERROR;
1366 }
1367
1368 duration_start(&state->bench);
1369
1370 if (NULL != filename)
1371 {
1372 int retval = fileio_open(&state->fileio, filename, filemode, FILEIO_BINARY);
1373 if (ERROR_OK != retval)
1374 {
1375 const char *msg = (FILEIO_READ == filemode) ? "read" : "write";
1376 command_print(cmd_ctx, "failed to open '%s' for %s access",
1377 filename, msg);
1378 return retval;
1379 }
1380 state->file_opened = true;
1381 }
1382
1383 if (!(state->oob_format & NAND_OOB_ONLY))
1384 {
1385 state->page_size = nand->page_size;
1386 state->page = malloc(nand->page_size);
1387 }
1388
1389 if (state->oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC | NAND_OOB_SW_ECC_KW))
1390 {
1391 if (nand->page_size == 512)
1392 {
1393 state->oob_size = 16;
1394 state->eccpos = nand_oob_16.eccpos;
1395 }
1396 else if (nand->page_size == 2048)
1397 {
1398 state->oob_size = 64;
1399 state->eccpos = nand_oob_64.eccpos;
1400 }
1401 state->oob = malloc(state->oob_size);
1402 }
1403
1404 return ERROR_OK;
1405 }
1406 static int nand_fileio_cleanup(struct nand_fileio_state *state)
1407 {
1408 if (state->file_opened)
1409 fileio_close(&state->fileio);
1410
1411 if (state->oob)
1412 {
1413 free(state->oob);
1414 state->oob = NULL;
1415 }
1416 if (state->page)
1417 {
1418 free(state->page);
1419 state->page = NULL;
1420 }
1421 return ERROR_OK;
1422 }
1423 static int nand_fileio_finish(struct nand_fileio_state *state)
1424 {
1425 nand_fileio_cleanup(state);
1426 return duration_measure(&state->bench);
1427 }
1428
1429 static COMMAND_HELPER(nand_fileio_parse_args, struct nand_fileio_state *state,
1430 struct nand_device **dev, enum fileio_access filemode,
1431 bool need_size, bool sw_ecc)
1432 {
1433 nand_fileio_init(state);
1434
1435 unsigned minargs = need_size ? 4 : 3;
1436 if (CMD_ARGC < minargs)
1437 return ERROR_COMMAND_SYNTAX_ERROR;
1438
1439 struct nand_device *nand;
1440 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
1441 if (ERROR_OK != retval)
1442 return retval;
1443
1444 if (NULL == nand->device)
1445 {
1446 command_print(CMD_CTX, "#%s: not probed", CMD_ARGV[0]);
1447 return ERROR_OK;
1448 }
1449
1450 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], state->address);
1451 if (need_size)
1452 {
1453 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], state->size);
1454 if (state->size % nand->page_size)
1455 {
1456 command_print(CMD_CTX, "only page-aligned sizes are supported");
1457 return ERROR_COMMAND_SYNTAX_ERROR;
1458 }
1459 }
1460
1461 if (CMD_ARGC > minargs)
1462 {
1463 for (unsigned i = minargs; i < CMD_ARGC; i++)
1464 {
1465 if (!strcmp(CMD_ARGV[i], "oob_raw"))
1466 state->oob_format |= NAND_OOB_RAW;
1467 else if (!strcmp(CMD_ARGV[i], "oob_only"))
1468 state->oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1469 else if (sw_ecc && !strcmp(CMD_ARGV[i], "oob_softecc"))
1470 state->oob_format |= NAND_OOB_SW_ECC;
1471 else if (sw_ecc && !strcmp(CMD_ARGV[i], "oob_softecc_kw"))
1472 state->oob_format |= NAND_OOB_SW_ECC_KW;
1473 else
1474 {
1475 command_print(CMD_CTX, "unknown option: %s", CMD_ARGV[i]);
1476 return ERROR_COMMAND_SYNTAX_ERROR;
1477 }
1478 }
1479 }
1480
1481 retval = nand_fileio_start(CMD_CTX, nand, CMD_ARGV[1], filemode, state);
1482 if (ERROR_OK != retval)
1483 return retval;
1484
1485 if (!need_size)
1486 state->size = state->fileio.size;
1487
1488 *dev = nand;
1489
1490 return ERROR_OK;
1491 }
1492
1493 /**
1494 * @returns If no error occurred, returns number of bytes consumed;
1495 * otherwise, returns a negative error code.)
1496 */
1497 static int nand_fileio_read(struct nand_device *nand,
1498 struct nand_fileio_state *s)
1499 {
1500 size_t total_read = 0;
1501 size_t one_read;
1502
1503 if (NULL != s->page)
1504 {
1505 fileio_read(&s->fileio, s->page_size, s->page, &one_read);
1506 if (one_read < s->page_size)
1507 memset(s->page + one_read, 0xff, s->page_size - one_read);
1508 total_read += one_read;
1509 }
1510
1511 if (s->oob_format & NAND_OOB_SW_ECC)
1512 {
1513 uint8_t ecc[3];
1514 memset(s->oob, 0xff, s->oob_size);
1515 for (uint32_t i = 0, j = 0; i < s->page_size; i += 256)
1516 {
1517 nand_calculate_ecc(nand, s->page + i, ecc);
1518 s->oob[s->eccpos[j++]] = ecc[0];
1519 s->oob[s->eccpos[j++]] = ecc[1];
1520 s->oob[s->eccpos[j++]] = ecc[2];
1521 }
1522 }
1523 else if (s->oob_format & NAND_OOB_SW_ECC_KW)
1524 {
1525 /*
1526 * In this case eccpos is not used as
1527 * the ECC data is always stored contigously
1528 * at the end of the OOB area. It consists
1529 * of 10 bytes per 512-byte data block.
1530 */
1531 uint8_t *ecc = s->oob + s->oob_size - s->page_size / 512 * 10;
1532 memset(s->oob, 0xff, s->oob_size);
1533 for (uint32_t i = 0; i < s->page_size; i += 512)
1534 {
1535 nand_calculate_ecc_kw(nand, s->page + i, ecc);
1536 ecc += 10;
1537 }
1538 }
1539 else if (NULL != s->oob)
1540 {
1541 fileio_read(&s->fileio, s->oob_size, s->oob, &one_read);
1542 if (one_read < s->oob_size)
1543 memset(s->oob + one_read, 0xff, s->oob_size - one_read);
1544 total_read += one_read;
1545 }
1546 return total_read;
1547 }
1548
1549 COMMAND_HANDLER(handle_nand_write_command)
1550 {
1551 struct nand_device *nand = NULL;
1552 struct nand_fileio_state s;
1553 int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
1554 &s, &nand, FILEIO_READ, false, true);
1555 if (ERROR_OK != retval)
1556 return retval;
1557
1558 uint32_t total_bytes = s.size;
1559 while (s.size > 0)
1560 {
1561 int bytes_read = nand_fileio_read(nand, &s);
1562 if (bytes_read <= 0)
1563 {
1564 command_print(CMD_CTX, "error while reading file");
1565 return nand_fileio_cleanup(&s);
1566 }
1567 s.size -= bytes_read;
1568
1569 retval = nand_write_page(nand, s.address / nand->page_size,
1570 s.page, s.page_size, s.oob, s.oob_size);
1571 if (ERROR_OK != retval)
1572 {
1573 command_print(CMD_CTX, "failed writing file %s "
1574 "to NAND flash %s at offset 0x%8.8" PRIx32,
1575 CMD_ARGV[1], CMD_ARGV[0], s.address);
1576 return nand_fileio_cleanup(&s);
1577 }
1578 s.address += s.page_size;
1579 }
1580
1581 if (nand_fileio_finish(&s))
1582 {
1583 command_print(CMD_CTX, "wrote file %s to NAND flash %s up to "
1584 "offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
1585 CMD_ARGV[1], CMD_ARGV[0], s.address, duration_elapsed(&s.bench),
1586 duration_kbps(&s.bench, total_bytes));
1587 }
1588 return ERROR_OK;
1589 }
1590
1591 COMMAND_HANDLER(handle_nand_verify_command)
1592 {
1593 struct nand_device *nand = NULL;
1594 struct nand_fileio_state file;
1595 int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
1596 &file, &nand, FILEIO_READ, false, true);
1597 if (ERROR_OK != retval)
1598 return retval;
1599
1600 struct nand_fileio_state dev;
1601 nand_fileio_init(&dev);
1602 dev.address = file.address;
1603 dev.size = file.size;
1604 dev.oob_format = file.oob_format;
1605 retval = nand_fileio_start(CMD_CTX, nand, NULL, FILEIO_NONE, &dev);
1606 if (ERROR_OK != retval)
1607 return retval;
1608
1609 while (file.size > 0)
1610 {
1611 int retval = nand_read_page(nand, dev.address / dev.page_size,
1612 dev.page, dev.page_size, dev.oob, dev.oob_size);
1613 if (ERROR_OK != retval)
1614 {
1615 command_print(CMD_CTX, "reading NAND flash page failed");
1616 nand_fileio_cleanup(&dev);
1617 return nand_fileio_cleanup(&file);
1618 }
1619
1620 int bytes_read = nand_fileio_read(nand, &file);
1621 if (bytes_read <= 0)
1622 {
1623 command_print(CMD_CTX, "error while reading file");
1624 nand_fileio_cleanup(&dev);
1625 return nand_fileio_cleanup(&file);
1626 }
1627
1628 if ((dev.page && memcmp(dev.page, file.page, dev.page_size)) ||
1629 (dev.oob && memcmp(dev.oob, file.oob, dev.oob_size)) )
1630 {
1631 command_print(CMD_CTX, "NAND flash contents differ "
1632 "at 0x%8.8" PRIx32, dev.address);
1633 nand_fileio_cleanup(&dev);
1634 return nand_fileio_cleanup(&file);
1635 }
1636
1637 file.size -= bytes_read;
1638 dev.address += nand->page_size;
1639 }
1640
1641 if (nand_fileio_finish(&file) == ERROR_OK)
1642 {
1643 command_print(CMD_CTX, "verified file %s in NAND flash %s "
1644 "up to offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
1645 CMD_ARGV[1], CMD_ARGV[0], dev.address, duration_elapsed(&file.bench),
1646 duration_kbps(&file.bench, dev.size));
1647 }
1648
1649 return nand_fileio_cleanup(&dev);
1650 }
1651
1652 COMMAND_HANDLER(handle_nand_dump_command)
1653 {
1654 struct nand_device *nand = NULL;
1655 struct nand_fileio_state s;
1656 int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
1657 &s, &nand, FILEIO_WRITE, true, false);
1658 if (ERROR_OK != retval)
1659 return retval;
1660
1661 while (s.size > 0)
1662 {
1663 size_t size_written;
1664 int retval = nand_read_page(nand, s.address / nand->page_size,
1665 s.page, s.page_size, s.oob, s.oob_size);
1666 if (ERROR_OK != retval)
1667 {
1668 command_print(CMD_CTX, "reading NAND flash page failed");
1669 return nand_fileio_cleanup(&s);
1670 }
1671
1672 if (NULL != s.page)
1673 fileio_write(&s.fileio, s.page_size, s.page, &size_written);
1674
1675 if (NULL != s.oob)
1676 fileio_write(&s.fileio, s.oob_size, s.oob, &size_written);
1677
1678 s.size -= nand->page_size;
1679 s.address += nand->page_size;
1680 }
1681
1682 if (nand_fileio_finish(&s) == ERROR_OK)
1683 {
1684 command_print(CMD_CTX, "dumped %zu bytes in %fs (%0.3f kb/s)",
1685 s.fileio.size, duration_elapsed(&s.bench),
1686 duration_kbps(&s.bench, s.fileio.size));
1687 }
1688 return ERROR_OK;
1689 }
1690
1691 COMMAND_HANDLER(handle_nand_raw_access_command)
1692 {
1693 if ((CMD_ARGC < 1) || (CMD_ARGC > 2))
1694 {
1695 return ERROR_COMMAND_SYNTAX_ERROR;
1696 }
1697
1698 struct nand_device *p;
1699 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1700 if (ERROR_OK != retval)
1701 return retval;
1702
1703 if (NULL == p->device)
1704 {
1705 command_print(CMD_CTX, "#%s: not probed", CMD_ARGV[0]);
1706 return ERROR_OK;
1707 }
1708
1709 if (CMD_ARGC == 2)
1710 COMMAND_PARSE_ENABLE(CMD_ARGV[1], p->use_raw);
1711
1712 const char *msg = p->use_raw ? "enabled" : "disabled";
1713 command_print(CMD_CTX, "raw access is %s", msg);
1714
1715 return ERROR_OK;
1716 }
1717
1718 static const struct command_registration nand_exec_command_handlers[] = {
1719 {
1720 .name = "list",
1721 .handler = &handle_nand_list_command,
1722 .mode = COMMAND_EXEC,
1723 .help = "list configured NAND flash devices",
1724 },
1725 {
1726 .name = "info",
1727 .handler = &handle_nand_info_command,
1728 .mode = COMMAND_EXEC,
1729 .usage = "<bank>",
1730 .help = "print info about a NAND flash device",
1731 },
1732 {
1733 .name = "probe",
1734 .handler = &handle_nand_probe_command,
1735 .mode = COMMAND_EXEC,
1736 .usage = "<bank>",
1737 .help = "identify NAND flash device <num>",
1738
1739 },
1740 {
1741 .name = "check_bad_blocks",
1742 .handler = &handle_nand_check_bad_blocks_command,
1743 .mode = COMMAND_EXEC,
1744 .usage = "<bank> [<offset> <length>]",
1745 .help = "check NAND flash device <num> for bad blocks",
1746 },
1747 {
1748 .name = "erase",
1749 .handler = &handle_nand_erase_command,
1750 .mode = COMMAND_EXEC,
1751 .usage = "<bank> [<offset> <length>]",
1752 .help = "erase blocks on NAND flash device",
1753 },
1754 {
1755 .name = "dump",
1756 .handler = &handle_nand_dump_command,
1757 .mode = COMMAND_EXEC,
1758 .usage = "<bank> <filename> <offset> <length> "
1759 "[oob_raw | oob_only]",
1760 .help = "dump from NAND flash device",
1761 },
1762 {
1763 .name = "verify",
1764 .handler = &handle_nand_verify_command,
1765 .mode = COMMAND_EXEC,
1766 .usage = "<bank> <filename> <offset> "
1767 "[oob_raw | oob_only | oob_softecc | oob_softecc_kw]",
1768 .help = "verify NAND flash device",
1769 },
1770 {
1771 .name = "write",
1772 .handler = &handle_nand_write_command,
1773 .mode = COMMAND_EXEC,
1774 .usage = "<bank> <filename> <offset> "
1775 "[oob_raw | oob_only | oob_softecc | oob_softecc_kw]",
1776 .help = "write to NAND flash device",
1777 },
1778 {
1779 .name = "raw_access",
1780 .handler = &handle_nand_raw_access_command,
1781 .mode = COMMAND_EXEC,
1782 .usage = "<num> ['enable'|'disable']",
1783 .help = "raw access to NAND flash device",
1784 },
1785 COMMAND_REGISTRATION_DONE
1786 };
1787
1788 int nand_init(struct command_context *cmd_ctx)
1789 {
1790 if (!nand_devices)
1791 return ERROR_OK;
1792 struct command *parent = command_find_in_context(cmd_ctx, "nand");
1793 return register_commands(cmd_ctx, parent, nand_exec_command_handlers);
1794 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)