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Simplify nand indentation.
[openocd.git] / src / flash / nand.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "nand.h"
28 #include "time_support.h"
29 #include "fileio.h"
30
31 static int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
32 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
33 static int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
34 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
35 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
36 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
37 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
38
39 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40
41 static int nand_read_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
42 //static int nand_read_plain(struct nand_device_s *device, uint32_t address, uint8_t *data, uint32_t data_size);
43
44 static int nand_write_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
45
46 /* NAND flash controller
47 */
48 extern nand_flash_controller_t davinci_nand_controller;
49 extern nand_flash_controller_t lpc3180_nand_controller;
50 extern nand_flash_controller_t orion_nand_controller;
51 extern nand_flash_controller_t s3c2410_nand_controller;
52 extern nand_flash_controller_t s3c2412_nand_controller;
53 extern nand_flash_controller_t s3c2440_nand_controller;
54 extern nand_flash_controller_t s3c2443_nand_controller;
55 extern nand_flash_controller_t imx31_nand_flash_controller;
56
57 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
58
59 static nand_flash_controller_t *nand_flash_controllers[] =
60 {
61 &davinci_nand_controller,
62 &lpc3180_nand_controller,
63 &orion_nand_controller,
64 &s3c2410_nand_controller,
65 &s3c2412_nand_controller,
66 &s3c2440_nand_controller,
67 &s3c2443_nand_controller,
68 &imx31_nand_flash_controller,
69 /* &boundary_scan_nand_controller, */
70 NULL
71 };
72
73 /* configured NAND devices and NAND Flash command handler */
74 static nand_device_t *nand_devices = NULL;
75 static command_t *nand_cmd;
76
77 /* Chip ID list
78 *
79 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
80 * options
81 *
82 * Pagesize; 0, 256, 512
83 * 0 get this information from the extended chip ID
84 * 256 256 Byte page size
85 * 512 512 Byte page size
86 */
87 static nand_info_t nand_flash_ids[] =
88 {
89 /* start "museum" IDs */
90 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
91 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
92 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
93 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
94 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
95 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
96 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
97 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
98 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
99 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
100
101 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
102 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
103 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
104 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
105 /* end "museum" IDs */
106
107 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
108 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
109 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
110 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
111
112 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
113 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
114 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
115 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
116
117 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
118 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
119 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
120 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
121
122 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
123 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
124 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
125 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
126 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
127 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
128 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
129
130 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
131
132 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
133 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
134 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
135 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
136
137 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
138 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
139 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
140 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
141
142 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
143 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
144 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
145 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
146
147 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
148 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
149 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
150 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
151
152 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
153 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
154 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
155 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
156
157 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
158 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
159 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
160 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
161
162 {NULL, 0, 0, 0, 0, 0 }
163 };
164
165 /* Manufacturer ID list
166 */
167 static nand_manufacturer_t nand_manuf_ids[] =
168 {
169 {0x0, "unknown"},
170 {NAND_MFR_TOSHIBA, "Toshiba"},
171 {NAND_MFR_SAMSUNG, "Samsung"},
172 {NAND_MFR_FUJITSU, "Fujitsu"},
173 {NAND_MFR_NATIONAL, "National"},
174 {NAND_MFR_RENESAS, "Renesas"},
175 {NAND_MFR_STMICRO, "ST Micro"},
176 {NAND_MFR_HYNIX, "Hynix"},
177 {NAND_MFR_MICRON, "Micron"},
178 {0x0, NULL},
179 };
180
181 /*
182 * Define default oob placement schemes for large and small page devices
183 */
184
185 #if 0
186 static nand_ecclayout_t nand_oob_8 = {
187 .eccbytes = 3,
188 .eccpos = {0, 1, 2},
189 .oobfree = {
190 {.offset = 3,
191 .length = 2},
192 {.offset = 6,
193 .length = 2}}
194 };
195 #endif
196
197 static nand_ecclayout_t nand_oob_16 = {
198 .eccbytes = 6,
199 .eccpos = {0, 1, 2, 3, 6, 7},
200 .oobfree = {
201 {.offset = 8,
202 . length = 8}}
203 };
204
205 static nand_ecclayout_t nand_oob_64 = {
206 .eccbytes = 24,
207 .eccpos = {
208 40, 41, 42, 43, 44, 45, 46, 47,
209 48, 49, 50, 51, 52, 53, 54, 55,
210 56, 57, 58, 59, 60, 61, 62, 63},
211 .oobfree = {
212 {.offset = 2,
213 .length = 38}}
214 };
215
216 /* nand device <nand_controller> [controller options]
217 */
218 static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
219 {
220 int i;
221 int retval;
222
223 if (argc < 1)
224 {
225 LOG_WARNING("incomplete flash device nand configuration");
226 return ERROR_FLASH_BANK_INVALID;
227 }
228
229 for (i = 0; nand_flash_controllers[i]; i++)
230 {
231 nand_device_t *p, *c;
232
233 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
234 {
235 /* register flash specific commands */
236 if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
237 {
238 LOG_ERROR("couldn't register '%s' commands", args[0]);
239 return retval;
240 }
241
242 c = malloc(sizeof(nand_device_t));
243
244 c->controller = nand_flash_controllers[i];
245 c->controller_priv = NULL;
246 c->manufacturer = NULL;
247 c->device = NULL;
248 c->bus_width = 0;
249 c->address_cycles = 0;
250 c->page_size = 0;
251 c->use_raw = 0;
252 c->next = NULL;
253
254 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
255 {
256 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
257 free(c);
258 return ERROR_OK;
259 }
260
261 /* put NAND device in linked list */
262 if (nand_devices)
263 {
264 /* find last flash device */
265 for (p = nand_devices; p && p->next; p = p->next);
266 if (p)
267 p->next = c;
268 }
269 else
270 {
271 nand_devices = c;
272 }
273
274 return ERROR_OK;
275 }
276 }
277
278 /* no valid NAND controller was found (i.e. the configuration option,
279 * didn't match one of the compiled-in controllers)
280 */
281 LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
282 LOG_ERROR("compiled-in NAND flash controllers:");
283 for (i = 0; nand_flash_controllers[i]; i++)
284 {
285 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
286 }
287
288 return ERROR_OK;
289 }
290
291 int nand_register_commands(struct command_context_s *cmd_ctx)
292 {
293 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
294
295 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
296
297 return ERROR_OK;
298 }
299
300 int nand_init(struct command_context_s *cmd_ctx)
301 {
302 if (nand_devices)
303 {
304 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
305 "list configured NAND flash devices");
306 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
307 "print info about NAND flash device <num>");
308 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
309 "identify NAND flash device <num>");
310 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
311 "check NAND flash device <num> for bad blocks [<offset> <length>]");
312 register_command(cmd_ctx, nand_cmd, "erase",
313 handle_nand_erase_command, COMMAND_EXEC,
314 "erase blocks on NAND flash device <num> [<offset> <length>]");
315 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
316 "dump from NAND flash device <num> <filename> "
317 "<offset> <length> [oob_raw | oob_only]");
318 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
319 "write to NAND flash device <num> <filename> <offset> [oob_raw | oob_only | oob_softecc | oob_softecc_kw]");
320 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
321 "raw access to NAND flash device <num> ['enable'|'disable']");
322 }
323
324 return ERROR_OK;
325 }
326
327 nand_device_t *get_nand_device_by_num(int num)
328 {
329 nand_device_t *p;
330 int i = 0;
331
332 for (p = nand_devices; p; p = p->next)
333 {
334 if (i++ == num)
335 {
336 return p;
337 }
338 }
339
340 return NULL;
341 }
342
343 int nand_command_get_device_by_num(struct command_context_s *cmd_ctx,
344 char *str, nand_device_t **device)
345 {
346 unsigned num;
347 COMMAND_PARSE_NUMBER(uint, str, num);
348 *device = get_nand_device_by_num(num);
349 if (!*device) {
350 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", str);
351 return ERROR_INVALID_ARGUMENTS;
352 }
353 return ERROR_OK;
354 }
355
356 static int nand_build_bbt(struct nand_device_s *device, int first, int last)
357 {
358 uint32_t page = 0x0;
359 int i;
360 uint8_t oob[6];
361
362 if ((first < 0) || (first >= device->num_blocks))
363 first = 0;
364
365 if ((last >= device->num_blocks) || (last == -1))
366 last = device->num_blocks - 1;
367
368 for (i = first; i < last; i++)
369 {
370 nand_read_page(device, page, NULL, 0, oob, 6);
371
372 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
373 || (((device->page_size == 512) && (oob[5] != 0xff)) ||
374 ((device->page_size == 2048) && (oob[0] != 0xff))))
375 {
376 LOG_WARNING("bad block: %i", i);
377 device->blocks[i].is_bad = 1;
378 }
379 else
380 {
381 device->blocks[i].is_bad = 0;
382 }
383
384 page += (device->erase_size / device->page_size);
385 }
386
387 return ERROR_OK;
388 }
389
390 int nand_read_status(struct nand_device_s *device, uint8_t *status)
391 {
392 if (!device->device)
393 return ERROR_NAND_DEVICE_NOT_PROBED;
394
395 /* Send read status command */
396 device->controller->command(device, NAND_CMD_STATUS);
397
398 alive_sleep(1);
399
400 /* read status */
401 if (device->device->options & NAND_BUSWIDTH_16)
402 {
403 uint16_t data;
404 device->controller->read_data(device, &data);
405 *status = data & 0xff;
406 }
407 else
408 {
409 device->controller->read_data(device, status);
410 }
411
412 return ERROR_OK;
413 }
414
415 static int nand_poll_ready(struct nand_device_s *device, int timeout)
416 {
417 uint8_t status;
418
419 device->controller->command(device, NAND_CMD_STATUS);
420 do {
421 if (device->device->options & NAND_BUSWIDTH_16) {
422 uint16_t data;
423 device->controller->read_data(device, &data);
424 status = data & 0xff;
425 } else {
426 device->controller->read_data(device, &status);
427 }
428 if (status & NAND_STATUS_READY)
429 break;
430 alive_sleep(1);
431 } while (timeout--);
432
433 return (status & NAND_STATUS_READY) != 0;
434 }
435
436 int nand_probe(struct nand_device_s *device)
437 {
438 uint8_t manufacturer_id, device_id;
439 uint8_t id_buff[6];
440 int retval;
441 int i;
442
443 /* clear device data */
444 device->device = NULL;
445 device->manufacturer = NULL;
446
447 /* clear device parameters */
448 device->bus_width = 0;
449 device->address_cycles = 0;
450 device->page_size = 0;
451 device->erase_size = 0;
452
453 /* initialize controller (device parameters are zero, use controller default) */
454 if ((retval = device->controller->init(device) != ERROR_OK))
455 {
456 switch (retval)
457 {
458 case ERROR_NAND_OPERATION_FAILED:
459 LOG_DEBUG("controller initialization failed");
460 return ERROR_NAND_OPERATION_FAILED;
461 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
462 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
463 return ERROR_NAND_OPERATION_FAILED;
464 default:
465 LOG_ERROR("BUG: unknown controller initialization failure");
466 return ERROR_NAND_OPERATION_FAILED;
467 }
468 }
469
470 device->controller->command(device, NAND_CMD_RESET);
471 device->controller->reset(device);
472
473 device->controller->command(device, NAND_CMD_READID);
474 device->controller->address(device, 0x0);
475
476 if (device->bus_width == 8)
477 {
478 device->controller->read_data(device, &manufacturer_id);
479 device->controller->read_data(device, &device_id);
480 }
481 else
482 {
483 uint16_t data_buf;
484 device->controller->read_data(device, &data_buf);
485 manufacturer_id = data_buf & 0xff;
486 device->controller->read_data(device, &data_buf);
487 device_id = data_buf & 0xff;
488 }
489
490 for (i = 0; nand_flash_ids[i].name; i++)
491 {
492 if (nand_flash_ids[i].id == device_id)
493 {
494 device->device = &nand_flash_ids[i];
495 break;
496 }
497 }
498
499 for (i = 0; nand_manuf_ids[i].name; i++)
500 {
501 if (nand_manuf_ids[i].id == manufacturer_id)
502 {
503 device->manufacturer = &nand_manuf_ids[i];
504 break;
505 }
506 }
507
508 if (!device->manufacturer)
509 {
510 device->manufacturer = &nand_manuf_ids[0];
511 device->manufacturer->id = manufacturer_id;
512 }
513
514 if (!device->device)
515 {
516 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
517 manufacturer_id, device_id);
518 return ERROR_NAND_OPERATION_FAILED;
519 }
520
521 LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
522
523 /* initialize device parameters */
524
525 /* bus width */
526 if (device->device->options & NAND_BUSWIDTH_16)
527 device->bus_width = 16;
528 else
529 device->bus_width = 8;
530
531 /* Do we need extended device probe information? */
532 if (device->device->page_size == 0 ||
533 device->device->erase_size == 0)
534 {
535 if (device->bus_width == 8)
536 {
537 device->controller->read_data(device, id_buff + 3);
538 device->controller->read_data(device, id_buff + 4);
539 device->controller->read_data(device, id_buff + 5);
540 }
541 else
542 {
543 uint16_t data_buf;
544
545 device->controller->read_data(device, &data_buf);
546 id_buff[3] = data_buf;
547
548 device->controller->read_data(device, &data_buf);
549 id_buff[4] = data_buf;
550
551 device->controller->read_data(device, &data_buf);
552 id_buff[5] = data_buf >> 8;
553 }
554 }
555
556 /* page size */
557 if (device->device->page_size == 0)
558 {
559 device->page_size = 1 << (10 + (id_buff[4] & 3));
560 }
561 else if (device->device->page_size == 256)
562 {
563 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
564 return ERROR_NAND_OPERATION_FAILED;
565 }
566 else
567 {
568 device->page_size = device->device->page_size;
569 }
570
571 /* number of address cycles */
572 if (device->page_size <= 512)
573 {
574 /* small page devices */
575 if (device->device->chip_size <= 32)
576 device->address_cycles = 3;
577 else if (device->device->chip_size <= 8*1024)
578 device->address_cycles = 4;
579 else
580 {
581 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
582 device->address_cycles = 5;
583 }
584 }
585 else
586 {
587 /* large page devices */
588 if (device->device->chip_size <= 128)
589 device->address_cycles = 4;
590 else if (device->device->chip_size <= 32*1024)
591 device->address_cycles = 5;
592 else
593 {
594 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
595 device->address_cycles = 6;
596 }
597 }
598
599 /* erase size */
600 if (device->device->erase_size == 0)
601 {
602 switch ((id_buff[4] >> 4) & 3) {
603 case 0:
604 device->erase_size = 64 << 10;
605 break;
606 case 1:
607 device->erase_size = 128 << 10;
608 break;
609 case 2:
610 device->erase_size = 256 << 10;
611 break;
612 case 3:
613 device->erase_size =512 << 10;
614 break;
615 }
616 }
617 else
618 {
619 device->erase_size = device->device->erase_size;
620 }
621
622 /* initialize controller, but leave parameters at the controllers default */
623 if ((retval = device->controller->init(device) != ERROR_OK))
624 {
625 switch (retval)
626 {
627 case ERROR_NAND_OPERATION_FAILED:
628 LOG_DEBUG("controller initialization failed");
629 return ERROR_NAND_OPERATION_FAILED;
630 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
631 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
632 device->bus_width, device->address_cycles, device->page_size);
633 return ERROR_NAND_OPERATION_FAILED;
634 default:
635 LOG_ERROR("BUG: unknown controller initialization failure");
636 return ERROR_NAND_OPERATION_FAILED;
637 }
638 }
639
640 device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
641 device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
642
643 for (i = 0; i < device->num_blocks; i++)
644 {
645 device->blocks[i].size = device->erase_size;
646 device->blocks[i].offset = i * device->erase_size;
647 device->blocks[i].is_erased = -1;
648 device->blocks[i].is_bad = -1;
649 }
650
651 return ERROR_OK;
652 }
653
654 static int nand_erase(struct nand_device_s *device, int first_block, int last_block)
655 {
656 int i;
657 uint32_t page;
658 uint8_t status;
659 int retval;
660
661 if (!device->device)
662 return ERROR_NAND_DEVICE_NOT_PROBED;
663
664 if ((first_block < 0) || (last_block > device->num_blocks))
665 return ERROR_INVALID_ARGUMENTS;
666
667 /* make sure we know if a block is bad before erasing it */
668 for (i = first_block; i <= last_block; i++)
669 {
670 if (device->blocks[i].is_bad == -1)
671 {
672 nand_build_bbt(device, i, last_block);
673 break;
674 }
675 }
676
677 for (i = first_block; i <= last_block; i++)
678 {
679 /* Send erase setup command */
680 device->controller->command(device, NAND_CMD_ERASE1);
681
682 page = i * (device->erase_size / device->page_size);
683
684 /* Send page address */
685 if (device->page_size <= 512)
686 {
687 /* row */
688 device->controller->address(device, page & 0xff);
689 device->controller->address(device, (page >> 8) & 0xff);
690
691 /* 3rd cycle only on devices with more than 32 MiB */
692 if (device->address_cycles >= 4)
693 device->controller->address(device, (page >> 16) & 0xff);
694
695 /* 4th cycle only on devices with more than 8 GiB */
696 if (device->address_cycles >= 5)
697 device->controller->address(device, (page >> 24) & 0xff);
698 }
699 else
700 {
701 /* row */
702 device->controller->address(device, page & 0xff);
703 device->controller->address(device, (page >> 8) & 0xff);
704
705 /* 3rd cycle only on devices with more than 128 MiB */
706 if (device->address_cycles >= 5)
707 device->controller->address(device, (page >> 16) & 0xff);
708 }
709
710 /* Send erase confirm command */
711 device->controller->command(device, NAND_CMD_ERASE2);
712
713 retval = device->controller->nand_ready ?
714 device->controller->nand_ready(device, 1000) :
715 nand_poll_ready(device, 1000);
716 if (!retval) {
717 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
718 return ERROR_NAND_OPERATION_TIMEOUT;
719 }
720
721 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
722 {
723 LOG_ERROR("couldn't read status");
724 return ERROR_NAND_OPERATION_FAILED;
725 }
726
727 if (status & 0x1)
728 {
729 LOG_ERROR("didn't erase %sblock %d; status: 0x%2.2x",
730 (device->blocks[i].is_bad == 1)
731 ? "bad " : "",
732 i, status);
733 /* continue; other blocks might still be erasable */
734 }
735
736 device->blocks[i].is_erased = 1;
737 }
738
739 return ERROR_OK;
740 }
741
742 #if 0
743 static int nand_read_plain(struct nand_device_s *device, uint32_t address, uint8_t *data, uint32_t data_size)
744 {
745 uint8_t *page;
746
747 if (!device->device)
748 return ERROR_NAND_DEVICE_NOT_PROBED;
749
750 if (address % device->page_size)
751 {
752 LOG_ERROR("reads need to be page aligned");
753 return ERROR_NAND_OPERATION_FAILED;
754 }
755
756 page = malloc(device->page_size);
757
758 while (data_size > 0)
759 {
760 uint32_t thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
761 uint32_t page_address;
762
763
764 page_address = address / device->page_size;
765
766 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
767
768 memcpy(data, page, thisrun_size);
769
770 address += thisrun_size;
771 data += thisrun_size;
772 data_size -= thisrun_size;
773 }
774
775 free(page);
776
777 return ERROR_OK;
778 }
779
780 static int nand_write_plain(struct nand_device_s *device, uint32_t address, uint8_t *data, uint32_t data_size)
781 {
782 uint8_t *page;
783
784 if (!device->device)
785 return ERROR_NAND_DEVICE_NOT_PROBED;
786
787 if (address % device->page_size)
788 {
789 LOG_ERROR("writes need to be page aligned");
790 return ERROR_NAND_OPERATION_FAILED;
791 }
792
793 page = malloc(device->page_size);
794
795 while (data_size > 0)
796 {
797 uint32_t thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
798 uint32_t page_address;
799
800 memset(page, 0xff, device->page_size);
801 memcpy(page, data, thisrun_size);
802
803 page_address = address / device->page_size;
804
805 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
806
807 address += thisrun_size;
808 data += thisrun_size;
809 data_size -= thisrun_size;
810 }
811
812 free(page);
813
814 return ERROR_OK;
815 }
816 #endif
817
818 int nand_write_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
819 {
820 uint32_t block;
821
822 if (!device->device)
823 return ERROR_NAND_DEVICE_NOT_PROBED;
824
825 block = page / (device->erase_size / device->page_size);
826 if (device->blocks[block].is_erased == 1)
827 device->blocks[block].is_erased = 0;
828
829 if (device->use_raw || device->controller->write_page == NULL)
830 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
831 else
832 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
833 }
834
835 static int nand_read_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
836 {
837 if (!device->device)
838 return ERROR_NAND_DEVICE_NOT_PROBED;
839
840 if (device->use_raw || device->controller->read_page == NULL)
841 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
842 else
843 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
844 }
845
846 int nand_read_page_raw(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
847 {
848 uint32_t i;
849
850 if (!device->device)
851 return ERROR_NAND_DEVICE_NOT_PROBED;
852
853 if (device->page_size <= 512)
854 {
855 /* small page device */
856 if (data)
857 device->controller->command(device, NAND_CMD_READ0);
858 else
859 device->controller->command(device, NAND_CMD_READOOB);
860
861 /* column (always 0, we start at the beginning of a page/OOB area) */
862 device->controller->address(device, 0x0);
863
864 /* row */
865 device->controller->address(device, page & 0xff);
866 device->controller->address(device, (page >> 8) & 0xff);
867
868 /* 4th cycle only on devices with more than 32 MiB */
869 if (device->address_cycles >= 4)
870 device->controller->address(device, (page >> 16) & 0xff);
871
872 /* 5th cycle only on devices with more than 8 GiB */
873 if (device->address_cycles >= 5)
874 device->controller->address(device, (page >> 24) & 0xff);
875 }
876 else
877 {
878 /* large page device */
879 device->controller->command(device, NAND_CMD_READ0);
880
881 /* column (0 when we start at the beginning of a page,
882 * or 2048 for the beginning of OOB area)
883 */
884 device->controller->address(device, 0x0);
885 if (data)
886 device->controller->address(device, 0x0);
887 else
888 device->controller->address(device, 0x8);
889
890 /* row */
891 device->controller->address(device, page & 0xff);
892 device->controller->address(device, (page >> 8) & 0xff);
893
894 /* 5th cycle only on devices with more than 128 MiB */
895 if (device->address_cycles >= 5)
896 device->controller->address(device, (page >> 16) & 0xff);
897
898 /* large page devices need a start command */
899 device->controller->command(device, NAND_CMD_READSTART);
900 }
901
902 if (device->controller->nand_ready) {
903 if (!device->controller->nand_ready(device, 100))
904 return ERROR_NAND_OPERATION_TIMEOUT;
905 } else {
906 alive_sleep(1);
907 }
908
909 if (data)
910 {
911 if (device->controller->read_block_data != NULL)
912 (device->controller->read_block_data)(device, data, data_size);
913 else
914 {
915 for (i = 0; i < data_size;)
916 {
917 if (device->device->options & NAND_BUSWIDTH_16)
918 {
919 device->controller->read_data(device, data);
920 data += 2;
921 i += 2;
922 }
923 else
924 {
925 device->controller->read_data(device, data);
926 data += 1;
927 i += 1;
928 }
929 }
930 }
931 }
932
933 if (oob)
934 {
935 if (device->controller->read_block_data != NULL)
936 (device->controller->read_block_data)(device, oob, oob_size);
937 else
938 {
939 for (i = 0; i < oob_size;)
940 {
941 if (device->device->options & NAND_BUSWIDTH_16)
942 {
943 device->controller->read_data(device, oob);
944 oob += 2;
945 i += 2;
946 }
947 else
948 {
949 device->controller->read_data(device, oob);
950 oob += 1;
951 i += 1;
952 }
953 }
954 }
955 }
956
957 return ERROR_OK;
958 }
959
960 int nand_write_page_raw(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
961 {
962 uint32_t i;
963 int retval;
964 uint8_t status;
965
966 if (!device->device)
967 return ERROR_NAND_DEVICE_NOT_PROBED;
968
969 device->controller->command(device, NAND_CMD_SEQIN);
970
971 if (device->page_size <= 512)
972 {
973 /* column (always 0, we start at the beginning of a page/OOB area) */
974 device->controller->address(device, 0x0);
975
976 /* row */
977 device->controller->address(device, page & 0xff);
978 device->controller->address(device, (page >> 8) & 0xff);
979
980 /* 4th cycle only on devices with more than 32 MiB */
981 if (device->address_cycles >= 4)
982 device->controller->address(device, (page >> 16) & 0xff);
983
984 /* 5th cycle only on devices with more than 8 GiB */
985 if (device->address_cycles >= 5)
986 device->controller->address(device, (page >> 24) & 0xff);
987 }
988 else
989 {
990 /* column (0 when we start at the beginning of a page,
991 * or 2048 for the beginning of OOB area)
992 */
993 device->controller->address(device, 0x0);
994 if (data)
995 device->controller->address(device, 0x0);
996 else
997 device->controller->address(device, 0x8);
998
999 /* row */
1000 device->controller->address(device, page & 0xff);
1001 device->controller->address(device, (page >> 8) & 0xff);
1002
1003 /* 5th cycle only on devices with more than 128 MiB */
1004 if (device->address_cycles >= 5)
1005 device->controller->address(device, (page >> 16) & 0xff);
1006 }
1007
1008 if (data)
1009 {
1010 if (device->controller->write_block_data != NULL)
1011 (device->controller->write_block_data)(device, data, data_size);
1012 else
1013 {
1014 for (i = 0; i < data_size;)
1015 {
1016 if (device->device->options & NAND_BUSWIDTH_16)
1017 {
1018 uint16_t data_buf = le_to_h_u16(data);
1019 device->controller->write_data(device, data_buf);
1020 data += 2;
1021 i += 2;
1022 }
1023 else
1024 {
1025 device->controller->write_data(device, *data);
1026 data += 1;
1027 i += 1;
1028 }
1029 }
1030 }
1031 }
1032
1033 if (oob)
1034 {
1035 if (device->controller->write_block_data != NULL)
1036 (device->controller->write_block_data)(device, oob, oob_size);
1037 else
1038 {
1039 for (i = 0; i < oob_size;)
1040 {
1041 if (device->device->options & NAND_BUSWIDTH_16)
1042 {
1043 uint16_t oob_buf = le_to_h_u16(data);
1044 device->controller->write_data(device, oob_buf);
1045 oob += 2;
1046 i += 2;
1047 }
1048 else
1049 {
1050 device->controller->write_data(device, *oob);
1051 oob += 1;
1052 i += 1;
1053 }
1054 }
1055 }
1056 }
1057
1058 device->controller->command(device, NAND_CMD_PAGEPROG);
1059
1060 retval = device->controller->nand_ready ?
1061 device->controller->nand_ready(device, 100) :
1062 nand_poll_ready(device, 100);
1063 if (!retval)
1064 return ERROR_NAND_OPERATION_TIMEOUT;
1065
1066 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
1067 {
1068 LOG_ERROR("couldn't read status");
1069 return ERROR_NAND_OPERATION_FAILED;
1070 }
1071
1072 if (status & NAND_STATUS_FAIL)
1073 {
1074 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1075 return ERROR_NAND_OPERATION_FAILED;
1076 }
1077
1078 return ERROR_OK;
1079 }
1080
1081 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1082 {
1083 nand_device_t *p;
1084 int i;
1085
1086 if (!nand_devices)
1087 {
1088 command_print(cmd_ctx, "no NAND flash devices configured");
1089 return ERROR_OK;
1090 }
1091
1092 for (p = nand_devices, i = 0; p; p = p->next, i++)
1093 {
1094 if (p->device)
1095 command_print(cmd_ctx, "#%i: %s (%s) "
1096 "pagesize: %i, buswidth: %i,\n\t"
1097 "blocksize: %i, blocks: %i",
1098 i, p->device->name, p->manufacturer->name,
1099 p->page_size, p->bus_width,
1100 p->erase_size, p->num_blocks);
1101 else
1102 command_print(cmd_ctx, "#%i: not probed", i);
1103 }
1104
1105 return ERROR_OK;
1106 }
1107
1108 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1109 {
1110 int i = 0;
1111 int j = 0;
1112 int first = -1;
1113 int last = -1;
1114
1115 nand_device_t *p;
1116 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1117 if (ERROR_OK != retval)
1118 return retval;
1119
1120 switch (argc) {
1121 default:
1122 return ERROR_COMMAND_SYNTAX_ERROR;
1123 case 1:
1124 first = 0;
1125 last = INT32_MAX;
1126 break;
1127 case 2:
1128 COMMAND_PARSE_NUMBER(int, args[1], i);
1129 first = last = i;
1130 i = 0;
1131 break;
1132 case 3:
1133 COMMAND_PARSE_NUMBER(int, args[1], first);
1134 COMMAND_PARSE_NUMBER(int, args[2], last);
1135 break;
1136 }
1137
1138 if (NULL == p->device)
1139 {
1140 command_print(cmd_ctx, "#%s: not probed", args[0]);
1141 return ERROR_OK;
1142 }
1143
1144 if (first >= p->num_blocks)
1145 first = p->num_blocks - 1;
1146
1147 if (last >= p->num_blocks)
1148 last = p->num_blocks - 1;
1149
1150 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1151 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1152
1153 for (j = first; j <= last; j++)
1154 {
1155 char *erase_state, *bad_state;
1156
1157 if (p->blocks[j].is_erased == 0)
1158 erase_state = "not erased";
1159 else if (p->blocks[j].is_erased == 1)
1160 erase_state = "erased";
1161 else
1162 erase_state = "erase state unknown";
1163
1164 if (p->blocks[j].is_bad == 0)
1165 bad_state = "";
1166 else if (p->blocks[j].is_bad == 1)
1167 bad_state = " (marked bad)";
1168 else
1169 bad_state = " (block condition unknown)";
1170
1171 command_print(cmd_ctx,
1172 "\t#%i: 0x%8.8" PRIx32 " (%" PRId32 "kB) %s%s",
1173 j,
1174 p->blocks[j].offset,
1175 p->blocks[j].size / 1024,
1176 erase_state,
1177 bad_state);
1178 }
1179
1180 return ERROR_OK;
1181 }
1182
1183 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1184 {
1185 if (argc != 1)
1186 {
1187 return ERROR_COMMAND_SYNTAX_ERROR;
1188 }
1189
1190 nand_device_t *p;
1191 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1192 if (ERROR_OK != retval)
1193 return retval;
1194
1195 if ((retval = nand_probe(p)) == ERROR_OK)
1196 {
1197 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1198 }
1199 else if (retval == ERROR_NAND_OPERATION_FAILED)
1200 {
1201 command_print(cmd_ctx, "probing failed for NAND flash device");
1202 }
1203 else
1204 {
1205 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1206 }
1207
1208 return ERROR_OK;
1209 }
1210
1211 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1212 {
1213 if (argc != 1 && argc != 3)
1214 {
1215 return ERROR_COMMAND_SYNTAX_ERROR;
1216
1217 }
1218
1219 nand_device_t *p;
1220 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1221 if (ERROR_OK != retval)
1222 return retval;
1223
1224 unsigned long offset;
1225 unsigned long length;
1226
1227 /* erase specified part of the chip; or else everything */
1228 if (argc == 3) {
1229 unsigned long size = p->erase_size * p->num_blocks;
1230
1231 COMMAND_PARSE_NUMBER(ulong, args[1], offset);
1232 if ((offset % p->erase_size) != 0 || offset >= size)
1233 return ERROR_INVALID_ARGUMENTS;
1234
1235 COMMAND_PARSE_NUMBER(ulong, args[2], length);
1236 if ((length == 0) || (length % p->erase_size) != 0
1237 || (length + offset) > size)
1238 return ERROR_INVALID_ARGUMENTS;
1239
1240 offset /= p->erase_size;
1241 length /= p->erase_size;
1242 } else {
1243 offset = 0;
1244 length = p->num_blocks;
1245 }
1246
1247 retval = nand_erase(p, offset, offset + length - 1);
1248 if (retval == ERROR_OK)
1249 {
1250 command_print(cmd_ctx, "erased blocks %lu to %lu "
1251 "on NAND flash device #%s '%s'",
1252 offset, offset + length,
1253 args[0], p->device->name);
1254 }
1255 else if (retval == ERROR_NAND_OPERATION_FAILED)
1256 {
1257 command_print(cmd_ctx, "erase failed");
1258 }
1259 else
1260 {
1261 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1262 }
1263
1264 return ERROR_OK;
1265 }
1266
1267 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1268 {
1269 int first = -1;
1270 int last = -1;
1271
1272 if ((argc < 1) || (argc > 3) || (argc == 2))
1273 {
1274 return ERROR_COMMAND_SYNTAX_ERROR;
1275
1276 }
1277
1278 nand_device_t *p;
1279 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1280 if (ERROR_OK != retval)
1281 return retval;
1282
1283 if (argc == 3)
1284 {
1285 unsigned long offset;
1286 unsigned long length;
1287
1288 COMMAND_PARSE_NUMBER(ulong, args[1], offset);
1289 if (offset % p->erase_size)
1290 return ERROR_INVALID_ARGUMENTS;
1291 offset /= p->erase_size;
1292
1293 COMMAND_PARSE_NUMBER(ulong, args[2], length);
1294 if (length % p->erase_size)
1295 return ERROR_INVALID_ARGUMENTS;
1296
1297 length -= 1;
1298 length /= p->erase_size;
1299
1300 first = offset;
1301 last = offset + length;
1302 }
1303
1304 retval = nand_build_bbt(p, first, last);
1305 if (retval == ERROR_OK)
1306 {
1307 command_print(cmd_ctx, "checked NAND flash device for bad blocks, "
1308 "use \"nand info\" command to list blocks");
1309 }
1310 else if (retval == ERROR_NAND_OPERATION_FAILED)
1311 {
1312 command_print(cmd_ctx, "error when checking for bad blocks on "
1313 "NAND flash device");
1314 }
1315 else
1316 {
1317 command_print(cmd_ctx, "unknown error when checking for bad "
1318 "blocks on NAND flash device");
1319 }
1320
1321 return ERROR_OK;
1322 }
1323
1324 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1325 {
1326 uint32_t offset;
1327 uint32_t binary_size;
1328 uint32_t buf_cnt;
1329 enum oob_formats oob_format = NAND_OOB_NONE;
1330
1331 fileio_t fileio;
1332
1333 duration_t duration;
1334 char *duration_text;
1335
1336 if (argc < 3)
1337 {
1338 return ERROR_COMMAND_SYNTAX_ERROR;
1339 }
1340
1341 nand_device_t *p;
1342 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1343 if (ERROR_OK != retval)
1344 return retval;
1345
1346 uint8_t *page = NULL;
1347 uint32_t page_size = 0;
1348 uint8_t *oob = NULL;
1349 uint32_t oob_size = 0;
1350 const int *eccpos = NULL;
1351
1352 COMMAND_PARSE_NUMBER(u32, args[2], offset);
1353
1354 if (argc > 3)
1355 {
1356 int i;
1357 for (i = 3; i < argc; i++)
1358 {
1359 if (!strcmp(args[i], "oob_raw"))
1360 oob_format |= NAND_OOB_RAW;
1361 else if (!strcmp(args[i], "oob_only"))
1362 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1363 else if (!strcmp(args[i], "oob_softecc"))
1364 oob_format |= NAND_OOB_SW_ECC;
1365 else if (!strcmp(args[i], "oob_softecc_kw"))
1366 oob_format |= NAND_OOB_SW_ECC_KW;
1367 else
1368 {
1369 command_print(cmd_ctx, "unknown option: %s", args[i]);
1370 return ERROR_COMMAND_SYNTAX_ERROR;
1371 }
1372 }
1373 }
1374
1375 duration_start_measure(&duration);
1376
1377 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1378 {
1379 return ERROR_OK;
1380 }
1381
1382 buf_cnt = binary_size = fileio.size;
1383
1384 if (!(oob_format & NAND_OOB_ONLY))
1385 {
1386 page_size = p->page_size;
1387 page = malloc(p->page_size);
1388 }
1389
1390 if (oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC | NAND_OOB_SW_ECC_KW))
1391 {
1392 if (p->page_size == 512) {
1393 oob_size = 16;
1394 eccpos = nand_oob_16.eccpos;
1395 } else if (p->page_size == 2048) {
1396 oob_size = 64;
1397 eccpos = nand_oob_64.eccpos;
1398 }
1399 oob = malloc(oob_size);
1400 }
1401
1402 if (offset % p->page_size)
1403 {
1404 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1405 fileio_close(&fileio);
1406 free(oob);
1407 free(page);
1408 return ERROR_OK;
1409 }
1410
1411 while (buf_cnt > 0)
1412 {
1413 uint32_t size_read;
1414
1415 if (NULL != page)
1416 {
1417 fileio_read(&fileio, page_size, page, &size_read);
1418 buf_cnt -= size_read;
1419 if (size_read < page_size)
1420 {
1421 memset(page + size_read, 0xff, page_size - size_read);
1422 }
1423 }
1424
1425 if (oob_format & NAND_OOB_SW_ECC)
1426 {
1427 uint32_t i, j;
1428 uint8_t ecc[3];
1429 memset(oob, 0xff, oob_size);
1430 for (i = 0, j = 0; i < page_size; i += 256) {
1431 nand_calculate_ecc(p, page + i, ecc);
1432 oob[eccpos[j++]] = ecc[0];
1433 oob[eccpos[j++]] = ecc[1];
1434 oob[eccpos[j++]] = ecc[2];
1435 }
1436 } else if (oob_format & NAND_OOB_SW_ECC_KW)
1437 {
1438 /*
1439 * In this case eccpos is not used as
1440 * the ECC data is always stored contigously
1441 * at the end of the OOB area. It consists
1442 * of 10 bytes per 512-byte data block.
1443 */
1444 uint32_t i;
1445 uint8_t *ecc = oob + oob_size - page_size/512 * 10;
1446 memset(oob, 0xff, oob_size);
1447 for (i = 0; i < page_size; i += 512) {
1448 nand_calculate_ecc_kw(p, page + i, ecc);
1449 ecc += 10;
1450 }
1451 }
1452 else if (NULL != oob)
1453 {
1454 fileio_read(&fileio, oob_size, oob, &size_read);
1455 buf_cnt -= size_read;
1456 if (size_read < oob_size)
1457 {
1458 memset(oob + size_read, 0xff, oob_size - size_read);
1459 }
1460 }
1461
1462 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1463 {
1464 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8" PRIx32 "",
1465 args[1], args[0], offset);
1466
1467 fileio_close(&fileio);
1468 free(oob);
1469 free(page);
1470
1471 return ERROR_OK;
1472 }
1473 offset += page_size;
1474 }
1475
1476 fileio_close(&fileio);
1477 free(oob);
1478 free(page);
1479 oob = NULL;
1480 page = NULL;
1481 duration_stop_measure(&duration, &duration_text);
1482 command_print(cmd_ctx, "wrote file %s to NAND flash %s up to offset 0x%8.8" PRIx32 " in %s",
1483 args[1], args[0], offset, duration_text);
1484 free(duration_text);
1485 duration_text = NULL;
1486
1487 return ERROR_OK;
1488 }
1489
1490 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1491 {
1492 if (argc < 4)
1493 {
1494 return ERROR_COMMAND_SYNTAX_ERROR;
1495 }
1496
1497 nand_device_t *p;
1498 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1499 if (ERROR_OK != retval)
1500 return retval;
1501
1502 if (NULL == p->device)
1503 {
1504 command_print(cmd_ctx, "#%s: not probed", args[0]);
1505 return ERROR_OK;
1506 }
1507
1508 fileio_t fileio;
1509 duration_t duration;
1510 char *duration_text;
1511
1512 uint8_t *page = NULL;
1513 uint32_t page_size = 0;
1514 uint8_t *oob = NULL;
1515 uint32_t oob_size = 0;
1516 uint32_t address;
1517 COMMAND_PARSE_NUMBER(u32, args[2], address);
1518 uint32_t size;
1519 COMMAND_PARSE_NUMBER(u32, args[3], size);
1520 uint32_t bytes_done = 0;
1521 enum oob_formats oob_format = NAND_OOB_NONE;
1522
1523 if (argc > 4)
1524 {
1525 int i;
1526 for (i = 4; i < argc; i++)
1527 {
1528 if (!strcmp(args[i], "oob_raw"))
1529 oob_format |= NAND_OOB_RAW;
1530 else if (!strcmp(args[i], "oob_only"))
1531 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1532 else
1533 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1534 }
1535 }
1536
1537 if ((address % p->page_size) || (size % p->page_size))
1538 {
1539 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1540 return ERROR_OK;
1541 }
1542
1543 if (!(oob_format & NAND_OOB_ONLY))
1544 {
1545 page_size = p->page_size;
1546 page = malloc(p->page_size);
1547 }
1548
1549 if (oob_format & NAND_OOB_RAW)
1550 {
1551 if (p->page_size == 512)
1552 oob_size = 16;
1553 else if (p->page_size == 2048)
1554 oob_size = 64;
1555 oob = malloc(oob_size);
1556 }
1557
1558 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1559 {
1560 return ERROR_OK;
1561 }
1562
1563 duration_start_measure(&duration);
1564
1565 while (size > 0)
1566 {
1567 uint32_t size_written;
1568 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1569 {
1570 command_print(cmd_ctx, "reading NAND flash page failed");
1571 free(page);
1572 free(oob);
1573 fileio_close(&fileio);
1574 return ERROR_OK;
1575 }
1576
1577 if (NULL != page)
1578 {
1579 fileio_write(&fileio, page_size, page, &size_written);
1580 bytes_done += page_size;
1581 }
1582
1583 if (NULL != oob)
1584 {
1585 fileio_write(&fileio, oob_size, oob, &size_written);
1586 bytes_done += oob_size;
1587 }
1588
1589 size -= p->page_size;
1590 address += p->page_size;
1591 }
1592
1593 free(page);
1594 page = NULL;
1595 free(oob);
1596 oob = NULL;
1597 fileio_close(&fileio);
1598
1599 duration_stop_measure(&duration, &duration_text);
1600 command_print(cmd_ctx, "dumped %lld byte in %s", fileio.size, duration_text);
1601 free(duration_text);
1602 duration_text = NULL;
1603
1604 return ERROR_OK;
1605 }
1606
1607 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1608 {
1609 if ((argc < 1) || (argc > 2))
1610 {
1611 return ERROR_COMMAND_SYNTAX_ERROR;
1612 }
1613
1614 nand_device_t *p;
1615 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1616 if (ERROR_OK != retval)
1617 return retval;
1618
1619 if (NULL == p->device)
1620 {
1621 command_print(cmd_ctx, "#%s: not probed", args[0]);
1622 return ERROR_OK;
1623 }
1624
1625 if (argc == 2)
1626 {
1627 if (strcmp("enable", args[1]) == 0)
1628 p->use_raw = 1;
1629 else if (strcmp("disable", args[1]) == 0)
1630 p->use_raw = 0;
1631 else
1632 return ERROR_COMMAND_SYNTAX_ERROR;
1633 }
1634
1635 const char *msg = p->use_raw ? "enabled" : "disabled";
1636 command_print(cmd_ctx, "raw access is %s", msg);
1637
1638 return ERROR_OK;
1639 }
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